diff options
author | Thomas Langer <thomas.langer@lantiq.com> | 2012-05-02 06:27:38 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2012-05-15 11:49:22 -0400 |
commit | 7705f6867bfc6f2ea42c3965a85df72abf070c86 (patch) | |
tree | 556ac1fafeb72b372873c404ab7e4cf47a917e63 /arch/mips | |
parent | a8d096ef78c4d9a664754e1fad5e82dec2feec68 (diff) |
MIPS: lantiq: fix early printk
The code was using a 32bit write operations in the early_printk code. This
resulted in 3 zero bytes also being written to the serial port. This patch
changes the memory access to 8bit.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3721/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 | ||||
-rw-r--r-- | arch/mips/lantiq/early_printk.c | 17 |
2 files changed, 14 insertions, 9 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 8a3c6be669d2..8bc9030525c0 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | |||
@@ -34,6 +34,12 @@ | |||
34 | #define LTQ_ASC1_BASE_ADDR 0x1E100C00 | 34 | #define LTQ_ASC1_BASE_ADDR 0x1E100C00 |
35 | #define LTQ_ASC_SIZE 0x400 | 35 | #define LTQ_ASC_SIZE 0x400 |
36 | 36 | ||
37 | /* | ||
38 | * during early_printk no ioremap is possible | ||
39 | * lets use KSEG1 instead | ||
40 | */ | ||
41 | #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) | ||
42 | |||
37 | /* RCU - reset control unit */ | 43 | /* RCU - reset control unit */ |
38 | #define LTQ_RCU_BASE_ADDR 0x1F203000 | 44 | #define LTQ_RCU_BASE_ADDR 0x1F203000 |
39 | #define LTQ_RCU_SIZE 0x1000 | 45 | #define LTQ_RCU_SIZE 0x1000 |
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c index 972e05f87631..9b28d0940ef4 100644 --- a/arch/mips/lantiq/early_printk.c +++ b/arch/mips/lantiq/early_printk.c | |||
@@ -6,17 +6,16 @@ | |||
6 | * Copyright (C) 2010 John Crispin <blogic@openwrt.org> | 6 | * Copyright (C) 2010 John Crispin <blogic@openwrt.org> |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #include <linux/init.h> | ||
10 | #include <linux/cpu.h> | 9 | #include <linux/cpu.h> |
11 | |||
12 | #include <lantiq.h> | ||
13 | #include <lantiq_soc.h> | 10 | #include <lantiq_soc.h> |
14 | 11 | ||
15 | /* no ioremap possible at this early stage, lets use KSEG1 instead */ | ||
16 | #define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) | ||
17 | #define ASC_BUF 1024 | 12 | #define ASC_BUF 1024 |
18 | #define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) | 13 | #define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048)) |
19 | #define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) | 14 | #ifdef __BIG_ENDIAN |
15 | #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3)) | ||
16 | #else | ||
17 | #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020)) | ||
18 | #endif | ||
20 | #define TXMASK 0x3F00 | 19 | #define TXMASK 0x3F00 |
21 | #define TXOFFSET 8 | 20 | #define TXOFFSET 8 |
22 | 21 | ||
@@ -27,7 +26,7 @@ void prom_putchar(char c) | |||
27 | local_irq_save(flags); | 26 | local_irq_save(flags); |
28 | do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); | 27 | do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); |
29 | if (c == '\n') | 28 | if (c == '\n') |
30 | ltq_w32('\r', LTQ_ASC_TBUF); | 29 | ltq_w8('\r', LTQ_ASC_TBUF); |
31 | ltq_w32(c, LTQ_ASC_TBUF); | 30 | ltq_w8(c, LTQ_ASC_TBUF); |
32 | local_irq_restore(flags); | 31 | local_irq_restore(flags); |
33 | } | 32 | } |