MIPS: ath79: add clock setup code for the QCA955X SoCs

The patch adds code to get various clock frequencies
from the PLLs used in the QCA955x SoCs.

Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4945/
Signed-off-by: John Crispin <blogic@openwrt.org>

1 files changed, 39 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 63a9f2b600b8..7b00e12afc1c 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -225,6 +225,41 @@
 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL  BIT(21)
 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL  BIT(24)
 
+#define QCA955X_PLL_CPU_CONFIG_REG              0x00
+#define QCA955X_PLL_DDR_CONFIG_REG              0x04
+#define QCA955X_PLL_CLK_CTRL_REG                0x08
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT       6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK        0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT     12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK      0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT     19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK      0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT      0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK       0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT       10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK        0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT     16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK      0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT     23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK      0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
 /*
  * USB_CONFIG block
  */
@@ -264,6 +299,8 @@
 #define AR934X_RESET_REG_BOOTSTRAP              0xb0
 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   0xac
 
+#define QCA955X_RESET_REG_BOOTSTRAP             0xb0
+
 #define MISC_INT_ETHSW                  BIT(12)
 #define MISC_INT_TIMER4                 BIT(10)
 #define MISC_INT_TIMER3                 BIT(9)
@@ -341,6 +378,8 @@
 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 #define AR934X_BOOTSTRAP_DDR1           BIT(0)
 
+#define QCA955X_BOOTSTRAP_REF_CLK_40    BIT(4)
+
 #define AR934X_PCIE_WMAC_INT_WMAC_MISC          BIT(0)
 #define AR934X_PCIE_WMAC_INT_WMAC_TX            BIT(1)
 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP          BIT(2)