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authorKelvin Cheung <keguang.zhang@gmail.com>2012-07-25 10:17:24 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-25 10:17:24 -0400
commitca585cf9fb818bfcfcac6968c2b242dcd0693b08 (patch)
treedd0d228367155b704e150bbfbbd56f7a6a6a00d1 /arch/mips/include/asm
parent2fa36399e63c911134f28b6878aada9b395c4209 (diff)
MIPS: Loongson 1B: Add board support
Adds basic platform devices for Loongson 1B, including serial port, ethernet, USB, RTC and interrupt handler. The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is built around a Synopsys IP Core. Use normal instead of enhanced descriptors. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4133/ Patchwork: https://patchwork.linux-mips.org/patch/4134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/mach-loongson1/irq.h73
-rw-r--r--arch/mips/include/asm/mach-loongson1/loongson1.h44
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h23
-rw-r--r--arch/mips/include/asm/mach-loongson1/prom.h24
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h33
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-wdt.h22
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h25
7 files changed, 244 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000000000000..da96ed42f733
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * IRQ mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_IRQ_H
14#define __ASM_MACH_LOONGSON1_IRQ_H
15
16/*
17 * CPU core Interrupt Numbers
18 */
19#define MIPS_CPU_IRQ_BASE 0
20#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
21
22#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
23#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
24#define INT0_IRQ MIPS_CPU_IRQ(2)
25#define INT1_IRQ MIPS_CPU_IRQ(3)
26#define INT2_IRQ MIPS_CPU_IRQ(4)
27#define INT3_IRQ MIPS_CPU_IRQ(5)
28#define INT4_IRQ MIPS_CPU_IRQ(6)
29#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
30
31#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
32
33/*
34 * INT0~3 Interrupt Numbers
35 */
36#define LS1X_IRQ_BASE MIPS_CPU_IRQS
37#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
38
39#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
40#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
41#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
42#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
43#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
44#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
45#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
46#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
47#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
48#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
49#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
50#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
51#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
52#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
53#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
54#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
55#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
56#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
57#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
58#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
59#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
60#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
61#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
62#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
63
64#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
65#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
66#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
67#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
68
69#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
70
71#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
72
73#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
new file mode 100644
index 000000000000..4e18e88cebbf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Register mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
14#define __ASM_MACH_LOONGSON1_LOONGSON1_H
15
16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17
18/* Loongson 1 Register Bases */
19#define LS1X_INTC_BASE 0x1fd01040
20#define LS1X_EHCI_BASE 0x1fe00000
21#define LS1X_OHCI_BASE 0x1fe08000
22#define LS1X_GMAC0_BASE 0x1fe10000
23#define LS1X_GMAC1_BASE 0x1fe20000
24
25#define LS1X_UART0_BASE 0x1fe40000
26#define LS1X_UART1_BASE 0x1fe44000
27#define LS1X_UART2_BASE 0x1fe48000
28#define LS1X_UART3_BASE 0x1fe4c000
29#define LS1X_CAN0_BASE 0x1fe50000
30#define LS1X_CAN1_BASE 0x1fe54000
31#define LS1X_I2C0_BASE 0x1fe58000
32#define LS1X_I2C1_BASE 0x1fe68000
33#define LS1X_I2C2_BASE 0x1fe70000
34#define LS1X_PWM_BASE 0x1fe5c000
35#define LS1X_WDT_BASE 0x1fe5c060
36#define LS1X_RTC_BASE 0x1fe64000
37#define LS1X_AC97_BASE 0x1fe74000
38#define LS1X_NAND_BASE 0x1fe78000
39#define LS1X_CLK_BASE 0x1fe78030
40
41#include <regs-clk.h>
42#include <regs-wdt.h>
43
44#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
new file mode 100644
index 000000000000..2f171617bade
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10
11#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
12#define __ASM_MACH_LOONGSON1_PLATFORM_H
13
14#include <linux/platform_device.h>
15
16extern struct platform_device ls1x_uart_device;
17extern struct platform_device ls1x_eth0_device;
18extern struct platform_device ls1x_ehci_device;
19extern struct platform_device ls1x_rtc_device;
20
21void ls1x_serial_setup(void);
22
23#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
new file mode 100644
index 000000000000..b871dc41b8d9
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __ASM_MACH_LOONGSON1_PROM_H
11#define __ASM_MACH_LOONGSON1_PROM_H
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16
17/* environment arguments from bootloader */
18extern unsigned long memsize, highmemsize;
19
20/* loongson-specific command line, env and memory initialization */
21extern char *prom_getenv(char *name);
22extern void __init prom_init_cmdline(void);
23
24#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 000000000000..8efa7fb9f73a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 Clock Register Definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
13#define __ASM_MACH_LOONGSON1_REGS_CLK_H
14
15#define LS1X_CLK_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
17
18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20
21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC (0x1f << 26)
24#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU (0x1f << 20)
26#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR (0x1f << 14)
28
29#define DIV_DC_SHIFT 26
30#define DIV_CPU_SHIFT 20
31#define DIV_DDR_SHIFT 14
32
33#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 000000000000..f897de68c527
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 watchdog register definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
13#define __ASM_MACH_LOONGSON1_REGS_WDT_H
14
15#define LS1X_WDT_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
17
18#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
19#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
20#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
21
22#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
new file mode 100644
index 000000000000..e3680a8fb349
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_LOONGSON1_WAR_H
9#define __ASM_MACH_LOONGSON1_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_LOONGSON1_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 13:58:41 -0500