MIPS: Loongson 1B: Add board support

Adds basic platform devices for Loongson 1B, including serial port,
ethernet, USB, RTC and interrupt handler.

The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is
built around a Synopsys IP Core.

Use normal instead of enhanced descriptors.

Thanks to Giuseppe for updating the normal descriptor in stmmac driver.
Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/4133/
Patchwork: https://patchwork.linux-mips.org/patch/4134/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 33 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 000000000000..8efa7fb9f73a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 Clock Register Definitions.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
+#define __ASM_MACH_LOONGSON1_REGS_CLK_H
+
+#define LS1X_CLK_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
+
+#define LS1X_CLK_PLL_FREQ               LS1X_CLK_REG(0x0)
+#define LS1X_CLK_PLL_DIV                LS1X_CLK_REG(0x4)
+
+/* Clock PLL Divisor Register Bits */
+#define DIV_DC_EN                       (0x1 << 31)
+#define DIV_DC                          (0x1f << 26)
+#define DIV_CPU_EN                      (0x1 << 25)
+#define DIV_CPU                         (0x1f << 20)
+#define DIV_DDR_EN                      (0x1 << 19)
+#define DIV_DDR                         (0x1f << 14)
+
+#define DIV_DC_SHIFT                    26
+#define DIV_CPU_SHIFT                   20
+#define DIV_DDR_SHIFT                   14
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */