Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next

4 files changed, 148 insertions, 48 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 8dec938af115..b86a1253a5bf 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -41,11 +41,37 @@
 #define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_RESET_SIZE       0x100
 
+#define AR71XX_PCI_MEM_BASE     0x10000000
+#define AR71XX_PCI_MEM_SIZE     0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS    0x10000000
+#define AR71XX_PCI_WIN1_OFFS    0x11000000
+#define AR71XX_PCI_WIN2_OFFS    0x12000000
+#define AR71XX_PCI_WIN3_OFFS    0x13000000
+#define AR71XX_PCI_WIN4_OFFS    0x14000000
+#define AR71XX_PCI_WIN5_OFFS    0x15000000
+#define AR71XX_PCI_WIN6_OFFS    0x16000000
+#define AR71XX_PCI_WIN7_OFFS    0x07000000
+
+#define AR71XX_PCI_CFG_BASE     \
+        (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE     0x100
+
 #define AR7240_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
 #define AR7240_USB_CTRL_SIZE    0x100
 #define AR7240_OHCI_BASE        0x1b000000
 #define AR7240_OHCI_SIZE        0x1000
 
+#define AR724X_PCI_MEM_BASE     0x10000000
+#define AR724X_PCI_MEM_SIZE     0x04000000
+
+#define AR724X_PCI_CFG_BASE     0x14000000
+#define AR724X_PCI_CFG_SIZE     0x1000
+#define AR724X_PCI_CRP_BASE     (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE     0x1000
+#define AR724X_PCI_CTRL_BASE    (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE    0x100
+
 #define AR724X_EHCI_BASE        0x1b000000
 #define AR724X_EHCI_SIZE        0x1000
 
@@ -68,6 +94,25 @@
 #define AR934X_SRIF_BASE        (AR71XX_APB_BASE + 0x00116000)
 #define AR934X_SRIF_SIZE        0x1000
 
+#define QCA955X_PCI_MEM_BASE0   0x10000000
+#define QCA955X_PCI_MEM_BASE1   0x12000000
+#define QCA955X_PCI_MEM_SIZE    0x02000000
+#define QCA955X_PCI_CFG_BASE0   0x14000000
+#define QCA955X_PCI_CFG_BASE1   0x16000000
+#define QCA955X_PCI_CFG_SIZE    0x1000
+#define QCA955X_PCI_CRP_BASE0   (AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1   (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE    0x1000
+#define QCA955X_PCI_CTRL_BASE0  (AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1  (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE   0x100
+
+#define QCA955X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE       0x20000
+#define QCA955X_EHCI0_BASE      0x1b000000
+#define QCA955X_EHCI1_BASE      0x1b400000
+#define QCA955X_EHCI_SIZE       0x1000
+
 /*
  * DDR_CTRL block
  */
@@ -199,6 +244,41 @@
 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL  BIT(21)
 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL  BIT(24)
 
+#define QCA955X_PLL_CPU_CONFIG_REG              0x00
+#define QCA955X_PLL_DDR_CONFIG_REG              0x04
+#define QCA955X_PLL_CLK_CTRL_REG                0x08
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT       6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK        0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT     12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK      0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT     19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK      0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT      0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK       0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT       10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK        0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT     16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK      0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT     23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK      0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS             BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS             BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS             BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT         5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT         10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT         15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK          0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL         BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL         BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL         BIT(24)
+
 /*
  * USB_CONFIG block
  */
@@ -238,6 +318,10 @@
 #define AR934X_RESET_REG_BOOTSTRAP              0xb0
 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   0xac
 
+#define QCA955X_RESET_REG_RESET_MODULE          0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP             0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS        0xac
+
 #define MISC_INT_ETHSW                  BIT(12)
 #define MISC_INT_TIMER4                 BIT(10)
 #define MISC_INT_TIMER3                 BIT(9)
@@ -315,6 +399,8 @@
 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
 #define AR934X_BOOTSTRAP_DDR1           BIT(0)
 
+#define QCA955X_BOOTSTRAP_REF_CLK_40    BIT(4)
+
 #define AR934X_PCIE_WMAC_INT_WMAC_MISC          BIT(0)
 #define AR934X_PCIE_WMAC_INT_WMAC_TX            BIT(1)
 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP          BIT(2)
@@ -333,6 +419,37 @@
          AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
          AR934X_PCIE_WMAC_INT_PCIE_RC3)
 
+#define QCA955X_EXT_INT_WMAC_MISC               BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX                 BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP               BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP               BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1                BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0           BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1           BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2           BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3           BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2                BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0           BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1           BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2           BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3           BIT(16)
+#define QCA955X_EXT_INT_USB1                    BIT(24)
+#define QCA955X_EXT_INT_USB2                    BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+        (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+         QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+        (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+         QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+         QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+        (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+         QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+         QCA955X_EXT_INT_PCIE_RC2_INT3)
+
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
 #define REV_ID_MAJOR_AR913X             0x00b0
@@ -344,6 +461,8 @@
 #define REV_ID_MAJOR_AR9341             0x0120
 #define REV_ID_MAJOR_AR9342             0x1120
 #define REV_ID_MAJOR_AR9344             0x2120
+#define REV_ID_MAJOR_QCA9556            0x0130
+#define REV_ID_MAJOR_QCA9558            0x1130
 
 #define AR71XX_REV_ID_MINOR_MASK        0x3
 #define AR71XX_REV_ID_MINOR_AR7130      0x0
@@ -364,6 +483,8 @@
 
 #define AR934X_REV_ID_REVISION_MASK     0xf
 
+#define QCA955X_REV_ID_REVISION_MASK    0xf
+
 /*
  * SPI block
  */
@@ -401,12 +522,15 @@
 #define AR71XX_GPIO_REG_INT_ENABLE      0x24
 #define AR71XX_GPIO_REG_FUNC            0x28
 
+#define AR934X_GPIO_REG_FUNC            0x6c
+
 #define AR71XX_GPIO_COUNT               16
 #define AR7240_GPIO_COUNT               18
 #define AR7241_GPIO_COUNT               20
 #define AR913X_GPIO_COUNT               22
 #define AR933X_GPIO_COUNT               30
 #define AR934X_GPIO_COUNT               23
+#define QCA955X_GPIO_COUNT              24
 
 /*
  * SRIF block
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 4f248c3d7b23..1557934aaca9 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -32,6 +32,8 @@ enum ath79_soc_type {
         ATH79_SOC_AR9341,
         ATH79_SOC_AR9342,
         ATH79_SOC_AR9344,
+        ATH79_SOC_QCA9556,
+        ATH79_SOC_QCA9558,
 };
 
 extern enum ath79_soc_type ath79_soc;
@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 }
 
+static inline int soc_is_qca9556(void)
+{
+        return ath79_soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+        return ath79_soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+        return soc_is_qca9556() || soc_is_qca9558();
+}
+
 extern void __iomem *ath79_ddr_base;
 extern void __iomem *ath79_pll_base;
 extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 0968f69e2018..5c9ca76a7ebf 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,13 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE       0
-#define NR_IRQS                 48
+#define NR_IRQS                 51
+
+#define ATH79_CPU_IRQ(_x)       (MIPS_CPU_IRQ_BASE + (_x))
 
 #define ATH79_MISC_IRQ_BASE     8
 #define ATH79_MISC_IRQ_COUNT    32
+#define ATH79_MISC_IRQ(_x)      (ATH79_MISC_IRQ_BASE + (_x))
 
 #define ATH79_PCI_IRQ_BASE      (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
 #define ATH79_PCI_IRQ_COUNT     6
@@ -23,25 +26,9 @@
 #define ATH79_IP2_IRQ_COUNT     2
 #define ATH79_IP2_IRQ(_x)       (ATH79_IP2_IRQ_BASE + (_x))
 
-#define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
-#define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
-#define ATH79_CPU_IRQ_GE0       (MIPS_CPU_IRQ_BASE + 4)
-#define ATH79_CPU_IRQ_GE1       (MIPS_CPU_IRQ_BASE + 5)
-#define ATH79_CPU_IRQ_MISC      (MIPS_CPU_IRQ_BASE + 6)
-#define ATH79_CPU_IRQ_TIMER     (MIPS_CPU_IRQ_BASE + 7)
-
-#define ATH79_MISC_IRQ_TIMER    (ATH79_MISC_IRQ_BASE + 0)
-#define ATH79_MISC_IRQ_ERROR    (ATH79_MISC_IRQ_BASE + 1)
-#define ATH79_MISC_IRQ_GPIO     (ATH79_MISC_IRQ_BASE + 2)
-#define ATH79_MISC_IRQ_UART     (ATH79_MISC_IRQ_BASE + 3)
-#define ATH79_MISC_IRQ_WDOG     (ATH79_MISC_IRQ_BASE + 4)
-#define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
-#define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
-#define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
-#define ATH79_MISC_IRQ_TIMER2   (ATH79_MISC_IRQ_BASE + 8)
-#define ATH79_MISC_IRQ_TIMER3   (ATH79_MISC_IRQ_BASE + 9)
-#define ATH79_MISC_IRQ_TIMER4   (ATH79_MISC_IRQ_BASE + 10)
-#define ATH79_MISC_IRQ_ETHSW    (ATH79_MISC_IRQ_BASE + 12)
+#define ATH79_IP3_IRQ_BASE      (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
+#define ATH79_IP3_IRQ_COUNT     3
+#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
 
 #include_next <irq.h>
 
diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h
deleted file mode 100644
index 7868f7fa028f..000000000000
--- a/arch/mips/include/asm/mach-ath79/pci.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  Atheros AR71XX/AR724X PCI support
- *
- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_ATH79_PCI_H
-#define __ASM_MACH_ATH79_PCI_H
-
-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
-int ar71xx_pcibios_init(void);
-#else
-static inline int ar71xx_pcibios_init(void) { return 0; }
-#endif
-
-#if defined(CONFIG_PCI_AR724X)
-int ar724x_pcibios_init(int irq);
-#else
-static inline int ar724x_pcibios_init(int irq) { return 0; }
-#endif
-
-#endif /* __ASM_MACH_ATH79_PCI_H */