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authorRalf Baechle <ralf@linux-mips.org>2013-02-21 06:51:33 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-21 06:51:33 -0500
commit8bfc245f9ad7bd4e461179e4e7852ef99b8b6144 (patch)
tree0ad091f645fbc8318634599d278966a53d3922ee /arch/mips/include
parent612663a974065c3445e641d046769fe4c55a6438 (diff)
parent535237cecab2b078114be712c67e89a0db61965f (diff)
Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/cpu-features.h7
-rw-r--r--arch/mips/include/asm/cpu.h5
-rw-r--r--arch/mips/include/asm/gic.h1
-rw-r--r--arch/mips/include/asm/hazards.h2
-rw-r--r--arch/mips/include/asm/irq_cpu.h6
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h124
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h17
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h27
-rw-r--r--arch/mips/include/asm/mach-ath79/pci.h28
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h (renamed from arch/mips/include/asm/mach-bcm47xx/nvram.h)13
-rw-r--r--arch/mips/include/asm/mach-lantiq/lantiq.h2
-rw-r--r--arch/mips/include/asm/mach-ralink/ralink_regs.h39
-rw-r--r--arch/mips/include/asm/mach-ralink/rt305x.h139
-rw-r--r--arch/mips/include/asm/mach-ralink/war.h25
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h28
-rw-r--r--arch/mips/include/asm/mipsregs.h311
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h79
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h12
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h48
-rw-r--r--arch/mips/include/asm/pci.h5
-rw-r--r--arch/mips/include/asm/time.h2
22 files changed, 651 insertions, 271 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1e83b24fa461..1a57e8b4d092 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -98,6 +98,9 @@
98#ifndef cpu_has_rixi 98#ifndef cpu_has_rixi
99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
100#endif 100#endif
101#ifndef cpu_has_mmips
102#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
103#endif
101#ifndef cpu_has_vtag_icache 104#ifndef cpu_has_vtag_icache
102#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
103#endif 106#endif
@@ -273,4 +276,8 @@
273#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 276#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
274#endif 277#endif
275 278
279#ifndef cpu_has_vz
280#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
281#endif
282
276#endif /* __ASM_CPU_FEATURES_H */ 283#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 9904697bd792..dd86ab205483 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -96,6 +96,7 @@
96#define PRID_IMP_1004K 0x9900 96#define PRID_IMP_1004K 0x9900
97#define PRID_IMP_1074K 0x9a00 97#define PRID_IMP_1074K 0x9a00
98#define PRID_IMP_M14KC 0x9c00 98#define PRID_IMP_M14KC 0x9c00
99#define PRID_IMP_M14KEC 0x9e00
99 100
100/* 101/*
101 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 102 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -264,6 +265,7 @@ enum cpu_type_enum {
264 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 265 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
265 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 266 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
266 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 267 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
268 CPU_M14KEC,
267 269
268 /* 270 /*
269 * MIPS64 class processors 271 * MIPS64 class processors
@@ -322,6 +324,7 @@ enum cpu_type_enum {
322#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 324#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
323#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 325#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
324#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 326#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
327#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
325 328
326/* 329/*
327 * CPU ASE encodings 330 * CPU ASE encodings
@@ -333,6 +336,6 @@ enum cpu_type_enum {
333#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 336#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
334#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 337#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
335#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 338#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
336 339#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
337 340
338#endif /* _ASM_CPU_H */ 341#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 61b06d7e7de1..bdc9786ab5a7 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -359,6 +359,7 @@ struct gic_shared_intr_map {
359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
360#define GIC_PIN_TO_VEC_OFFSET (1) 360#define GIC_PIN_TO_VEC_OFFSET (1)
361 361
362extern int gic_present;
362extern unsigned long _gic_base; 363extern unsigned long _gic_base;
363extern unsigned int gic_irq_base; 364extern unsigned int gic_irq_base;
364extern unsigned int gic_irq_flags[]; 365extern unsigned int gic_irq_flags[];
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 568544b6e856..44d6a5bde4a1 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -141,7 +141,7 @@ do { \
141 141
142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
144 defined(CONFIG_CPU_R5500) 144 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
145 145
146/* 146/*
147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index ef6a07cddb23..3f11fdb3ed8c 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
17extern void rm7k_cpu_irq_init(void); 17extern void rm7k_cpu_irq_init(void);
18extern void rm9k_cpu_irq_init(void); 18extern void rm9k_cpu_irq_init(void);
19 19
20#ifdef CONFIG_IRQ_DOMAIN
21struct device_node;
22extern int mips_cpu_intc_init(struct device_node *of_node,
23 struct device_node *parent);
24#endif
25
20#endif /* _ASM_IRQ_CPU_H */ 26#endif /* _ASM_IRQ_CPU_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 8dec938af115..b86a1253a5bf 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -41,11 +41,37 @@
41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42#define AR71XX_RESET_SIZE 0x100 42#define AR71XX_RESET_SIZE 0x100
43 43
44#define AR71XX_PCI_MEM_BASE 0x10000000
45#define AR71XX_PCI_MEM_SIZE 0x07000000
46
47#define AR71XX_PCI_WIN0_OFFS 0x10000000
48#define AR71XX_PCI_WIN1_OFFS 0x11000000
49#define AR71XX_PCI_WIN2_OFFS 0x12000000
50#define AR71XX_PCI_WIN3_OFFS 0x13000000
51#define AR71XX_PCI_WIN4_OFFS 0x14000000
52#define AR71XX_PCI_WIN5_OFFS 0x15000000
53#define AR71XX_PCI_WIN6_OFFS 0x16000000
54#define AR71XX_PCI_WIN7_OFFS 0x07000000
55
56#define AR71XX_PCI_CFG_BASE \
57 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
58#define AR71XX_PCI_CFG_SIZE 0x100
59
44#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 60#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
45#define AR7240_USB_CTRL_SIZE 0x100 61#define AR7240_USB_CTRL_SIZE 0x100
46#define AR7240_OHCI_BASE 0x1b000000 62#define AR7240_OHCI_BASE 0x1b000000
47#define AR7240_OHCI_SIZE 0x1000 63#define AR7240_OHCI_SIZE 0x1000
48 64
65#define AR724X_PCI_MEM_BASE 0x10000000
66#define AR724X_PCI_MEM_SIZE 0x04000000
67
68#define AR724X_PCI_CFG_BASE 0x14000000
69#define AR724X_PCI_CFG_SIZE 0x1000
70#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
71#define AR724X_PCI_CRP_SIZE 0x1000
72#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
73#define AR724X_PCI_CTRL_SIZE 0x100
74
49#define AR724X_EHCI_BASE 0x1b000000 75#define AR724X_EHCI_BASE 0x1b000000
50#define AR724X_EHCI_SIZE 0x1000 76#define AR724X_EHCI_SIZE 0x1000
51 77
@@ -68,6 +94,25 @@
68#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) 94#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
69#define AR934X_SRIF_SIZE 0x1000 95#define AR934X_SRIF_SIZE 0x1000
70 96
97#define QCA955X_PCI_MEM_BASE0 0x10000000
98#define QCA955X_PCI_MEM_BASE1 0x12000000
99#define QCA955X_PCI_MEM_SIZE 0x02000000
100#define QCA955X_PCI_CFG_BASE0 0x14000000
101#define QCA955X_PCI_CFG_BASE1 0x16000000
102#define QCA955X_PCI_CFG_SIZE 0x1000
103#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
104#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
105#define QCA955X_PCI_CRP_SIZE 0x1000
106#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
107#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
108#define QCA955X_PCI_CTRL_SIZE 0x100
109
110#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
111#define QCA955X_WMAC_SIZE 0x20000
112#define QCA955X_EHCI0_BASE 0x1b000000
113#define QCA955X_EHCI1_BASE 0x1b400000
114#define QCA955X_EHCI_SIZE 0x1000
115
71/* 116/*
72 * DDR_CTRL block 117 * DDR_CTRL block
73 */ 118 */
@@ -199,6 +244,41 @@
199#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 244#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
200#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 245#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
201 246
247#define QCA955X_PLL_CPU_CONFIG_REG 0x00
248#define QCA955X_PLL_DDR_CONFIG_REG 0x04
249#define QCA955X_PLL_CLK_CTRL_REG 0x08
250
251#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
252#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
253#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
254#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
255#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
256#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
257#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
258#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
259
260#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
261#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
262#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
263#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
264#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
265#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
266#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
267#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
268
269#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
270#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
271#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
272#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
273#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
274#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
275#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
276#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
277#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
278#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
279#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
280#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
281
202/* 282/*
203 * USB_CONFIG block 283 * USB_CONFIG block
204 */ 284 */
@@ -238,6 +318,10 @@
238#define AR934X_RESET_REG_BOOTSTRAP 0xb0 318#define AR934X_RESET_REG_BOOTSTRAP 0xb0
239#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 319#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
240 320
321#define QCA955X_RESET_REG_RESET_MODULE 0x1c
322#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
323#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
324
241#define MISC_INT_ETHSW BIT(12) 325#define MISC_INT_ETHSW BIT(12)
242#define MISC_INT_TIMER4 BIT(10) 326#define MISC_INT_TIMER4 BIT(10)
243#define MISC_INT_TIMER3 BIT(9) 327#define MISC_INT_TIMER3 BIT(9)
@@ -315,6 +399,8 @@
315#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 399#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
316#define AR934X_BOOTSTRAP_DDR1 BIT(0) 400#define AR934X_BOOTSTRAP_DDR1 BIT(0)
317 401
402#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
403
318#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 404#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
319#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 405#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
320#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 406#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
@@ -333,6 +419,37 @@
333 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 419 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
334 AR934X_PCIE_WMAC_INT_PCIE_RC3) 420 AR934X_PCIE_WMAC_INT_PCIE_RC3)
335 421
422#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
423#define QCA955X_EXT_INT_WMAC_TX BIT(1)
424#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
425#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
426#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
427#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
428#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
429#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
430#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
431#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
432#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
433#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
434#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
435#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
436#define QCA955X_EXT_INT_USB1 BIT(24)
437#define QCA955X_EXT_INT_USB2 BIT(28)
438
439#define QCA955X_EXT_INT_WMAC_ALL \
440 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
441 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
442
443#define QCA955X_EXT_INT_PCIE_RC1_ALL \
444 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
445 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
446 QCA955X_EXT_INT_PCIE_RC1_INT3)
447
448#define QCA955X_EXT_INT_PCIE_RC2_ALL \
449 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
450 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
451 QCA955X_EXT_INT_PCIE_RC2_INT3)
452
336#define REV_ID_MAJOR_MASK 0xfff0 453#define REV_ID_MAJOR_MASK 0xfff0
337#define REV_ID_MAJOR_AR71XX 0x00a0 454#define REV_ID_MAJOR_AR71XX 0x00a0
338#define REV_ID_MAJOR_AR913X 0x00b0 455#define REV_ID_MAJOR_AR913X 0x00b0
@@ -344,6 +461,8 @@
344#define REV_ID_MAJOR_AR9341 0x0120 461#define REV_ID_MAJOR_AR9341 0x0120
345#define REV_ID_MAJOR_AR9342 0x1120 462#define REV_ID_MAJOR_AR9342 0x1120
346#define REV_ID_MAJOR_AR9344 0x2120 463#define REV_ID_MAJOR_AR9344 0x2120
464#define REV_ID_MAJOR_QCA9556 0x0130
465#define REV_ID_MAJOR_QCA9558 0x1130
347 466
348#define AR71XX_REV_ID_MINOR_MASK 0x3 467#define AR71XX_REV_ID_MINOR_MASK 0x3
349#define AR71XX_REV_ID_MINOR_AR7130 0x0 468#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -364,6 +483,8 @@
364 483
365#define AR934X_REV_ID_REVISION_MASK 0xf 484#define AR934X_REV_ID_REVISION_MASK 0xf
366 485
486#define QCA955X_REV_ID_REVISION_MASK 0xf
487
367/* 488/*
368 * SPI block 489 * SPI block
369 */ 490 */
@@ -401,12 +522,15 @@
401#define AR71XX_GPIO_REG_INT_ENABLE 0x24 522#define AR71XX_GPIO_REG_INT_ENABLE 0x24
402#define AR71XX_GPIO_REG_FUNC 0x28 523#define AR71XX_GPIO_REG_FUNC 0x28
403 524
525#define AR934X_GPIO_REG_FUNC 0x6c
526
404#define AR71XX_GPIO_COUNT 16 527#define AR71XX_GPIO_COUNT 16
405#define AR7240_GPIO_COUNT 18 528#define AR7240_GPIO_COUNT 18
406#define AR7241_GPIO_COUNT 20 529#define AR7241_GPIO_COUNT 20
407#define AR913X_GPIO_COUNT 22 530#define AR913X_GPIO_COUNT 22
408#define AR933X_GPIO_COUNT 30 531#define AR933X_GPIO_COUNT 30
409#define AR934X_GPIO_COUNT 23 532#define AR934X_GPIO_COUNT 23
533#define QCA955X_GPIO_COUNT 24
410 534
411/* 535/*
412 * SRIF block 536 * SRIF block
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 4f248c3d7b23..1557934aaca9 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -32,6 +32,8 @@ enum ath79_soc_type {
32 ATH79_SOC_AR9341, 32 ATH79_SOC_AR9341,
33 ATH79_SOC_AR9342, 33 ATH79_SOC_AR9342,
34 ATH79_SOC_AR9344, 34 ATH79_SOC_AR9344,
35 ATH79_SOC_QCA9556,
36 ATH79_SOC_QCA9558,
35}; 37};
36 38
37extern enum ath79_soc_type ath79_soc; 39extern enum ath79_soc_type ath79_soc;
@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
98 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); 100 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
99} 101}
100 102
103static inline int soc_is_qca9556(void)
104{
105 return ath79_soc == ATH79_SOC_QCA9556;
106}
107
108static inline int soc_is_qca9558(void)
109{
110 return ath79_soc == ATH79_SOC_QCA9558;
111}
112
113static inline int soc_is_qca955x(void)
114{
115 return soc_is_qca9556() || soc_is_qca9558();
116}
117
101extern void __iomem *ath79_ddr_base; 118extern void __iomem *ath79_ddr_base;
102extern void __iomem *ath79_pll_base; 119extern void __iomem *ath79_pll_base;
103extern void __iomem *ath79_reset_base; 120extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 0968f69e2018..5c9ca76a7ebf 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,13 @@
10#define __ASM_MACH_ATH79_IRQ_H 10#define __ASM_MACH_ATH79_IRQ_H
11 11
12#define MIPS_CPU_IRQ_BASE 0 12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 48 13#define NR_IRQS 51
14
15#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
14 16
15#define ATH79_MISC_IRQ_BASE 8 17#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 32 18#define ATH79_MISC_IRQ_COUNT 32
19#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
17 20
18#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) 21#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
19#define ATH79_PCI_IRQ_COUNT 6 22#define ATH79_PCI_IRQ_COUNT 6
@@ -23,25 +26,9 @@
23#define ATH79_IP2_IRQ_COUNT 2 26#define ATH79_IP2_IRQ_COUNT 2
24#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) 27#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
25 28
26#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) 29#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
27#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) 30#define ATH79_IP3_IRQ_COUNT 3
28#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) 31#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
29#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
30#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
31#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
32
33#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
34#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
35#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
36#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
37#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
38#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
39#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
40#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
41#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
42#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
43#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
44#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
45 32
46#include_next <irq.h> 33#include_next <irq.h>
47 34
diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h
deleted file mode 100644
index 7868f7fa028f..000000000000
--- a/arch/mips/include/asm/mach-ath79/pci.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Atheros AR71XX/AR724X PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#ifndef __ASM_MACH_ATH79_PCI_H
14#define __ASM_MACH_ATH79_PCI_H
15
16#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
17int ar71xx_pcibios_init(void);
18#else
19static inline int ar71xx_pcibios_init(void) { return 0; }
20#endif
21
22#if defined(CONFIG_PCI_AR724X)
23int ar724x_pcibios_init(int irq);
24#else
25static inline int ar724x_pcibios_init(int irq) { return 0; }
26#endif
27
28#endif /* __ASM_MACH_ATH79_PCI_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
index 69ef3efe06e7..b8e7be8f34dd 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
@@ -8,8 +8,8 @@
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10 10
11#ifndef __NVRAM_H 11#ifndef __BCM47XX_NVRAM_H
12#define __NVRAM_H 12#define __BCM47XX_NVRAM_H
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
@@ -32,12 +32,9 @@ struct nvram_header {
32#define NVRAM_MAX_VALUE_LEN 255 32#define NVRAM_MAX_VALUE_LEN 255
33#define NVRAM_MAX_PARAM_LEN 64 33#define NVRAM_MAX_PARAM_LEN 64
34 34
35#define NVRAM_ERR_INV_PARAM -8 35extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
36#define NVRAM_ERR_ENVNOTFOUND -9
37 36
38extern int nvram_getenv(char *name, char *val, size_t val_len); 37static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
39
40static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
41{ 38{
42 if (strchr(buf, ':')) 39 if (strchr(buf, ':'))
43 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], 40 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
@@ -51,4 +48,4 @@ static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
51 printk(KERN_WARNING "Can not parse mac address: %s\n", buf); 48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
52} 49}
53 50
54#endif 51#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 5e8a6e965756..f196cceb7322 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
34extern void ltq_disable_irq(struct irq_data *data); 34extern void ltq_disable_irq(struct irq_data *data);
35extern void ltq_mask_and_ack_irq(struct irq_data *data); 35extern void ltq_mask_and_ack_irq(struct irq_data *data);
36extern void ltq_enable_irq(struct irq_data *data); 36extern void ltq_enable_irq(struct irq_data *data);
37extern int ltq_eiu_get_irq(int exin);
37 38
38/* clock handling */ 39/* clock handling */
39extern int clk_activate(struct clk *clk); 40extern int clk_activate(struct clk *clk);
@@ -41,6 +42,7 @@ extern void clk_deactivate(struct clk *clk);
41extern struct clk *clk_get_cpu(void); 42extern struct clk *clk_get_cpu(void);
42extern struct clk *clk_get_fpi(void); 43extern struct clk *clk_get_fpi(void);
43extern struct clk *clk_get_io(void); 44extern struct clk *clk_get_io(void);
45extern struct clk *clk_get_ppe(void);
44 46
45/* find out what bootsource we have */ 47/* find out what bootsource we have */
46extern unsigned char ltq_boot_select(void); 48extern unsigned char ltq_boot_select(void);
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
new file mode 100644
index 000000000000..5a508f9f9432
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -0,0 +1,39 @@
1/*
2 * Ralink SoC register definitions
3 *
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#ifndef _RALINK_REGS_H_
14#define _RALINK_REGS_H_
15
16extern __iomem void *rt_sysc_membase;
17extern __iomem void *rt_memc_membase;
18
19static inline void rt_sysc_w32(u32 val, unsigned reg)
20{
21 __raw_writel(val, rt_sysc_membase + reg);
22}
23
24static inline u32 rt_sysc_r32(unsigned reg)
25{
26 return __raw_readl(rt_sysc_membase + reg);
27}
28
29static inline void rt_memc_w32(u32 val, unsigned reg)
30{
31 __raw_writel(val, rt_memc_membase + reg);
32}
33
34static inline u32 rt_memc_r32(unsigned reg)
35{
36 return __raw_readl(rt_memc_membase + reg);
37}
38
39#endif /* _RALINK_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
new file mode 100644
index 000000000000..7d344f2d7d0a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -0,0 +1,139 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#ifndef _RT305X_REGS_H_
14#define _RT305X_REGS_H_
15
16enum rt305x_soc_type {
17 RT305X_SOC_UNKNOWN = 0,
18 RT305X_SOC_RT3050,
19 RT305X_SOC_RT3052,
20 RT305X_SOC_RT3350,
21 RT305X_SOC_RT3352,
22 RT305X_SOC_RT5350,
23};
24
25extern enum rt305x_soc_type rt305x_soc;
26
27static inline int soc_is_rt3050(void)
28{
29 return rt305x_soc == RT305X_SOC_RT3050;
30}
31
32static inline int soc_is_rt3052(void)
33{
34 return rt305x_soc == RT305X_SOC_RT3052;
35}
36
37static inline int soc_is_rt305x(void)
38{
39 return soc_is_rt3050() || soc_is_rt3052();
40}
41
42static inline int soc_is_rt3350(void)
43{
44 return rt305x_soc == RT305X_SOC_RT3350;
45}
46
47static inline int soc_is_rt3352(void)
48{
49 return rt305x_soc == RT305X_SOC_RT3352;
50}
51
52static inline int soc_is_rt5350(void)
53{
54 return rt305x_soc == RT305X_SOC_RT5350;
55}
56
57#define RT305X_SYSC_BASE 0x10000000
58
59#define SYSC_REG_CHIP_NAME0 0x00
60#define SYSC_REG_CHIP_NAME1 0x04
61#define SYSC_REG_CHIP_ID 0x0c
62#define SYSC_REG_SYSTEM_CONFIG 0x10
63
64#define RT3052_CHIP_NAME0 0x30335452
65#define RT3052_CHIP_NAME1 0x20203235
66
67#define RT3350_CHIP_NAME0 0x33335452
68#define RT3350_CHIP_NAME1 0x20203035
69
70#define RT3352_CHIP_NAME0 0x33335452
71#define RT3352_CHIP_NAME1 0x20203235
72
73#define RT5350_CHIP_NAME0 0x33355452
74#define RT5350_CHIP_NAME1 0x20203035
75
76#define CHIP_ID_ID_MASK 0xff
77#define CHIP_ID_ID_SHIFT 8
78#define CHIP_ID_REV_MASK 0xff
79
80#define RT305X_SYSCFG_CPUCLK_SHIFT 18
81#define RT305X_SYSCFG_CPUCLK_MASK 0x1
82#define RT305X_SYSCFG_CPUCLK_LOW 0x0
83#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
84
85#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
86#define RT305X_SYSCFG_CPUCLK_MASK 0x1
87#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
88
89#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
90#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
91#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
92#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
93
94#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
95#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
96#define RT5350_SYSCFG0_CPUCLK_360 0x0
97#define RT5350_SYSCFG0_CPUCLK_320 0x2
98#define RT5350_SYSCFG0_CPUCLK_300 0x3
99
100/* multi function gpio pins */
101#define RT305X_GPIO_I2C_SD 1
102#define RT305X_GPIO_I2C_SCLK 2
103#define RT305X_GPIO_SPI_EN 3
104#define RT305X_GPIO_SPI_CLK 4
105/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
106#define RT305X_GPIO_7 7
107#define RT305X_GPIO_10 10
108#define RT305X_GPIO_14 14
109#define RT305X_GPIO_UART1_TXD 15
110#define RT305X_GPIO_UART1_RXD 16
111#define RT305X_GPIO_JTAG_TDO 17
112#define RT305X_GPIO_JTAG_TDI 18
113#define RT305X_GPIO_MDIO_MDC 22
114#define RT305X_GPIO_MDIO_MDIO 23
115#define RT305X_GPIO_SDRAM_MD16 24
116#define RT305X_GPIO_SDRAM_MD31 39
117#define RT305X_GPIO_GE0_TXD0 40
118#define RT305X_GPIO_GE0_RXCLK 51
119
120#define RT305X_GPIO_MODE_I2C BIT(0)
121#define RT305X_GPIO_MODE_SPI BIT(1)
122#define RT305X_GPIO_MODE_UART0_SHIFT 2
123#define RT305X_GPIO_MODE_UART0_MASK 0x7
124#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
125#define RT305X_GPIO_MODE_UARTF 0x0
126#define RT305X_GPIO_MODE_PCM_UARTF 0x1
127#define RT305X_GPIO_MODE_PCM_I2S 0x2
128#define RT305X_GPIO_MODE_I2S_UARTF 0x3
129#define RT305X_GPIO_MODE_PCM_GPIO 0x4
130#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
131#define RT305X_GPIO_MODE_GPIO_I2S 0x6
132#define RT305X_GPIO_MODE_GPIO 0x7
133#define RT305X_GPIO_MODE_UART1 BIT(5)
134#define RT305X_GPIO_MODE_JTAG BIT(6)
135#define RT305X_GPIO_MODE_MDIO BIT(7)
136#define RT305X_GPIO_MODE_SDRAM BIT(8)
137#define RT305X_GPIO_MODE_RGMII BIT(9)
138
139#endif
diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h
new file mode 100644
index 000000000000..a7b712cf2d28
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_RALINK_WAR_H
9#define __ASM_MACH_RALINK_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_RALINK_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 1465b1193b12..44a09a64160a 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -1,21 +1,14 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * This file is subject to the terms and conditions of the GNU General Public
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * License. See the file "COPYING" in the main directory of this archive
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details. 4 * for more details.
13 * 5 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Defines of the MIPS boards specific address-MAP, registers, etc. 6 * Defines of the MIPS boards specific address-MAP, registers, etc.
7 *
8 * Copyright (C) 2000,2012 MIPS Technologies, Inc.
9 * All rights reserved.
10 * Authors: Carsten Langgaard <carstenl@mips.com>
11 * Steven J. Hill <sjhill@mips.com>
19 */ 12 */
20#ifndef __ASM_MIPS_BOARDS_GENERIC_H 13#ifndef __ASM_MIPS_BOARDS_GENERIC_H
21#define __ASM_MIPS_BOARDS_GENERIC_H 14#define __ASM_MIPS_BOARDS_GENERIC_H
@@ -30,13 +23,6 @@
30#define ASCII_DISPLAY_WORD_BASE 0x1f000410 23#define ASCII_DISPLAY_WORD_BASE 0x1f000410
31#define ASCII_DISPLAY_POS_BASE 0x1f000418 24#define ASCII_DISPLAY_POS_BASE 0x1f000418
32 25
33
34/*
35 * Yamon Prom print address.
36 */
37#define YAMON_PROM_PRINT_ADDR 0x1fc00504
38
39
40/* 26/*
41 * Reset register. 27 * Reset register.
42 */ 28 */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2145162674b9..12b70c25906a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -595,6 +595,8 @@
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
598 600
599#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 601#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
600#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 602#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
@@ -1158,36 +1160,26 @@ do { \
1158 __res; \ 1160 __res; \
1159}) 1161})
1160 1162
1163#ifdef HAVE_AS_DSP
1161#define rddsp(mask) \ 1164#define rddsp(mask) \
1162({ \ 1165({ \
1163 unsigned int __res; \ 1166 unsigned int __dspctl; \
1164 \ 1167 \
1165 __asm__ __volatile__( \ 1168 __asm__ __volatile__( \
1166 " .set push \n" \ 1169 " rddsp %0, %x1 \n" \
1167 " .set noat \n" \ 1170 : "=r" (__dspctl) \
1168 " # rddsp $1, %x1 \n" \
1169 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1170 " move %0, $1 \n" \
1171 " .set pop \n" \
1172 : "=r" (__res) \
1173 : "i" (mask)); \ 1171 : "i" (mask)); \
1174 __res; \ 1172 __dspctl; \
1175}) 1173})
1176 1174
1177#define wrdsp(val, mask) \ 1175#define wrdsp(val, mask) \
1178do { \ 1176do { \
1179 __asm__ __volatile__( \ 1177 __asm__ __volatile__( \
1180 " .set push \n" \ 1178 " wrdsp %0, %x1 \n" \
1181 " .set noat \n" \
1182 " move $1, %0 \n" \
1183 " # wrdsp $1, %x1 \n" \
1184 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1185 " .set pop \n" \
1186 : \ 1179 : \
1187 : "r" (val), "i" (mask)); \ 1180 : "r" (val), "i" (mask)); \
1188} while (0) 1181} while (0)
1189 1182
1190#if 0 /* Need DSP ASE capable assembler ... */
1191#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1183#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1192#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1184#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1193#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1185#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
@@ -1210,230 +1202,177 @@ do { \
1210 1202
1211#else 1203#else
1212 1204
1213#define mfhi0() \ 1205#ifdef CONFIG_CPU_MICROMIPS
1214({ \ 1206#define rddsp(mask) \
1215 unsigned long __treg; \
1216 \
1217 __asm__ __volatile__( \
1218 " .set push \n" \
1219 " .set noat \n" \
1220 " # mfhi %0, $ac0 \n" \
1221 " .word 0x00000810 \n" \
1222 " move %0, $1 \n" \
1223 " .set pop \n" \
1224 : "=r" (__treg)); \
1225 __treg; \
1226})
1227
1228#define mfhi1() \
1229({ \
1230 unsigned long __treg; \
1231 \
1232 __asm__ __volatile__( \
1233 " .set push \n" \
1234 " .set noat \n" \
1235 " # mfhi %0, $ac1 \n" \
1236 " .word 0x00200810 \n" \
1237 " move %0, $1 \n" \
1238 " .set pop \n" \
1239 : "=r" (__treg)); \
1240 __treg; \
1241})
1242
1243#define mfhi2() \
1244({ \
1245 unsigned long __treg; \
1246 \
1247 __asm__ __volatile__( \
1248 " .set push \n" \
1249 " .set noat \n" \
1250 " # mfhi %0, $ac2 \n" \
1251 " .word 0x00400810 \n" \
1252 " move %0, $1 \n" \
1253 " .set pop \n" \
1254 : "=r" (__treg)); \
1255 __treg; \
1256})
1257
1258#define mfhi3() \
1259({ \
1260 unsigned long __treg; \
1261 \
1262 __asm__ __volatile__( \
1263 " .set push \n" \
1264 " .set noat \n" \
1265 " # mfhi %0, $ac3 \n" \
1266 " .word 0x00600810 \n" \
1267 " move %0, $1 \n" \
1268 " .set pop \n" \
1269 : "=r" (__treg)); \
1270 __treg; \
1271})
1272
1273#define mflo0() \
1274({ \
1275 unsigned long __treg; \
1276 \
1277 __asm__ __volatile__( \
1278 " .set push \n" \
1279 " .set noat \n" \
1280 " # mflo %0, $ac0 \n" \
1281 " .word 0x00000812 \n" \
1282 " move %0, $1 \n" \
1283 " .set pop \n" \
1284 : "=r" (__treg)); \
1285 __treg; \
1286})
1287
1288#define mflo1() \
1289({ \
1290 unsigned long __treg; \
1291 \
1292 __asm__ __volatile__( \
1293 " .set push \n" \
1294 " .set noat \n" \
1295 " # mflo %0, $ac1 \n" \
1296 " .word 0x00200812 \n" \
1297 " move %0, $1 \n" \
1298 " .set pop \n" \
1299 : "=r" (__treg)); \
1300 __treg; \
1301})
1302
1303#define mflo2() \
1304({ \
1305 unsigned long __treg; \
1306 \
1307 __asm__ __volatile__( \
1308 " .set push \n" \
1309 " .set noat \n" \
1310 " # mflo %0, $ac2 \n" \
1311 " .word 0x00400812 \n" \
1312 " move %0, $1 \n" \
1313 " .set pop \n" \
1314 : "=r" (__treg)); \
1315 __treg; \
1316})
1317
1318#define mflo3() \
1319({ \ 1207({ \
1320 unsigned long __treg; \ 1208 unsigned int __res; \
1321 \ 1209 \
1322 __asm__ __volatile__( \ 1210 __asm__ __volatile__( \
1323 " .set push \n" \
1324 " .set noat \n" \
1325 " # mflo %0, $ac3 \n" \
1326 " .word 0x00600812 \n" \
1327 " move %0, $1 \n" \
1328 " .set pop \n" \
1329 : "=r" (__treg)); \
1330 __treg; \
1331})
1332
1333#define mthi0(x) \
1334do { \
1335 __asm__ __volatile__( \
1336 " .set push \n" \ 1211 " .set push \n" \
1337 " .set noat \n" \ 1212 " .set noat \n" \
1338 " move $1, %0 \n" \ 1213 " # rddsp $1, %x1 \n" \
1339 " # mthi $1, $ac0 \n" \ 1214 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1340 " .word 0x00200011 \n" \ 1215 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1216 " move %0, $1 \n" \
1341 " .set pop \n" \ 1217 " .set pop \n" \
1342 : \ 1218 : "=r" (__res) \
1343 : "r" (x)); \ 1219 : "i" (mask)); \
1344} while (0) 1220 __res; \
1221})
1345 1222
1346#define mthi1(x) \ 1223#define wrdsp(val, mask) \
1347do { \ 1224do { \
1348 __asm__ __volatile__( \ 1225 __asm__ __volatile__( \
1349 " .set push \n" \ 1226 " .set push \n" \
1350 " .set noat \n" \ 1227 " .set noat \n" \
1351 " move $1, %0 \n" \ 1228 " move $1, %0 \n" \
1352 " # mthi $1, $ac1 \n" \ 1229 " # wrdsp $1, %x1 \n" \
1353 " .word 0x00200811 \n" \ 1230 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1231 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1354 " .set pop \n" \ 1232 " .set pop \n" \
1355 : \ 1233 : \
1356 : "r" (x)); \ 1234 : "r" (val), "i" (mask)); \
1357} while (0) 1235} while (0)
1358 1236
1359#define mthi2(x) \ 1237#define _umips_dsp_mfxxx(ins) \
1360do { \ 1238({ \
1239 unsigned long __treg; \
1240 \
1361 __asm__ __volatile__( \ 1241 __asm__ __volatile__( \
1362 " .set push \n" \ 1242 " .set push \n" \
1363 " .set noat \n" \ 1243 " .set noat \n" \
1364 " move $1, %0 \n" \ 1244 " .hword 0x0001 \n" \
1365 " # mthi $1, $ac2 \n" \ 1245 " .hword %x1 \n" \
1366 " .word 0x00201011 \n" \ 1246 " move %0, $1 \n" \
1367 " .set pop \n" \ 1247 " .set pop \n" \
1368 : \ 1248 : "=r" (__treg) \
1369 : "r" (x)); \ 1249 : "i" (ins)); \
1370} while (0) 1250 __treg; \
1251})
1371 1252
1372#define mthi3(x) \ 1253#define _umips_dsp_mtxxx(val, ins) \
1373do { \ 1254do { \
1374 __asm__ __volatile__( \ 1255 __asm__ __volatile__( \
1375 " .set push \n" \ 1256 " .set push \n" \
1376 " .set noat \n" \ 1257 " .set noat \n" \
1377 " move $1, %0 \n" \ 1258 " move $1, %0 \n" \
1378 " # mthi $1, $ac3 \n" \ 1259 " .hword 0x0001 \n" \
1379 " .word 0x00201811 \n" \ 1260 " .hword %x1 \n" \
1380 " .set pop \n" \ 1261 " .set pop \n" \
1381 : \ 1262 : \
1382 : "r" (x)); \ 1263 : "r" (val), "i" (ins)); \
1383} while (0) 1264} while (0)
1384 1265
1385#define mtlo0(x) \ 1266#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1386do { \ 1267#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1268
1269#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1270#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1271
1272#define mflo0() _umips_dsp_mflo(0)
1273#define mflo1() _umips_dsp_mflo(1)
1274#define mflo2() _umips_dsp_mflo(2)
1275#define mflo3() _umips_dsp_mflo(3)
1276
1277#define mfhi0() _umips_dsp_mfhi(0)
1278#define mfhi1() _umips_dsp_mfhi(1)
1279#define mfhi2() _umips_dsp_mfhi(2)
1280#define mfhi3() _umips_dsp_mfhi(3)
1281
1282#define mtlo0(x) _umips_dsp_mtlo(x, 0)
1283#define mtlo1(x) _umips_dsp_mtlo(x, 1)
1284#define mtlo2(x) _umips_dsp_mtlo(x, 2)
1285#define mtlo3(x) _umips_dsp_mtlo(x, 3)
1286
1287#define mthi0(x) _umips_dsp_mthi(x, 0)
1288#define mthi1(x) _umips_dsp_mthi(x, 1)
1289#define mthi2(x) _umips_dsp_mthi(x, 2)
1290#define mthi3(x) _umips_dsp_mthi(x, 3)
1291
1292#else /* !CONFIG_CPU_MICROMIPS */
1293#define rddsp(mask) \
1294({ \
1295 unsigned int __res; \
1296 \
1387 __asm__ __volatile__( \ 1297 __asm__ __volatile__( \
1388 " .set push \n" \ 1298 " .set push \n" \
1389 " .set noat \n" \ 1299 " .set noat \n" \
1390 " move $1, %0 \n" \ 1300 " # rddsp $1, %x1 \n" \
1391 " # mtlo $1, $ac0 \n" \ 1301 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1392 " .word 0x00200013 \n" \ 1302 " move %0, $1 \n" \
1393 " .set pop \n" \ 1303 " .set pop \n" \
1394 : \ 1304 : "=r" (__res) \
1395 : "r" (x)); \ 1305 : "i" (mask)); \
1396} while (0) 1306 __res; \
1307})
1397 1308
1398#define mtlo1(x) \ 1309#define wrdsp(val, mask) \
1399do { \ 1310do { \
1400 __asm__ __volatile__( \ 1311 __asm__ __volatile__( \
1401 " .set push \n" \ 1312 " .set push \n" \
1402 " .set noat \n" \ 1313 " .set noat \n" \
1403 " move $1, %0 \n" \ 1314 " move $1, %0 \n" \
1404 " # mtlo $1, $ac1 \n" \ 1315 " # wrdsp $1, %x1 \n" \
1405 " .word 0x00200813 \n" \ 1316 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1406 " .set pop \n" \ 1317 " .set pop \n" \
1407 : \ 1318 : \
1408 : "r" (x)); \ 1319 : "r" (val), "i" (mask)); \
1409} while (0) 1320} while (0)
1410 1321
1411#define mtlo2(x) \ 1322#define _dsp_mfxxx(ins) \
1412do { \ 1323({ \
1324 unsigned long __treg; \
1325 \
1413 __asm__ __volatile__( \ 1326 __asm__ __volatile__( \
1414 " .set push \n" \ 1327 " .set push \n" \
1415 " .set noat \n" \ 1328 " .set noat \n" \
1416 " move $1, %0 \n" \ 1329 " .word (0x00000810 | %1) \n" \
1417 " # mtlo $1, $ac2 \n" \ 1330 " move %0, $1 \n" \
1418 " .word 0x00201013 \n" \
1419 " .set pop \n" \ 1331 " .set pop \n" \
1420 : \ 1332 : "=r" (__treg) \
1421 : "r" (x)); \ 1333 : "i" (ins)); \
1422} while (0) 1334 __treg; \
1335})
1423 1336
1424#define mtlo3(x) \ 1337#define _dsp_mtxxx(val, ins) \
1425do { \ 1338do { \
1426 __asm__ __volatile__( \ 1339 __asm__ __volatile__( \
1427 " .set push \n" \ 1340 " .set push \n" \
1428 " .set noat \n" \ 1341 " .set noat \n" \
1429 " move $1, %0 \n" \ 1342 " move $1, %0 \n" \
1430 " # mtlo $1, $ac3 \n" \ 1343 " .word (0x00200011 | %1) \n" \
1431 " .word 0x00201813 \n" \
1432 " .set pop \n" \ 1344 " .set pop \n" \
1433 : \ 1345 : \
1434 : "r" (x)); \ 1346 : "r" (val), "i" (ins)); \
1435} while (0) 1347} while (0)
1436 1348
1349#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1350#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1351
1352#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1353#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1354
1355#define mflo0() _dsp_mflo(0)
1356#define mflo1() _dsp_mflo(1)
1357#define mflo2() _dsp_mflo(2)
1358#define mflo3() _dsp_mflo(3)
1359
1360#define mfhi0() _dsp_mfhi(0)
1361#define mfhi1() _dsp_mfhi(1)
1362#define mfhi2() _dsp_mfhi(2)
1363#define mfhi3() _dsp_mfhi(3)
1364
1365#define mtlo0(x) _dsp_mtlo(x, 0)
1366#define mtlo1(x) _dsp_mtlo(x, 1)
1367#define mtlo2(x) _dsp_mtlo(x, 2)
1368#define mtlo3(x) _dsp_mtlo(x, 3)
1369
1370#define mthi0(x) _dsp_mthi(x, 0)
1371#define mthi1(x) _dsp_mthi(x, 1)
1372#define mthi2(x) _dsp_mthi(x, 2)
1373#define mthi3(x) _dsp_mthi(x, 3)
1374
1375#endif /* CONFIG_CPU_MICROMIPS */
1437#endif 1376#endif
1438 1377
1439/* 1378/*
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 8ffae43107e6..8ad2e0f81719 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -68,6 +68,85 @@ do { \
68 __write_64bit_c0_register($9, 7, (val)); \ 68 __write_64bit_c0_register($9, 7, (val)); \
69} while (0) 69} while (0)
70 70
71/*
72 * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
73 * standard functions will be very inefficient. This provides
74 * optimized functions for the normal operations on the registers.
75 *
76 * Call with interrupts disabled.
77 */
78static inline void ack_c0_eirr(int irq)
79{
80 __asm__ __volatile__(
81 ".set push\n\t"
82 ".set mips64\n\t"
83 ".set noat\n\t"
84 "li $1, 1\n\t"
85 "dsllv $1, $1, %0\n\t"
86 "dmtc0 $1, $9, 6\n\t"
87 ".set pop"
88 : : "r" (irq));
89}
90
91static inline void set_c0_eimr(int irq)
92{
93 __asm__ __volatile__(
94 ".set push\n\t"
95 ".set mips64\n\t"
96 ".set noat\n\t"
97 "li $1, 1\n\t"
98 "dsllv %0, $1, %0\n\t"
99 "dmfc0 $1, $9, 7\n\t"
100 "or $1, %0\n\t"
101 "dmtc0 $1, $9, 7\n\t"
102 ".set pop"
103 : "+r" (irq));
104}
105
106static inline void clear_c0_eimr(int irq)
107{
108 __asm__ __volatile__(
109 ".set push\n\t"
110 ".set mips64\n\t"
111 ".set noat\n\t"
112 "li $1, 1\n\t"
113 "dsllv %0, $1, %0\n\t"
114 "dmfc0 $1, $9, 7\n\t"
115 "or $1, %0\n\t"
116 "xor $1, %0\n\t"
117 "dmtc0 $1, $9, 7\n\t"
118 ".set pop"
119 : "+r" (irq));
120}
121
122/*
123 * Read c0 eimr and c0 eirr, do AND of the two values, the result is
124 * the interrupts which are raised and are not masked.
125 */
126static inline uint64_t read_c0_eirr_and_eimr(void)
127{
128 uint64_t val;
129
130#ifdef CONFIG_64BIT
131 val = read_c0_eimr() & read_c0_eirr();
132#else
133 __asm__ __volatile__(
134 ".set push\n\t"
135 ".set mips64\n\t"
136 ".set noat\n\t"
137 "dmfc0 %M0, $9, 6\n\t"
138 "dmfc0 %L0, $9, 7\n\t"
139 "and %M0, %L0\n\t"
140 "dsll %L0, %M0, 32\n\t"
141 "dsra %M0, %M0, 32\n\t"
142 "dsra %L0, %L0, 32\n\t"
143 ".set pop"
144 : "=r" (val));
145#endif
146
147 return val;
148}
149
71static inline int hard_smp_processor_id(void) 150static inline int hard_smp_processor_id(void)
72{ 151{
73 return __read_32bit_c0_register($15, 1) & 0x3ff; 152 return __read_32bit_c0_register($15, 1) & 0x3ff;
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 7b63a6b722a0..6d2e58a9a542 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
46#define CPU_BLOCKID_FPU 9 46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10 47#define CPU_BLOCKID_MAP 10
48 48
49#define ICU_DEFEATURE 0x100
50
49#define LSU_DEFEATURE 0x304 51#define LSU_DEFEATURE 0x304
50#define LSU_DEBUG_ADDR 0x305 52#define LSU_DEBUG_ADDR 0x305
51#define LSU_DEBUG_DATA0 0x306 53#define LSU_DEBUG_DATA0 0x306
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 46ace0ca26d8..3df53017fe51 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -261,6 +261,8 @@
261#define PIC_LOCAL_SCHEDULING 1 261#define PIC_LOCAL_SCHEDULING 1
262#define PIC_GLOBAL_SCHEDULING 0 262#define PIC_GLOBAL_SCHEDULING 0
263 263
264#define PIC_CLK_HZ 133333333
265
264#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 266#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
265#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 267#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
266#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 268#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
@@ -315,6 +317,12 @@ nlm_pic_read_timer(uint64_t base, int timer)
315 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); 317 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
316} 318}
317 319
320static inline uint32_t
321nlm_pic_read_timer32(uint64_t base, int timer)
322{
323 return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
324}
325
318static inline void 326static inline void
319nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) 327nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
320{ 328{
@@ -376,9 +384,9 @@ nlm_pic_ack(uint64_t base, int irt_num)
376} 384}
377 385
378static inline void 386static inline void
379nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) 387nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
380{ 388{
381 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt); 389 nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
382} 390}
383 391
384int nlm_irq_to_irt(int irq); 392int nlm_irq_to_irt(int irq);
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 2f549453585e..63c99176dffe 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -35,10 +35,11 @@
35#ifndef _ASM_NLM_XLR_PIC_H 35#ifndef _ASM_NLM_XLR_PIC_H
36#define _ASM_NLM_XLR_PIC_H 36#define _ASM_NLM_XLR_PIC_H
37 37
38#define PIC_CLKS_PER_SEC 66666666ULL 38#define PIC_CLK_HZ 66666666
39/* PIC hardware interrupt numbers */ 39/* PIC hardware interrupt numbers */
40#define PIC_IRT_WD_INDEX 0 40#define PIC_IRT_WD_INDEX 0
41#define PIC_IRT_TIMER_0_INDEX 1 41#define PIC_IRT_TIMER_0_INDEX 1
42#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX)
42#define PIC_IRT_TIMER_1_INDEX 2 43#define PIC_IRT_TIMER_1_INDEX 2
43#define PIC_IRT_TIMER_2_INDEX 3 44#define PIC_IRT_TIMER_2_INDEX 3
44#define PIC_IRT_TIMER_3_INDEX 4 45#define PIC_IRT_TIMER_3_INDEX 4
@@ -99,6 +100,7 @@
99 100
100/* PIC Registers */ 101/* PIC Registers */
101#define PIC_CTRL 0x00 102#define PIC_CTRL 0x00
103#define PIC_CTRL_STE 8 /* timer enable start bit */
102#define PIC_IPI 0x04 104#define PIC_IPI 0x04
103#define PIC_INT_ACK 0x06 105#define PIC_INT_ACK 0x06
104 106
@@ -251,12 +253,52 @@ nlm_pic_ack(uint64_t base, int irt)
251} 253}
252 254
253static inline void 255static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) 256nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
255{ 257{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); 258 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */ 259 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt), 260 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq); 261 (en << 30) | (1 << 6) | irq);
262}
263
264static inline uint64_t
265nlm_pic_read_timer(uint64_t base, int timer)
266{
267 uint32_t up1, up2, low;
268
269 up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
270 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
271 up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
272
273 if (up1 != up2) /* wrapped, get the new low */
274 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
275 return ((uint64_t)up2 << 32) | low;
276
277}
278
279static inline uint32_t
280nlm_pic_read_timer32(uint64_t base, int timer)
281{
282 return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
283}
284
285static inline void
286nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
287{
288 uint32_t up, low;
289 uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
290 int en;
291
292 en = (irq > 0);
293 up = value >> 32;
294 low = value & 0xFFFFFFFF;
295 nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low);
296 nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up);
297 nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0);
298
299 /* enable the timer */
300 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
301 nlm_write_reg(base, PIC_CTRL, pic_ctrl);
260} 302}
261#endif 303#endif
262#endif /* _ASM_NLM_XLR_PIC_H */ 304#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index e224876cc344..b8e24fd4cbc5 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -144,8 +144,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
144 144
145extern char * (*pcibios_plat_setup)(char *str); 145extern char * (*pcibios_plat_setup)(char *str);
146 146
147#ifdef CONFIG_OF
147/* this function parses memory ranges from a device node */ 148/* this function parses memory ranges from a device node */
148extern void pci_load_of_ranges(struct pci_controller *hose, 149extern void pci_load_of_ranges(struct pci_controller *hose,
149 struct device_node *node); 150 struct device_node *node);
151#else
152static inline void pci_load_of_ranges(struct pci_controller *hose,
153 struct device_node *node) {}
154#endif
150 155
151#endif /* _ASM_PCI_H */ 156#endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 96353075cc60..debc8009bd58 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
75 75
76static inline int init_mips_clocksource(void) 76static inline int init_mips_clocksource(void)
77{ 77{
78#ifdef CONFIG_CSRC_R4K 78#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC)
79 return init_r4k_clocksource(); 79 return init_r4k_clocksource();
80#else 80#else
81 return 0; 81 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-17 17:19:27 -0400