[MIPS] IRQ cleanups

This is a big irq cleanup patch.

* Use set_irq_chip() to register irq_chip.
* Initialize .mask, .unmask, .mask_ack field.  Functions for these
  method are already exist in most case.
* Do not initialize .startup, .shutdown, .enable, .disable fields if
  default routines provided by irq_chip_set_defaults() were suitable.
* Remove redundant irq_desc initializations.
* Remove unnecessary local_irq_save/local_irq_restore, spin_lock.

With this cleanup, it would be easy to switch to slightly lightwait
irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ().

Though whole this patch is quite large, changes in each irq_chip are
not quite simple.  Please review and test on your platform.  Thanks.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 0 insertions, 6 deletions

diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..c8430c07355e 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
 static inline void dec_kn02_be_init(void)
 {
         volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
-        unsigned long flags;
 
         kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
         kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
 
-        spin_lock_irqsave(&kn02_lock, flags);
-
         /* Preset write-only bits of the Control Register cache. */
         cached_kn02_csr = *csr | KN02_CSR_LEDS;
 
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void)
         cached_kn02_csr |= KN02_CSR_CORRECT;
         *csr = cached_kn02_csr;
         iob();
-
-        spin_unlock_irqrestore(&kn02_lock, flags);
 }
 
 static inline void dec_kn03_be_init(void)