[MIPS] IRQ cleanups

This is a big irq cleanup patch.

* Use set_irq_chip() to register irq_chip.
* Initialize .mask, .unmask, .mask_ack field.  Functions for these
  method are already exist in most case.
* Do not initialize .startup, .shutdown, .enable, .disable fields if
  default routines provided by irq_chip_set_defaults() were suitable.
* Remove redundant irq_desc initializations.
* Remove unnecessary local_irq_save/local_irq_restore, spin_lock.

With this cleanup, it would be easy to switch to slightly lightwait
irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ().

Though whole this patch is quite large, changes in each irq_chip are
not quite simple.  Please review and test on your platform.  Thanks.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 20 insertions, 111 deletions

diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..c8430c07355e 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
 static inline void dec_kn02_be_init(void)
 {
         volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
-        unsigned long flags;
 
         kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
         kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
 
-        spin_lock_irqsave(&kn02_lock, flags);
-
         /* Preset write-only bits of the Control Register cache. */
         cached_kn02_csr = *csr | KN02_CSR_LEDS;
 
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void)
         cached_kn02_csr |= KN02_CSR_CORRECT;
         *csr = cached_kn02_csr;
         iob();
-
-        spin_unlock_irqrestore(&kn02_lock, flags);
 }
 
 static inline void dec_kn03_be_init(void)
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..d0af08bdbb4e 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
 #include <asm/dec/ioasic_ints.h>
 
 
-static DEFINE_SPINLOCK(ioasic_lock);
-
 static int ioasic_irq_base;
 
 
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq)
         ioasic_write(IO_REG_SIR, sir);
 }
 
-static inline void enable_ioasic_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&ioasic_lock, flags);
-        unmask_ioasic_irq(irq);
-        spin_unlock_irqrestore(&ioasic_lock, flags);
-}
-
-static inline void disable_ioasic_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&ioasic_lock, flags);
-        mask_ioasic_irq(irq);
-        spin_unlock_irqrestore(&ioasic_lock, flags);
-}
-
-
-static inline unsigned int startup_ioasic_irq(unsigned int irq)
-{
-        enable_ioasic_irq(irq);
-        return 0;
-}
-
-#define shutdown_ioasic_irq disable_ioasic_irq
-
 static inline void ack_ioasic_irq(unsigned int irq)
 {
-        spin_lock(&ioasic_lock);
         mask_ioasic_irq(irq);
-        spin_unlock(&ioasic_lock);
         fast_iob();
 }
 
 static inline void end_ioasic_irq(unsigned int irq)
 {
         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                enable_ioasic_irq(irq);
+                unmask_ioasic_irq(irq);
 }
 
 static struct irq_chip ioasic_irq_type = {
         .typename = "IO-ASIC",
-        .startup = startup_ioasic_irq,
-        .shutdown = shutdown_ioasic_irq,
-        .enable = enable_ioasic_irq,
-        .disable = disable_ioasic_irq,
         .ack = ack_ioasic_irq,
+        .mask = mask_ioasic_irq,
+        .mask_ack = ack_ioasic_irq,
+        .unmask = unmask_ioasic_irq,
         .end = end_ioasic_irq,
 };
 
 
-#define startup_ioasic_dma_irq startup_ioasic_irq
-
-#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
-
-#define enable_ioasic_dma_irq enable_ioasic_irq
+#define unmask_ioasic_dma_irq unmask_ioasic_irq
 
-#define disable_ioasic_dma_irq disable_ioasic_irq
+#define mask_ioasic_dma_irq mask_ioasic_irq
 
 #define ack_ioasic_dma_irq ack_ioasic_irq
 
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
 
 static struct irq_chip ioasic_dma_irq_type = {
         .typename = "IO-ASIC-DMA",
-        .startup = startup_ioasic_dma_irq,
-        .shutdown = shutdown_ioasic_dma_irq,
-        .enable = enable_ioasic_dma_irq,
-        .disable = disable_ioasic_dma_irq,
         .ack = ack_ioasic_dma_irq,
+        .mask = mask_ioasic_dma_irq,
+        .mask_ack = ack_ioasic_dma_irq,
+        .unmask = unmask_ioasic_dma_irq,
         .end = end_ioasic_dma_irq,
 };
 
@@ -140,18 +102,10 @@ void __init init_ioasic_irqs(int base)
         ioasic_write(IO_REG_SIMR, 0);
         fast_iob();
 
-        for (i = base; i < base + IO_INR_DMA; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-                irq_desc[i].chip = &ioasic_irq_type;
-        }
-        for (; i < base + IO_IRQ_LINES; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-                irq_desc[i].chip = &ioasic_dma_irq_type;
-        }
+        for (i = base; i < base + IO_INR_DMA; i++)
+                set_irq_chip(i, &ioasic_irq_type);
+        for (; i < base + IO_IRQ_LINES; i++)
+                set_irq_chip(i, &ioasic_dma_irq_type);
 
         ioasic_irq_base = base;
 }
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a57..c761d97787ec 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
  * There is no default value -- it has to be initialized.
  */
 u32 cached_kn02_csr;
-DEFINE_SPINLOCK(kn02_lock);
 
 
 static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq)
         *csr = cached_kn02_csr;
 }
 
-static inline void enable_kn02_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&kn02_lock, flags);
-        unmask_kn02_irq(irq);
-        spin_unlock_irqrestore(&kn02_lock, flags);
-}
-
-static inline void disable_kn02_irq(unsigned int irq)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&kn02_lock, flags);
-        mask_kn02_irq(irq);
-        spin_unlock_irqrestore(&kn02_lock, flags);
-}
-
-
-static unsigned int startup_kn02_irq(unsigned int irq)
-{
-        enable_kn02_irq(irq);
-        return 0;
-}
-
-#define shutdown_kn02_irq disable_kn02_irq
-
 static void ack_kn02_irq(unsigned int irq)
 {
-        spin_lock(&kn02_lock);
         mask_kn02_irq(irq);
-        spin_unlock(&kn02_lock);
         iob();
 }
 
 static void end_kn02_irq(unsigned int irq)
 {
         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-                enable_kn02_irq(irq);
+                unmask_kn02_irq(irq);
 }
 
 static struct irq_chip kn02_irq_type = {
         .typename = "KN02-CSR",
-        .startup = startup_kn02_irq,
-        .shutdown = shutdown_kn02_irq,
-        .enable = enable_kn02_irq,
-        .disable = disable_kn02_irq,
         .ack = ack_kn02_irq,
+        .mask = mask_kn02_irq,
+        .mask_ack = ack_kn02_irq,
+        .unmask = unmask_kn02_irq,
         .end = end_kn02_irq,
 };
 
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base)
 {
         volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
                                                        KN02_CSR);
-        unsigned long flags;
         int i;
 
         /* Mask interrupts. */
-        spin_lock_irqsave(&kn02_lock, flags);
         cached_kn02_csr &= ~KN02_CSR_IOINTEN;
         *csr = cached_kn02_csr;
         iob();
-        spin_unlock_irqrestore(&kn02_lock, flags);
-
-        for (i = base; i < base + KN02_IRQ_LINES; i++) {
-                irq_desc[i].status = IRQ_DISABLED;
-                irq_desc[i].action = 0;
-                irq_desc[i].depth = 1;
-                irq_desc[i].chip = &kn02_irq_type;
-        }
+
+        for (i = base; i < base + KN02_IRQ_LINES; i++)
+                set_irq_chip(i, &kn02_irq_type);
 
         kn02_irq_base = base;
 }