Merge ../linux-2.6 by hand

4 files changed, 449 insertions, 0 deletions

diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile
new file mode 100644
index 000000000000..22b673cf55af
--- /dev/null
+++ b/arch/mips/au1000/pb1200/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Alchemy Semiconductor PB1200 board.
+#
+
+lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
new file mode 100644
index 000000000000..a45b17538ac9
--- /dev/null
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -0,0 +1,193 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Alchemy Pb1200/Db1200 board setup.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/mc146818rtc.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
+#include <linux/ide.h>
+#endif
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/mach-pb1x00/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/mach-db1x00/db1200.h>
+#define PB1200_ETH_INT DB1200_ETH_INT
+#define PB1200_IDE_INT DB1200_IDE_INT
+#endif
+
+extern void _board_init_irq(void);
+extern void     (*board_init_irq)(void);
+
+void board_reset (void)
+{
+        bcsr->resets = 0;
+        bcsr->system = 0;
+}
+
+void __init board_setup(void)
+{
+        char *argptr = NULL;
+        u32 pin_func;
+
+#if 0
+        /* Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
+         * but it is board specific code, so put it here.
+         */
+        pin_func = au_readl(SYS_PINFUNC);
+        au_sync();
+        pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+        au_writel(pin_func, SYS_PINFUNC);
+
+        au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
+        au_sync();
+#endif
+
+#if defined(CONFIG_I2C_AU1550)
+        {
+        u32 freq0, clksrc;
+
+        /* Select SMBUS in CPLD */
+        bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
+
+        pin_func = au_readl(SYS_PINFUNC);
+        au_sync();
+        pin_func &= ~(3<<17 | 1<<4);
+        /* Set GPIOs correctly */
+        pin_func |= 2<<17;
+        au_writel(pin_func, SYS_PINFUNC);
+        au_sync();
+
+        /* The i2c driver depends on 50Mhz clock */
+        freq0 = au_readl(SYS_FREQCTRL0);
+        au_sync();
+        freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
+        freq0 |= (3<<SYS_FC_FRDIV1_BIT);
+        /* 396Mhz / (3+1)*2 == 49.5Mhz */
+        au_writel(freq0, SYS_FREQCTRL0);
+        au_sync();
+        freq0 |= SYS_FC_FE1;
+        au_writel(freq0, SYS_FREQCTRL0);
+        au_sync();
+
+        clksrc = au_readl(SYS_CLKSRC);
+        au_sync();
+        clksrc &= ~0x01f00000;
+        /* bit 22 is EXTCLK0 for PSC0 */
+        clksrc |= (0x3 << 22);
+        au_writel(clksrc, SYS_CLKSRC);
+        au_sync();
+        }
+#endif
+
+#ifdef CONFIG_FB_AU1200
+        argptr = prom_getcmdline();
+#ifdef CONFIG_MIPS_PB1200
+        strcat(argptr, " video=au1200fb:panel:bs");
+#endif
+#ifdef CONFIG_MIPS_DB1200
+        strcat(argptr, " video=au1200fb:panel:bs");
+#endif
+#endif
+
+        /* The Pb1200 development board uses external MUX for PSC0 to
+        support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
+        */
+#if defined(CONFIG_AU1XXX_PSC_SPI) && defined(CONFIG_I2C_AU1550)
+        #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
+                        Refer to Pb1200/Db1200 documentation.
+#elif defined( CONFIG_AU1XXX_PSC_SPI )
+        bcsr->resets |= BCSR_RESETS_PCS0MUX;
+        /*Hard Coding Value to enable Temp Sensors [bit 14] Value for SOC Au1200. Pls refer documentation*/
+          bcsr->resets =0x900f;
+#elif defined( CONFIG_I2C_AU1550 )
+        bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
+#endif
+        au_sync();
+
+#ifdef CONFIG_MIPS_PB1200
+        printk("AMD Alchemy Pb1200 Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1200
+        printk("AMD Alchemy Db1200 Board\n");
+#endif
+
+        /* Setup Pb1200 External Interrupt Controller */
+        {
+                extern void (*board_init_irq)(void);
+                extern void _board_init_irq(void);
+                board_init_irq = _board_init_irq;
+        }
+}
+
+int
+board_au1200fb_panel (void)
+{
+        BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+        int p;
+
+        p = bcsr->switches;
+        p >>= 8;
+        p &= 0x0F;
+        return p;
+}
+
+int
+board_au1200fb_panel_init (void)
+{
+        /* Apply power */
+    BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+        bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
+        /*printk("board_au1200fb_panel_init()\n"); */
+        return 0;
+}
+
+int
+board_au1200fb_panel_shutdown (void)
+{
+        /* Remove power */
+    BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+        bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
+        /*printk("board_au1200fb_panel_shutdown()\n"); */
+        return 0;
+}
+
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
new file mode 100644
index 000000000000..27f09e374e15
--- /dev/null
+++ b/arch/mips/au1000/pb1200/init.c
@@ -0,0 +1,69 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      PB1200 board setup
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *              ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+extern void  __init prom_init_cmdline(void);
+extern char *prom_getenv(char *envname);
+
+const char *get_system_type(void)
+{
+        return "Alchemy Pb1200";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = (int) fw_arg0;
+        prom_argv = (char **) fw_arg1;
+        prom_envp = (char **) fw_arg2;
+
+        mips_machgroup = MACH_GROUP_ALCHEMY;
+        mips_machtype = MACH_PB1200;
+
+        prom_init_cmdline();
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str) {
+                memsize = 0x08000000;
+        } else {
+                memsize = simple_strtol(memsize_str, NULL, 0);
+        }
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
new file mode 100644
index 000000000000..59e70e5cf325
--- /dev/null
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -0,0 +1,182 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Au1xxx irq map table
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <asm/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/mach-pb1x00/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/mach-db1x00/db1200.h>
+#define PB1200_INT_BEGIN DB1200_INT_BEGIN
+#define PB1200_INT_END DB1200_INT_END
+#endif
+
+au1xxx_irq_map_t au1xxx_irq_map[] = {
+        { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
+};
+
+int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
+
+/*
+ *      Support for External interrupts on the PbAu1200 Development platform.
+ */
+static volatile int pb1200_cascade_en=0;
+
+irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
+{
+        unsigned short bisr = bcsr->int_status;
+        int extirq_nr = 0;
+
+        /* Clear all the edge interrupts. This has no effect on level */
+        bcsr->int_status = bisr;
+        for( ; bisr; bisr &= (bisr-1) )
+        {
+                extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
+                /* Ack and dispatch IRQ */
+                do_IRQ(extirq_nr,regs);
+        }
+        return IRQ_RETVAL(1);
+}
+
+inline void pb1200_enable_irq(unsigned int irq_nr)
+{
+        bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
+        bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
+}
+
+inline void pb1200_disable_irq(unsigned int irq_nr)
+{
+        bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
+        bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
+}
+
+static unsigned int pb1200_startup_irq( unsigned int irq_nr )
+{
+        if (++pb1200_cascade_en == 1)
+        {
+                request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
+                        0, "Pb1200 Cascade", (void *)&pb1200_cascade_handler );
+#ifdef CONFIG_MIPS_PB1200
+    /* We have a problem with CPLD rev3. Enable a workaround */
+        if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
+        {
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
+                printk("updated to latest revision. This software will not\n");
+                printk("work on anything less than CPLD rev4\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                printk("\nWARNING!!!\n");
+                while(1);
+        }
+#endif
+        }
+        pb1200_enable_irq(irq_nr);
+        return 0;
+}
+
+static void pb1200_shutdown_irq( unsigned int irq_nr )
+{
+        pb1200_disable_irq(irq_nr);
+        if (--pb1200_cascade_en == 0)
+        {
+                free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
+        }
+        return;
+}
+
+static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
+{
+        pb1200_disable_irq( irq_nr );
+}
+
+static void pb1200_end_irq(unsigned int irq_nr)
+{
+        if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+                pb1200_enable_irq(irq_nr);
+        }
+}
+
+static struct hw_interrupt_type external_irq_type =
+{
+#ifdef CONFIG_MIPS_PB1200
+        "Pb1200 Ext",
+#endif
+#ifdef CONFIG_MIPS_DB1200
+        "Db1200 Ext",
+#endif
+        pb1200_startup_irq,
+        pb1200_shutdown_irq,
+        pb1200_enable_irq,
+        pb1200_disable_irq,
+        pb1200_mask_and_ack_irq,
+        pb1200_end_irq,
+        NULL
+};
+
+void _board_init_irq(void)
+{
+        int irq_nr;
+
+        for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
+        {
+                irq_desc[irq_nr].handler = &external_irq_type;
+                pb1200_disable_irq(irq_nr);
+        }
+
+        /* GPIO_7 can not be hooked here, so it is hooked upon first
+        request of any source attached to the cascade */
+}
+