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authorDavid S. Miller <davem@davemloft.net>2010-02-28 22:23:06 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-28 22:23:06 -0500
commit47871889c601d8199c51a4086f77eebd77c29b0b (patch)
tree40cdcac3bff0ee40cc33dcca61d0577cdf965f77 /arch/mips/alchemy
parentc16cc0b464b8876cfd57ce1c1dbcb6f9a6a0bce3 (diff)
parent30ff056c42c665b9ea535d8515890857ae382540 (diff)
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Conflicts: drivers/firmware/iscsi_ibft.c
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/Kconfig28
-rw-r--r--arch/mips/alchemy/common/Makefile7
-rw-r--r--arch/mips/alchemy/common/clocks.c7
-rw-r--r--arch/mips/alchemy/common/dbdma.c187
-rw-r--r--arch/mips/alchemy/common/dma.c36
-rw-r--r--arch/mips/alchemy/common/gpiolib-au1000.c10
-rw-r--r--arch/mips/alchemy/common/irq.c436
-rw-r--r--arch/mips/alchemy/common/platform.c153
-rw-r--r--arch/mips/alchemy/common/prom.c28
-rw-r--r--arch/mips/alchemy/common/puts.c68
-rw-r--r--arch/mips/alchemy/common/reset.c188
-rw-r--r--arch/mips/alchemy/common/setup.c40
-rw-r--r--arch/mips/alchemy/common/time.c35
-rw-r--r--arch/mips/alchemy/devboards/Makefile6
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c148
-rw-r--r--arch/mips/alchemy/devboards/db1200/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c561
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c118
-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c204
-rw-r--r--arch/mips/alchemy/devboards/db1x00/irqmap.c90
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c118
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c34
-rw-r--r--arch/mips/alchemy/devboards/pb1100/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c55
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c50
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c96
-rw-r--r--arch/mips/alchemy/devboards/pb1200/irqmap.c134
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c63
-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c54
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c49
-rw-r--r--arch/mips/alchemy/devboards/pb1550/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c49
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c69
-rw-r--r--arch/mips/alchemy/devboards/platform.c222
-rw-r--r--arch/mips/alchemy/devboards/platform.h21
-rw-r--r--arch/mips/alchemy/devboards/pm.c32
-rw-r--r--arch/mips/alchemy/devboards/prom.c5
-rw-r--r--arch/mips/alchemy/mtx-1/Makefile2
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c49
-rw-r--r--arch/mips/alchemy/mtx-1/init.c6
-rw-r--r--arch/mips/alchemy/mtx-1/irqmap.c56
-rw-r--r--arch/mips/alchemy/xxs1500/Makefile4
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c60
-rw-r--r--arch/mips/alchemy/xxs1500/init.c6
-rw-r--r--arch/mips/alchemy/xxs1500/irqmap.c52
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c63
49 files changed, 2428 insertions, 1282 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 00b498e97c83..df3b1a7eb15d 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,5 +1,5 @@
1# au1000-style gpio 1# au1000-style gpio and interrupt controllers
2config ALCHEMY_GPIO_AU1000 2config ALCHEMY_GPIOINT_AU1000
3 bool 3 bool
4 4
5# select this in your board config if you don't want to use the gpio 5# select this in your board config if you don't want to use the gpio
@@ -20,12 +20,14 @@ config MIPS_MTX1
20 select HW_HAS_PCI 20 select HW_HAS_PCI
21 select SOC_AU1500 21 select SOC_AU1500
22 select SYS_SUPPORTS_LITTLE_ENDIAN 22 select SYS_SUPPORTS_LITTLE_ENDIAN
23 select SYS_HAS_EARLY_PRINTK
23 24
24config MIPS_BOSPORUS 25config MIPS_BOSPORUS
25 bool "Alchemy Bosporus board" 26 bool "Alchemy Bosporus board"
26 select SOC_AU1500 27 select SOC_AU1500
27 select DMA_NONCOHERENT 28 select DMA_NONCOHERENT
28 select SYS_SUPPORTS_LITTLE_ENDIAN 29 select SYS_SUPPORTS_LITTLE_ENDIAN
30 select SYS_HAS_EARLY_PRINTK
29 31
30config MIPS_DB1000 32config MIPS_DB1000
31 bool "Alchemy DB1000 board" 33 bool "Alchemy DB1000 board"
@@ -33,12 +35,14 @@ config MIPS_DB1000
33 select DMA_NONCOHERENT 35 select DMA_NONCOHERENT
34 select HW_HAS_PCI 36 select HW_HAS_PCI
35 select SYS_SUPPORTS_LITTLE_ENDIAN 37 select SYS_SUPPORTS_LITTLE_ENDIAN
38 select SYS_HAS_EARLY_PRINTK
36 39
37config MIPS_DB1100 40config MIPS_DB1100
38 bool "Alchemy DB1100 board" 41 bool "Alchemy DB1100 board"
39 select SOC_AU1100 42 select SOC_AU1100
40 select DMA_NONCOHERENT 43 select DMA_NONCOHERENT
41 select SYS_SUPPORTS_LITTLE_ENDIAN 44 select SYS_SUPPORTS_LITTLE_ENDIAN
45 select SYS_HAS_EARLY_PRINTK
42 46
43config MIPS_DB1200 47config MIPS_DB1200
44 bool "Alchemy DB1200 board" 48 bool "Alchemy DB1200 board"
@@ -46,6 +50,7 @@ config MIPS_DB1200
46 select DMA_COHERENT 50 select DMA_COHERENT
47 select MIPS_DISABLE_OBSOLETE_IDE 51 select MIPS_DISABLE_OBSOLETE_IDE
48 select SYS_SUPPORTS_LITTLE_ENDIAN 52 select SYS_SUPPORTS_LITTLE_ENDIAN
53 select SYS_HAS_EARLY_PRINTK
49 54
50config MIPS_DB1500 55config MIPS_DB1500
51 bool "Alchemy DB1500 board" 56 bool "Alchemy DB1500 board"
@@ -55,6 +60,7 @@ config MIPS_DB1500
55 select MIPS_DISABLE_OBSOLETE_IDE 60 select MIPS_DISABLE_OBSOLETE_IDE
56 select SYS_SUPPORTS_BIG_ENDIAN 61 select SYS_SUPPORTS_BIG_ENDIAN
57 select SYS_SUPPORTS_LITTLE_ENDIAN 62 select SYS_SUPPORTS_LITTLE_ENDIAN
63 select SYS_HAS_EARLY_PRINTK
58 64
59config MIPS_DB1550 65config MIPS_DB1550
60 bool "Alchemy DB1550 board" 66 bool "Alchemy DB1550 board"
@@ -63,12 +69,14 @@ config MIPS_DB1550
63 select DMA_NONCOHERENT 69 select DMA_NONCOHERENT
64 select MIPS_DISABLE_OBSOLETE_IDE 70 select MIPS_DISABLE_OBSOLETE_IDE
65 select SYS_SUPPORTS_LITTLE_ENDIAN 71 select SYS_SUPPORTS_LITTLE_ENDIAN
72 select SYS_HAS_EARLY_PRINTK
66 73
67config MIPS_MIRAGE 74config MIPS_MIRAGE
68 bool "Alchemy Mirage board" 75 bool "Alchemy Mirage board"
69 select DMA_NONCOHERENT 76 select DMA_NONCOHERENT
70 select SOC_AU1500 77 select SOC_AU1500
71 select SYS_SUPPORTS_LITTLE_ENDIAN 78 select SYS_SUPPORTS_LITTLE_ENDIAN
79 select SYS_HAS_EARLY_PRINTK
72 80
73config MIPS_PB1000 81config MIPS_PB1000
74 bool "Alchemy PB1000 board" 82 bool "Alchemy PB1000 board"
@@ -77,6 +85,7 @@ config MIPS_PB1000
77 select HW_HAS_PCI 85 select HW_HAS_PCI
78 select SWAP_IO_SPACE 86 select SWAP_IO_SPACE
79 select SYS_SUPPORTS_LITTLE_ENDIAN 87 select SYS_SUPPORTS_LITTLE_ENDIAN
88 select SYS_HAS_EARLY_PRINTK
80 89
81config MIPS_PB1100 90config MIPS_PB1100
82 bool "Alchemy PB1100 board" 91 bool "Alchemy PB1100 board"
@@ -85,6 +94,7 @@ config MIPS_PB1100
85 select HW_HAS_PCI 94 select HW_HAS_PCI
86 select SWAP_IO_SPACE 95 select SWAP_IO_SPACE
87 select SYS_SUPPORTS_LITTLE_ENDIAN 96 select SYS_SUPPORTS_LITTLE_ENDIAN
97 select SYS_HAS_EARLY_PRINTK
88 98
89config MIPS_PB1200 99config MIPS_PB1200
90 bool "Alchemy PB1200 board" 100 bool "Alchemy PB1200 board"
@@ -92,6 +102,7 @@ config MIPS_PB1200
92 select DMA_NONCOHERENT 102 select DMA_NONCOHERENT
93 select MIPS_DISABLE_OBSOLETE_IDE 103 select MIPS_DISABLE_OBSOLETE_IDE
94 select SYS_SUPPORTS_LITTLE_ENDIAN 104 select SYS_SUPPORTS_LITTLE_ENDIAN
105 select SYS_HAS_EARLY_PRINTK
95 106
96config MIPS_PB1500 107config MIPS_PB1500
97 bool "Alchemy PB1500 board" 108 bool "Alchemy PB1500 board"
@@ -99,6 +110,7 @@ config MIPS_PB1500
99 select DMA_NONCOHERENT 110 select DMA_NONCOHERENT
100 select HW_HAS_PCI 111 select HW_HAS_PCI
101 select SYS_SUPPORTS_LITTLE_ENDIAN 112 select SYS_SUPPORTS_LITTLE_ENDIAN
113 select SYS_HAS_EARLY_PRINTK
102 114
103config MIPS_PB1550 115config MIPS_PB1550
104 bool "Alchemy PB1550 board" 116 bool "Alchemy PB1550 board"
@@ -107,39 +119,41 @@ config MIPS_PB1550
107 select HW_HAS_PCI 119 select HW_HAS_PCI
108 select MIPS_DISABLE_OBSOLETE_IDE 120 select MIPS_DISABLE_OBSOLETE_IDE
109 select SYS_SUPPORTS_LITTLE_ENDIAN 121 select SYS_SUPPORTS_LITTLE_ENDIAN
122 select SYS_HAS_EARLY_PRINTK
110 123
111config MIPS_XXS1500 124config MIPS_XXS1500
112 bool "MyCable XXS1500 board" 125 bool "MyCable XXS1500 board"
113 select DMA_NONCOHERENT 126 select DMA_NONCOHERENT
114 select SOC_AU1500 127 select SOC_AU1500
115 select SYS_SUPPORTS_LITTLE_ENDIAN 128 select SYS_SUPPORTS_LITTLE_ENDIAN
129 select SYS_HAS_EARLY_PRINTK
116 130
117endchoice 131endchoice
118 132
119config SOC_AU1000 133config SOC_AU1000
120 bool 134 bool
121 select SOC_AU1X00 135 select SOC_AU1X00
122 select ALCHEMY_GPIO_AU1000 136 select ALCHEMY_GPIOINT_AU1000
123 137
124config SOC_AU1100 138config SOC_AU1100
125 bool 139 bool
126 select SOC_AU1X00 140 select SOC_AU1X00
127 select ALCHEMY_GPIO_AU1000 141 select ALCHEMY_GPIOINT_AU1000
128 142
129config SOC_AU1500 143config SOC_AU1500
130 bool 144 bool
131 select SOC_AU1X00 145 select SOC_AU1X00
132 select ALCHEMY_GPIO_AU1000 146 select ALCHEMY_GPIOINT_AU1000
133 147
134config SOC_AU1550 148config SOC_AU1550
135 bool 149 bool
136 select SOC_AU1X00 150 select SOC_AU1X00
137 select ALCHEMY_GPIO_AU1000 151 select ALCHEMY_GPIOINT_AU1000
138 152
139config SOC_AU1200 153config SOC_AU1200
140 bool 154 bool
141 select SOC_AU1X00 155 select SOC_AU1X00
142 select ALCHEMY_GPIO_AU1000 156 select ALCHEMY_GPIOINT_AU1000
143 157
144config SOC_AU1X00 158config SOC_AU1X00
145 bool 159 bool
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index b67fb512529d..06c0e65a54b5 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -5,14 +5,15 @@
5# Makefile for the Alchemy Au1xx0 CPUs, generic files. 5# Makefile for the Alchemy Au1xx0 CPUs, generic files.
6# 6#
7 7
8obj-y += prom.o irq.o puts.o time.o reset.o \ 8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
9 clocks.o platform.o power.o setup.o \
10 sleeper.o dma.o dbdma.o 9 sleeper.o dma.o dbdma.o
11 10
11obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
12
12# optional gpiolib support 13# optional gpiolib support
13ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
14 ifeq ($(CONFIG_GPIOLIB),y) 15 ifeq ($(CONFIG_GPIOLIB),y)
15 obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o 16 obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
16 endif 17 endif
17endif 18endif
18 19
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index d8991854530e..460c6285c1bb 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -40,8 +40,6 @@
40static unsigned int au1x00_clock; /* Hz */ 40static unsigned int au1x00_clock; /* Hz */
41static unsigned long uart_baud_base; 41static unsigned long uart_baud_base;
42 42
43static DEFINE_SPINLOCK(time_lock);
44
45/* 43/*
46 * Set the au1000_clock 44 * Set the au1000_clock
47 */ 45 */
@@ -84,9 +82,6 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
84unsigned long au1xxx_calc_clock(void) 82unsigned long au1xxx_calc_clock(void)
85{ 83{
86 unsigned long cpu_speed; 84 unsigned long cpu_speed;
87 unsigned long flags;
88
89 spin_lock_irqsave(&time_lock, flags);
90 85
91 /* 86 /*
92 * On early Au1000, sys_cpupll was write-only. Since these 87 * On early Au1000, sys_cpupll was write-only. Since these
@@ -108,8 +103,6 @@ unsigned long au1xxx_calc_clock(void)
108 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) 103 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
109 & 0x03) + 2) * 16)); 104 & 0x03) + 2) * 16));
110 105
111 spin_unlock_irqrestore(&time_lock, flags);
112
113 set_au1x00_speed(cpu_speed); 106 set_au1x00_speed(cpu_speed);
114 107
115 return cpu_speed; 108 return cpu_speed;
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index f9201ca2295b..99ae84ce5af3 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -30,6 +30,7 @@
30 * 30 *
31 */ 31 */
32 32
33#include <linux/init.h>
33#include <linux/kernel.h> 34#include <linux/kernel.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
35#include <linux/spinlock.h> 36#include <linux/spinlock.h>
@@ -58,7 +59,6 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
58 59
59static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; 60static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
60static int dbdma_initialized; 61static int dbdma_initialized;
61static void au1xxx_dbdma_init(void);
62 62
63static dbdev_tab_t dbdev_tab[] = { 63static dbdev_tab_t dbdev_tab[] = {
64#ifdef CONFIG_SOC_AU1550 64#ifdef CONFIG_SOC_AU1550
@@ -237,7 +237,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
237 void (*callback)(int, void *), void *callparam) 237 void (*callback)(int, void *), void *callparam)
238{ 238{
239 unsigned long flags; 239 unsigned long flags;
240 u32 used, chan, rv; 240 u32 used, chan;
241 u32 dcp; 241 u32 dcp;
242 int i; 242 int i;
243 dbdev_tab_t *stp, *dtp; 243 dbdev_tab_t *stp, *dtp;
@@ -250,8 +250,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
250 * which can't be done successfully during board set up. 250 * which can't be done successfully during board set up.
251 */ 251 */
252 if (!dbdma_initialized) 252 if (!dbdma_initialized)
253 au1xxx_dbdma_init(); 253 return 0;
254 dbdma_initialized = 1;
255 254
256 stp = find_dbdev_id(srcid); 255 stp = find_dbdev_id(srcid);
257 if (stp == NULL) 256 if (stp == NULL)
@@ -261,7 +260,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
261 return 0; 260 return 0;
262 261
263 used = 0; 262 used = 0;
264 rv = 0;
265 263
266 /* Check to see if we can get both channels. */ 264 /* Check to see if we can get both channels. */
267 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); 265 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
@@ -282,63 +280,65 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
282 used++; 280 used++;
283 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); 281 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
284 282
285 if (!used) { 283 if (used)
286 /* Let's see if we can allocate a channel for it. */ 284 return 0;
287 ctp = NULL;
288 chan = 0;
289 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
290 for (i = 0; i < NUM_DBDMA_CHANS; i++)
291 if (chan_tab_ptr[i] == NULL) {
292 /*
293 * If kmalloc fails, it is caught below same
294 * as a channel not available.
295 */
296 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
297 chan_tab_ptr[i] = ctp;
298 break;
299 }
300 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
301
302 if (ctp != NULL) {
303 memset(ctp, 0, sizeof(chan_tab_t));
304 ctp->chan_index = chan = i;
305 dcp = DDMA_CHANNEL_BASE;
306 dcp += (0x0100 * chan);
307 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
308 cp = (au1x_dma_chan_t *)dcp;
309 ctp->chan_src = stp;
310 ctp->chan_dest = dtp;
311 ctp->chan_callback = callback;
312 ctp->chan_callparam = callparam;
313
314 /* Initialize channel configuration. */
315 i = 0;
316 if (stp->dev_intlevel)
317 i |= DDMA_CFG_SED;
318 if (stp->dev_intpolarity)
319 i |= DDMA_CFG_SP;
320 if (dtp->dev_intlevel)
321 i |= DDMA_CFG_DED;
322 if (dtp->dev_intpolarity)
323 i |= DDMA_CFG_DP;
324 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
325 (dtp->dev_flags & DEV_FLAGS_SYNC))
326 i |= DDMA_CFG_SYNC;
327 cp->ddma_cfg = i;
328 au_sync();
329 285
330 /* Return a non-zero value that can be used to 286 /* Let's see if we can allocate a channel for it. */
331 * find the channel information in subsequent 287 ctp = NULL;
332 * operations. 288 chan = 0;
289 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
290 for (i = 0; i < NUM_DBDMA_CHANS; i++)
291 if (chan_tab_ptr[i] == NULL) {
292 /*
293 * If kmalloc fails, it is caught below same
294 * as a channel not available.
333 */ 295 */
334 rv = (u32)(&chan_tab_ptr[chan]); 296 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
335 } else { 297 chan_tab_ptr[i] = ctp;
336 /* Release devices */ 298 break;
337 stp->dev_flags &= ~DEV_FLAGS_INUSE;
338 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
339 } 299 }
300 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
301
302 if (ctp != NULL) {
303 memset(ctp, 0, sizeof(chan_tab_t));
304 ctp->chan_index = chan = i;
305 dcp = DDMA_CHANNEL_BASE;
306 dcp += (0x0100 * chan);
307 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
308 cp = (au1x_dma_chan_t *)dcp;
309 ctp->chan_src = stp;
310 ctp->chan_dest = dtp;
311 ctp->chan_callback = callback;
312 ctp->chan_callparam = callparam;
313
314 /* Initialize channel configuration. */
315 i = 0;
316 if (stp->dev_intlevel)
317 i |= DDMA_CFG_SED;
318 if (stp->dev_intpolarity)
319 i |= DDMA_CFG_SP;
320 if (dtp->dev_intlevel)
321 i |= DDMA_CFG_DED;
322 if (dtp->dev_intpolarity)
323 i |= DDMA_CFG_DP;
324 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
325 (dtp->dev_flags & DEV_FLAGS_SYNC))
326 i |= DDMA_CFG_SYNC;
327 cp->ddma_cfg = i;
328 au_sync();
329
330 /*
331 * Return a non-zero value that can be used to find the channel
332 * information in subsequent operations.
333 */
334 return (u32)(&chan_tab_ptr[chan]);
340 } 335 }
341 return rv; 336
337 /* Release devices */
338 stp->dev_flags &= ~DEV_FLAGS_INUSE;
339 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
340
341 return 0;
342} 342}
343EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); 343EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
344 344
@@ -572,7 +572,7 @@ EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
572 * This updates the source pointer and byte count. Normally used 572 * This updates the source pointer and byte count. Normally used
573 * for memory to fifo transfers. 573 * for memory to fifo transfers.
574 */ 574 */
575u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) 575u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
576{ 576{
577 chan_tab_t *ctp; 577 chan_tab_t *ctp;
578 au1x_ddma_desc_t *dp; 578 au1x_ddma_desc_t *dp;
@@ -598,7 +598,7 @@ u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
598 return 0; 598 return 0;
599 599
600 /* Load up buffer address and byte count. */ 600 /* Load up buffer address and byte count. */
601 dp->dscr_source0 = virt_to_phys(buf); 601 dp->dscr_source0 = buf & ~0UL;
602 dp->dscr_cmd1 = nbytes; 602 dp->dscr_cmd1 = nbytes;
603 /* Check flags */ 603 /* Check flags */
604 if (flags & DDMA_FLAGS_IE) 604 if (flags & DDMA_FLAGS_IE)
@@ -625,14 +625,13 @@ u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
625 /* Return something non-zero. */ 625 /* Return something non-zero. */
626 return nbytes; 626 return nbytes;
627} 627}
628EXPORT_SYMBOL(_au1xxx_dbdma_put_source); 628EXPORT_SYMBOL(au1xxx_dbdma_put_source);
629 629
630/* Put a destination buffer into the DMA ring. 630/* Put a destination buffer into the DMA ring.
631 * This updates the destination pointer and byte count. Normally used 631 * This updates the destination pointer and byte count. Normally used
632 * to place an empty buffer into the ring for fifo to memory transfers. 632 * to place an empty buffer into the ring for fifo to memory transfers.
633 */ 633 */
634u32 634u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
635_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
636{ 635{
637 chan_tab_t *ctp; 636 chan_tab_t *ctp;
638 au1x_ddma_desc_t *dp; 637 au1x_ddma_desc_t *dp;
@@ -662,7 +661,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
662 if (flags & DDMA_FLAGS_NOIE) 661 if (flags & DDMA_FLAGS_NOIE)
663 dp->dscr_cmd0 &= ~DSCR_CMD0_IE; 662 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
664 663
665 dp->dscr_dest0 = virt_to_phys(buf); 664 dp->dscr_dest0 = buf & ~0UL;
666 dp->dscr_cmd1 = nbytes; 665 dp->dscr_cmd1 = nbytes;
667#if 0 666#if 0
668 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", 667 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
@@ -688,7 +687,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
688 /* Return something non-zero. */ 687 /* Return something non-zero. */
689 return nbytes; 688 return nbytes;
690} 689}
691EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); 690EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
692 691
693/* 692/*
694 * Get a destination buffer into the DMA ring. 693 * Get a destination buffer into the DMA ring.
@@ -871,28 +870,6 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
871 return IRQ_RETVAL(1); 870 return IRQ_RETVAL(1);
872} 871}
873 872
874static void au1xxx_dbdma_init(void)
875{
876 int irq_nr;
877
878 dbdma_gptr->ddma_config = 0;
879 dbdma_gptr->ddma_throttle = 0;
880 dbdma_gptr->ddma_inten = 0xffff;
881 au_sync();
882
883#if defined(CONFIG_SOC_AU1550)
884 irq_nr = AU1550_DDMA_INT;
885#elif defined(CONFIG_SOC_AU1200)
886 irq_nr = AU1200_DDMA_INT;
887#else
888 #error Unknown Au1x00 SOC
889#endif
890
891 if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
892 "Au1xxx dbdma", (void *)dbdma_gptr))
893 printk(KERN_ERR "Can't get 1550 dbdma irq");
894}
895
896void au1xxx_dbdma_dump(u32 chanid) 873void au1xxx_dbdma_dump(u32 chanid)
897{ 874{
898 chan_tab_t *ctp; 875 chan_tab_t *ctp;
@@ -906,7 +883,7 @@ void au1xxx_dbdma_dump(u32 chanid)
906 dtp = ctp->chan_dest; 883 dtp = ctp->chan_dest;
907 cp = ctp->chan_ptr; 884 cp = ctp->chan_ptr;
908 885
909 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", 886 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n",
910 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, 887 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
911 dtp - dbdev_tab); 888 dtp - dbdev_tab);
912 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n", 889 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
@@ -1041,4 +1018,38 @@ void au1xxx_dbdma_resume(void)
1041 } 1018 }
1042} 1019}
1043#endif /* CONFIG_PM */ 1020#endif /* CONFIG_PM */
1021
1022static int __init au1xxx_dbdma_init(void)
1023{
1024 int irq_nr, ret;
1025
1026 dbdma_gptr->ddma_config = 0;
1027 dbdma_gptr->ddma_throttle = 0;
1028 dbdma_gptr->ddma_inten = 0xffff;
1029 au_sync();
1030
1031 switch (alchemy_get_cputype()) {
1032 case ALCHEMY_CPU_AU1550:
1033 irq_nr = AU1550_DDMA_INT;
1034 break;
1035 case ALCHEMY_CPU_AU1200:
1036 irq_nr = AU1200_DDMA_INT;
1037 break;
1038 default:
1039 return -ENODEV;
1040 }
1041
1042 ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
1043 "Au1xxx dbdma", (void *)dbdma_gptr);
1044 if (ret)
1045 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1046 else {
1047 dbdma_initialized = 1;
1048 printk(KERN_INFO "Alchemy DBDMA initialized\n");
1049 }
1050
1051 return ret;
1052}
1053subsys_initcall(au1xxx_dbdma_init);
1054
1044#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 1055#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index d6fbda232e6a..d5278877891d 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -29,6 +29,8 @@
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 * 30 *
31 */ 31 */
32
33#include <linux/init.h>
32#include <linux/module.h> 34#include <linux/module.h>
33#include <linux/kernel.h> 35#include <linux/kernel.h>
34#include <linux/errno.h> 36#include <linux/errno.h>
@@ -188,17 +190,14 @@ int request_au1000_dma(int dev_id, const char *dev_str,
188 dev = &dma_dev_table[dev_id]; 190 dev = &dma_dev_table[dev_id];
189 191
190 if (irqhandler) { 192 if (irqhandler) {
191 chan->irq = AU1000_DMA_INT_BASE + i;
192 chan->irq_dev = irq_dev_id; 193 chan->irq_dev = irq_dev_id;
193 ret = request_irq(chan->irq, irqhandler, irqflags, dev_str, 194 ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
194 chan->irq_dev); 195 chan->irq_dev);
195 if (ret) { 196 if (ret) {
196 chan->irq = 0;
197 chan->irq_dev = NULL; 197 chan->irq_dev = NULL;
198 return ret; 198 return ret;
199 } 199 }
200 } else { 200 } else {
201 chan->irq = 0;
202 chan->irq_dev = NULL; 201 chan->irq_dev = NULL;
203 } 202 }
204 203
@@ -226,13 +225,40 @@ void free_au1000_dma(unsigned int dmanr)
226 } 225 }
227 226
228 disable_dma(dmanr); 227 disable_dma(dmanr);
229 if (chan->irq) 228 if (chan->irq_dev)
230 free_irq(chan->irq, chan->irq_dev); 229 free_irq(chan->irq, chan->irq_dev);
231 230
232 chan->irq = 0;
233 chan->irq_dev = NULL; 231 chan->irq_dev = NULL;
234 chan->dev_id = -1; 232 chan->dev_id = -1;
235} 233}
236EXPORT_SYMBOL(free_au1000_dma); 234EXPORT_SYMBOL(free_au1000_dma);
237 235
236static int __init au1000_dma_init(void)
237{
238 int base, i;
239
240 switch (alchemy_get_cputype()) {
241 case ALCHEMY_CPU_AU1000:
242 base = AU1000_DMA_INT_BASE;
243 break;
244 case ALCHEMY_CPU_AU1500:
245 base = AU1500_DMA_INT_BASE;
246 break;
247 case ALCHEMY_CPU_AU1100:
248 base = AU1100_DMA_INT_BASE;
249 break;
250 default:
251 goto out;
252 }
253
254 for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
255 au1000_dma_table[i].irq = base + i;
256
257 printk(KERN_INFO "Alchemy DMA initialized\n");
258
259out:
260 return 0;
261}
262arch_initcall(au1000_dma_init);
263
238#endif /* AU1000 AU1500 AU1100 */ 264#endif /* AU1000 AU1500 AU1100 */
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
index 1bfa91f939f4..c8e1a94d4a95 100644
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -36,7 +36,6 @@
36#include <asm/mach-au1x00/au1000.h> 36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h> 37#include <asm/mach-au1x00/gpio.h>
38 38
39#if !defined(CONFIG_SOC_AU1000)
40static int gpio2_get(struct gpio_chip *chip, unsigned offset) 39static int gpio2_get(struct gpio_chip *chip, unsigned offset)
41{ 40{
42 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); 41 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
@@ -63,7 +62,7 @@ static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
63{ 62{
64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); 63 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
65} 64}
66#endif /* !defined(CONFIG_SOC_AU1000) */ 65
67 66
68static int gpio1_get(struct gpio_chip *chip, unsigned offset) 67static int gpio1_get(struct gpio_chip *chip, unsigned offset)
69{ 68{
@@ -104,7 +103,6 @@ struct gpio_chip alchemy_gpio_chip[] = {
104 .base = ALCHEMY_GPIO1_BASE, 103 .base = ALCHEMY_GPIO1_BASE,
105 .ngpio = ALCHEMY_GPIO1_NUM, 104 .ngpio = ALCHEMY_GPIO1_NUM,
106 }, 105 },
107#if !defined(CONFIG_SOC_AU1000)
108 [1] = { 106 [1] = {
109 .label = "alchemy-gpio2", 107 .label = "alchemy-gpio2",
110 .direction_input = gpio2_direction_input, 108 .direction_input = gpio2_direction_input,
@@ -115,15 +113,13 @@ struct gpio_chip alchemy_gpio_chip[] = {
115 .base = ALCHEMY_GPIO2_BASE, 113 .base = ALCHEMY_GPIO2_BASE,
116 .ngpio = ALCHEMY_GPIO2_NUM, 114 .ngpio = ALCHEMY_GPIO2_NUM,
117 }, 115 },
118#endif
119}; 116};
120 117
121static int __init alchemy_gpiolib_init(void) 118static int __init alchemy_gpiolib_init(void)
122{ 119{
123 gpiochip_add(&alchemy_gpio_chip[0]); 120 gpiochip_add(&alchemy_gpio_chip[0]);
124#if !defined(CONFIG_SOC_AU1000) 121 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
125 gpiochip_add(&alchemy_gpio_chip[1]); 122 gpiochip_add(&alchemy_gpio_chip[1]);
126#endif
127 123
128 return 0; 124 return 0;
129} 125}
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index d670928afcfd..b2821ace4d00 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -39,168 +39,180 @@
39 39
40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); 40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
41 41
42/* NOTE on interrupt priorities: The original writers of this code said:
43 *
44 * Because of the tight timing of SETUP token to reply transactions,
45 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
46 * needs the highest priority.
47 */
48
42/* per-processor fixed function irqs */ 49/* per-processor fixed function irqs */
43struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = { 50struct au1xxx_irqmap {
44 51 int im_irq;
45#if defined(CONFIG_SOC_AU1000) 52 int im_type;
46 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 53 int im_request; /* set 1 to get higher priority */
47 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 54};
48 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 55
49 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 56struct au1xxx_irqmap au1000_irqmap[] __initdata = {
50 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 57 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
51 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 58 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
52 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 59 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
53 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 60 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
54 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 61 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
55 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 62 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
56 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 63 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 64 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 65 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 66 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 67 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
61 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 68 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
62 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 69 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
63 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 70 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
64 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 71 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
65 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 72 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
66 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 73 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
67 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 74 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
68 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 75 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
69 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 76 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
70 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 77 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
71 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 78 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
72 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 79 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
73 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 80 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
74 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 81 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
75 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
76 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
77
78#elif defined(CONFIG_SOC_AU1500)
79
80 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
81 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
82 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
84 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
85 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
86 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
87 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
88 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
89 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
90 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
92 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
93 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
95 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
96 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
97 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
98 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
99 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
100 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
101 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
102 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
104 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
105 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
107 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
108 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
109
110#elif defined(CONFIG_SOC_AU1100)
111
112 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
113 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
114 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
115 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
116 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
121 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
122 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
127 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
128 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
129 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
130 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
131 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
132 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
133 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
134 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 82 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 83 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
139 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 84 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 85 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
141 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 86 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
142 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 87 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
143 88 { -1, },
144#elif defined(CONFIG_SOC_AU1550) 89};
145 90
146 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 91struct au1xxx_irqmap au1500_irqmap[] __initdata = {
147 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 92 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
148 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 93 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 94 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
150 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 95 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 96 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 97 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
153 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 98 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
154 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 99 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 100 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
156 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 101 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 102 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
158 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 103 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
159 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 104 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 105 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
161 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 106 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
162 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 107 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
163 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 108 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
164 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 109 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
165 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 110 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
166 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 111 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
167 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 112 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
168 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 113 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
169 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 114 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
115 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
116 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
117 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
118 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
121 { -1, },
122};
123
124struct au1xxx_irqmap au1100_irqmap[] __initdata = {
125 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
127 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
128 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
129 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
130 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
131 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
132 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
133 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
134 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
138 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
139 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
141 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
142 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
143 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
144 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
145 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
146 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
147 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
148 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
149 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
150 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
151 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
153 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
154 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
156 { -1, },
157};
158
159struct au1xxx_irqmap au1550_irqmap[] __initdata = {
160 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
161 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
162 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
163 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
164 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
165 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
166 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
167 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
168 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
169 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
171 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
172 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
175 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
176 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
177 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
178 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
180 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
181 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
182 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
183 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
170 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 184 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 185 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
172 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 186 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 187 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174 188 { -1, },
175#elif defined(CONFIG_SOC_AU1200) 189};
176 190
177 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 191struct au1xxx_irqmap au1200_irqmap[] __initdata = {
178 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, 192 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
179 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 193 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
180 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 194 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
181 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 195 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
182 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 196 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 197 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 198 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
185 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 199 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 200 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 201 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 202 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
189 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 203 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
190 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 204 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
191 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 205 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
192 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 206 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
193 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 207 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
194 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 208 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
195 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 209 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
196 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 210 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
197 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 211 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
198 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 212 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
199 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 213 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
200 214 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
201#else 215 { -1, },
202#error "Error: Unknown Alchemy SOC"
203#endif
204}; 216};
205 217
206 218
@@ -306,7 +318,7 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
306 * nowhere in the current kernel sources is it disabled. --mlau 318 * nowhere in the current kernel sources is it disabled. --mlau
307 */ 319 */
308#if defined(CONFIG_MIPS_PB1000) 320#if defined(CONFIG_MIPS_PB1000)
309 if (irq_nr == AU1000_GPIO_15) 321 if (irq_nr == AU1000_GPIO15_INT)
310 au_writel(0x4000, PB1000_MDR); /* enable int */ 322 au_writel(0x4000, PB1000_MDR); /* enable int */
311#endif 323#endif
312 au_sync(); 324 au_sync();
@@ -378,11 +390,13 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
378 390
379static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 391static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
380{ 392{
381 unsigned int bit = irq - AU1000_INTC1_INT_BASE; 393 int bit = irq - AU1000_INTC1_INT_BASE;
382 unsigned long wakemsk, flags; 394 unsigned long wakemsk, flags;
383 395
384 /* only GPIO 0-7 can act as wakeup source: */ 396 /* only GPIO 0-7 can act as wakeup source. Fortunately these
385 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) 397 * are wired up identically on all supported variants.
398 */
399 if ((bit < 0) || (bit > 7))
386 return -EINVAL; 400 return -EINVAL;
387 401
388 local_irq_save(flags); 402 local_irq_save(flags);
@@ -504,11 +518,11 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
504asmlinkage void plat_irq_dispatch(void) 518asmlinkage void plat_irq_dispatch(void)
505{ 519{
506 unsigned int pending = read_c0_status() & read_c0_cause(); 520 unsigned int pending = read_c0_status() & read_c0_cause();
507 unsigned long s, off, bit; 521 unsigned long s, off;
508 522
509 if (pending & CAUSEF_IP7) { 523 if (pending & CAUSEF_IP7) {
510 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 524 off = MIPS_CPU_IRQ_BASE + 7;
511 return; 525 goto handle;
512 } else if (pending & CAUSEF_IP2) { 526 } else if (pending & CAUSEF_IP2) {
513 s = IC0_REQ0INT; 527 s = IC0_REQ0INT;
514 off = AU1000_INTC0_INT_BASE; 528 off = AU1000_INTC0_INT_BASE;
@@ -524,58 +538,20 @@ asmlinkage void plat_irq_dispatch(void)
524 } else 538 } else
525 goto spurious; 539 goto spurious;
526 540
527 bit = 0;
528 s = au_readl(s); 541 s = au_readl(s);
529 if (unlikely(!s)) { 542 if (unlikely(!s)) {
530spurious: 543spurious:
531 spurious_interrupt(); 544 spurious_interrupt();
532 return; 545 return;
533 } 546 }
534#ifdef AU1000_USB_DEV_REQ_INT 547 off += __ffs(s);
535 /* 548handle:
536 * Because of the tight timing of SETUP token to reply 549 do_IRQ(off);
537 * transactions, the USB devices-side packet complete
538 * interrupt needs the highest priority.
539 */
540 bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
541 if ((pending & CAUSEF_IP2) && (s & bit)) {
542 do_IRQ(AU1000_USB_DEV_REQ_INT);
543 return;
544 }
545#endif
546 do_IRQ(__ffs(s) + off);
547} 550}
548 551
549/* setup edge/level and assign request 0/1 */ 552static void __init au1000_init_irq(struct au1xxx_irqmap *map)
550void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
551{ 553{
552 unsigned int bit, irq_nr; 554 unsigned int bit, irq_nr;
553
554 while (count--) {
555 irq_nr = map[count].im_irq;
556
557 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
558 (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
559 ((irq_nr < AU1000_INTC1_INT_BASE) ||
560 (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
561 continue;
562
563 if (irq_nr >= AU1000_INTC1_INT_BASE) {
564 bit = irq_nr - AU1000_INTC1_INT_BASE;
565 if (map[count].im_request)
566 au_writel(1 << bit, IC1_ASSIGNCLR);
567 } else {
568 bit = irq_nr - AU1000_INTC0_INT_BASE;
569 if (map[count].im_request)
570 au_writel(1 << bit, IC0_ASSIGNCLR);
571 }
572
573 au1x_ic_settype(irq_nr, map[count].im_type);
574 }
575}
576
577void __init arch_init_irq(void)
578{
579 int i; 555 int i;
580 556
581 /* 557 /*
@@ -585,7 +561,7 @@ void __init arch_init_irq(void)
585 au_writel(0xffffffff, IC0_CFG1CLR); 561 au_writel(0xffffffff, IC0_CFG1CLR);
586 au_writel(0xffffffff, IC0_CFG2CLR); 562 au_writel(0xffffffff, IC0_CFG2CLR);
587 au_writel(0xffffffff, IC0_MASKCLR); 563 au_writel(0xffffffff, IC0_MASKCLR);
588 au_writel(0xffffffff, IC0_ASSIGNSET); 564 au_writel(0xffffffff, IC0_ASSIGNCLR);
589 au_writel(0xffffffff, IC0_WAKECLR); 565 au_writel(0xffffffff, IC0_WAKECLR);
590 au_writel(0xffffffff, IC0_SRCSET); 566 au_writel(0xffffffff, IC0_SRCSET);
591 au_writel(0xffffffff, IC0_FALLINGCLR); 567 au_writel(0xffffffff, IC0_FALLINGCLR);
@@ -596,7 +572,7 @@ void __init arch_init_irq(void)
596 au_writel(0xffffffff, IC1_CFG1CLR); 572 au_writel(0xffffffff, IC1_CFG1CLR);
597 au_writel(0xffffffff, IC1_CFG2CLR); 573 au_writel(0xffffffff, IC1_CFG2CLR);
598 au_writel(0xffffffff, IC1_MASKCLR); 574 au_writel(0xffffffff, IC1_MASKCLR);
599 au_writel(0xffffffff, IC1_ASSIGNSET); 575 au_writel(0xffffffff, IC1_ASSIGNCLR);
600 au_writel(0xffffffff, IC1_WAKECLR); 576 au_writel(0xffffffff, IC1_WAKECLR);
601 au_writel(0xffffffff, IC1_SRCSET); 577 au_writel(0xffffffff, IC1_SRCSET);
602 au_writel(0xffffffff, IC1_FALLINGCLR); 578 au_writel(0xffffffff, IC1_FALLINGCLR);
@@ -619,11 +595,43 @@ void __init arch_init_irq(void)
619 /* 595 /*
620 * Initialize IC0, which is fixed per processor. 596 * Initialize IC0, which is fixed per processor.
621 */ 597 */
622 au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map)); 598 while (map->im_irq != -1) {
599 irq_nr = map->im_irq;
623 600
624 /* Boards can register additional (GPIO-based) IRQs. 601 if (irq_nr >= AU1000_INTC1_INT_BASE) {
625 */ 602 bit = irq_nr - AU1000_INTC1_INT_BASE;
626 board_init_irq(); 603 if (map->im_request)
604 au_writel(1 << bit, IC1_ASSIGNSET);
605 } else {
606 bit = irq_nr - AU1000_INTC0_INT_BASE;
607 if (map->im_request)
608 au_writel(1 << bit, IC0_ASSIGNSET);
609 }
610
611 au1x_ic_settype(irq_nr, map->im_type);
612 ++map;
613 }
627 614
628 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); 615 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
629} 616}
617
618void __init arch_init_irq(void)
619{
620 switch (alchemy_get_cputype()) {
621 case ALCHEMY_CPU_AU1000:
622 au1000_init_irq(au1000_irqmap);
623 break;
624 case ALCHEMY_CPU_AU1500:
625 au1000_init_irq(au1500_irqmap);
626 break;
627 case ALCHEMY_CPU_AU1100:
628 au1000_init_irq(au1100_irqmap);
629 break;
630 case ALCHEMY_CPU_AU1550:
631 au1000_init_irq(au1550_irqmap);
632 break;
633 case ALCHEMY_CPU_AU1200:
634 au1000_init_irq(au1200_irqmap);
635 break;
636 }
637}
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 117f99f70649..2580e77624d2 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -19,39 +19,40 @@
19#include <asm/mach-au1x00/au1xxx.h> 19#include <asm/mach-au1x00/au1xxx.h>
20#include <asm/mach-au1x00/au1xxx_dbdma.h> 20#include <asm/mach-au1x00/au1xxx_dbdma.h>
21#include <asm/mach-au1x00/au1100_mmc.h> 21#include <asm/mach-au1x00/au1100_mmc.h>
22 22#include <asm/mach-au1x00/au1xxx_eth.h>
23#define PORT(_base, _irq) \ 23
24 { \ 24#define PORT(_base, _irq) \
25 .iobase = _base, \ 25 { \
26 .membase = (void __iomem *)_base,\ 26 .mapbase = _base, \
27 .mapbase = CPHYSADDR(_base), \ 27 .irq = _irq, \
28 .irq = _irq, \ 28 .regshift = 2, \
29 .regshift = 2, \ 29 .iotype = UPIO_AU, \
30 .iotype = UPIO_AU, \ 30 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
31 .flags = UPF_SKIP_TEST \ 31 UPF_FIXED_TYPE, \
32 .type = PORT_16550A, \
32 } 33 }
33 34
34static struct plat_serial8250_port au1x00_uart_data[] = { 35static struct plat_serial8250_port au1x00_uart_data[] = {
35#if defined(CONFIG_SERIAL_8250_AU1X00) 36#if defined(CONFIG_SERIAL_8250_AU1X00)
36#if defined(CONFIG_SOC_AU1000) 37#if defined(CONFIG_SOC_AU1000)
37 PORT(UART0_ADDR, AU1000_UART0_INT), 38 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
38 PORT(UART1_ADDR, AU1000_UART1_INT), 39 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
39 PORT(UART2_ADDR, AU1000_UART2_INT), 40 PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),
40 PORT(UART3_ADDR, AU1000_UART3_INT), 41 PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),
41#elif defined(CONFIG_SOC_AU1500) 42#elif defined(CONFIG_SOC_AU1500)
42 PORT(UART0_ADDR, AU1500_UART0_INT), 43 PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),
43 PORT(UART3_ADDR, AU1500_UART3_INT), 44 PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),
44#elif defined(CONFIG_SOC_AU1100) 45#elif defined(CONFIG_SOC_AU1100)
45 PORT(UART0_ADDR, AU1100_UART0_INT), 46 PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),
46 PORT(UART1_ADDR, AU1100_UART1_INT), 47 PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),
47 PORT(UART3_ADDR, AU1100_UART3_INT), 48 PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),
48#elif defined(CONFIG_SOC_AU1550) 49#elif defined(CONFIG_SOC_AU1550)
49 PORT(UART0_ADDR, AU1550_UART0_INT), 50 PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),
50 PORT(UART1_ADDR, AU1550_UART1_INT), 51 PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),
51 PORT(UART3_ADDR, AU1550_UART3_INT), 52 PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),
52#elif defined(CONFIG_SOC_AU1200) 53#elif defined(CONFIG_SOC_AU1200)
53 PORT(UART0_ADDR, AU1200_UART0_INT), 54 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
54 PORT(UART1_ADDR, AU1200_UART1_INT), 55 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
55#endif 56#endif
56#endif /* CONFIG_SERIAL_8250_AU1X00 */ 57#endif /* CONFIG_SERIAL_8250_AU1X00 */
57 { }, 58 { },
@@ -73,8 +74,8 @@ static struct resource au1xxx_usb_ohci_resources[] = {
73 .flags = IORESOURCE_MEM, 74 .flags = IORESOURCE_MEM,
74 }, 75 },
75 [1] = { 76 [1] = {
76 .start = AU1000_USB_HOST_INT, 77 .start = FOR_PLATFORM_C_USB_HOST_INT,
77 .end = AU1000_USB_HOST_INT, 78 .end = FOR_PLATFORM_C_USB_HOST_INT,
78 .flags = IORESOURCE_IRQ, 79 .flags = IORESOURCE_IRQ,
79 }, 80 },
80}; 81};
@@ -132,8 +133,8 @@ static struct resource au1xxx_usb_ehci_resources[] = {
132 .flags = IORESOURCE_MEM, 133 .flags = IORESOURCE_MEM,
133 }, 134 },
134 [1] = { 135 [1] = {
135 .start = AU1000_USB_HOST_INT, 136 .start = AU1200_USB_INT,
136 .end = AU1000_USB_HOST_INT, 137 .end = AU1200_USB_INT,
137 .flags = IORESOURCE_IRQ, 138 .flags = IORESOURCE_IRQ,
138 }, 139 },
139}; 140};
@@ -308,11 +309,6 @@ static struct platform_device au1200_mmc1_device = {
308#endif /* #ifndef CONFIG_MIPS_DB1200 */ 309#endif /* #ifndef CONFIG_MIPS_DB1200 */
309#endif /* #ifdef CONFIG_SOC_AU1200 */ 310#endif /* #ifdef CONFIG_SOC_AU1200 */
310 311
311static struct platform_device au1x00_pcmcia_device = {
312 .name = "au1x00-pcmcia",
313 .id = 0,
314};
315
316/* All Alchemy demoboards with I2C have this #define in their headers */ 312/* All Alchemy demoboards with I2C have this #define in their headers */
317#ifdef SMBUS_PSC_BASE 313#ifdef SMBUS_PSC_BASE
318static struct resource pbdb_smbus_resources[] = { 314static struct resource pbdb_smbus_resources[] = {
@@ -331,10 +327,92 @@ static struct platform_device pbdb_smbus_device = {
331}; 327};
332#endif 328#endif
333 329
330/* Macro to help defining the Ethernet MAC resources */
331#define MAC_RES(_base, _enable, _irq) \
332 { \
333 .start = CPHYSADDR(_base), \
334 .end = CPHYSADDR(_base + 0xffff), \
335 .flags = IORESOURCE_MEM, \
336 }, \
337 { \
338 .start = CPHYSADDR(_enable), \
339 .end = CPHYSADDR(_enable + 0x3), \
340 .flags = IORESOURCE_MEM, \
341 }, \
342 { \
343 .start = _irq, \
344 .end = _irq, \
345 .flags = IORESOURCE_IRQ \
346 }
347
348static struct resource au1xxx_eth0_resources[] = {
349#if defined(CONFIG_SOC_AU1000)
350 MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT),
351#elif defined(CONFIG_SOC_AU1100)
352 MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT),
353#elif defined(CONFIG_SOC_AU1550)
354 MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT),
355#elif defined(CONFIG_SOC_AU1500)
356 MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT),
357#endif
358};
359
360
361static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
362 .phy1_search_mac0 = 1,
363};
364
365static struct platform_device au1xxx_eth0_device = {
366 .name = "au1000-eth",
367 .id = 0,
368 .num_resources = ARRAY_SIZE(au1xxx_eth0_resources),
369 .resource = au1xxx_eth0_resources,
370 .dev.platform_data = &au1xxx_eth0_platform_data,
371};
372
373#ifndef CONFIG_SOC_AU1100
374static struct resource au1xxx_eth1_resources[] = {
375#if defined(CONFIG_SOC_AU1000)
376 MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT),
377#elif defined(CONFIG_SOC_AU1550)
378 MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT),
379#elif defined(CONFIG_SOC_AU1500)
380 MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT),
381#endif
382};
383
384static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
385 .phy1_search_mac0 = 1,
386};
387
388static struct platform_device au1xxx_eth1_device = {
389 .name = "au1000-eth",
390 .id = 1,
391 .num_resources = ARRAY_SIZE(au1xxx_eth1_resources),
392 .resource = au1xxx_eth1_resources,
393 .dev.platform_data = &au1xxx_eth1_platform_data,
394};
395#endif
396
397void __init au1xxx_override_eth_cfg(unsigned int port,
398 struct au1000_eth_platform_data *eth_data)
399{
400 if (!eth_data || port > 1)
401 return;
402
403 if (port == 0)
404 memcpy(&au1xxx_eth0_platform_data, eth_data,
405 sizeof(struct au1000_eth_platform_data));
406#ifndef CONFIG_SOC_AU1100
407 else
408 memcpy(&au1xxx_eth1_platform_data, eth_data,
409 sizeof(struct au1000_eth_platform_data));
410#endif
411}
412
334static struct platform_device *au1xxx_platform_devices[] __initdata = { 413static struct platform_device *au1xxx_platform_devices[] __initdata = {
335 &au1xx0_uart_device, 414 &au1xx0_uart_device,
336 &au1xxx_usb_ohci_device, 415 &au1xxx_usb_ohci_device,
337 &au1x00_pcmcia_device,
338#ifdef CONFIG_FB_AU1100 416#ifdef CONFIG_FB_AU1100
339 &au1100_lcd_device, 417 &au1100_lcd_device,
340#endif 418#endif
@@ -351,6 +429,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
351#ifdef SMBUS_PSC_BASE 429#ifdef SMBUS_PSC_BASE
352 &pbdb_smbus_device, 430 &pbdb_smbus_device,
353#endif 431#endif
432 &au1xxx_eth0_device,
354}; 433};
355 434
356static int __init au1xxx_platform_init(void) 435static int __init au1xxx_platform_init(void)
@@ -362,6 +441,12 @@ static int __init au1xxx_platform_init(void)
362 for (i = 0; au1x00_uart_data[i].flags; i++) 441 for (i = 0; au1x00_uart_data[i].flags; i++)
363 au1x00_uart_data[i].uartclk = uartclk; 442 au1x00_uart_data[i].uartclk = uartclk;
364 443
444#ifndef CONFIG_SOC_AU1100
445 /* Register second MAC if enabled in pinfunc */
446 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
447 platform_device_register(&au1xxx_eth1_device);
448#endif
449
365 return platform_add_devices(au1xxx_platform_devices, 450 return platform_add_devices(au1xxx_platform_devices,
366 ARRAY_SIZE(au1xxx_platform_devices)); 451 ARRAY_SIZE(au1xxx_platform_devices));
367} 452}
diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c
index 18b310b475ca..c29511b11d44 100644
--- a/arch/mips/alchemy/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
@@ -43,29 +43,15 @@ int prom_argc;
43char **prom_argv; 43char **prom_argv;
44char **prom_envp; 44char **prom_envp;
45 45
46char * __init_or_module prom_getcmdline(void)
47{
48 return &(arcs_cmdline[0]);
49}
50
51void prom_init_cmdline(void) 46void prom_init_cmdline(void)
52{ 47{
53 char *cp; 48 int i;
54 int actr;
55
56 actr = 1; /* Always ignore argv[0] */
57 49
58 cp = &(arcs_cmdline[0]); 50 for (i = 1; i < prom_argc; i++) {
59 while (actr < prom_argc) { 51 strlcat(arcs_cmdline, prom_argv[i], COMMAND_LINE_SIZE);
60 strcpy(cp, prom_argv[actr]); 52 if (i < (prom_argc - 1))
61 cp += strlen(prom_argv[actr]); 53 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
62 *cp++ = ' ';
63 actr++;
64 } 54 }
65 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
66 --cp;
67 if (prom_argc > 1)
68 *cp = '\0';
69} 55}
70 56
71char *prom_getenv(char *envname) 57char *prom_getenv(char *envname)
@@ -121,14 +107,12 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
121int prom_get_ethernet_addr(char *ethernet_addr) 107int prom_get_ethernet_addr(char *ethernet_addr)
122{ 108{
123 char *ethaddr_str; 109 char *ethaddr_str;
124 char *argptr;
125 110
126 /* Check the environment variables first */ 111 /* Check the environment variables first */
127 ethaddr_str = prom_getenv("ethaddr"); 112 ethaddr_str = prom_getenv("ethaddr");
128 if (!ethaddr_str) { 113 if (!ethaddr_str) {
129 /* Check command line */ 114 /* Check command line */
130 argptr = prom_getcmdline(); 115 ethaddr_str = strstr(arcs_cmdline, "ethaddr=");
131 ethaddr_str = strstr(argptr, "ethaddr=");
132 if (!ethaddr_str) 116 if (!ethaddr_str)
133 return -1; 117 return -1;
134 118
diff --git a/arch/mips/alchemy/common/puts.c b/arch/mips/alchemy/common/puts.c
deleted file mode 100644
index 55bbe24d45b6..000000000000
--- a/arch/mips/alchemy/common/puts.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Low level UART routines to directly access Alchemy UART.
5 *
6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <asm/mach-au1x00/au1000.h>
31
32#define SERIAL_BASE UART_BASE
33#define SER_CMD 0x7
34#define SER_DATA 0x1
35#define TX_BUSY 0x20
36
37#define TIMEOUT 0xffffff
38#define SLOW_DOWN
39
40static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
41
42#ifdef SLOW_DOWN
43static inline void slow_down(void)
44{
45 int k;
46
47 for (k = 0; k < 10000; k++);
48}
49#else
50#define slow_down()
51#endif
52
53void
54prom_putchar(const unsigned char c)
55{
56 unsigned char ch;
57 int i = 0;
58
59 do {
60 ch = com1[SER_CMD];
61 slow_down();
62 i++;
63 if (i > TIMEOUT)
64 break;
65 } while (0 == (ch & TX_BUSY));
66
67 com1[SER_DATA] = c;
68}
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
deleted file mode 100644
index 4791011e8f92..000000000000
--- a/arch/mips/alchemy/common/reset.c
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Au1xx0 reset routines.
5 *
6 * Copyright 2001, 2006, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/gpio.h>
31
32#include <asm/cacheflush.h>
33#include <asm/mach-au1x00/au1000.h>
34
35void au1000_restart(char *command)
36{
37 /* Set all integrated peripherals to disabled states */
38 extern void board_reset(void);
39 u32 prid = read_c0_prid();
40
41 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
42
43 switch (prid & 0xFF000000) {
44 case 0x00000000: /* Au1000 */
45 au_writel(0x02, 0xb0000010); /* ac97_enable */
46 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
47 asm("sync");
48 au_writel(0x00, 0xb017fffc); /* usbh_enable */
49 au_writel(0x00, 0xb0200058); /* usbd_enable */
50 au_writel(0x00, 0xb0300040); /* ir_enable */
51 au_writel(0x00, 0xb4004104); /* mac dma */
52 au_writel(0x00, 0xb4004114); /* mac dma */
53 au_writel(0x00, 0xb4004124); /* mac dma */
54 au_writel(0x00, 0xb4004134); /* mac dma */
55 au_writel(0x00, 0xb0520000); /* macen0 */
56 au_writel(0x00, 0xb0520004); /* macen1 */
57 au_writel(0x00, 0xb1000008); /* i2s_enable */
58 au_writel(0x00, 0xb1100100); /* uart0_enable */
59 au_writel(0x00, 0xb1200100); /* uart1_enable */
60 au_writel(0x00, 0xb1300100); /* uart2_enable */
61 au_writel(0x00, 0xb1400100); /* uart3_enable */
62 au_writel(0x02, 0xb1600100); /* ssi0_enable */
63 au_writel(0x02, 0xb1680100); /* ssi1_enable */
64 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
65 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
66 au_writel(0x00, 0xb1900028); /* sys_clksrc */
67 au_writel(0x10, 0xb1900060); /* sys_cpupll */
68 au_writel(0x00, 0xb1900064); /* sys_auxpll */
69 au_writel(0x00, 0xb1900100); /* sys_pininputen */
70 break;
71 case 0x01000000: /* Au1500 */
72 au_writel(0x02, 0xb0000010); /* ac97_enable */
73 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
74 asm("sync");
75 au_writel(0x00, 0xb017fffc); /* usbh_enable */
76 au_writel(0x00, 0xb0200058); /* usbd_enable */
77 au_writel(0x00, 0xb4004104); /* mac dma */
78 au_writel(0x00, 0xb4004114); /* mac dma */
79 au_writel(0x00, 0xb4004124); /* mac dma */
80 au_writel(0x00, 0xb4004134); /* mac dma */
81 au_writel(0x00, 0xb1520000); /* macen0 */
82 au_writel(0x00, 0xb1520004); /* macen1 */
83 au_writel(0x00, 0xb1100100); /* uart0_enable */
84 au_writel(0x00, 0xb1400100); /* uart3_enable */
85 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
86 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
87 au_writel(0x00, 0xb1900028); /* sys_clksrc */
88 au_writel(0x10, 0xb1900060); /* sys_cpupll */
89 au_writel(0x00, 0xb1900064); /* sys_auxpll */
90 au_writel(0x00, 0xb1900100); /* sys_pininputen */
91 break;
92 case 0x02000000: /* Au1100 */
93 au_writel(0x02, 0xb0000010); /* ac97_enable */
94 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
95 asm("sync");
96 au_writel(0x00, 0xb017fffc); /* usbh_enable */
97 au_writel(0x00, 0xb0200058); /* usbd_enable */
98 au_writel(0x00, 0xb0300040); /* ir_enable */
99 au_writel(0x00, 0xb4004104); /* mac dma */
100 au_writel(0x00, 0xb4004114); /* mac dma */
101 au_writel(0x00, 0xb4004124); /* mac dma */
102 au_writel(0x00, 0xb4004134); /* mac dma */
103 au_writel(0x00, 0xb0520000); /* macen0 */
104 au_writel(0x00, 0xb1000008); /* i2s_enable */
105 au_writel(0x00, 0xb1100100); /* uart0_enable */
106 au_writel(0x00, 0xb1200100); /* uart1_enable */
107 au_writel(0x00, 0xb1400100); /* uart3_enable */
108 au_writel(0x02, 0xb1600100); /* ssi0_enable */
109 au_writel(0x02, 0xb1680100); /* ssi1_enable */
110 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
111 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
112 au_writel(0x00, 0xb1900028); /* sys_clksrc */
113 au_writel(0x10, 0xb1900060); /* sys_cpupll */
114 au_writel(0x00, 0xb1900064); /* sys_auxpll */
115 au_writel(0x00, 0xb1900100); /* sys_pininputen */
116 break;
117 case 0x03000000: /* Au1550 */
118 au_writel(0x00, 0xb1a00004); /* psc 0 */
119 au_writel(0x00, 0xb1b00004); /* psc 1 */
120 au_writel(0x00, 0xb0a00004); /* psc 2 */
121 au_writel(0x00, 0xb0b00004); /* psc 3 */
122 au_writel(0x00, 0xb017fffc); /* usbh_enable */
123 au_writel(0x00, 0xb0200058); /* usbd_enable */
124 au_writel(0x00, 0xb4004104); /* mac dma */
125 au_writel(0x00, 0xb4004114); /* mac dma */
126 au_writel(0x00, 0xb4004124); /* mac dma */
127 au_writel(0x00, 0xb4004134); /* mac dma */
128 au_writel(0x00, 0xb1520000); /* macen0 */
129 au_writel(0x00, 0xb1520004); /* macen1 */
130 au_writel(0x00, 0xb1100100); /* uart0_enable */
131 au_writel(0x00, 0xb1200100); /* uart1_enable */
132 au_writel(0x00, 0xb1400100); /* uart3_enable */
133 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
134 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
135 au_writel(0x00, 0xb1900028); /* sys_clksrc */
136 au_writel(0x10, 0xb1900060); /* sys_cpupll */
137 au_writel(0x00, 0xb1900064); /* sys_auxpll */
138 au_writel(0x00, 0xb1900100); /* sys_pininputen */
139 break;
140 }
141
142 set_c0_status(ST0_BEV | ST0_ERL);
143 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
144 flush_cache_all();
145 write_c0_wired(0);
146
147 /* Give board a chance to do a hardware reset */
148 board_reset();
149
150 /* Jump to the beggining in case board_reset() is empty */
151 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
152}
153
154void au1000_halt(void)
155{
156#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
157 /* Power off system */
158 printk(KERN_NOTICE "\n** Powering off...\n");
159 au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
160 au_sync();
161 while (1); /* should not get here */
162#else
163 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
164#ifdef CONFIG_MIPS_MIRAGE
165 gpio_direction_output(210, 1);
166#endif
167#ifdef CONFIG_MIPS_DB1200
168 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
169#endif
170#ifdef CONFIG_PM
171 au_sleep();
172
173 /* Should not get here */
174 printk(KERN_ERR "Unable to put CPU in sleep mode\n");
175 while (1);
176#else
177 while (1)
178 __asm__(".set\tmips3\n\t"
179 "wait\n\t"
180 ".set\tmips0");
181#endif
182#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
183}
184
185void au1000_power_off(void)
186{
187 au1000_halt();
188}
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 6184baa56786..561e5da2658b 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -29,18 +29,13 @@
29#include <linux/ioport.h> 29#include <linux/ioport.h>
30#include <linux/jiffies.h> 30#include <linux/jiffies.h>
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/pm.h>
33 32
34#include <asm/mipsregs.h> 33#include <asm/mipsregs.h>
35#include <asm/reboot.h>
36#include <asm/time.h> 34#include <asm/time.h>
37 35
38#include <au1000.h> 36#include <au1000.h>
39 37
40extern void __init board_setup(void); 38extern void __init board_setup(void);
41extern void au1000_restart(char *);
42extern void au1000_halt(void);
43extern void au1000_power_off(void);
44extern void set_cpuspec(void); 39extern void set_cpuspec(void);
45 40
46void __init plat_mem_setup(void) 41void __init plat_mem_setup(void)
@@ -57,10 +52,6 @@ void __init plat_mem_setup(void)
57 /* this is faster than wasting cycles trying to approximate it */ 52 /* this is faster than wasting cycles trying to approximate it */
58 preset_lpj = (est_freq >> 1) / HZ; 53 preset_lpj = (est_freq >> 1) / HZ;
59 54
60 _machine_restart = au1000_restart;
61 _machine_halt = au1000_halt;
62 pm_power_off = au1000_power_off;
63
64 board_setup(); /* board specific setup */ 55 board_setup(); /* board specific setup */
65 56
66 if (au1xxx_cpu_needs_config_od()) 57 if (au1xxx_cpu_needs_config_od())
@@ -78,37 +69,20 @@ void __init plat_mem_setup(void)
78 iomem_resource.end = IOMEM_RESOURCE_END; 69 iomem_resource.end = IOMEM_RESOURCE_END;
79} 70}
80 71
81#if defined(CONFIG_64BIT_PHYS_ADDR) 72#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
82/* This routine should be valid for all Au1x based boards */ 73/* This routine should be valid for all Au1x based boards */
83phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 74phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
84{ 75{
76 u32 start = (u32)Au1500_PCI_MEM_START;
77 u32 end = (u32)Au1500_PCI_MEM_END;
78
85 /* Don't fixup 36-bit addresses */ 79 /* Don't fixup 36-bit addresses */
86 if ((phys_addr >> 32) != 0) 80 if ((phys_addr >> 32) != 0)
87 return phys_addr; 81 return phys_addr;
88 82
89#ifdef CONFIG_PCI 83 /* Check for PCI memory window */
90 { 84 if (phys_addr >= start && (phys_addr + size - 1) <= end)
91 u32 start = (u32)Au1500_PCI_MEM_START; 85 return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
92 u32 end = (u32)Au1500_PCI_MEM_END;
93
94 /* Check for PCI memory window */
95 if (phys_addr >= start && (phys_addr + size - 1) <= end)
96 return (phys_t)
97 ((phys_addr - start) + Au1500_PCI_MEM_START);
98 }
99#endif
100
101 /*
102 * All Au1xx0 SOCs have a PCMCIA controller.
103 * We setup our 32-bit pseudo addresses to be equal to the
104 * 36-bit addr >> 4, to make it easier to check the address
105 * and fix it.
106 * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
107 * The pseudo address we use is 0xF400 0000. Any address over
108 * 0xF400 0000 is a PCMCIA pseudo address.
109 */
110 if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF))
111 return (phys_t)(phys_addr << 4);
112 86
113 /* default nop */ 87 /* default nop */
114 return phys_addr; 88 return phys_addr;
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 379a664809b0..2aecb2fdf982 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> 2 * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
3 * 3 *
4 * Previous incarnations were: 4 * Previous incarnations were:
5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
@@ -85,7 +85,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
85 .name = "rtcmatch2", 85 .name = "rtcmatch2",
86 .features = CLOCK_EVT_FEAT_ONESHOT, 86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .rating = 100, 87 .rating = 100,
88 .irq = AU1000_RTC_MATCH2_INT,
89 .set_next_event = au1x_rtcmatch2_set_next_event, 88 .set_next_event = au1x_rtcmatch2_set_next_event,
90 .set_mode = au1x_rtcmatch2_set_mode, 89 .set_mode = au1x_rtcmatch2_set_mode,
91 .cpumask = cpu_all_mask, 90 .cpumask = cpu_all_mask,
@@ -98,11 +97,13 @@ static struct irqaction au1x_rtcmatch2_irqaction = {
98 .dev_id = &au1x_rtcmatch2_clockdev, 97 .dev_id = &au1x_rtcmatch2_clockdev,
99}; 98};
100 99
101void __init plat_time_init(void) 100static int __init alchemy_time_init(unsigned int m2int)
102{ 101{
103 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; 102 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
104 unsigned long t; 103 unsigned long t;
105 104
105 au1x_rtcmatch2_clockdev.irq = m2int;
106
106 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
107 * has been detected. If so install the rtcmatch2 clocksource, 108 * has been detected. If so install the rtcmatch2 clocksource,
108 * otherwise don't bother. Note that both bits being set is by 109 * otherwise don't bother. Note that both bits being set is by
@@ -148,13 +149,18 @@ void __init plat_time_init(void)
148 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); 149 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
149 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ 150 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
150 clockevents_register_device(cd); 151 clockevents_register_device(cd);
151 setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); 152 setup_irq(m2int, &au1x_rtcmatch2_irqaction);
152 153
153 printk(KERN_INFO "Alchemy clocksource installed\n"); 154 printk(KERN_INFO "Alchemy clocksource installed\n");
154 155
155 return; 156 return 0;
156 157
157cntr_err: 158cntr_err:
159 return -1;
160}
161
162static void __init alchemy_setup_c0timer(void)
163{
158 /* 164 /*
159 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this 165 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
160 * function is called. Because the Alchemy counters are unusable 166 * function is called. Because the Alchemy counters are unusable
@@ -166,3 +172,22 @@ cntr_err:
166 r4k_clockevent_init(); 172 r4k_clockevent_init();
167 init_r4k_clocksource(); 173 init_r4k_clocksource();
168} 174}
175
176static int alchemy_m2inttab[] __initdata = {
177 AU1000_RTC_MATCH2_INT,
178 AU1500_RTC_MATCH2_INT,
179 AU1100_RTC_MATCH2_INT,
180 AU1550_RTC_MATCH2_INT,
181 AU1200_RTC_MATCH2_INT,
182};
183
184void __init plat_time_init(void)
185{
186 int t;
187
188 t = alchemy_get_cputype();
189 if (t == ALCHEMY_CPU_UNKNOWN)
190 alchemy_setup_c0timer();
191 else if (alchemy_time_init(alchemy_m2inttab[t]))
192 alchemy_setup_c0timer();
193}
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 730f9f2b30e8..ecbd37f9ee87 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -2,7 +2,7 @@
2# Alchemy Develboards 2# Alchemy Develboards
3# 3#
4 4
5obj-y += prom.o 5obj-y += prom.o bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/ 7obj-$(CONFIG_MIPS_PB1000) += pb1000/
8obj-$(CONFIG_MIPS_PB1100) += pb1100/ 8obj-$(CONFIG_MIPS_PB1100) += pb1100/
@@ -11,8 +11,10 @@ obj-$(CONFIG_MIPS_PB1500) += pb1500/
11obj-$(CONFIG_MIPS_PB1550) += pb1550/ 11obj-$(CONFIG_MIPS_PB1550) += pb1550/
12obj-$(CONFIG_MIPS_DB1000) += db1x00/ 12obj-$(CONFIG_MIPS_DB1000) += db1x00/
13obj-$(CONFIG_MIPS_DB1100) += db1x00/ 13obj-$(CONFIG_MIPS_DB1100) += db1x00/
14obj-$(CONFIG_MIPS_DB1200) += pb1200/ 14obj-$(CONFIG_MIPS_DB1200) += db1200/
15obj-$(CONFIG_MIPS_DB1500) += db1x00/ 15obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/ 16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ 17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ 18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
19
20EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
new file mode 100644
index 000000000000..3bc4fd2155d7
--- /dev/null
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -0,0 +1,148 @@
1/*
2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
3 *
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address.
7 * All registers are 16bits wide with 32bit spacing.
8 */
9
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/spinlock.h>
13#include <asm/addrspace.h>
14#include <asm/io.h>
15#include <asm/mach-db1x00/bcsr.h>
16
17static struct bcsr_reg {
18 void __iomem *raddr;
19 spinlock_t lock;
20} bcsr_regs[BCSR_CNT];
21
22static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
23static int bcsr_csc_base; /* linux-irq of first cascaded irq */
24
25void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
26{
27 int i;
28
29 bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
30 bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
31
32 bcsr_virt = (void __iomem *)bcsr1_phys;
33
34 for (i = 0; i < BCSR_CNT; i++) {
35 if (i >= BCSR_HEXLEDS)
36 bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
37 (0x04 * (i - BCSR_HEXLEDS));
38 else
39 bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
40 (0x04 * i);
41
42 spin_lock_init(&bcsr_regs[i].lock);
43 }
44}
45
46unsigned short bcsr_read(enum bcsr_id reg)
47{
48 unsigned short r;
49 unsigned long flags;
50
51 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
52 r = __raw_readw(bcsr_regs[reg].raddr);
53 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
54 return r;
55}
56EXPORT_SYMBOL_GPL(bcsr_read);
57
58void bcsr_write(enum bcsr_id reg, unsigned short val)
59{
60 unsigned long flags;
61
62 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
63 __raw_writew(val, bcsr_regs[reg].raddr);
64 wmb();
65 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
66}
67EXPORT_SYMBOL_GPL(bcsr_write);
68
69void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
70{
71 unsigned short r;
72 unsigned long flags;
73
74 spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
75 r = __raw_readw(bcsr_regs[reg].raddr);
76 r &= ~clr;
77 r |= set;
78 __raw_writew(r, bcsr_regs[reg].raddr);
79 wmb();
80 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
81}
82EXPORT_SYMBOL_GPL(bcsr_mod);
83
84/*
85 * DB1200/PB1200 CPLD IRQ muxer
86 */
87static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
88{
89 unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
90
91 for ( ; bisr; bisr &= bisr - 1)
92 generic_handle_irq(bcsr_csc_base + __ffs(bisr));
93}
94
95/* NOTE: both the enable and mask bits must be cleared, otherwise the
96 * CPLD generates tons of spurious interrupts (at least on my DB1200).
97 * -- mlau
98 */
99static void bcsr_irq_mask(unsigned int irq_nr)
100{
101 unsigned short v = 1 << (irq_nr - bcsr_csc_base);
102 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
103 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
104 wmb();
105}
106
107static void bcsr_irq_maskack(unsigned int irq_nr)
108{
109 unsigned short v = 1 << (irq_nr - bcsr_csc_base);
110 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
111 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
112 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
113 wmb();
114}
115
116static void bcsr_irq_unmask(unsigned int irq_nr)
117{
118 unsigned short v = 1 << (irq_nr - bcsr_csc_base);
119 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
120 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
121 wmb();
122}
123
124static struct irq_chip bcsr_irq_type = {
125 .name = "CPLD",
126 .mask = bcsr_irq_mask,
127 .mask_ack = bcsr_irq_maskack,
128 .unmask = bcsr_irq_unmask,
129};
130
131void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
132{
133 unsigned int irq;
134
135 /* mask & disable & ack all */
136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
137 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
138 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
139 wmb();
140
141 bcsr_csc_base = csc_start;
142
143 for (irq = csc_start; irq <= csc_end; irq++)
144 set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
145 handle_level_irq, "level");
146
147 set_irq_chained_handler(hook_irq, bcsr_csc_handler);
148}
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
new file mode 100644
index 000000000000..17840a5e2738
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/Makefile
@@ -0,0 +1 @@
obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
new file mode 100644
index 000000000000..3cb95a98ab31
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -0,0 +1,561 @@
1/*
2 * DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008-2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/platform_device.h>
32#include <linux/serial_8250.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/flash.h>
35#include <linux/smc91x.h>
36
37#include <asm/mach-au1x00/au1100_mmc.h>
38#include <asm/mach-au1x00/au1xxx_dbdma.h>
39#include <asm/mach-au1x00/au1550_spi.h>
40#include <asm/mach-db1x00/bcsr.h>
41#include <asm/mach-db1x00/db1200.h>
42
43#include "../platform.h"
44
45static struct mtd_partition db1200_spiflash_parts[] = {
46 {
47 .name = "DB1200 SPI flash",
48 .offset = 0,
49 .size = MTDPART_SIZ_FULL,
50 },
51};
52
53static struct flash_platform_data db1200_spiflash_data = {
54 .name = "s25fl001",
55 .parts = db1200_spiflash_parts,
56 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
57 .type = "m25p10",
58};
59
60static struct spi_board_info db1200_spi_devs[] __initdata = {
61 {
62 /* TI TMP121AIDBVR temp sensor */
63 .modalias = "tmp121",
64 .max_speed_hz = 2000000,
65 .bus_num = 0,
66 .chip_select = 0,
67 .mode = 0,
68 },
69 {
70 /* Spansion S25FL001D0FMA SPI flash */
71 .modalias = "m25p80",
72 .max_speed_hz = 50000000,
73 .bus_num = 0,
74 .chip_select = 1,
75 .mode = 0,
76 .platform_data = &db1200_spiflash_data,
77 },
78};
79
80static struct i2c_board_info db1200_i2c_devs[] __initdata = {
81 {
82 /* AT24C04-10 I2C eeprom */
83 I2C_BOARD_INFO("24c04", 0x52),
84 },
85 {
86 /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
87 I2C_BOARD_INFO("ne1619", 0x2d),
88 },
89 {
90 /* I2S audio codec WM8731 */
91 I2C_BOARD_INFO("wm8731", 0x1b),
92 },
93};
94
95/**********************************************************************/
96
97static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 struct nand_chip *this = mtd->priv;
101 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
102
103 ioaddr &= 0xffffff00;
104
105 if (ctrl & NAND_CLE) {
106 ioaddr += MEM_STNAND_CMD;
107 } else if (ctrl & NAND_ALE) {
108 ioaddr += MEM_STNAND_ADDR;
109 } else {
110 /* assume we want to r/w real data by default */
111 ioaddr += MEM_STNAND_DATA;
112 }
113 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
114 if (cmd != NAND_CMD_NONE) {
115 __raw_writeb(cmd, this->IO_ADDR_W);
116 wmb();
117 }
118}
119
120static int au1200_nand_device_ready(struct mtd_info *mtd)
121{
122 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
123}
124
125static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
126
127static struct mtd_partition db1200_nand_parts[] = {
128 {
129 .name = "NAND FS 0",
130 .offset = 0,
131 .size = 8 * 1024 * 1024,
132 },
133 {
134 .name = "NAND FS 1",
135 .offset = MTDPART_OFS_APPEND,
136 .size = MTDPART_SIZ_FULL
137 },
138};
139
140struct platform_nand_data db1200_nand_platdata = {
141 .chip = {
142 .nr_chips = 1,
143 .chip_offset = 0,
144 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
145 .partitions = db1200_nand_parts,
146 .chip_delay = 20,
147 .part_probe_types = db1200_part_probes,
148 },
149 .ctrl = {
150 .dev_ready = au1200_nand_device_ready,
151 .cmd_ctrl = au1200_nand_cmd_ctrl,
152 },
153};
154
155static struct resource db1200_nand_res[] = {
156 [0] = {
157 .start = DB1200_NAND_PHYS_ADDR,
158 .end = DB1200_NAND_PHYS_ADDR + 0xff,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device db1200_nand_dev = {
164 .name = "gen_nand",
165 .num_resources = ARRAY_SIZE(db1200_nand_res),
166 .resource = db1200_nand_res,
167 .id = -1,
168 .dev = {
169 .platform_data = &db1200_nand_platdata,
170 }
171};
172
173/**********************************************************************/
174
175static struct smc91x_platdata db1200_eth_data = {
176 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
177 .leda = RPC_LED_100_10,
178 .ledb = RPC_LED_TX_RX,
179};
180
181static struct resource db1200_eth_res[] = {
182 [0] = {
183 .start = DB1200_ETH_PHYS_ADDR,
184 .end = DB1200_ETH_PHYS_ADDR + 0xf,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = DB1200_ETH_INT,
189 .end = DB1200_ETH_INT,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device db1200_eth_dev = {
195 .dev = {
196 .platform_data = &db1200_eth_data,
197 },
198 .name = "smc91x",
199 .id = -1,
200 .num_resources = ARRAY_SIZE(db1200_eth_res),
201 .resource = db1200_eth_res,
202};
203
204/**********************************************************************/
205
206static struct resource db1200_ide_res[] = {
207 [0] = {
208 .start = DB1200_IDE_PHYS_ADDR,
209 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = DB1200_IDE_INT,
214 .end = DB1200_IDE_INT,
215 .flags = IORESOURCE_IRQ,
216 }
217};
218
219static u64 ide_dmamask = DMA_32BIT_MASK;
220
221static struct platform_device db1200_ide_dev = {
222 .name = "au1200-ide",
223 .id = 0,
224 .dev = {
225 .dma_mask = &ide_dmamask,
226 .coherent_dma_mask = DMA_32BIT_MASK,
227 },
228 .num_resources = ARRAY_SIZE(db1200_ide_res),
229 .resource = db1200_ide_res,
230};
231
232/**********************************************************************/
233
234static struct platform_device db1200_rtc_dev = {
235 .name = "rtc-au1xxx",
236 .id = -1,
237};
238
239/**********************************************************************/
240
241/* SD carddetects: they're supposed to be edge-triggered, but ack
242 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
243 * is disabled and its counterpart enabled. The 500ms timeout is
244 * because the carddetect isn't debounced in hardware.
245 */
246static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
247{
248 void(*mmc_cd)(struct mmc_host *, unsigned long);
249
250 if (irq == DB1200_SD0_INSERT_INT) {
251 disable_irq_nosync(DB1200_SD0_INSERT_INT);
252 enable_irq(DB1200_SD0_EJECT_INT);
253 } else {
254 disable_irq_nosync(DB1200_SD0_EJECT_INT);
255 enable_irq(DB1200_SD0_INSERT_INT);
256 }
257
258 /* link against CONFIG_MMC=m */
259 mmc_cd = symbol_get(mmc_detect_change);
260 if (mmc_cd) {
261 mmc_cd(ptr, msecs_to_jiffies(500));
262 symbol_put(mmc_detect_change);
263 }
264
265 return IRQ_HANDLED;
266}
267
268static int db1200_mmc_cd_setup(void *mmc_host, int en)
269{
270 int ret;
271
272 if (en) {
273 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
274 IRQF_DISABLED, "sd_insert", mmc_host);
275 if (ret)
276 goto out;
277
278 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
279 IRQF_DISABLED, "sd_eject", mmc_host);
280 if (ret) {
281 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
282 goto out;
283 }
284
285 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
286 enable_irq(DB1200_SD0_EJECT_INT);
287 else
288 enable_irq(DB1200_SD0_INSERT_INT);
289
290 } else {
291 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
292 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
293 }
294 ret = 0;
295out:
296 return ret;
297}
298
299static void db1200_mmc_set_power(void *mmc_host, int state)
300{
301 if (state) {
302 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
303 msleep(400); /* stabilization time */
304 } else
305 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
306}
307
308static int db1200_mmc_card_readonly(void *mmc_host)
309{
310 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
311}
312
313static int db1200_mmc_card_inserted(void *mmc_host)
314{
315 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
316}
317
318static void db1200_mmcled_set(struct led_classdev *led,
319 enum led_brightness brightness)
320{
321 if (brightness != LED_OFF)
322 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
323 else
324 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
325}
326
327static struct led_classdev db1200_mmc_led = {
328 .brightness_set = db1200_mmcled_set,
329};
330
331/* needed by arch/mips/alchemy/common/platform.c */
332struct au1xmmc_platform_data au1xmmc_platdata[] = {
333 [0] = {
334 .cd_setup = db1200_mmc_cd_setup,
335 .set_power = db1200_mmc_set_power,
336 .card_inserted = db1200_mmc_card_inserted,
337 .card_readonly = db1200_mmc_card_readonly,
338 .led = &db1200_mmc_led,
339 },
340};
341
342/**********************************************************************/
343
344static struct resource au1200_psc0_res[] = {
345 [0] = {
346 .start = PSC0_PHYS_ADDR,
347 .end = PSC0_PHYS_ADDR + 0x000fffff,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AU1200_PSC0_INT,
352 .end = AU1200_PSC0_INT,
353 .flags = IORESOURCE_IRQ,
354 },
355 [2] = {
356 .start = DSCR_CMD0_PSC0_TX,
357 .end = DSCR_CMD0_PSC0_TX,
358 .flags = IORESOURCE_DMA,
359 },
360 [3] = {
361 .start = DSCR_CMD0_PSC0_RX,
362 .end = DSCR_CMD0_PSC0_RX,
363 .flags = IORESOURCE_DMA,
364 },
365};
366
367static struct platform_device db1200_i2c_dev = {
368 .name = "au1xpsc_smbus",
369 .id = 0, /* bus number */
370 .num_resources = ARRAY_SIZE(au1200_psc0_res),
371 .resource = au1200_psc0_res,
372};
373
374static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
375{
376 if (cs)
377 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
378 else
379 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
380}
381
382static struct au1550_spi_info db1200_spi_platdata = {
383 .mainclk_hz = 50000000, /* PSC0 clock */
384 .num_chipselect = 2,
385 .activate_cs = db1200_spi_cs_en,
386};
387
388static u64 spi_dmamask = DMA_32BIT_MASK;
389
390static struct platform_device db1200_spi_dev = {
391 .dev = {
392 .dma_mask = &spi_dmamask,
393 .coherent_dma_mask = DMA_32BIT_MASK,
394 .platform_data = &db1200_spi_platdata,
395 },
396 .name = "au1550-spi",
397 .id = 0, /* bus number */
398 .num_resources = ARRAY_SIZE(au1200_psc0_res),
399 .resource = au1200_psc0_res,
400};
401
402static struct resource au1200_psc1_res[] = {
403 [0] = {
404 .start = PSC1_PHYS_ADDR,
405 .end = PSC1_PHYS_ADDR + 0x000fffff,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = AU1200_PSC1_INT,
410 .end = AU1200_PSC1_INT,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 .start = DSCR_CMD0_PSC1_TX,
415 .end = DSCR_CMD0_PSC1_TX,
416 .flags = IORESOURCE_DMA,
417 },
418 [3] = {
419 .start = DSCR_CMD0_PSC1_RX,
420 .end = DSCR_CMD0_PSC1_RX,
421 .flags = IORESOURCE_DMA,
422 },
423};
424
425static struct platform_device db1200_audio_dev = {
426 /* name assigned later based on switch setting */
427 .id = 1, /* PSC ID */
428 .num_resources = ARRAY_SIZE(au1200_psc1_res),
429 .resource = au1200_psc1_res,
430};
431
432static struct platform_device *db1200_devs[] __initdata = {
433 NULL, /* PSC0, selected by S6.8 */
434 &db1200_ide_dev,
435 &db1200_eth_dev,
436 &db1200_rtc_dev,
437 &db1200_nand_dev,
438 &db1200_audio_dev,
439};
440
441static int __init db1200_dev_init(void)
442{
443 unsigned long pfc;
444 unsigned short sw;
445 int swapped;
446
447 i2c_register_board_info(0, db1200_i2c_devs,
448 ARRAY_SIZE(db1200_i2c_devs));
449 spi_register_board_info(db1200_spi_devs,
450 ARRAY_SIZE(db1200_i2c_devs));
451
452 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
453 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
454 */
455
456 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
457 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
458 * allow to free it without crippling the SPI interface).
459 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
460 * it as an input pin which is pulled high on the boards).
461 */
462 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
463
464 /* switch off OTG VBUS supply */
465 gpio_request(215, "otg-vbus");
466 gpio_direction_output(215, 1);
467
468 printk(KERN_INFO "DB1200 device configuration:\n");
469
470 sw = bcsr_read(BCSR_SWITCHES);
471 if (sw & BCSR_SWITCHES_DIP_8) {
472 db1200_devs[0] = &db1200_i2c_dev;
473 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
474
475 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
476
477 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
478 printk(KERN_INFO " OTG port VBUS supply available!\n");
479 } else {
480 db1200_devs[0] = &db1200_spi_dev;
481 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
482
483 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
484
485 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
486 printk(KERN_INFO " OTG port VBUS supply disabled\n");
487 }
488 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
489 wmb();
490
491 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
492 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
493 */
494 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
495 if (sw == BCSR_SWITCHES_DIP_8) {
496 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
497 db1200_audio_dev.name = "au1xpsc_i2s";
498 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
499 } else {
500 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
501 db1200_audio_dev.name = "au1xpsc_ac97";
502 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
503 }
504
505 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
506 __raw_writel(PSC_SEL_CLK_SERCLK,
507 (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
508 wmb();
509
510 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
511 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
512 PCMCIA_MEM_PHYS_ADDR,
513 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
514 PCMCIA_IO_PHYS_ADDR,
515 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
516 DB1200_PC0_INT,
517 DB1200_PC0_INSERT_INT,
518 /*DB1200_PC0_STSCHG_INT*/0,
519 DB1200_PC0_EJECT_INT,
520 0);
521
522 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
523 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
524 PCMCIA_MEM_PHYS_ADDR + 0x004000000,
525 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
526 PCMCIA_IO_PHYS_ADDR + 0x004000000,
527 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
528 DB1200_PC1_INT,
529 DB1200_PC1_INSERT_INT,
530 /*DB1200_PC1_STSCHG_INT*/0,
531 DB1200_PC1_EJECT_INT,
532 1);
533
534 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
535 db1x_register_norflash(64 << 20, 2, swapped);
536
537 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
538}
539device_initcall(db1200_dev_init);
540
541/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
542int board_au1200fb_panel(void)
543{
544 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
545}
546
547int board_au1200fb_panel_init(void)
548{
549 /* Apply power */
550 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
551 BCSR_BOARD_LCDBL);
552 return 0;
553}
554
555int board_au1200fb_panel_shutdown(void)
556{
557 /* Remove power */
558 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
559 BCSR_BOARD_LCDBL, 0);
560 return 0;
561}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
new file mode 100644
index 000000000000..379536e3abd1
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -0,0 +1,118 @@
1/*
2 * Alchemy/AMD/RMI DB1200 board setup.
3 *
4 * Licensed under the terms outlined in the file COPYING in the root of
5 * this source archive.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <asm/mach-au1x00/au1000.h>
13#include <asm/mach-db1x00/bcsr.h>
14#include <asm/mach-db1x00/db1200.h>
15
16const char *get_system_type(void)
17{
18 return "Alchemy Db1200";
19}
20
21void __init board_setup(void)
22{
23 unsigned long freq0, clksrc, div, pfc;
24 unsigned short whoami;
25
26 bcsr_init(DB1200_BCSR_PHYS_ADDR,
27 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
28
29 whoami = bcsr_read(BCSR_WHOAMI);
30 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
31 " Board-ID %d Daughtercard ID %d\n",
32 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
33
34 /* SMBus/SPI on PSC0, Audio on PSC1 */
35 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
36 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
37 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
38 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
39 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
40 wmb();
41
42 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
43 * CPU clock; all other clock generators off/unused.
44 */
45 div = (get_au1x00_speed() + 25000000) / 50000000;
46 if (div & 1)
47 div++;
48 div = ((div >> 1) - 1) & 0xff;
49
50 freq0 = div << SYS_FC_FRDIV0_BIT;
51 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
52 wmb();
53 freq0 |= SYS_FC_FE0; /* enable F0 */
54 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
55 wmb();
56
57 /* psc0_intclk comes 1:1 from F0 */
58 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
59 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
60 wmb();
61}
62
63/* use the hexleds to count the number of times the cpu has entered
64 * wait, the dots to indicate whether the CPU is currently idle or
65 * active (dots off = sleeping, dots on = working) for cases where
66 * the number doesn't change for a long(er) period of time.
67 */
68static void db1200_wait(void)
69{
70 __asm__(" .set push \n"
71 " .set mips3 \n"
72 " .set noreorder \n"
73 " cache 0x14, 0(%0) \n"
74 " cache 0x14, 32(%0) \n"
75 " cache 0x14, 64(%0) \n"
76 /* dots off: we're about to call wait */
77 " lui $26, 0xb980 \n"
78 " ori $27, $0, 3 \n"
79 " sb $27, 0x18($26) \n"
80 " sync \n"
81 " nop \n"
82 " wait \n"
83 " nop \n"
84 " nop \n"
85 " nop \n"
86 " nop \n"
87 " nop \n"
88 /* dots on: there's work to do, increment cntr */
89 " lui $26, 0xb980 \n"
90 " sb $0, 0x18($26) \n"
91 " lui $26, 0xb9c0 \n"
92 " lb $27, 0($26) \n"
93 " addiu $27, $27, 1 \n"
94 " sb $27, 0($26) \n"
95 " sync \n"
96 " .set pop \n"
97 : : "r" (db1200_wait));
98}
99
100static int __init db1200_arch_init(void)
101{
102 /* GPIO7 is low-level triggered CPLD cascade */
103 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
104 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
105
106 /* do not autoenable these: CPLD has broken edge int handling,
107 * and the CD handler setup requires manual enabling to work
108 * around that.
109 */
110 irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
111 irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
112
113 if (cpu_wait)
114 cpu_wait = db1200_wait;
115
116 return 0;
117}
118arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
index 432241ab8677..613c0c0c8be9 100644
--- a/arch/mips/alchemy/devboards/db1x00/Makefile
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards. 5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6# 6#
7 7
8obj-y := board_setup.o irqmap.o 8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index de30d8ea7176..50c9bef99daa 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -29,59 +29,139 @@
29 29
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/pm.h>
32 34
33#include <asm/mach-au1x00/au1000.h> 35#include <asm/mach-au1x00/au1000.h>
36#include <asm/mach-au1x00/au1xxx_eth.h>
34#include <asm/mach-db1x00/db1x00.h> 37#include <asm/mach-db1x00/db1x00.h>
38#include <asm/mach-db1x00/bcsr.h>
39#include <asm/reboot.h>
35 40
36#include <prom.h> 41#include <prom.h>
37 42
43#ifdef CONFIG_MIPS_DB1500
44char irq_tab_alchemy[][5] __initdata = {
45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
47};
48
49#endif
38 50
39static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 51
52#ifdef CONFIG_MIPS_DB1550
53char irq_tab_alchemy[][5] __initdata = {
54 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
55 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
56 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
57};
58#endif
59
60
61#ifdef CONFIG_MIPS_BOSPORUS
62char irq_tab_alchemy[][5] __initdata = {
63 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
64 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
65 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
66};
67
68/*
69 * Micrel/Kendin 5 port switch attached to MAC0,
70 * MAC0 is associated with PHY address 5 (== WAN port)
71 * MAC1 is not associated with any PHY, since it's connected directly
72 * to the switch.
73 * no interrupts are used
74 */
75static struct au1000_eth_platform_data eth0_pdata = {
76 .phy_static_config = 1,
77 .phy_addr = 5,
78};
79
80static void bosporus_power_off(void)
81{
82 printk(KERN_INFO "It's now safe to turn off power\n");
83 while (1)
84 asm volatile (".set mips3 ; wait ; .set mips0");
85}
40 86
41const char *get_system_type(void) 87const char *get_system_type(void)
42{ 88{
43#ifdef CONFIG_MIPS_BOSPORUS
44 return "Alchemy Bosporus Gateway Reference"; 89 return "Alchemy Bosporus Gateway Reference";
45#else 90}
46 return "Alchemy Db1x00";
47#endif 91#endif
92
93
94#ifdef CONFIG_MIPS_MIRAGE
95char irq_tab_alchemy[][5] __initdata = {
96 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
97 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
98 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
99};
100
101static void mirage_power_off(void)
102{
103 alchemy_gpio_direction_output(210, 1);
104}
105
106const char *get_system_type(void)
107{
108 return "Alchemy Mirage";
109}
110#endif
111
112
113#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
114static void mips_softreset(void)
115{
116 asm volatile ("jr\t%0" : : "r"(0xbfc00000));
48} 117}
49 118
50void board_reset(void) 119#else
120
121const char *get_system_type(void)
51{ 122{
52 /* Hit BCSR.SW_RESET[RESET] */ 123 return "Alchemy Db1x00";
53 bcsr->swreset = 0x0000;
54} 124}
125#endif
126
55 127
56void __init board_setup(void) 128void __init board_setup(void)
57{ 129{
58 u32 pin_func = 0; 130 unsigned long bcsr1, bcsr2;
59 char *argptr; 131 u32 pin_func;
60 132
61 argptr = prom_getcmdline(); 133 bcsr1 = DB1000_BCSR_PHYS_ADDR;
62#ifdef CONFIG_SERIAL_8250_CONSOLE 134 bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
63 argptr = strstr(argptr, "console="); 135
64 if (argptr == NULL) { 136 pin_func = 0;
65 argptr = prom_getcmdline(); 137
66 strcat(argptr, " console=ttyS0,115200"); 138#ifdef CONFIG_MIPS_DB1000
67 } 139 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
140#endif
141#ifdef CONFIG_MIPS_DB1500
142 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
68#endif 143#endif
144#ifdef CONFIG_MIPS_DB1100
145 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
146#endif
147#ifdef CONFIG_MIPS_BOSPORUS
148 au1xxx_override_eth_cfg(0, &eth0_pdata);
69 149
70#ifdef CONFIG_FB_AU1100 150 printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
71 argptr = strstr(argptr, "video=");
72 if (argptr == NULL) {
73 argptr = prom_getcmdline();
74 /* default panel */
75 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
76 }
77#endif 151#endif
152#ifdef CONFIG_MIPS_MIRAGE
153 printk(KERN_INFO "AMD Alchemy Mirage Board\n");
154#endif
155#ifdef CONFIG_MIPS_DB1550
156 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
78 157
79#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) 158 bcsr1 = DB1550_BCSR_PHYS_ADDR;
80 /* au1000 does not support vra, au1500 and au1100 do */ 159 bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
81 strcat(argptr, " au1000_audio=vra");
82 argptr = prom_getcmdline();
83#endif 160#endif
84 161
162 /* initialize board register space */
163 bcsr_init(bcsr1, bcsr2);
164
85 /* Not valid for Au1550 */ 165 /* Not valid for Au1550 */
86#if defined(CONFIG_IRDA) && \ 166#if defined(CONFIG_IRDA) && \
87 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100)) 167 (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
@@ -89,11 +169,10 @@ void __init board_setup(void)
89 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; 169 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
90 au_writel(pin_func, SYS_PINFUNC); 170 au_writel(pin_func, SYS_PINFUNC);
91 /* Power off until the driver is in use */ 171 /* Power off until the driver is in use */
92 bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; 172 bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
93 bcsr->resets |= BCSR_RESETS_IRDA_MODE_OFF; 173 BCSR_RESETS_IRDA_MODE_OFF);
94 au_sync();
95#endif 174#endif
96 bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ 175 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
97 176
98 /* Enable GPIO[31:0] inputs */ 177 /* Enable GPIO[31:0] inputs */
99 alchemy_gpio1_input_enable(); 178 alchemy_gpio1_input_enable();
@@ -120,26 +199,53 @@ void __init board_setup(void)
120 * be part of the audio driver. 199 * be part of the audio driver.
121 */ 200 */
122 alchemy_gpio_direction_output(209, 1); 201 alchemy_gpio_direction_output(209, 1);
123#endif
124
125 au_sync();
126 202
127#ifdef CONFIG_MIPS_DB1000 203 pm_power_off = mirage_power_off;
128 printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); 204 _machine_halt = mirage_power_off;
129#endif 205 _machine_restart = (void(*)(char *))mips_softreset;
130#ifdef CONFIG_MIPS_DB1500
131 printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
132#endif
133#ifdef CONFIG_MIPS_DB1100
134 printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
135#endif 206#endif
207
136#ifdef CONFIG_MIPS_BOSPORUS 208#ifdef CONFIG_MIPS_BOSPORUS
137 printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); 209 pm_power_off = bosporus_power_off;
210 _machine_halt = bosporus_power_off;
211 _machine_restart = (void(*)(char *))mips_softreset;
138#endif 212#endif
139#ifdef CONFIG_MIPS_MIRAGE 213 au_sync();
140 printk(KERN_INFO "AMD Alchemy Mirage Board\n"); 214}
141#endif 215
142#ifdef CONFIG_MIPS_DB1550 216static int __init db1x00_init_irq(void)
143 printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n"); 217{
218#if defined(CONFIG_MIPS_MIRAGE)
219 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
220#elif defined(CONFIG_MIPS_DB1550)
221 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
222 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
223 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
224 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
225 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
226 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
227#elif defined(CONFIG_MIPS_DB1500)
228 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
229 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
230 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
231 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
232 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
233 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
234#elif defined(CONFIG_MIPS_DB1100)
235 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
236 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
237 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
238 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
239 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
240 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
241#elif defined(CONFIG_MIPS_DB1000)
242 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
243 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
244 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
245 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
246 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
247 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
144#endif 248#endif
249 return 0;
145} 250}
251arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/irqmap.c b/arch/mips/alchemy/devboards/db1x00/irqmap.c
deleted file mode 100644
index 0b09025087c6..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/irqmap.c
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/interrupt.h>
31
32#include <asm/mach-au1x00/au1000.h>
33
34#ifdef CONFIG_MIPS_DB1500
35char irq_tab_alchemy[][5] __initdata = {
36 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT371 */
37 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
38};
39#endif
40
41#ifdef CONFIG_MIPS_BOSPORUS
42char irq_tab_alchemy[][5] __initdata = {
43 [11] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 11 - miniPCI */
44 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - SN1741 */
45 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
46};
47#endif
48
49#ifdef CONFIG_MIPS_MIRAGE
50char irq_tab_alchemy[][5] __initdata = {
51 [11] = { -1, INTD, INTX, INTX, INTX }, /* IDSEL 11 - SMI VGX */
52 [12] = { -1, INTX, INTX, INTC, INTX }, /* IDSEL 12 - PNX1300 */
53 [13] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 13 - miniPCI */
54};
55#endif
56
57#ifdef CONFIG_MIPS_DB1550
58char irq_tab_alchemy[][5] __initdata = {
59 [11] = { -1, INTC, INTX, INTX, INTX }, /* IDSEL 11 - on-board HPT371 */
60 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
61 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
62};
63#endif
64
65
66struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
67
68#ifndef CONFIG_MIPS_MIRAGE
69#ifdef CONFIG_MIPS_DB1550
70 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
71 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
72#else
73 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */
74 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */
75 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
76
77 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */
78 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */
79 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
80#endif
81#else
82 { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */
83#endif
84
85};
86
87void __init board_init_irq(void)
88{
89 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
90}
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
new file mode 100644
index 000000000000..978d5ab3d678
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -0,0 +1,118 @@
1/*
2 * DBAu1xxx board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1xxx.h>
25#include <asm/mach-db1x00/bcsr.h>
26#include "../platform.h"
27
28/* DB1xxx PCMCIA interrupt sources:
29 * CD0/1 GPIO0/3
30 * STSCHG0/1 GPIO1/4
31 * CARD0/1 GPIO2/5
32 * Db1550: 0/1, 21/22, 3/5
33 */
34
35#define DB1XXX_HAS_PCMCIA
36#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
37
38#if defined(CONFIG_MIPS_DB1000)
39#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
40#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
41#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
42#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
43#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
44#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
45#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
46#define BOARD_FLASH_WIDTH 4 /* 32-bits */
47#elif defined(CONFIG_MIPS_DB1100)
48#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
49#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
50#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
51#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
52#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
53#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
54#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
55#define BOARD_FLASH_WIDTH 4 /* 32-bits */
56#elif defined(CONFIG_MIPS_DB1500)
57#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
58#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
59#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
60#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
61#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
62#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
63#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
64#define BOARD_FLASH_WIDTH 4 /* 32-bits */
65#elif defined(CONFIG_MIPS_DB1550)
66#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
67#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
68#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
69#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
70#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
71#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
72#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
73#define BOARD_FLASH_WIDTH 4 /* 32-bits */
74#else
75/* other board: no PCMCIA */
76#undef DB1XXX_HAS_PCMCIA
77#undef F_SWAPPED
78#define F_SWAPPED 0
79#if defined(CONFIG_MIPS_BOSPORUS)
80#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */
81#define BOARD_FLASH_WIDTH 2 /* 16-bits */
82#elif defined(CONFIG_MIPS_MIRAGE)
83#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */
84#define BOARD_FLASH_WIDTH 4 /* 32-bits */
85#endif
86#endif
87
88static int __init db1xxx_dev_init(void)
89{
90#ifdef DB1XXX_HAS_PCMCIA
91 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
92 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
93 PCMCIA_MEM_PHYS_ADDR,
94 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
95 PCMCIA_IO_PHYS_ADDR,
96 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
97 DB1XXX_PCMCIA_CARD0,
98 DB1XXX_PCMCIA_CD0,
99 /*DB1XXX_PCMCIA_STSCHG0*/0,
100 0,
101 0);
102
103 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
104 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
105 PCMCIA_MEM_PHYS_ADDR + 0x004000000,
106 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
107 PCMCIA_IO_PHYS_ADDR + 0x004000000,
108 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
109 DB1XXX_PCMCIA_CARD1,
110 DB1XXX_PCMCIA_CD1,
111 /*DB1XXX_PCMCIA_STSCHG1*/0,
112 0,
113 1);
114#endif
115 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
116 return 0;
117}
118device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index cd273545e810..b5311d8a29ab 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -31,11 +31,7 @@
31#include <asm/mach-pb1x00/pb1000.h> 31#include <asm/mach-pb1x00/pb1000.h>
32#include <prom.h> 32#include <prom.h>
33 33
34 34#include "../platform.h"
35struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
36 { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 },
37};
38
39 35
40const char *get_system_type(void) 36const char *get_system_type(void)
41{ 37{
@@ -46,25 +42,14 @@ void board_reset(void)
46{ 42{
47} 43}
48 44
49void __init board_init_irq(void)
50{
51 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
52}
53
54void __init board_setup(void) 45void __init board_setup(void)
55{ 46{
56 u32 pin_func, static_cfg0; 47 u32 pin_func, static_cfg0;
57 u32 sys_freqctrl, sys_clksrc; 48 u32 sys_freqctrl, sys_clksrc;
58 u32 prid = read_c0_prid(); 49 u32 prid = read_c0_prid();
59 50
60#ifdef CONFIG_SERIAL_8250_CONSOLE 51 sys_freqctrl = 0;
61 char *argptr = prom_getcmdline(); 52 sys_clksrc = 0;
62 argptr = strstr(argptr, "console=");
63 if (argptr == NULL) {
64 argptr = prom_getcmdline();
65 strcat(argptr, " console=ttyS0,115200");
66 }
67#endif
68 53
69 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 54 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
70 au_writel(8, SYS_AUXPLL); 55 au_writel(8, SYS_AUXPLL);
@@ -193,3 +178,16 @@ void __init board_setup(void)
193 break; 178 break;
194 } 179 }
195} 180}
181
182static int __init pb1000_init_irq(void)
183{
184 set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
185 return 0;
186}
187arch_initcall(pb1000_init_irq);
188
189static int __init pb1000_device_init(void)
190{
191 return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
192}
193device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
index c586dd7e91dc..7e3756c83fe5 100644
--- a/arch/mips/alchemy/devboards/pb1100/Makefile
+++ b/arch/mips/alchemy/devboards/pb1100/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1100 board. 5# Makefile for the Alchemy Semiconductor Pb1100 board.
6# 6#
7 7
8obj-y := board_setup.o 8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 61263081ef58..c7b4caa81a35 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -29,19 +29,11 @@
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30 30
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1100.h> 32#include <asm/mach-db1x00/bcsr.h>
33 33
34#include <prom.h> 34#include <prom.h>
35 35
36 36
37struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
38 { AU1000_GPIO_9, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */
39 { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */
40 { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */
41 { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */
42};
43
44
45const char *get_system_type(void) 37const char *get_system_type(void)
46{ 38{
47 return "Alchemy Pb1100"; 39 return "Alchemy Pb1100";
@@ -49,43 +41,15 @@ const char *get_system_type(void)
49 41
50void board_reset(void) 42void board_reset(void)
51{ 43{
52 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 44 bcsr_write(BCSR_SYSTEM, 0);
53 au_writel(0x00000000, PB1100_RST_VDDI);
54}
55
56void __init board_init_irq(void)
57{
58 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
59} 45}
60 46
61void __init board_setup(void) 47void __init board_setup(void)
62{ 48{
63 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; 49 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
64 char *argptr;
65
66 argptr = prom_getcmdline();
67#ifdef CONFIG_SERIAL_8250_CONSOLE
68 argptr = strstr(argptr, "console=");
69 if (argptr == NULL) {
70 argptr = prom_getcmdline();
71 strcat(argptr, " console=ttyS0,115200");
72 }
73#endif
74
75#ifdef CONFIG_FB_AU1100
76 argptr = strstr(argptr, "video=");
77 if (argptr == NULL) {
78 argptr = prom_getcmdline();
79 /* default panel */
80 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
81 }
82#endif
83 50
84#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) 51 bcsr_init(DB1000_BCSR_PHYS_ADDR,
85 /* au1000 does not support vra, au1500 and au1100 do */ 52 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
86 strcat(argptr, " au1000_audio=vra");
87 argptr = prom_getcmdline();
88#endif
89 53
90 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 54 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
91 au_writel(8, SYS_AUXPLL); 55 au_writel(8, SYS_AUXPLL);
@@ -155,3 +119,14 @@ void __init board_setup(void)
155 au_sync(); 119 au_sync();
156 } 120 }
157} 121}
122
123static int __init pb1100_init_irq(void)
124{
125 set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
126 set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
127 set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
128 set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
129
130 return 0;
131}
132arch_initcall(pb1100_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
new file mode 100644
index 000000000000..2c8dc29759fd
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -0,0 +1,50 @@
1/*
2 * Pb1100 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22
23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-db1x00/bcsr.h>
25
26#include "../platform.h"
27
28static int __init pb1100_dev_init(void)
29{
30 int swapped;
31
32 /* PCMCIA. single socket, identical to Pb1500 */
33 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
34 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
35 PCMCIA_MEM_PHYS_ADDR,
36 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
37 PCMCIA_IO_PHYS_ADDR,
38 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
39 AU1100_GPIO11_INT, /* card */
40 AU1100_GPIO9_INT, /* insert */
41 /*AU1100_GPIO10_INT*/0, /* stschg */
42 0, /* eject */
43 0); /* id */
44
45 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
46 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
47
48 return 0;
49}
50device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index c8c3a99fb68a..2ea9b02ef09f 100644
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -2,6 +2,6 @@
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. 2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3# 3#
4 4
5obj-y := board_setup.o irqmap.o platform.o 5obj-y := board_setup.o platform.o
6 6
7EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 94e6b7e7753d..3184063f8042 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -25,11 +25,23 @@
25 */ 25 */
26 26
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/interrupt.h>
28#include <linux/sched.h> 29#include <linux/sched.h>
29 30
30#include <prom.h> 31#include <asm/mach-au1x00/au1000.h>
31#include <au1xxx.h> 32#include <asm/mach-db1x00/bcsr.h>
33
34#ifdef CONFIG_MIPS_PB1200
35#include <asm/mach-pb1x00/pb1200.h>
36#endif
37
38#ifdef CONFIG_MIPS_DB1200
39#include <asm/mach-db1x00/db1200.h>
40#define PB1200_INT_BEGIN DB1200_INT_BEGIN
41#define PB1200_INT_END DB1200_INT_END
42#endif
32 43
44#include <prom.h>
33 45
34const char *get_system_type(void) 46const char *get_system_type(void)
35{ 47{
@@ -38,25 +50,15 @@ const char *get_system_type(void)
38 50
39void board_reset(void) 51void board_reset(void)
40{ 52{
41 bcsr->resets = 0; 53 bcsr_write(BCSR_RESETS, 0);
42 bcsr->system = 0; 54 bcsr_write(BCSR_SYSTEM, 0);
43} 55}
44 56
45void __init board_setup(void) 57void __init board_setup(void)
46{ 58{
47 char *argptr; 59 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
48 60 bcsr_init(PB1200_BCSR_PHYS_ADDR,
49 argptr = prom_getcmdline(); 61 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
50#ifdef CONFIG_SERIAL_8250_CONSOLE
51 argptr = strstr(argptr, "console=");
52 if (argptr == NULL) {
53 argptr = prom_getcmdline();
54 strcat(argptr, " console=ttyS0,115200");
55 }
56#endif
57#ifdef CONFIG_FB_AU1200
58 strcat(argptr, " video=au1200fb:panel:bs");
59#endif
60 62
61#if 0 63#if 0
62 { 64 {
@@ -82,7 +84,7 @@ void __init board_setup(void)
82 u32 pin_func; 84 u32 pin_func;
83 85
84 /* Select SMBus in CPLD */ 86 /* Select SMBus in CPLD */
85 bcsr->resets &= ~BCSR_RESETS_PCS0MUX; 87 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
86 88
87 pin_func = au_readl(SYS_PINFUNC); 89 pin_func = au_readl(SYS_PINFUNC);
88 au_sync(); 90 au_sync();
@@ -116,38 +118,54 @@ void __init board_setup(void)
116 118
117 /* 119 /*
118 * The Pb1200 development board uses external MUX for PSC0 to 120 * The Pb1200 development board uses external MUX for PSC0 to
119 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI 121 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
120 */ 122 */
121#ifdef CONFIG_I2C_AU1550 123#ifdef CONFIG_I2C_AU1550
122 bcsr->resets &= ~BCSR_RESETS_PCS0MUX; 124 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
123#endif 125#endif
124 au_sync(); 126 au_sync();
127}
125 128
126#ifdef CONFIG_MIPS_PB1200 129static int __init pb1200_init_irq(void)
127 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); 130{
128#endif 131 /* We have a problem with CPLD rev 3. */
129#ifdef CONFIG_MIPS_DB1200 132 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
130 printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); 133 printk(KERN_ERR "WARNING!!!\n");
131#endif 134 printk(KERN_ERR "WARNING!!!\n");
135 printk(KERN_ERR "WARNING!!!\n");
136 printk(KERN_ERR "WARNING!!!\n");
137 printk(KERN_ERR "WARNING!!!\n");
138 printk(KERN_ERR "WARNING!!!\n");
139 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
140 printk(KERN_ERR "updated to latest revision. This software will\n");
141 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
142 printk(KERN_ERR "WARNING!!!\n");
143 printk(KERN_ERR "WARNING!!!\n");
144 printk(KERN_ERR "WARNING!!!\n");
145 printk(KERN_ERR "WARNING!!!\n");
146 printk(KERN_ERR "WARNING!!!\n");
147 printk(KERN_ERR "WARNING!!!\n");
148 panic("Game over. Your score is 0.");
149 }
150
151 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
152 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
153
154 return 0;
132} 155}
156arch_initcall(pb1200_init_irq);
157
133 158
134int board_au1200fb_panel(void) 159int board_au1200fb_panel(void)
135{ 160{
136 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 161 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
137 int p;
138
139 p = bcsr->switches;
140 p >>= 8;
141 p &= 0x0F;
142 return p;
143} 162}
144 163
145int board_au1200fb_panel_init(void) 164int board_au1200fb_panel_init(void)
146{ 165{
147 /* Apply power */ 166 /* Apply power */
148 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 167 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
149 168 BCSR_BOARD_LCDBL);
150 bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
151 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */ 169 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
152 return 0; 170 return 0;
153} 171}
@@ -155,10 +173,8 @@ int board_au1200fb_panel_init(void)
155int board_au1200fb_panel_shutdown(void) 173int board_au1200fb_panel_shutdown(void)
156{ 174{
157 /* Remove power */ 175 /* Remove power */
158 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 176 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
159 177 BCSR_BOARD_LCDBL, 0);
160 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
161 BCSR_BOARD_LCDBL);
162 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */ 178 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
163 return 0; 179 return 0;
164} 180}
diff --git a/arch/mips/alchemy/devboards/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c
deleted file mode 100644
index fe47498da280..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/irqmap.c
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/interrupt.h>
28
29#include <asm/mach-au1x00/au1000.h>
30
31#ifdef CONFIG_MIPS_PB1200
32#include <asm/mach-pb1x00/pb1200.h>
33#endif
34
35#ifdef CONFIG_MIPS_DB1200
36#include <asm/mach-db1x00/db1200.h>
37#define PB1200_INT_BEGIN DB1200_INT_BEGIN
38#define PB1200_INT_END DB1200_INT_END
39#endif
40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 /* This is external interrupt cascade */
43 { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 },
44};
45
46
47/*
48 * Support for External interrupts on the Pb1200 Development platform.
49 */
50
51static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
52{
53 unsigned short bisr = bcsr->int_status;
54
55 for ( ; bisr; bisr &= bisr - 1)
56 generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
57}
58
59/* NOTE: both the enable and mask bits must be cleared, otherwise the
60 * CPLD generates tons of spurious interrupts (at least on the DB1200).
61 */
62static void pb1200_mask_irq(unsigned int irq_nr)
63{
64 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
65 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
66 au_sync();
67}
68
69static void pb1200_maskack_irq(unsigned int irq_nr)
70{
71 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
72 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
73 bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */
74 au_sync();
75}
76
77static void pb1200_unmask_irq(unsigned int irq_nr)
78{
79 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
80 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
81 au_sync();
82}
83
84static struct irq_chip pb1200_cpld_irq_type = {
85#ifdef CONFIG_MIPS_PB1200
86 .name = "Pb1200 Ext",
87#endif
88#ifdef CONFIG_MIPS_DB1200
89 .name = "Db1200 Ext",
90#endif
91 .mask = pb1200_mask_irq,
92 .mask_ack = pb1200_maskack_irq,
93 .unmask = pb1200_unmask_irq,
94};
95
96void __init board_init_irq(void)
97{
98 unsigned int irq;
99
100 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
101
102#ifdef CONFIG_MIPS_PB1200
103 /* We have a problem with CPLD rev 3. */
104 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
105 printk(KERN_ERR "WARNING!!!\n");
106 printk(KERN_ERR "WARNING!!!\n");
107 printk(KERN_ERR "WARNING!!!\n");
108 printk(KERN_ERR "WARNING!!!\n");
109 printk(KERN_ERR "WARNING!!!\n");
110 printk(KERN_ERR "WARNING!!!\n");
111 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
112 printk(KERN_ERR "updated to latest revision. This software will\n");
113 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
114 printk(KERN_ERR "WARNING!!!\n");
115 printk(KERN_ERR "WARNING!!!\n");
116 printk(KERN_ERR "WARNING!!!\n");
117 printk(KERN_ERR "WARNING!!!\n");
118 printk(KERN_ERR "WARNING!!!\n");
119 printk(KERN_ERR "WARNING!!!\n");
120 panic("Game over. Your score is 0.");
121 }
122#endif
123 /* mask & disable & ack all */
124 bcsr->intclr_mask = 0xffff;
125 bcsr->intclr = 0xffff;
126 bcsr->int_status = 0xffff;
127 au_sync();
128
129 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++)
130 set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
131 handle_level_irq, "level");
132
133 set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler);
134}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index b93dff4a6789..3ef2dceeb796 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -26,27 +26,30 @@
26 26
27#include <asm/mach-au1x00/au1xxx.h> 27#include <asm/mach-au1x00/au1xxx.h>
28#include <asm/mach-au1x00/au1100_mmc.h> 28#include <asm/mach-au1x00/au1100_mmc.h>
29#include <asm/mach-db1x00/bcsr.h>
30
31#include "../platform.h"
29 32
30static int mmc_activity; 33static int mmc_activity;
31 34
32static void pb1200mmc0_set_power(void *mmc_host, int state) 35static void pb1200mmc0_set_power(void *mmc_host, int state)
33{ 36{
34 if (state) 37 if (state)
35 bcsr->board |= BCSR_BOARD_SD0PWR; 38 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
36 else 39 else
37 bcsr->board &= ~BCSR_BOARD_SD0PWR; 40 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
38 41
39 au_sync_delay(1); 42 msleep(1);
40} 43}
41 44
42static int pb1200mmc0_card_readonly(void *mmc_host) 45static int pb1200mmc0_card_readonly(void *mmc_host)
43{ 46{
44 return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; 47 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
45} 48}
46 49
47static int pb1200mmc0_card_inserted(void *mmc_host) 50static int pb1200mmc0_card_inserted(void *mmc_host)
48{ 51{
49 return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; 52 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
50} 53}
51 54
52static void pb1200_mmcled_set(struct led_classdev *led, 55static void pb1200_mmcled_set(struct led_classdev *led,
@@ -54,10 +57,10 @@ static void pb1200_mmcled_set(struct led_classdev *led,
54{ 57{
55 if (brightness != LED_OFF) { 58 if (brightness != LED_OFF) {
56 if (++mmc_activity == 1) 59 if (++mmc_activity == 1)
57 bcsr->disk_leds &= ~(1 << 8); 60 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
58 } else { 61 } else {
59 if (--mmc_activity == 0) 62 if (--mmc_activity == 0)
60 bcsr->disk_leds |= (1 << 8); 63 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
61 } 64 }
62} 65}
63 66
@@ -65,27 +68,25 @@ static struct led_classdev pb1200mmc_led = {
65 .brightness_set = pb1200_mmcled_set, 68 .brightness_set = pb1200_mmcled_set,
66}; 69};
67 70
68#ifndef CONFIG_MIPS_DB1200
69static void pb1200mmc1_set_power(void *mmc_host, int state) 71static void pb1200mmc1_set_power(void *mmc_host, int state)
70{ 72{
71 if (state) 73 if (state)
72 bcsr->board |= BCSR_BOARD_SD1PWR; 74 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
73 else 75 else
74 bcsr->board &= ~BCSR_BOARD_SD1PWR; 76 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
75 77
76 au_sync_delay(1); 78 msleep(1);
77} 79}
78 80
79static int pb1200mmc1_card_readonly(void *mmc_host) 81static int pb1200mmc1_card_readonly(void *mmc_host)
80{ 82{
81 return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; 83 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
82} 84}
83 85
84static int pb1200mmc1_card_inserted(void *mmc_host) 86static int pb1200mmc1_card_inserted(void *mmc_host)
85{ 87{
86 return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; 88 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
87} 89}
88#endif
89 90
90const struct au1xmmc_platform_data au1xmmc_platdata[2] = { 91const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
91 [0] = { 92 [0] = {
@@ -95,7 +96,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
95 .cd_setup = NULL, /* use poll-timer in driver */ 96 .cd_setup = NULL, /* use poll-timer in driver */
96 .led = &pb1200mmc_led, 97 .led = &pb1200mmc_led,
97 }, 98 },
98#ifndef CONFIG_MIPS_DB1200
99 [1] = { 99 [1] = {
100 .set_power = pb1200mmc1_set_power, 100 .set_power = pb1200mmc1_set_power,
101 .card_inserted = pb1200mmc1_card_inserted, 101 .card_inserted = pb1200mmc1_card_inserted,
@@ -103,7 +103,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
103 .cd_setup = NULL, /* use poll-timer in driver */ 103 .cd_setup = NULL, /* use poll-timer in driver */
104 .led = &pb1200mmc_led, 104 .led = &pb1200mmc_led,
105 }, 105 },
106#endif
107}; 106};
108 107
109static struct resource ide_resources[] = { 108static struct resource ide_resources[] = {
@@ -169,8 +168,36 @@ static struct platform_device *board_platform_devices[] __initdata = {
169 168
170static int __init board_register_devices(void) 169static int __init board_register_devices(void)
171{ 170{
171 int swapped;
172
173 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
174 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
175 PCMCIA_MEM_PHYS_ADDR,
176 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
177 PCMCIA_IO_PHYS_ADDR,
178 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
179 PB1200_PC0_INT,
180 PB1200_PC0_INSERT_INT,
181 /*PB1200_PC0_STSCHG_INT*/0,
182 PB1200_PC0_EJECT_INT,
183 0);
184
185 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
186 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
187 PCMCIA_MEM_PHYS_ADDR + 0x008000000,
188 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
189 PCMCIA_IO_PHYS_ADDR + 0x008000000,
190 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
191 PB1200_PC1_INT,
192 PB1200_PC1_INSERT_INT,
193 /*PB1200_PC1_STSCHG_INT*/0,
194 PB1200_PC1_EJECT_INT,
195 1);
196
197 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
198 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
199
172 return platform_add_devices(board_platform_devices, 200 return platform_add_devices(board_platform_devices,
173 ARRAY_SIZE(board_platform_devices)); 201 ARRAY_SIZE(board_platform_devices));
174} 202}
175 203device_initcall(board_register_devices);
176arch_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
index 173b419a7479..e83b151b5b63 100644
--- a/arch/mips/alchemy/devboards/pb1500/Makefile
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1500 board. 5# Makefile for the Alchemy Semiconductor Pb1500 board.
6# 6#
7 7
8obj-y := board_setup.o 8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index d7a56569e7ed..fa9770ac358a 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -29,22 +29,14 @@
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30 30
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-pb1x00/pb1500.h> 32#include <asm/mach-db1x00/bcsr.h>
33 33
34#include <prom.h> 34#include <prom.h>
35 35
36 36
37char irq_tab_alchemy[][5] __initdata = { 37char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */ 38 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */ 39 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
40};
41
42struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
43 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
44 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
45 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
46 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
47 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
48}; 40};
49 41
50 42
@@ -55,35 +47,16 @@ const char *get_system_type(void)
55 47
56void board_reset(void) 48void board_reset(void)
57{ 49{
58 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 50 bcsr_write(BCSR_SYSTEM, 0);
59 au_writel(0x00000000, PB1500_RST_VDDI);
60}
61
62void __init board_init_irq(void)
63{
64 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
65} 51}
66 52
67void __init board_setup(void) 53void __init board_setup(void)
68{ 54{
69 u32 pin_func; 55 u32 pin_func;
70 u32 sys_freqctrl, sys_clksrc; 56 u32 sys_freqctrl, sys_clksrc;
71 char *argptr;
72
73 argptr = prom_getcmdline();
74#ifdef CONFIG_SERIAL_8250_CONSOLE
75 argptr = strstr(argptr, "console=");
76 if (argptr == NULL) {
77 argptr = prom_getcmdline();
78 strcat(argptr, " console=ttyS0,115200");
79 }
80#endif
81 57
82#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) 58 bcsr_init(DB1000_BCSR_PHYS_ADDR,
83 /* au1000 does not support vra, au1500 and au1100 do */ 59 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
84 strcat(argptr, " au1000_audio=vra");
85 argptr = prom_getcmdline();
86#endif
87 60
88 sys_clksrc = sys_freqctrl = pin_func = 0; 61 sys_clksrc = sys_freqctrl = pin_func = 0;
89 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 62 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
@@ -163,3 +136,18 @@ void __init board_setup(void)
163 au_sync(); 136 au_sync();
164 } 137 }
165} 138}
139
140static int __init pb1500_init_irq(void)
141{
142 set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
143 set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
144 set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
145 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
146 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
147 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
148 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
149 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
150
151 return 0;
152}
153arch_initcall(pb1500_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
new file mode 100644
index 000000000000..d443bc7aa76e
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -0,0 +1,49 @@
1/*
2 * Pb1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-db1x00/bcsr.h>
24
25#include "../platform.h"
26
27static int __init pb1500_dev_init(void)
28{
29 int swapped;
30
31 /* PCMCIA. single socket, identical to Pb1500 */
32 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
33 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
34 PCMCIA_MEM_PHYS_ADDR,
35 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
36 PCMCIA_IO_PHYS_ADDR,
37 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
38 AU1500_GPIO11_INT, /* card */
39 AU1500_GPIO9_INT, /* insert */
40 /*AU1500_GPIO10_INT*/0, /* stschg */
41 0, /* eject */
42 0); /* id */
43
44 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
45 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
46
47 return 0;
48}
49device_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
index cff95bcdb2ca..9661b6ec5dd3 100644
--- a/arch/mips/alchemy/devboards/pb1550/Makefile
+++ b/arch/mips/alchemy/devboards/pb1550/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1550 board. 5# Makefile for the Alchemy Semiconductor Pb1550 board.
6# 6#
7 7
8obj-y := board_setup.o 8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b6e9e7d247a3..1e8fb3ddd726 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -32,18 +32,15 @@
32 32
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34#include <asm/mach-pb1x00/pb1550.h> 34#include <asm/mach-pb1x00/pb1550.h>
35#include <asm/mach-db1x00/bcsr.h>
36#include <asm/mach-au1x00/gpio.h>
35 37
36#include <prom.h> 38#include <prom.h>
37 39
38 40
39char irq_tab_alchemy[][5] __initdata = { 41char irq_tab_alchemy[][5] __initdata = {
40 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */ 42 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
41 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */ 43 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
42};
43
44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
45 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
46 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
47}; 44};
48 45
49const char *get_system_type(void) 46const char *get_system_type(void)
@@ -53,28 +50,17 @@ const char *get_system_type(void)
53 50
54void board_reset(void) 51void board_reset(void)
55{ 52{
56 /* Hit BCSR.SYSTEM[RESET] */ 53 bcsr_write(BCSR_SYSTEM, 0);
57 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
58}
59
60void __init board_init_irq(void)
61{
62 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
63} 54}
64 55
65void __init board_setup(void) 56void __init board_setup(void)
66{ 57{
67 u32 pin_func; 58 u32 pin_func;
68 59
69#ifdef CONFIG_SERIAL_8250_CONSOLE 60 bcsr_init(PB1550_BCSR_PHYS_ADDR,
70 char *argptr; 61 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
71 argptr = prom_getcmdline(); 62
72 argptr = strstr(argptr, "console="); 63 alchemy_gpio2_enable();
73 if (argptr == NULL) {
74 argptr = prom_getcmdline();
75 strcat(argptr, " console=ttyS0,115200");
76 }
77#endif
78 64
79 /* 65 /*
80 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, 66 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
@@ -85,8 +71,21 @@ void __init board_setup(void)
85 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; 71 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
86 au_writel(pin_func, SYS_PINFUNC); 72 au_writel(pin_func, SYS_PINFUNC);
87 73
88 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */ 74 bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
89 au_sync();
90 75
91 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n"); 76 printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
92} 77}
78
79static int __init pb1550_init_irq(void)
80{
81 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
82 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
83 set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
84
85 /* enable both PCMCIA card irqs in the shared line */
86 alchemy_gpio2_enable_int(201);
87 alchemy_gpio2_enable_int(202);
88
89 return 0;
90}
91arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
new file mode 100644
index 000000000000..d7150d0f49c0
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -0,0 +1,69 @@
1/*
2 * Pb1550 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22
23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-pb1x00/pb1550.h>
25#include <asm/mach-db1x00/bcsr.h>
26
27#include "../platform.h"
28
29static int __init pb1550_dev_init(void)
30{
31 int swapped;
32
33 /* Pb1550, like all others, also has statuschange irqs; however they're
34 * wired up on one of the Au1550's shared GPIO201_205 line, which also
35 * services the PCMCIA card interrupts. So we ignore statuschange and
36 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
37 * drivers are used to shared irqs and b) statuschange isn't really use-
38 * ful anyway.
39 */
40 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
41 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
42 PCMCIA_MEM_PHYS_ADDR,
43 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 PCMCIA_IO_PHYS_ADDR,
45 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
46 AU1550_GPIO201_205_INT,
47 AU1550_GPIO0_INT,
48 0,
49 0,
50 0);
51
52 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
53 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
54 PCMCIA_MEM_PHYS_ADDR + 0x008000000,
55 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
56 PCMCIA_IO_PHYS_ADDR + 0x008000000,
57 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
58 AU1550_GPIO201_205_INT,
59 AU1550_GPIO1_INT,
60 0,
61 0,
62 1);
63
64 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
65 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
66
67 return 0;
68}
69device_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
new file mode 100644
index 000000000000..49a4b3244d8e
--- /dev/null
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -0,0 +1,222 @@
1/*
2 * devoard misc stuff.
3 */
4
5#include <linux/init.h>
6#include <linux/mtd/mtd.h>
7#include <linux/mtd/map.h>
8#include <linux/mtd/physmap.h>
9#include <linux/slab.h>
10#include <linux/platform_device.h>
11#include <linux/pm.h>
12
13#include <asm/reboot.h>
14#include <asm/mach-db1x00/bcsr.h>
15
16static void db1x_power_off(void)
17{
18 bcsr_write(BCSR_RESETS, 0);
19 bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET);
20}
21
22static void db1x_reset(char *c)
23{
24 bcsr_write(BCSR_RESETS, 0);
25 bcsr_write(BCSR_SYSTEM, 0);
26}
27
28static int __init db1x_poweroff_setup(void)
29{
30 if (!pm_power_off)
31 pm_power_off = db1x_power_off;
32 if (!_machine_halt)
33 _machine_halt = db1x_power_off;
34 if (!_machine_restart)
35 _machine_restart = db1x_reset;
36
37 return 0;
38}
39late_initcall(db1x_poweroff_setup);
40
41/* register a pcmcia socket */
42int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
43 phys_addr_t pcmcia_attr_end,
44 phys_addr_t pcmcia_mem_start,
45 phys_addr_t pcmcia_mem_end,
46 phys_addr_t pcmcia_io_start,
47 phys_addr_t pcmcia_io_end,
48 int card_irq,
49 int cd_irq,
50 int stschg_irq,
51 int eject_irq,
52 int id)
53{
54 int cnt, i, ret;
55 struct resource *sr;
56 struct platform_device *pd;
57
58 cnt = 5;
59 if (eject_irq)
60 cnt++;
61 if (stschg_irq)
62 cnt++;
63
64 sr = kzalloc(sizeof(struct resource) * cnt, GFP_KERNEL);
65 if (!sr)
66 return -ENOMEM;
67
68 pd = platform_device_alloc("db1xxx_pcmcia", id);
69 if (!pd) {
70 ret = -ENOMEM;
71 goto out;
72 }
73
74 sr[0].name = "pcmcia-attr";
75 sr[0].flags = IORESOURCE_MEM;
76 sr[0].start = pcmcia_attr_start;
77 sr[0].end = pcmcia_attr_end;
78
79 sr[1].name = "pcmcia-mem";
80 sr[1].flags = IORESOURCE_MEM;
81 sr[1].start = pcmcia_mem_start;
82 sr[1].end = pcmcia_mem_end;
83
84 sr[2].name = "pcmcia-io";
85 sr[2].flags = IORESOURCE_MEM;
86 sr[2].start = pcmcia_io_start;
87 sr[2].end = pcmcia_io_end;
88
89 sr[3].name = "insert";
90 sr[3].flags = IORESOURCE_IRQ;
91 sr[3].start = sr[3].end = cd_irq;
92
93 sr[4].name = "card";
94 sr[4].flags = IORESOURCE_IRQ;
95 sr[4].start = sr[4].end = card_irq;
96
97 i = 5;
98 if (stschg_irq) {
99 sr[i].name = "stschg";
100 sr[i].flags = IORESOURCE_IRQ;
101 sr[i].start = sr[i].end = stschg_irq;
102 i++;
103 }
104 if (eject_irq) {
105 sr[i].name = "eject";
106 sr[i].flags = IORESOURCE_IRQ;
107 sr[i].start = sr[i].end = eject_irq;
108 }
109
110 pd->resource = sr;
111 pd->num_resources = cnt;
112
113 ret = platform_device_add(pd);
114 if (!ret)
115 return 0;
116
117 platform_device_put(pd);
118out:
119 kfree(sr);
120 return ret;
121}
122
123#define YAMON_SIZE 0x00100000
124#define YAMON_ENV_SIZE 0x00040000
125
126int __init db1x_register_norflash(unsigned long size, int width,
127 int swapped)
128{
129 struct physmap_flash_data *pfd;
130 struct platform_device *pd;
131 struct mtd_partition *parts;
132 struct resource *res;
133 int ret, i;
134
135 if (size < (8 * 1024 * 1024))
136 return -EINVAL;
137
138 ret = -ENOMEM;
139 parts = kzalloc(sizeof(struct mtd_partition) * 5, GFP_KERNEL);
140 if (!parts)
141 goto out;
142
143 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
144 if (!res)
145 goto out1;
146
147 pfd = kzalloc(sizeof(struct physmap_flash_data), GFP_KERNEL);
148 if (!pfd)
149 goto out2;
150
151 pd = platform_device_alloc("physmap-flash", 0);
152 if (!pd)
153 goto out3;
154
155 /* NOR flash ends at 0x20000000, regardless of size */
156 res->start = 0x20000000 - size;
157 res->end = 0x20000000 - 1;
158 res->flags = IORESOURCE_MEM;
159
160 /* partition setup. Most Develboards have a switch which allows
161 * to swap the physical locations of the 2 NOR flash banks.
162 */
163 i = 0;
164 if (!swapped) {
165 /* first NOR chip */
166 parts[i].offset = 0;
167 parts[i].name = "User FS";
168 parts[i].size = size / 2;
169 i++;
170 }
171
172 parts[i].offset = MTDPART_OFS_APPEND;
173 parts[i].name = "User FS 2";
174 parts[i].size = (size / 2) - (0x20000000 - 0x1fc00000);
175 i++;
176
177 parts[i].offset = MTDPART_OFS_APPEND;
178 parts[i].name = "YAMON";
179 parts[i].size = YAMON_SIZE;
180 parts[i].mask_flags = MTD_WRITEABLE;
181 i++;
182
183 parts[i].offset = MTDPART_OFS_APPEND;
184 parts[i].name = "raw kernel";
185 parts[i].size = 0x00400000 - YAMON_SIZE - YAMON_ENV_SIZE;
186 i++;
187
188 parts[i].offset = MTDPART_OFS_APPEND;
189 parts[i].name = "YAMON Env";
190 parts[i].size = YAMON_ENV_SIZE;
191 parts[i].mask_flags = MTD_WRITEABLE;
192 i++;
193
194 if (swapped) {
195 parts[i].offset = MTDPART_OFS_APPEND;
196 parts[i].name = "User FS";
197 parts[i].size = size / 2;
198 i++;
199 }
200
201 pfd->width = width;
202 pfd->parts = parts;
203 pfd->nr_parts = 5;
204
205 pd->dev.platform_data = pfd;
206 pd->resource = res;
207 pd->num_resources = 1;
208
209 ret = platform_device_add(pd);
210 if (!ret)
211 return ret;
212
213 platform_device_put(pd);
214out3:
215 kfree(pfd);
216out2:
217 kfree(res);
218out1:
219 kfree(parts);
220out:
221 return ret;
222}
diff --git a/arch/mips/alchemy/devboards/platform.h b/arch/mips/alchemy/devboards/platform.h
new file mode 100644
index 000000000000..5ac055d2cda9
--- /dev/null
+++ b/arch/mips/alchemy/devboards/platform.h
@@ -0,0 +1,21 @@
1#ifndef _DEVBOARD_PLATFORM_H_
2#define _DEVBOARD_PLATFORM_H_
3
4#include <linux/init.h>
5
6int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
7 phys_addr_t pcmcia_attr_len,
8 phys_addr_t pcmcia_mem_start,
9 phys_addr_t pcmcia_mem_end,
10 phys_addr_t pcmcia_io_start,
11 phys_addr_t pcmcia_io_end,
12 int card_irq,
13 int cd_irq,
14 int stschg_irq,
15 int eject_irq,
16 int id);
17
18int __init db1x_register_norflash(unsigned long size, int width,
19 int swapped);
20
21#endif
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index 632f9862a0fb..4bbd3133e451 100644
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -10,6 +10,7 @@
10#include <linux/sysfs.h> 10#include <linux/sysfs.h>
11#include <asm/mach-au1x00/au1000.h> 11#include <asm/mach-au1x00/au1000.h>
12#include <asm/mach-au1x00/gpio.h> 12#include <asm/mach-au1x00/gpio.h>
13#include <asm/mach-db1x00/bcsr.h>
13 14
14/* 15/*
15 * Generic suspend userspace interface for Alchemy development boards. 16 * Generic suspend userspace interface for Alchemy development boards.
@@ -26,6 +27,20 @@ static unsigned long db1x_pm_last_wakesrc;
26 27
27static int db1x_pm_enter(suspend_state_t state) 28static int db1x_pm_enter(suspend_state_t state)
28{ 29{
30 unsigned short bcsrs[16];
31 int i, j, hasint;
32
33 /* save CPLD regs */
34 hasint = bcsr_read(BCSR_WHOAMI);
35 hasint = BCSR_WHOAMI_BOARD(hasint) >= BCSR_WHOAMI_DB1200;
36 j = (hasint) ? BCSR_MASKSET : BCSR_SYSTEM;
37
38 for (i = BCSR_STATUS; i <= j; i++)
39 bcsrs[i] = bcsr_read(i);
40
41 /* shut off hexleds */
42 bcsr_write(BCSR_HEXCLEAR, 3);
43
29 /* enable GPIO based wakeup */ 44 /* enable GPIO based wakeup */
30 alchemy_gpio1_input_enable(); 45 alchemy_gpio1_input_enable();
31 46
@@ -52,6 +67,23 @@ static int db1x_pm_enter(suspend_state_t state)
52 /* ...and now the sandman can come! */ 67 /* ...and now the sandman can come! */
53 au_sleep(); 68 au_sleep();
54 69
70
71 /* restore CPLD regs */
72 for (i = BCSR_STATUS; i <= BCSR_SYSTEM; i++)
73 bcsr_write(i, bcsrs[i]);
74
75 /* restore CPLD int registers */
76 if (hasint) {
77 bcsr_write(BCSR_INTCLR, 0xffff);
78 bcsr_write(BCSR_MASKCLR, 0xffff);
79 bcsr_write(BCSR_INTSTAT, 0xffff);
80 bcsr_write(BCSR_INTSET, bcsrs[BCSR_INTSET]);
81 bcsr_write(BCSR_MASKSET, bcsrs[BCSR_MASKSET]);
82 }
83
84 /* light up hexleds */
85 bcsr_write(BCSR_HEXCLEAR, 0);
86
55 return 0; 87 return 0;
56} 88}
57 89
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index 0042bd6b1d7d..b30df5c97ad3 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -60,3 +60,8 @@ void __init prom_init(void)
60 strict_strtoul(memsize_str, 0, &memsize); 60 strict_strtoul(memsize_str, 0, &memsize);
61 add_memory_region(0, memsize, BOOT_MEM_RAM); 61 add_memory_region(0, memsize, BOOT_MEM_RAM);
62} 62}
63
64void prom_putchar(unsigned char c)
65{
66 alchemy_uart_putchar(UART0_PHYS_ADDR, c);
67}
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 7c67b3d33bec..4a53815b3c6c 100644
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -6,7 +6,7 @@
6# Makefile for 4G Systems MTX-1 board. 6# Makefile for 4G Systems MTX-1 board.
7# 7#
8 8
9lib-y := init.o board_setup.o irqmap.o 9lib-y := init.o board_setup.o
10obj-y := platform.o 10obj-y := platform.o
11 11
12EXTRA_CFLAGS += -Werror 12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 45b61c9b82b9..a9f0336e1f1f 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -30,32 +30,43 @@
30 30
31#include <linux/gpio.h> 31#include <linux/gpio.h>
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/pm.h>
33 35
36#include <asm/reboot.h>
34#include <asm/mach-au1x00/au1000.h> 37#include <asm/mach-au1x00/au1000.h>
35 38
36#include <prom.h> 39#include <prom.h>
37 40
41char irq_tab_alchemy[][5] __initdata = {
42 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
43 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
44 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
45 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
46 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
47 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
48 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
49 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
50};
51
38extern int (*board_pci_idsel)(unsigned int devsel, int assert); 52extern int (*board_pci_idsel)(unsigned int devsel, int assert);
39int mtx1_pci_idsel(unsigned int devsel, int assert); 53int mtx1_pci_idsel(unsigned int devsel, int assert);
40 54
41void board_reset(void) 55static void mtx1_reset(char *c)
42{ 56{
43 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 57 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
44 au_writel(0x00000000, 0xAE00001C); 58 au_writel(0x00000000, 0xAE00001C);
45} 59}
46 60
47void __init board_setup(void) 61static void mtx1_power_off(void)
48{ 62{
49#ifdef CONFIG_SERIAL_8250_CONSOLE 63 printk(KERN_ALERT "It's now safe to remove power\n");
50 char *argptr; 64 while (1)
51 argptr = prom_getcmdline(); 65 asm volatile (".set mips3 ; wait ; .set mips1");
52 argptr = strstr(argptr, "console="); 66}
53 if (argptr == NULL) {
54 argptr = prom_getcmdline();
55 strcat(argptr, " console=ttyS0,115200");
56 }
57#endif
58 67
68void __init board_setup(void)
69{
59 alchemy_gpio2_enable(); 70 alchemy_gpio2_enable();
60 71
61#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 72#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
@@ -86,6 +97,10 @@ void __init board_setup(void)
86 alchemy_gpio_direction_output(211, 1); /* green on */ 97 alchemy_gpio_direction_output(211, 1); /* green on */
87 alchemy_gpio_direction_output(212, 0); /* red off */ 98 alchemy_gpio_direction_output(212, 0); /* red off */
88 99
100 pm_power_off = mtx1_power_off;
101 _machine_halt = mtx1_power_off;
102 _machine_restart = mtx1_reset;
103
89 printk(KERN_INFO "4G Systems MTX-1 Board\n"); 104 printk(KERN_INFO "4G Systems MTX-1 Board\n");
90} 105}
91 106
@@ -109,3 +124,15 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
109 au_sync_udelay(1); 124 au_sync_udelay(1);
110 return 1; 125 return 1;
111} 126}
127
128static int __init mtx1_init_irq(void)
129{
130 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
131 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
132 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
133 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
134 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
135
136 return 0;
137}
138arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index 5e871c8d9e96..f8d25575fa05 100644
--- a/arch/mips/alchemy/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -32,6 +32,7 @@
32#include <linux/init.h> 32#include <linux/init.h>
33 33
34#include <asm/bootinfo.h> 34#include <asm/bootinfo.h>
35#include <asm/mach-au1x00/au1000.h>
35 36
36#include <prom.h> 37#include <prom.h>
37 38
@@ -58,3 +59,8 @@ void __init prom_init(void)
58 strict_strtoul(memsize_str, 0, &memsize); 59 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 60 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 61}
62
63void prom_putchar(unsigned char c)
64{
65 alchemy_uart_putchar(UART0_PHYS_ADDR, c);
66}
diff --git a/arch/mips/alchemy/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c
deleted file mode 100644
index f1ab12ab3433..000000000000
--- a/arch/mips/alchemy/mtx-1/irqmap.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <asm/mach-au1x00/au1000.h>
32
33char irq_tab_alchemy[][5] __initdata = {
34 [0] = { -1, INTA, INTA, INTX, INTX }, /* IDSEL 00 - AdapterA-Slot0 (top) */
35 [1] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
36 [2] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 02 - AdapterB-Slot0 (top) */
37 [3] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
38 [4] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 04 - AdapterC-Slot0 (top) */
39 [5] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
40 [6] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 06 - AdapterD-Slot0 (top) */
41 [7] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
42};
43
44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
45 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
46 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
47 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
48 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
49 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
50};
51
52
53void __init board_init_irq(void)
54{
55 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
56}
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index db3c526f64d8..4dc81d794cb8 100644
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -5,4 +5,6 @@
5# Makefile for MyCable XXS1500 board. 5# Makefile for MyCable XXS1500 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8lib-y := init.o board_setup.o platform.o
9
10EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 4de2d48caed8..47b42927607b 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -25,31 +25,35 @@
25 25
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/interrupt.h>
28#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/pm.h>
29 31
32#include <asm/reboot.h>
30#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
31 34
32#include <prom.h> 35#include <prom.h>
33 36
34void board_reset(void) 37static void xxs1500_reset(char *c)
35{ 38{
36 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 39 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
37 au_writel(0x00000000, 0xAE00001C); 40 au_writel(0x00000000, 0xAE00001C);
38} 41}
39 42
43static void xxs1500_power_off(void)
44{
45 printk(KERN_ALERT "It's now safe to remove power\n");
46 while (1)
47 asm volatile (".set mips3 ; wait ; .set mips1");
48}
49
40void __init board_setup(void) 50void __init board_setup(void)
41{ 51{
42 u32 pin_func; 52 u32 pin_func;
43 53
44#ifdef CONFIG_SERIAL_8250_CONSOLE 54 pm_power_off = xxs1500_power_off;
45 char *argptr; 55 _machine_halt = xxs1500_power_off;
46 argptr = prom_getcmdline(); 56 _machine_restart = xxs1500_reset;
47 argptr = strstr(argptr, "console=");
48 if (argptr == NULL) {
49 argptr = prom_getcmdline();
50 strcat(argptr, " console=ttyS0,115200");
51 }
52#endif
53 57
54 alchemy_gpio1_input_enable(); 58 alchemy_gpio1_input_enable();
55 alchemy_gpio2_enable(); 59 alchemy_gpio2_enable();
@@ -68,22 +72,6 @@ void __init board_setup(void)
68 /* Enable DTR = USB power up */ 72 /* Enable DTR = USB power up */
69 au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */ 73 au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
70 74
71#ifdef CONFIG_PCMCIA_XXS1500
72 /* GPIO 0, 1, and 4 are inputs */
73 alchemy_gpio_direction_input(0);
74 alchemy_gpio_direction_input(1);
75 alchemy_gpio_direction_input(4);
76
77 /* GPIO2 208/9/10/11 are inputs */
78 alchemy_gpio_direction_input(208);
79 alchemy_gpio_direction_input(209);
80 alchemy_gpio_direction_input(210);
81 alchemy_gpio_direction_input(211);
82
83 /* Turn off power */
84 alchemy_gpio_direction_output(214, 0);
85#endif
86
87#ifdef CONFIG_PCI 75#ifdef CONFIG_PCI
88#if defined(__MIPSEB__) 76#if defined(__MIPSEB__)
89 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); 77 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
@@ -92,3 +80,23 @@ void __init board_setup(void)
92#endif 80#endif
93#endif 81#endif
94} 82}
83
84static int __init xxs1500_init_irq(void)
85{
86 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
87 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
88 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
89 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
90 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
91 set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
92
93 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
94 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
95 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
96 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
97 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
98 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
99
100 return 0;
101}
102arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 456fa142c093..15125c2fda7d 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -30,6 +30,7 @@
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31 31
32#include <asm/bootinfo.h> 32#include <asm/bootinfo.h>
33#include <asm/mach-au1x00/au1000.h>
33 34
34#include <prom.h> 35#include <prom.h>
35 36
@@ -56,3 +57,8 @@ void __init prom_init(void)
56 strict_strtoul(memsize_str, 0, &memsize); 57 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 58 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 59}
60
61void prom_putchar(unsigned char c)
62{
63 alchemy_uart_putchar(UART0_PHYS_ADDR, c);
64}
diff --git a/arch/mips/alchemy/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c
deleted file mode 100644
index 0f0f3012e5fd..000000000000
--- a/arch/mips/alchemy/xxs1500/irqmap.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <asm/mach-au1x00/au1000.h>
32
33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
34 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
35 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
36 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
37 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
38 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
39 { AU1500_GPIO_207, IRQF_TRIGGER_LOW, 0 },
40
41 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
42 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
43 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 },
44 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 },
45 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* CF interrupt */
46 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 },
47};
48
49void __init board_init_irq(void)
50{
51 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
52}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
new file mode 100644
index 000000000000..e87c45cde61b
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -0,0 +1,63 @@
1/*
2 * XXS1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach-au1x00/au1000.h>
25
26static struct resource xxs1500_pcmcia_res[] = {
27 {
28 .name = "pcmcia-io",
29 .flags = IORESOURCE_MEM,
30 .start = PCMCIA_IO_PHYS_ADDR,
31 .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
32 },
33 {
34 .name = "pcmcia-attr",
35 .flags = IORESOURCE_MEM,
36 .start = PCMCIA_ATTR_PHYS_ADDR,
37 .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
38 },
39 {
40 .name = "pcmcia-mem",
41 .flags = IORESOURCE_MEM,
42 .start = PCMCIA_MEM_PHYS_ADDR,
43 .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 },
45};
46
47static struct platform_device xxs1500_pcmcia_dev = {
48 .name = "xxs1500_pcmcia",
49 .id = -1,
50 .num_resources = ARRAY_SIZE(xxs1500_pcmcia_res),
51 .resource = xxs1500_pcmcia_res,
52};
53
54static struct platform_device *xxs1500_devs[] __initdata = {
55 &xxs1500_pcmcia_dev,
56};
57
58static int __init xxs1500_dev_init(void)
59{
60 return platform_add_devices(xxs1500_devs,
61 ARRAY_SIZE(xxs1500_devs));
62}
63device_initcall(xxs1500_dev_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 00:37:06 -0400