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-rw-r--r--arch/mips/alchemy/common/irq.c436
1 files changed, 222 insertions, 214 deletions
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index d670928afcfd..b2821ace4d00 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -39,168 +39,180 @@
39 39
40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); 40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
41 41
42/* NOTE on interrupt priorities: The original writers of this code said:
43 *
44 * Because of the tight timing of SETUP token to reply transactions,
45 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
46 * needs the highest priority.
47 */
48
42/* per-processor fixed function irqs */ 49/* per-processor fixed function irqs */
43struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = { 50struct au1xxx_irqmap {
44 51 int im_irq;
45#if defined(CONFIG_SOC_AU1000) 52 int im_type;
46 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 53 int im_request; /* set 1 to get higher priority */
47 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 54};
48 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 55
49 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 56struct au1xxx_irqmap au1000_irqmap[] __initdata = {
50 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 57 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
51 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 58 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
52 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, 59 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
53 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, 60 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
54 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, 61 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
55 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, 62 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
56 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, 63 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, 64 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, 65 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, 66 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 67 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
61 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 68 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
62 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 69 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
63 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 70 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
64 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 71 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
65 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 72 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
66 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 73 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
67 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 74 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
68 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 75 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
69 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 76 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
70 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 77 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
71 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 78 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
72 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 79 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
73 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 80 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
74 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 81 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
75 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
76 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
77
78#elif defined(CONFIG_SOC_AU1500)
79
80 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
81 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
82 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
84 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
85 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
86 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
87 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
88 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
89 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
90 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
92 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
93 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
95 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
96 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
97 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
98 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
99 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
100 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
101 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
102 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
104 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
105 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
107 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
108 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
109
110#elif defined(CONFIG_SOC_AU1100)
111
112 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
113 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
114 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
115 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
116 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
121 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
122 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
127 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
128 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
129 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
130 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
131 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
132 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
133 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
134 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 82 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 83 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
139 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 84 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 85 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
141 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 86 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
142 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, 87 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
143 88 { -1, },
144#elif defined(CONFIG_SOC_AU1550) 89};
145 90
146 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 91struct au1xxx_irqmap au1500_irqmap[] __initdata = {
147 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, 92 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
148 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, 93 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 94 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
150 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 95 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, 96 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, 97 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
153 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 98 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
154 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 99 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 100 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
156 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 101 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 102 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
158 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 103 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
159 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 104 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 105 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
161 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 106 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
162 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 107 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
163 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 108 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
164 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 109 { AU1500_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
165 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 110 { AU1500_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
166 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 111 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
167 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 112 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
168 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 113 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
169 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 114 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
115 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
116 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
117 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
118 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
121 { -1, },
122};
123
124struct au1xxx_irqmap au1100_irqmap[] __initdata = {
125 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
127 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
128 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
129 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
130 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
131 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
132 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
133 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
134 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
138 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
139 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
141 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
142 { AU1100_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
143 { AU1100_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
144 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
145 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
146 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
147 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
148 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
149 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
150 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
151 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
153 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
154 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
156 { -1, },
157};
158
159struct au1xxx_irqmap au1550_irqmap[] __initdata = {
160 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
161 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
162 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
163 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
164 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
165 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
166 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
167 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
168 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
169 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
171 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
172 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
175 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
176 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
177 { AU1550_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
178 { AU1550_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1550_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
180 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
181 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
182 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
183 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },
170 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, 184 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, 185 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
172 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 186 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 187 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174 188 { -1, },
175#elif defined(CONFIG_SOC_AU1200) 189};
176 190
177 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 191struct au1xxx_irqmap au1200_irqmap[] __initdata = {
178 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, 192 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
179 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 193 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
180 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 194 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
181 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 195 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
182 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 196 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 197 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 198 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
185 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 199 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 200 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 201 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, 202 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
189 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 203 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
190 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 204 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
191 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, 205 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
192 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, 206 { AU1200_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
193 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, 207 { AU1200_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
194 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, 208 { AU1200_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
195 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, 209 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
196 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, 210 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
197 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 211 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
198 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 212 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
199 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, 213 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
200 214 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
201#else 215 { -1, },
202#error "Error: Unknown Alchemy SOC"
203#endif
204}; 216};
205 217
206 218
@@ -306,7 +318,7 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
306 * nowhere in the current kernel sources is it disabled. --mlau 318 * nowhere in the current kernel sources is it disabled. --mlau
307 */ 319 */
308#if defined(CONFIG_MIPS_PB1000) 320#if defined(CONFIG_MIPS_PB1000)
309 if (irq_nr == AU1000_GPIO_15) 321 if (irq_nr == AU1000_GPIO15_INT)
310 au_writel(0x4000, PB1000_MDR); /* enable int */ 322 au_writel(0x4000, PB1000_MDR); /* enable int */
311#endif 323#endif
312 au_sync(); 324 au_sync();
@@ -378,11 +390,13 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
378 390
379static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 391static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
380{ 392{
381 unsigned int bit = irq - AU1000_INTC1_INT_BASE; 393 int bit = irq - AU1000_INTC1_INT_BASE;
382 unsigned long wakemsk, flags; 394 unsigned long wakemsk, flags;
383 395
384 /* only GPIO 0-7 can act as wakeup source: */ 396 /* only GPIO 0-7 can act as wakeup source. Fortunately these
385 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7)) 397 * are wired up identically on all supported variants.
398 */
399 if ((bit < 0) || (bit > 7))
386 return -EINVAL; 400 return -EINVAL;
387 401
388 local_irq_save(flags); 402 local_irq_save(flags);
@@ -504,11 +518,11 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
504asmlinkage void plat_irq_dispatch(void) 518asmlinkage void plat_irq_dispatch(void)
505{ 519{
506 unsigned int pending = read_c0_status() & read_c0_cause(); 520 unsigned int pending = read_c0_status() & read_c0_cause();
507 unsigned long s, off, bit; 521 unsigned long s, off;
508 522
509 if (pending & CAUSEF_IP7) { 523 if (pending & CAUSEF_IP7) {
510 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 524 off = MIPS_CPU_IRQ_BASE + 7;
511 return; 525 goto handle;
512 } else if (pending & CAUSEF_IP2) { 526 } else if (pending & CAUSEF_IP2) {
513 s = IC0_REQ0INT; 527 s = IC0_REQ0INT;
514 off = AU1000_INTC0_INT_BASE; 528 off = AU1000_INTC0_INT_BASE;
@@ -524,58 +538,20 @@ asmlinkage void plat_irq_dispatch(void)
524 } else 538 } else
525 goto spurious; 539 goto spurious;
526 540
527 bit = 0;
528 s = au_readl(s); 541 s = au_readl(s);
529 if (unlikely(!s)) { 542 if (unlikely(!s)) {
530spurious: 543spurious:
531 spurious_interrupt(); 544 spurious_interrupt();
532 return; 545 return;
533 } 546 }
534#ifdef AU1000_USB_DEV_REQ_INT 547 off += __ffs(s);
535 /* 548handle:
536 * Because of the tight timing of SETUP token to reply 549 do_IRQ(off);
537 * transactions, the USB devices-side packet complete
538 * interrupt needs the highest priority.
539 */
540 bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
541 if ((pending & CAUSEF_IP2) && (s & bit)) {
542 do_IRQ(AU1000_USB_DEV_REQ_INT);
543 return;
544 }
545#endif
546 do_IRQ(__ffs(s) + off);
547} 550}
548 551
549/* setup edge/level and assign request 0/1 */ 552static void __init au1000_init_irq(struct au1xxx_irqmap *map)
550void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
551{ 553{
552 unsigned int bit, irq_nr; 554 unsigned int bit, irq_nr;
553
554 while (count--) {
555 irq_nr = map[count].im_irq;
556
557 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
558 (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
559 ((irq_nr < AU1000_INTC1_INT_BASE) ||
560 (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
561 continue;
562
563 if (irq_nr >= AU1000_INTC1_INT_BASE) {
564 bit = irq_nr - AU1000_INTC1_INT_BASE;
565 if (map[count].im_request)
566 au_writel(1 << bit, IC1_ASSIGNCLR);
567 } else {
568 bit = irq_nr - AU1000_INTC0_INT_BASE;
569 if (map[count].im_request)
570 au_writel(1 << bit, IC0_ASSIGNCLR);
571 }
572
573 au1x_ic_settype(irq_nr, map[count].im_type);
574 }
575}
576
577void __init arch_init_irq(void)
578{
579 int i; 555 int i;
580 556
581 /* 557 /*
@@ -585,7 +561,7 @@ void __init arch_init_irq(void)
585 au_writel(0xffffffff, IC0_CFG1CLR); 561 au_writel(0xffffffff, IC0_CFG1CLR);
586 au_writel(0xffffffff, IC0_CFG2CLR); 562 au_writel(0xffffffff, IC0_CFG2CLR);
587 au_writel(0xffffffff, IC0_MASKCLR); 563 au_writel(0xffffffff, IC0_MASKCLR);
588 au_writel(0xffffffff, IC0_ASSIGNSET); 564 au_writel(0xffffffff, IC0_ASSIGNCLR);
589 au_writel(0xffffffff, IC0_WAKECLR); 565 au_writel(0xffffffff, IC0_WAKECLR);
590 au_writel(0xffffffff, IC0_SRCSET); 566 au_writel(0xffffffff, IC0_SRCSET);
591 au_writel(0xffffffff, IC0_FALLINGCLR); 567 au_writel(0xffffffff, IC0_FALLINGCLR);
@@ -596,7 +572,7 @@ void __init arch_init_irq(void)
596 au_writel(0xffffffff, IC1_CFG1CLR); 572 au_writel(0xffffffff, IC1_CFG1CLR);
597 au_writel(0xffffffff, IC1_CFG2CLR); 573 au_writel(0xffffffff, IC1_CFG2CLR);
598 au_writel(0xffffffff, IC1_MASKCLR); 574 au_writel(0xffffffff, IC1_MASKCLR);
599 au_writel(0xffffffff, IC1_ASSIGNSET); 575 au_writel(0xffffffff, IC1_ASSIGNCLR);
600 au_writel(0xffffffff, IC1_WAKECLR); 576 au_writel(0xffffffff, IC1_WAKECLR);
601 au_writel(0xffffffff, IC1_SRCSET); 577 au_writel(0xffffffff, IC1_SRCSET);
602 au_writel(0xffffffff, IC1_FALLINGCLR); 578 au_writel(0xffffffff, IC1_FALLINGCLR);
@@ -619,11 +595,43 @@ void __init arch_init_irq(void)
619 /* 595 /*
620 * Initialize IC0, which is fixed per processor. 596 * Initialize IC0, which is fixed per processor.
621 */ 597 */
622 au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map)); 598 while (map->im_irq != -1) {
599 irq_nr = map->im_irq;
623 600
624 /* Boards can register additional (GPIO-based) IRQs. 601 if (irq_nr >= AU1000_INTC1_INT_BASE) {
625 */ 602 bit = irq_nr - AU1000_INTC1_INT_BASE;
626 board_init_irq(); 603 if (map->im_request)
604 au_writel(1 << bit, IC1_ASSIGNSET);
605 } else {
606 bit = irq_nr - AU1000_INTC0_INT_BASE;
607 if (map->im_request)
608 au_writel(1 << bit, IC0_ASSIGNSET);
609 }
610
611 au1x_ic_settype(irq_nr, map->im_type);
612 ++map;
613 }
627 614
628 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); 615 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
629} 616}
617
618void __init arch_init_irq(void)
619{
620 switch (alchemy_get_cputype()) {
621 case ALCHEMY_CPU_AU1000:
622 au1000_init_irq(au1000_irqmap);
623 break;
624 case ALCHEMY_CPU_AU1500:
625 au1000_init_irq(au1500_irqmap);
626 break;
627 case ALCHEMY_CPU_AU1100:
628 au1000_init_irq(au1100_irqmap);
629 break;
630 case ALCHEMY_CPU_AU1550:
631 au1000_init_irq(au1550_irqmap);
632 break;
633 case ALCHEMY_CPU_AU1200:
634 au1000_init_irq(au1200_irqmap);
635 break;
636 }
637}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 12:58:27 -0500