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authorMark Maule <maule@sgi.com>2005-11-07 16:48:50 -0500
committerTony Luck <tony.luck@intel.com>2005-11-08 13:07:09 -0500
commit6fb93a92ec2a012fa525499c330522bbb8c18d80 (patch)
treeb64e157335242a8d257fb9d24fe6f09b8f4c99f6 /arch/ia64/sn/pci/pcibr/pcibr_reg.c
parentcbb921443424fb8019e52bae83e442d01f7715ef (diff)
[IA64] altix: misc pci interrupt related fixes
Fix a couple of altix interrupt related bugs. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/sn/pci/pcibr/pcibr_reg.c')
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_reg.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 4f718c3e93d3..5d534091262c 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -131,7 +131,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
131 __sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits); 131 __sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
132 break; 132 break;
133 case PCIBR_BRIDGETYPE_PIC: 133 case PCIBR_BRIDGETYPE_PIC:
134 __sn_clrq_relaxed(&ptr->pic.p_int_enable, ~bits); 134 __sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);
135 break; 135 break;
136 default: 136 default:
137 panic 137 panic