diff options
author | Sonic Zhang <sonic.zhang@analog.com> | 2014-01-28 03:55:22 -0500 |
---|---|---|
committer | Wolfram Sang <wsa@the-dreams.de> | 2014-03-09 03:41:18 -0400 |
commit | 5029a22a45056603497c82445db9dd203b050e82 (patch) | |
tree | 0e49bbd4a91d9a2c3508d7b928e0e0c93dc726ba /arch/blackfin/include | |
parent | 45126da22452ac3d4685401a1e921a39ac0ff2f6 (diff) |
i2c: bfin-twi: remove unnecessary Blackfin SSYNC from the driver
Put necessary SSYNC code into blackfin twi arch header. The generic TWI
driver should not contain any architecture specific code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r-- | arch/blackfin/include/asm/bfin_twi.h | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h index 34cc395f8b77..aaa0834d34aa 100644 --- a/arch/blackfin/include/asm/bfin_twi.h +++ b/arch/blackfin/include/asm/bfin_twi.h | |||
@@ -18,7 +18,6 @@ static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ | |||
18 | { bfin_write16(&iface->regs_base->reg, v); } | 18 | { bfin_write16(&iface->regs_base->reg, v); } |
19 | 19 | ||
20 | DEFINE_TWI_REG(CLKDIV, clkdiv) | 20 | DEFINE_TWI_REG(CLKDIV, clkdiv) |
21 | DEFINE_TWI_REG(CONTROL, control) | ||
22 | DEFINE_TWI_REG(SLAVE_CTL, slave_ctl) | 21 | DEFINE_TWI_REG(SLAVE_CTL, slave_ctl) |
23 | DEFINE_TWI_REG(SLAVE_STAT, slave_stat) | 22 | DEFINE_TWI_REG(SLAVE_STAT, slave_stat) |
24 | DEFINE_TWI_REG(SLAVE_ADDR, slave_addr) | 23 | DEFINE_TWI_REG(SLAVE_ADDR, slave_addr) |
@@ -27,7 +26,6 @@ DEFINE_TWI_REG(MASTER_STAT, master_stat) | |||
27 | DEFINE_TWI_REG(MASTER_ADDR, master_addr) | 26 | DEFINE_TWI_REG(MASTER_ADDR, master_addr) |
28 | DEFINE_TWI_REG(INT_STAT, int_stat) | 27 | DEFINE_TWI_REG(INT_STAT, int_stat) |
29 | DEFINE_TWI_REG(INT_MASK, int_mask) | 28 | DEFINE_TWI_REG(INT_MASK, int_mask) |
30 | DEFINE_TWI_REG(FIFO_CTL, fifo_ctl) | ||
31 | DEFINE_TWI_REG(FIFO_STAT, fifo_stat) | 29 | DEFINE_TWI_REG(FIFO_STAT, fifo_stat) |
32 | DEFINE_TWI_REG(XMT_DATA8, xmt_data8) | 30 | DEFINE_TWI_REG(XMT_DATA8, xmt_data8) |
33 | DEFINE_TWI_REG(XMT_DATA16, xmt_data16) | 31 | DEFINE_TWI_REG(XMT_DATA16, xmt_data16) |
@@ -60,4 +58,25 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) | |||
60 | } | 58 | } |
61 | #endif | 59 | #endif |
62 | 60 | ||
61 | static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface) | ||
62 | { | ||
63 | return bfin_read16(&iface->regs_base->fifo_ctl); | ||
64 | } | ||
65 | |||
66 | static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v) | ||
67 | { | ||
68 | bfin_write16(&iface->regs_base->fifo_ctl, v); | ||
69 | SSYNC(); | ||
70 | } | ||
71 | |||
72 | static inline u16 read_CONTROL(struct bfin_twi_iface *iface) | ||
73 | { | ||
74 | return bfin_read16(&iface->regs_base->control); | ||
75 | } | ||
76 | |||
77 | static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v) | ||
78 | { | ||
79 | SSYNC(); | ||
80 | bfin_write16(&iface->regs_base->control, v); | ||
81 | } | ||
63 | #endif | 82 | #endif |