diff options
author | Scott Jiang <scott.jiang.linux@gmail.com> | 2012-05-16 06:08:04 -0400 |
---|---|---|
committer | Bob Liu <lliubbo@gmail.com> | 2012-05-21 02:54:18 -0400 |
commit | e578bbdeb8db3656eff428f097d6c8ed2f3718a5 (patch) | |
tree | dc3ed858db9bc996e8e0ddd9853f72f29f76d58c /arch/blackfin/include/asm | |
parent | 7adede5b9b6c85c1218dd992e940719c2656c1a4 (diff) |
blackfin: add spi/sport3/ppi head file for bf60x
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/include/asm')
-rw-r--r-- | arch/blackfin/include/asm/bfin6xx_spi.h | 258 | ||||
-rw-r--r-- | arch/blackfin/include/asm/bfin_ppi.h | 128 | ||||
-rw-r--r-- | arch/blackfin/include/asm/bfin_sport3.h | 107 |
3 files changed, 493 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/bfin6xx_spi.h b/arch/blackfin/include/asm/bfin6xx_spi.h new file mode 100644 index 000000000000..89370b653dcd --- /dev/null +++ b/arch/blackfin/include/asm/bfin6xx_spi.h | |||
@@ -0,0 +1,258 @@ | |||
1 | /* | ||
2 | * Analog Devices SPI3 controller driver | ||
3 | * | ||
4 | * Copyright (c) 2011 Analog Devices Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef _SPI_CHANNEL_H_ | ||
21 | #define _SPI_CHANNEL_H_ | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | |||
25 | /* SPI_CONTROL */ | ||
26 | #define SPI_CTL_EN 0x00000001 /* Enable */ | ||
27 | #define SPI_CTL_MSTR 0x00000002 /* Master/Slave */ | ||
28 | #define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ | ||
29 | #define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ | ||
30 | #define SPI_CTL_CPHA 0x00000010 /* Clock Phase */ | ||
31 | #define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ | ||
32 | #define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ | ||
33 | #define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */ | ||
34 | #define SPI_CTL_EMISO 0x00000100 /* Enable MISO */ | ||
35 | #define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */ | ||
36 | #define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */ | ||
37 | #define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */ | ||
38 | #define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */ | ||
39 | #define SPI_CTL_LSBF 0x00001000 /* LSB First */ | ||
40 | #define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */ | ||
41 | #define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */ | ||
42 | #define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */ | ||
43 | #define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */ | ||
44 | #define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */ | ||
45 | #define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */ | ||
46 | #define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */ | ||
47 | #define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */ | ||
48 | #define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */ | ||
49 | #define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */ | ||
50 | #define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */ | ||
51 | #define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */ | ||
52 | #define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */ | ||
53 | /* SPI_RX_CONTROL */ | ||
54 | #define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */ | ||
55 | #define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */ | ||
56 | #define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */ | ||
57 | #define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */ | ||
58 | #define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */ | ||
59 | #define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */ | ||
60 | #define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */ | ||
61 | #define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */ | ||
62 | #define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */ | ||
63 | #define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */ | ||
64 | #define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */ | ||
65 | #define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */ | ||
66 | #define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */ | ||
67 | #define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */ | ||
68 | #define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */ | ||
69 | #define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */ | ||
70 | #define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */ | ||
71 | #define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */ | ||
72 | #define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */ | ||
73 | #define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */ | ||
74 | #define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */ | ||
75 | #define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */ | ||
76 | /* SPI_TX_CONTROL */ | ||
77 | #define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */ | ||
78 | #define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */ | ||
79 | #define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */ | ||
80 | #define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */ | ||
81 | #define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */ | ||
82 | #define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */ | ||
83 | #define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */ | ||
84 | #define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */ | ||
85 | #define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */ | ||
86 | #define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */ | ||
87 | #define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */ | ||
88 | #define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */ | ||
89 | #define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */ | ||
90 | #define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */ | ||
91 | #define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */ | ||
92 | #define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */ | ||
93 | #define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */ | ||
94 | #define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */ | ||
95 | #define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */ | ||
96 | #define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */ | ||
97 | #define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */ | ||
98 | #define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */ | ||
99 | /* SPI_CLOCK */ | ||
100 | #define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */ | ||
101 | /* SPI_DELAY */ | ||
102 | #define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */ | ||
103 | #define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */ | ||
104 | #define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */ | ||
105 | /* SPI_SSEL */ | ||
106 | #define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */ | ||
107 | #define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */ | ||
108 | #define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */ | ||
109 | #define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */ | ||
110 | #define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */ | ||
111 | #define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */ | ||
112 | #define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */ | ||
113 | #define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */ | ||
114 | #define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */ | ||
115 | #define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */ | ||
116 | #define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */ | ||
117 | #define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */ | ||
118 | #define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */ | ||
119 | #define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */ | ||
120 | /* SPI_RWC */ | ||
121 | #define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */ | ||
122 | /* SPI_RWCR */ | ||
123 | #define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */ | ||
124 | /* SPI_TWC */ | ||
125 | #define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */ | ||
126 | /* SPI_TWCR */ | ||
127 | #define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */ | ||
128 | /* SPI_IMASK */ | ||
129 | #define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ | ||
130 | #define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ | ||
131 | #define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ | ||
132 | #define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ | ||
133 | #define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ | ||
134 | #define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ | ||
135 | #define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */ | ||
136 | #define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */ | ||
137 | #define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */ | ||
138 | #define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ | ||
139 | /* SPI_IMASKCL */ | ||
140 | #define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ | ||
141 | #define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ | ||
142 | #define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ | ||
143 | #define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ | ||
144 | #define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ | ||
145 | #define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ | ||
146 | #define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */ | ||
147 | #define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */ | ||
148 | #define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */ | ||
149 | #define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ | ||
150 | /* SPI_IMASKST */ | ||
151 | #define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ | ||
152 | #define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ | ||
153 | #define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ | ||
154 | #define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ | ||
155 | #define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ | ||
156 | #define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ | ||
157 | #define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */ | ||
158 | #define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */ | ||
159 | #define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */ | ||
160 | #define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ | ||
161 | /* SPI_STATUS */ | ||
162 | #define SPI_STAT_SPIF 0x00000001 /* SPI Finished */ | ||
163 | #define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */ | ||
164 | #define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */ | ||
165 | #define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */ | ||
166 | #define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */ | ||
167 | #define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */ | ||
168 | #define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */ | ||
169 | #define SPI_STAT_RS 0x00000100 /* Receive Start Indication */ | ||
170 | #define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */ | ||
171 | #define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */ | ||
172 | #define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */ | ||
173 | #define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */ | ||
174 | #define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */ | ||
175 | #define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */ | ||
176 | #define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */ | ||
177 | #define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */ | ||
178 | #define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */ | ||
179 | #define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */ | ||
180 | #define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */ | ||
181 | #define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */ | ||
182 | #define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */ | ||
183 | #define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */ | ||
184 | #define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */ | ||
185 | #define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */ | ||
186 | #define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */ | ||
187 | #define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */ | ||
188 | /* SPI_ILAT */ | ||
189 | #define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ | ||
190 | #define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ | ||
191 | #define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */ | ||
192 | #define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */ | ||
193 | #define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */ | ||
194 | #define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */ | ||
195 | #define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */ | ||
196 | #define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */ | ||
197 | #define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */ | ||
198 | #define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */ | ||
199 | /* SPI_ILATCL */ | ||
200 | #define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ | ||
201 | #define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ | ||
202 | #define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */ | ||
203 | #define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */ | ||
204 | #define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */ | ||
205 | #define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */ | ||
206 | #define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */ | ||
207 | #define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */ | ||
208 | #define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */ | ||
209 | #define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ | ||
210 | |||
211 | /* | ||
212 | * bfin spi3 registers layout | ||
213 | */ | ||
214 | struct bfin_spi_regs { | ||
215 | u32 revid; | ||
216 | u32 control; | ||
217 | u32 rx_control; | ||
218 | u32 tx_control; | ||
219 | u32 clock; | ||
220 | u32 delay; | ||
221 | u32 ssel; | ||
222 | u32 rwc; | ||
223 | u32 rwcr; | ||
224 | u32 twc; | ||
225 | u32 twcr; | ||
226 | u32 reserved0; | ||
227 | u32 emask; | ||
228 | u32 emaskcl; | ||
229 | u32 emaskst; | ||
230 | u32 reserved1; | ||
231 | u32 status; | ||
232 | u32 elat; | ||
233 | u32 elatcl; | ||
234 | u32 reserved2; | ||
235 | u32 rfifo; | ||
236 | u32 reserved3; | ||
237 | u32 tfifo; | ||
238 | }; | ||
239 | |||
240 | #define MAX_CTRL_CS 8 /* cs in spi controller */ | ||
241 | |||
242 | /* device.platform_data for SSP controller devices */ | ||
243 | struct bfin6xx_spi_master { | ||
244 | u16 num_chipselect; | ||
245 | u16 pin_req[7]; | ||
246 | }; | ||
247 | |||
248 | /* spi_board_info.controller_data for SPI slave devices, | ||
249 | * copied to spi_device.platform_data ... mostly for dma tuning | ||
250 | */ | ||
251 | struct bfin6xx_spi_chip { | ||
252 | u32 control; | ||
253 | u16 cs_chg_udelay; /* Some devices require 16-bit delays */ | ||
254 | u32 tx_dummy_val; /* tx value for rx only transfer */ | ||
255 | bool enable_dma; | ||
256 | }; | ||
257 | |||
258 | #endif /* _SPI_CHANNEL_H_ */ | ||
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h index 3be05faa2c65..a4e872e16e75 100644 --- a/arch/blackfin/include/asm/bfin_ppi.h +++ b/arch/blackfin/include/asm/bfin_ppi.h | |||
@@ -10,6 +10,7 @@ | |||
10 | #define __ASM_BFIN_PPI_H__ | 10 | #define __ASM_BFIN_PPI_H__ |
11 | 11 | ||
12 | #include <linux/types.h> | 12 | #include <linux/types.h> |
13 | #include <asm/blackfin.h> | ||
13 | 14 | ||
14 | /* | 15 | /* |
15 | * All Blackfin system MMRs are padded to 32bits even if the register | 16 | * All Blackfin system MMRs are padded to 32bits even if the register |
@@ -48,6 +49,133 @@ struct bfin_eppi_regs { | |||
48 | u32 clip; | 49 | u32 clip; |
49 | }; | 50 | }; |
50 | 51 | ||
52 | /* | ||
53 | * bfin eppi3 registers layout | ||
54 | */ | ||
55 | struct bfin_eppi3_regs { | ||
56 | u32 stat; | ||
57 | u32 hcnt; | ||
58 | u32 hdly; | ||
59 | u32 vcnt; | ||
60 | u32 vdly; | ||
61 | u32 frame; | ||
62 | u32 line; | ||
63 | u32 clkdiv; | ||
64 | u32 ctl; | ||
65 | u32 fs1_wlhb; | ||
66 | u32 fs1_paspl; | ||
67 | u32 fs2_wlvb; | ||
68 | u32 fs2_palpf; | ||
69 | u32 imsk; | ||
70 | u32 oddclip; | ||
71 | u32 evenclip; | ||
72 | u32 fs1_dly; | ||
73 | u32 fs2_dly; | ||
74 | u32 ctl2; | ||
75 | }; | ||
76 | |||
51 | #undef __BFP | 77 | #undef __BFP |
52 | 78 | ||
79 | #ifdef EPPI0_CTL2 | ||
80 | #define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */ | ||
81 | #define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */ | ||
82 | #define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */ | ||
83 | #define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */ | ||
84 | #define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */ | ||
85 | #define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */ | ||
86 | #define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */ | ||
87 | #define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */ | ||
88 | #define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */ | ||
89 | #define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */ | ||
90 | |||
91 | #define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */ | ||
92 | |||
93 | #define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */ | ||
94 | |||
95 | #define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */ | ||
96 | |||
97 | #define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */ | ||
98 | |||
99 | #define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */ | ||
100 | |||
101 | #define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */ | ||
102 | |||
103 | #define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */ | ||
104 | |||
105 | #define EPPI_CTL_EN 0x00000001 /* PPI Enable */ | ||
106 | #define EPPI_CTL_DIR 0x00000002 /* PPI Direction */ | ||
107 | #define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */ | ||
108 | #define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */ | ||
109 | #define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */ | ||
110 | #define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */ | ||
111 | #define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */ | ||
112 | #define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */ | ||
113 | #define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */ | ||
114 | #define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */ | ||
115 | #define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */ | ||
116 | #define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */ | ||
117 | #define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */ | ||
118 | #define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */ | ||
119 | #define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ | ||
120 | #define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */ | ||
121 | #define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */ | ||
122 | #define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */ | ||
123 | #define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */ | ||
124 | #define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */ | ||
125 | #define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */ | ||
126 | #define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */ | ||
127 | #define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */ | ||
128 | #define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */ | ||
129 | #define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */ | ||
130 | #define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */ | ||
131 | #define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */ | ||
132 | #define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */ | ||
133 | #define EPPI_CTL_DLEN 0x00070000 /* Data Length */ | ||
134 | #define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */ | ||
135 | #define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */ | ||
136 | #define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */ | ||
137 | #define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */ | ||
138 | #define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */ | ||
139 | #define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */ | ||
140 | #define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */ | ||
141 | #define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */ | ||
142 | #define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */ | ||
143 | #define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */ | ||
144 | #define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */ | ||
145 | #define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */ | ||
146 | #define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */ | ||
147 | #define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */ | ||
148 | #define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */ | ||
149 | #define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */ | ||
150 | #define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */ | ||
151 | #define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */ | ||
152 | #define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */ | ||
153 | #define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */ | ||
154 | #define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */ | ||
155 | |||
156 | #define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */ | ||
157 | #define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */ | ||
158 | #define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */ | ||
159 | #define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */ | ||
160 | |||
161 | #define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */ | ||
162 | #define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */ | ||
163 | |||
164 | #define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */ | ||
165 | #define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */ | ||
166 | #define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */ | ||
167 | #define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */ | ||
168 | #define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */ | ||
169 | #define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */ | ||
170 | #define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */ | ||
171 | #define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */ | ||
172 | |||
173 | #define EPPI_ODDCLIP_HIGHODD 0xFFFF0000 | ||
174 | #define EPPI_ODDCLIP_LOWODD 0x0000FFFF | ||
175 | |||
176 | #define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000 | ||
177 | #define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF | ||
178 | |||
179 | #define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */ | ||
180 | #endif | ||
53 | #endif | 181 | #endif |
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h new file mode 100644 index 000000000000..03c00220d69b --- /dev/null +++ b/arch/blackfin/include/asm/bfin_sport3.h | |||
@@ -0,0 +1,107 @@ | |||
1 | /* | ||
2 | * bfin_sport - Analog Devices BF6XX SPORT registers | ||
3 | * | ||
4 | * Copyright (c) 2012 Analog Devices Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef _BFIN_SPORT3_H_ | ||
21 | #define _BFIN_SPORT3_H_ | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | |||
25 | #define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */ | ||
26 | #define SPORT_CTL_DTYPE 0x00000006 /* Data type select */ | ||
27 | #define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */ | ||
28 | #define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */ | ||
29 | #define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */ | ||
30 | #define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */ | ||
31 | #define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */ | ||
32 | #define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */ | ||
33 | #define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */ | ||
34 | #define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */ | ||
35 | #define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */ | ||
36 | #define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */ | ||
37 | #define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */ | ||
38 | #define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */ | ||
39 | #define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */ | ||
40 | #define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */ | ||
41 | #define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */ | ||
42 | #define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */ | ||
43 | #define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */ | ||
44 | #define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */ | ||
45 | #define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */ | ||
46 | #define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */ | ||
47 | #define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */ | ||
48 | #define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */ | ||
49 | #define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */ | ||
50 | #define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */ | ||
51 | #define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */ | ||
52 | #define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */ | ||
53 | #define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */ | ||
54 | #define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */ | ||
55 | #define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */ | ||
56 | #define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */ | ||
57 | #define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */ | ||
58 | |||
59 | #define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */ | ||
60 | #define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */ | ||
61 | |||
62 | #define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */ | ||
63 | #define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */ | ||
64 | #define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */ | ||
65 | #define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */ | ||
66 | #define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */ | ||
67 | |||
68 | #define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */ | ||
69 | #define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */ | ||
70 | |||
71 | #define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */ | ||
72 | #define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */ | ||
73 | #define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */ | ||
74 | #define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */ | ||
75 | #define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */ | ||
76 | #define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */ | ||
77 | |||
78 | #define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */ | ||
79 | |||
80 | #define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */ | ||
81 | #define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */ | ||
82 | #define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */ | ||
83 | |||
84 | struct sport_register { | ||
85 | u32 spctl; | ||
86 | u32 div; | ||
87 | u32 spmctl; | ||
88 | u32 spcs0; | ||
89 | u32 spcs1; | ||
90 | u32 spcs2; | ||
91 | u32 spcs3; | ||
92 | u32 spcnt; | ||
93 | u32 sperrctl; | ||
94 | u32 spmstat; | ||
95 | u32 spctl2; | ||
96 | u32 txa; | ||
97 | u32 rxa; | ||
98 | u32 txb; | ||
99 | u32 rxb; | ||
100 | u32 revid; | ||
101 | }; | ||
102 | |||
103 | struct bfin_snd_platform_data { | ||
104 | const unsigned short *pin_req; | ||
105 | }; | ||
106 | |||
107 | #endif | ||