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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/blackfin/include/asm/cacheflush.h
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/blackfin/include/asm/cacheflush.h')
-rw-r--r--arch/blackfin/include/asm/cacheflush.h26
1 files changed, 21 insertions, 5 deletions
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 2666ff8ea952..9a5b2c572ebf 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -11,6 +11,9 @@
11 11
12#include <asm/blackfin.h> /* for SSYNC() */ 12#include <asm/blackfin.h> /* for SSYNC() */
13#include <asm/sections.h> /* for _ramend */ 13#include <asm/sections.h> /* for _ramend */
14#ifdef CONFIG_SMP
15#include <asm/smp.h>
16#endif
14 17
15extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 18extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
16extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 19extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
@@ -36,8 +39,13 @@ extern void blackfin_invalidate_entire_icache(void);
36 39
37static inline void flush_icache_range(unsigned start, unsigned end) 40static inline void flush_icache_range(unsigned start, unsigned end)
38{ 41{
39#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 42#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
40 blackfin_dcache_flush_range(start, end); 43 if (end <= physical_mem_end)
44 blackfin_dcache_flush_range(start, end);
45#endif
46#if defined(CONFIG_BFIN_L2_WRITEBACK)
47 if (start >= L2_START && end <= L2_START + L2_LENGTH)
48 blackfin_dcache_flush_range(start, end);
41#endif 49#endif
42 50
43 /* Make sure all write buffers in the data side of the core 51 /* Make sure all write buffers in the data side of the core
@@ -49,9 +57,17 @@ static inline void flush_icache_range(unsigned start, unsigned end)
49 * the pipeline. 57 * the pipeline.
50 */ 58 */
51 SSYNC(); 59 SSYNC();
52#if defined(CONFIG_BFIN_ICACHE) 60#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
53 blackfin_icache_flush_range(start, end); 61 if (end <= physical_mem_end) {
54 flush_icache_range_others(start, end); 62 blackfin_icache_flush_range(start, end);
63 flush_icache_range_others(start, end);
64 }
65#endif
66#if defined(CONFIG_BFIN_L2_ICACHEABLE)
67 if (start >= L2_START && end <= L2_START + L2_LENGTH) {
68 blackfin_icache_flush_range(start, end);
69 flush_icache_range_others(start, end);
70 }
55#endif 71#endif
56} 72}
57 73