aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/include
diff options
context:
space:
mode:
authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/blackfin/include
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/blackfin/include')
-rw-r--r--arch/blackfin/include/asm/Kbuild1
-rw-r--r--arch/blackfin/include/asm/atomic.h2
-rw-r--r--arch/blackfin/include/asm/bfin-global.h10
-rw-r--r--arch/blackfin/include/asm/bfin5xx_spi.h96
-rw-r--r--arch/blackfin/include/asm/bfin_can.h9
-rw-r--r--arch/blackfin/include/asm/bfin_dma.h91
-rw-r--r--arch/blackfin/include/asm/bfin_pfmon.h44
-rw-r--r--arch/blackfin/include/asm/bfin_ppi.h53
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h277
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h4
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h45
-rw-r--r--arch/blackfin/include/asm/bitops.h7
-rw-r--r--arch/blackfin/include/asm/cache.h2
-rw-r--r--arch/blackfin/include/asm/cachectl.h20
-rw-r--r--arch/blackfin/include/asm/cacheflush.h26
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h9
-rw-r--r--arch/blackfin/include/asm/cpu.h3
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h24
-rw-r--r--arch/blackfin/include/asm/dma.h37
-rw-r--r--arch/blackfin/include/asm/dpmc.h5
-rw-r--r--arch/blackfin/include/asm/entry.h8
-rw-r--r--arch/blackfin/include/asm/gptimers.h18
-rw-r--r--arch/blackfin/include/asm/io.h268
-rw-r--r--arch/blackfin/include/asm/ipipe.h97
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h11
-rw-r--r--arch/blackfin/include/asm/irq_handler.h25
-rw-r--r--arch/blackfin/include/asm/irqflags.h339
-rw-r--r--arch/blackfin/include/asm/kgdb.h7
-rw-r--r--arch/blackfin/include/asm/mmu_context.h8
-rw-r--r--arch/blackfin/include/asm/perf_event.h1
-rw-r--r--arch/blackfin/include/asm/processor.h4
-rw-r--r--arch/blackfin/include/asm/ptrace.h10
-rw-r--r--arch/blackfin/include/asm/serial.h1
-rw-r--r--arch/blackfin/include/asm/smp.h9
-rw-r--r--arch/blackfin/include/asm/spinlock.h28
-rw-r--r--arch/blackfin/include/asm/system.h40
-rw-r--r--arch/blackfin/include/asm/traps.h2
-rw-r--r--arch/blackfin/include/asm/unistd.h9
-rw-r--r--arch/blackfin/include/mach-common/irq.h57
-rw-r--r--arch/blackfin/include/mach-common/pll.h86
-rw-r--r--arch/blackfin/include/mach-common/ports-a.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-b.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-c.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-d.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-e.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-f.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-g.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-h.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-i.h25
-rw-r--r--arch/blackfin/include/mach-common/ports-j.h25
50 files changed, 1418 insertions, 625 deletions
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index d9eb29e2555c..9e7c5379d3ff 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,4 +1,5 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += bfin_sport.h 3header-y += bfin_sport.h
4header-y += cachectl.h
4header-y += fixed_code.h 5header-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index d27c6274247d..e48508957160 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -121,4 +121,6 @@ static inline int atomic_test_mask(int mask, atomic_t *v)
121 121
122#endif 122#endif
123 123
124#include <asm-generic/atomic64.h>
125
124#endif 126#endif
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 121cc04d877d..17bcbf60bcae 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -49,16 +49,6 @@ extern void dump_bfin_trace_buffer(void);
49#define dump_bfin_trace_buffer() 49#define dump_bfin_trace_buffer()
50#endif 50#endif
51 51
52/* init functions only */
53extern int init_arch_irq(void);
54extern void init_exception_vectors(void);
55extern void program_IAR(void);
56
57extern asmlinkage void lower_to_irq14(void);
58extern asmlinkage void bfin_return_from_exception(void);
59extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
60extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
61
62extern void *l1_data_A_sram_alloc(size_t); 52extern void *l1_data_A_sram_alloc(size_t);
63extern void *l1_data_B_sram_alloc(size_t); 53extern void *l1_data_B_sram_alloc(size_t);
64extern void *l1_inst_sram_alloc(size_t); 54extern void *l1_inst_sram_alloc(size_t);
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index ed4f8c6db0cd..5392583d0253 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -11,26 +11,17 @@
11 11
12#define MIN_SPI_BAUD_VAL 2 12#define MIN_SPI_BAUD_VAL 2
13 13
14#define SPI_READ 0
15#define SPI_WRITE 1
16
17#define SPI_CTRL_OFF 0x0
18#define SPI_FLAG_OFF 0x4
19#define SPI_STAT_OFF 0x8
20#define SPI_TXBUFF_OFF 0xc
21#define SPI_RXBUFF_OFF 0x10
22#define SPI_BAUD_OFF 0x14
23#define SPI_SHAW_OFF 0x18
24
25
26#define BIT_CTL_ENABLE 0x4000 14#define BIT_CTL_ENABLE 0x4000
27#define BIT_CTL_OPENDRAIN 0x2000 15#define BIT_CTL_OPENDRAIN 0x2000
28#define BIT_CTL_MASTER 0x1000 16#define BIT_CTL_MASTER 0x1000
29#define BIT_CTL_POLAR 0x0800 17#define BIT_CTL_CPOL 0x0800
30#define BIT_CTL_PHASE 0x0400 18#define BIT_CTL_CPHA 0x0400
31#define BIT_CTL_BITORDER 0x0200 19#define BIT_CTL_LSBF 0x0200
32#define BIT_CTL_WORDSIZE 0x0100 20#define BIT_CTL_WORDSIZE 0x0100
33#define BIT_CTL_MISOENABLE 0x0020 21#define BIT_CTL_EMISO 0x0020
22#define BIT_CTL_PSSE 0x0010
23#define BIT_CTL_GM 0x0008
24#define BIT_CTL_SZ 0x0004
34#define BIT_CTL_RXMOD 0x0000 25#define BIT_CTL_RXMOD 0x0000
35#define BIT_CTL_TXMOD 0x0001 26#define BIT_CTL_TXMOD 0x0001
36#define BIT_CTL_TIMOD_DMA_TX 0x0003 27#define BIT_CTL_TIMOD_DMA_TX 0x0003
@@ -50,61 +41,28 @@
50#define BIT_STU_SENDOVER 0x0001 41#define BIT_STU_SENDOVER 0x0001
51#define BIT_STU_RECVFULL 0x0020 42#define BIT_STU_RECVFULL 0x0020
52 43
53#define CFG_SPI_ENABLE 1 44/*
54#define CFG_SPI_DISABLE 0 45 * All Blackfin system MMRs are padded to 32bits even if the register
55 46 * itself is only 16bits. So use a helper macro to streamline this.
56#define CFG_SPI_OUTENABLE 1 47 */
57#define CFG_SPI_OUTDISABLE 0 48#define __BFP(m) u16 m; u16 __pad_##m
58
59#define CFG_SPI_ACTLOW 1
60#define CFG_SPI_ACTHIGH 0
61
62#define CFG_SPI_PHASESTART 1
63#define CFG_SPI_PHASEMID 0
64
65#define CFG_SPI_MASTER 1
66#define CFG_SPI_SLAVE 0
67
68#define CFG_SPI_SENELAST 0
69#define CFG_SPI_SENDZERO 1
70
71#define CFG_SPI_RCVFLUSH 1
72#define CFG_SPI_RCVDISCARD 0
73
74#define CFG_SPI_LSBFIRST 1
75#define CFG_SPI_MSBFIRST 0
76
77#define CFG_SPI_WORDSIZE16 1
78#define CFG_SPI_WORDSIZE8 0
79
80#define CFG_SPI_MISOENABLE 1
81#define CFG_SPI_MISODISABLE 0
82
83#define CFG_SPI_READ 0x00
84#define CFG_SPI_WRITE 0x01
85#define CFG_SPI_DMAREAD 0x02
86#define CFG_SPI_DMAWRITE 0x03
87 49
88#define CFG_SPI_CSCLEARALL 0 50/*
89#define CFG_SPI_CHIPSEL1 1 51 * bfin spi registers layout
90#define CFG_SPI_CHIPSEL2 2 52 */
91#define CFG_SPI_CHIPSEL3 3 53struct bfin_spi_regs {
92#define CFG_SPI_CHIPSEL4 4 54 __BFP(ctl);
93#define CFG_SPI_CHIPSEL5 5 55 __BFP(flg);
94#define CFG_SPI_CHIPSEL6 6 56 __BFP(stat);
95#define CFG_SPI_CHIPSEL7 7 57 __BFP(tdbr);
58 __BFP(rdbr);
59 __BFP(baud);
60 __BFP(shadow);
61};
96 62
97#define CFG_SPI_CS1VALUE 1 63#undef __BFP
98#define CFG_SPI_CS2VALUE 2
99#define CFG_SPI_CS3VALUE 3
100#define CFG_SPI_CS4VALUE 4
101#define CFG_SPI_CS5VALUE 5
102#define CFG_SPI_CS6VALUE 6
103#define CFG_SPI_CS7VALUE 7
104 64
105#define CMD_SPI_SET_BAUDRATE 2 65#define MAX_CTRL_CS 8 /* cs in spi controller */
106#define CMD_SPI_GET_SYSTEMCLOCK 25
107#define CMD_SPI_SET_WRITECONTINUOUS 26
108 66
109/* device.platform_data for SSP controller devices */ 67/* device.platform_data for SSP controller devices */
110struct bfin5xx_spi_master { 68struct bfin5xx_spi_master {
@@ -120,9 +78,7 @@ struct bfin5xx_spi_chip {
120 u16 ctl_reg; 78 u16 ctl_reg;
121 u8 enable_dma; 79 u8 enable_dma;
122 u8 bits_per_word; 80 u8 bits_per_word;
123 u8 cs_change_per_word;
124 u16 cs_chg_udelay; /* Some devices require 16-bit delays */ 81 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
125 u32 cs_gpio;
126 /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ 82 /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
127 u16 idle_tx_val; 83 u16 idle_tx_val;
128 u8 pio_interrupt; /* Enable spi data irq */ 84 u8 pio_interrupt; /* Enable spi data irq */
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
index eec0076a385b..b1492e0bcabb 100644
--- a/arch/blackfin/include/asm/bfin_can.h
+++ b/arch/blackfin/include/asm/bfin_can.h
@@ -34,6 +34,7 @@ struct bfin_can_mask_regs {
34}; 34};
35 35
36struct bfin_can_channel_regs { 36struct bfin_can_channel_regs {
37 /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
37 u16 data[8]; 38 u16 data[8];
38 __BFP(dlc); 39 __BFP(dlc);
39 __BFP(tsv); 40 __BFP(tsv);
@@ -83,16 +84,18 @@ struct bfin_can_regs {
83 __BFP(gif); /* offset 0x9c */ 84 __BFP(gif); /* offset 0x9c */
84 __BFP(control); /* offset 0xa0 */ 85 __BFP(control); /* offset 0xa0 */
85 __BFP(intr); /* offset 0xa4 */ 86 __BFP(intr); /* offset 0xa4 */
86 u32 __pad3[1]; 87 __BFP(version); /* offset 0xa8 */
87 __BFP(mbtd); /* offset 0xac */ 88 __BFP(mbtd); /* offset 0xac */
88 __BFP(ewr); /* offset 0xb0 */ 89 __BFP(ewr); /* offset 0xb0 */
89 __BFP(esr); /* offset 0xb4 */ 90 __BFP(esr); /* offset 0xb4 */
90 u32 __pad4[2]; 91 u32 __pad3[2];
91 __BFP(ucreg); /* offset 0xc0 */ 92 __BFP(ucreg); /* offset 0xc0 */
92 __BFP(uccnt); /* offset 0xc4 */ 93 __BFP(uccnt); /* offset 0xc4 */
93 __BFP(ucrc); /* offset 0xc8 */ 94 __BFP(ucrc); /* offset 0xc8 */
94 __BFP(uccnf); /* offset 0xcc */ 95 __BFP(uccnf); /* offset 0xcc */
95 u32 __pad5[12]; 96 u32 __pad4[1];
97 __BFP(version2); /* offset 0xd4 */
98 u32 __pad5[10];
96 99
97 /* 100 /*
98 * channel(mailbox) mask and message registers 101 * channel(mailbox) mask and message registers
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
new file mode 100644
index 000000000000..d51120744148
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -0,0 +1,91 @@
1/*
2 * bfin_dma.h - Blackfin DMA defines/structures/etc...
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_DMA_H__
10#define __ASM_BFIN_DMA_H__
11
12#include <linux/types.h>
13
14/* DMA_CONFIG Masks */
15#define DMAEN 0x0001 /* DMA Channel Enable */
16#define WNR 0x0002 /* Channel Direction (W/R*) */
17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
18#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
19#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
20#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
21#define RESTART 0x0020 /* DMA Buffer Clear */
22#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
23#define DI_EN 0x0080 /* Data Interrupt Enable */
24#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
25#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
26#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
27#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
28#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
29#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
30#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
31#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
32#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
33#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
34#define NDSIZE 0x0f00 /* Next Descriptor Size */
35#define DMAFLOW 0x7000 /* Flow Control */
36#define DMAFLOW_STOP 0x0000 /* Stop Mode */
37#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
38#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
39#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
40#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
41
42/* DMA_IRQ_STATUS Masks */
43#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
44#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
45#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
46#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
47
48/*
49 * All Blackfin system MMRs are padded to 32bits even if the register
50 * itself is only 16bits. So use a helper macro to streamline this.
51 */
52#define __BFP(m) u16 m; u16 __pad_##m
53
54/*
55 * bfin dma registers layout
56 */
57struct bfin_dma_regs {
58 u32 next_desc_ptr;
59 u32 start_addr;
60 __BFP(config);
61 u32 __pad0;
62 __BFP(x_count);
63 __BFP(x_modify);
64 __BFP(y_count);
65 __BFP(y_modify);
66 u32 curr_desc_ptr;
67 u32 curr_addr;
68 __BFP(irq_status);
69 __BFP(peripheral_map);
70 __BFP(curr_x_count);
71 u32 __pad1;
72 __BFP(curr_y_count);
73 u32 __pad2;
74};
75
76/*
77 * bfin handshake mdma registers layout
78 */
79struct bfin_hmdma_regs {
80 __BFP(control);
81 __BFP(ecinit);
82 __BFP(bcinit);
83 __BFP(ecurgent);
84 __BFP(ecoverflow);
85 __BFP(ecount);
86 __BFP(bcount);
87};
88
89#undef __BFP
90
91#endif
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
new file mode 100644
index 000000000000..accd47e2db40
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -0,0 +1,44 @@
1/*
2 * Blackfin Performance Monitor definitions
3 *
4 * Copyright 2005-2011 Analog Devices Inc.
5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later).
7 */
8
9#ifndef __ASM_BFIN_PFMON_H__
10#define __ASM_BFIN_PFMON_H__
11
12/* PFCTL Masks */
13#define PFMON_MASK 0xff
14#define PFCEN_MASK 0x3
15#define PFCEN_DISABLE 0x0
16#define PFCEN_ENABLE_USER 0x1
17#define PFCEN_ENABLE_SUPV 0x2
18#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
19
20#define PFPWR_P 0
21#define PEMUSW0_P 2
22#define PFCEN0_P 3
23#define PFMON0_P 5
24#define PEMUSW1_P 13
25#define PFCEN1_P 14
26#define PFMON1_P 16
27#define PFCNT0_P 24
28#define PFCNT1_P 25
29
30#define PFPWR (1 << PFPWR_P)
31#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
32#define PEMUSW0 PEMUSW(0, 1)
33#define PEMUSW1 PEMUSW(1, 1)
34#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
35#define PFCEN0 PFCEN(0, PFCEN_MASK)
36#define PFCEN1 PFCEN(1, PFCEN_MASK)
37#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
38#define PFCNT0 PFCNT(0, 1)
39#define PFCNT1 PFCNT(1, 1)
40#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
41#define PFMON0 PFMON(0, PFMON_MASK)
42#define PFMON1 PFMON(1, PFMON_MASK)
43
44#endif
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
new file mode 100644
index 000000000000..3be05faa2c65
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_ppi.h
@@ -0,0 +1,53 @@
1/*
2 * bfin_ppi.h - interface to Blackfin PPIs
3 *
4 * Copyright 2005-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_PPI_H__
10#define __ASM_BFIN_PPI_H__
11
12#include <linux/types.h>
13
14/*
15 * All Blackfin system MMRs are padded to 32bits even if the register
16 * itself is only 16bits. So use a helper macro to streamline this.
17 */
18#define __BFP(m) u16 m; u16 __pad_##m
19
20/*
21 * bfin ppi registers layout
22 */
23struct bfin_ppi_regs {
24 __BFP(control);
25 __BFP(status);
26 __BFP(count);
27 __BFP(delay);
28 __BFP(frame);
29};
30
31/*
32 * bfin eppi registers layout
33 */
34struct bfin_eppi_regs {
35 __BFP(status);
36 __BFP(hcount);
37 __BFP(hdelay);
38 __BFP(vcount);
39 __BFP(vdelay);
40 __BFP(frame);
41 __BFP(line);
42 __BFP(clkdiv);
43 u32 control;
44 u32 fs1w_hbl;
45 u32 fs1p_avpl;
46 u32 fs2w_lvb;
47 u32 fs2p_lavf;
48 u32 clip;
49};
50
51#undef __BFP
52
53#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 000000000000..7fd0ec7b5b0f
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,277 @@
1/*
2 * bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_ASM_SERIAL_H__
10#define __BFIN_ASM_SERIAL_H__
11
12#include <linux/serial_core.h>
13#include <linux/spinlock.h>
14#include <mach/anomaly.h>
15#include <mach/bfin_serial.h>
16
17#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
18 defined(CONFIG_BFIN_UART1_CTSRTS) || \
19 defined(CONFIG_BFIN_UART2_CTSRTS) || \
20 defined(CONFIG_BFIN_UART3_CTSRTS)
21# ifdef BFIN_UART_BF54X_STYLE
22# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
23# else
24# define CONFIG_SERIAL_BFIN_CTSRTS
25# endif
26#endif
27
28struct circ_buf;
29struct timer_list;
30struct work_struct;
31
32struct bfin_serial_port {
33 struct uart_port port;
34 unsigned int old_status;
35 int status_irq;
36#ifndef BFIN_UART_BF54X_STYLE
37 unsigned int lsr;
38#endif
39#ifdef CONFIG_SERIAL_BFIN_DMA
40 int tx_done;
41 int tx_count;
42 struct circ_buf rx_dma_buf;
43 struct timer_list rx_dma_timer;
44 int rx_dma_nrows;
45 spinlock_t rx_lock;
46 unsigned int tx_dma_channel;
47 unsigned int rx_dma_channel;
48 struct work_struct tx_dma_workqueue;
49#elif ANOMALY_05000363
50 unsigned int anomaly_threshold;
51#endif
52#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
53 int scts;
54#endif
55#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
56 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
57 int cts_pin;
58 int rts_pin;
59#endif
60};
61
62/* UART_LCR Masks */
63#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
64#define STB 0x04 /* Stop Bits */
65#define PEN 0x08 /* Parity Enable */
66#define EPS 0x10 /* Even Parity Select */
67#define STP 0x20 /* Stick Parity */
68#define SB 0x40 /* Set Break */
69#define DLAB 0x80 /* Divisor Latch Access */
70
71/* UART_LSR Masks */
72#define DR 0x01 /* Data Ready */
73#define OE 0x02 /* Overrun Error */
74#define PE 0x04 /* Parity Error */
75#define FE 0x08 /* Framing Error */
76#define BI 0x10 /* Break Interrupt */
77#define THRE 0x20 /* THR Empty */
78#define TEMT 0x40 /* TSR and UART_THR Empty */
79#define TFI 0x80 /* Transmission Finished Indicator */
80
81/* UART_IER Masks */
82#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
83#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
84#define ELSI 0x04 /* Enable RX Status Interrupt */
85#define EDSSI 0x08 /* Enable Modem Status Interrupt */
86#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
87#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
88#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
89
90/* UART_MCR Masks */
91#define XOFF 0x01 /* Transmitter Off */
92#define MRTS 0x02 /* Manual Request To Send */
93#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
94#define RFRT 0x08 /* Receive FIFO RTS Threshold */
95#define LOOP_ENA 0x10 /* Loopback Mode Enable */
96#define FCPOL 0x20 /* Flow Control Pin Polarity */
97#define ARTS 0x40 /* Automatic Request To Send */
98#define ACTS 0x80 /* Automatic Clear To Send */
99
100/* UART_MSR Masks */
101#define SCTS 0x01 /* Sticky CTS */
102#define CTS 0x10 /* Clear To Send */
103#define RFCS 0x20 /* Receive FIFO Count Status */
104
105/* UART_GCTL Masks */
106#define UCEN 0x01 /* Enable UARTx Clocks */
107#define IREN 0x02 /* Enable IrDA Mode */
108#define TPOLC 0x04 /* IrDA TX Polarity Change */
109#define RPOLC 0x08 /* IrDA RX Polarity Change */
110#define FPE 0x10 /* Force Parity Error On Transmit */
111#define FFE 0x20 /* Force Framing Error On Transmit */
112
113#ifdef BFIN_UART_BF54X_STYLE
114# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
115# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
116# define OFFSET_GCTL 0x08 /* Global Control Register */
117# define OFFSET_LCR 0x0C /* Line Control Register */
118# define OFFSET_MCR 0x10 /* Modem Control Register */
119# define OFFSET_LSR 0x14 /* Line Status Register */
120# define OFFSET_MSR 0x18 /* Modem Status Register */
121# define OFFSET_SCR 0x1C /* SCR Scratch Register */
122# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
123# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
124# define OFFSET_THR 0x28 /* Transmit Holding register */
125# define OFFSET_RBR 0x2C /* Receive Buffer register */
126#else /* BF533 style */
127# define OFFSET_THR 0x00 /* Transmit Holding register */
128# define OFFSET_RBR 0x00 /* Receive Buffer register */
129# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
130# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
131# define OFFSET_IER 0x04 /* Interrupt Enable Register */
132# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
133# define OFFSET_LCR 0x0C /* Line Control Register */
134# define OFFSET_MCR 0x10 /* Modem Control Register */
135# define OFFSET_LSR 0x14 /* Line Status Register */
136# define OFFSET_MSR 0x18 /* Modem Status Register */
137# define OFFSET_SCR 0x1C /* SCR Scratch Register */
138# define OFFSET_GCTL 0x24 /* Global Control Register */
139/* code should not need IIR, so force build error if they use it */
140# undef OFFSET_IIR
141#endif
142
143/*
144 * All Blackfin system MMRs are padded to 32bits even if the register
145 * itself is only 16bits. So use a helper macro to streamline this.
146 */
147#define __BFP(m) u16 m; u16 __pad_##m
148struct bfin_uart_regs {
149#ifdef BFIN_UART_BF54X_STYLE
150 __BFP(dll);
151 __BFP(dlh);
152 __BFP(gctl);
153 __BFP(lcr);
154 __BFP(mcr);
155 __BFP(lsr);
156 __BFP(msr);
157 __BFP(scr);
158 __BFP(ier_set);
159 __BFP(ier_clear);
160 __BFP(thr);
161 __BFP(rbr);
162#else
163 union {
164 u16 dll;
165 u16 thr;
166 const u16 rbr;
167 };
168 const u16 __pad0;
169 union {
170 u16 dlh;
171 u16 ier;
172 };
173 const u16 __pad1;
174 const __BFP(iir);
175 __BFP(lcr);
176 __BFP(mcr);
177 __BFP(lsr);
178 __BFP(msr);
179 __BFP(scr);
180 const u32 __pad2;
181 __BFP(gctl);
182#endif
183};
184#undef __BFP
185
186#ifndef port_membase
187# define port_membase(p) 0
188#endif
189
190#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
191#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
192#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
193#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
194#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
195#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
196#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
197
198#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
199#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
200#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
201#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
202#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
203#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
204
205#ifdef BFIN_UART_BF54X_STYLE
206
207#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
208#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
209#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
210
211#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
212#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
213
214#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
215#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
216#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
217
218/* This handles hard CTS/RTS */
219#define BFIN_UART_CTSRTS_HARD
220#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
221#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
222#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
223#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
224#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
225#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
226
227#else /* BF533 style */
228
229#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
230#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
231#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
232#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
233
234#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
235#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
236
237#ifndef put_lsr_cache
238# define put_lsr_cache(p, v)
239#endif
240#ifndef get_lsr_cache
241# define get_lsr_cache(p) 0
242#endif
243
244/* The hardware clears the LSR bits upon read, so we need to cache
245 * some of the more fun bits in software so they don't get lost
246 * when checking the LSR in other code paths (TX).
247 */
248static inline void UART_CLEAR_LSR(void *p)
249{
250 put_lsr_cache(p, 0);
251 bfin_write16(port_membase(p) + OFFSET_LSR, -1);
252}
253static inline unsigned int UART_GET_LSR(void *p)
254{
255 unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
256 put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
257 return lsr | get_lsr_cache(p);
258}
259static inline void UART_PUT_LSR(void *p, uint16_t val)
260{
261 put_lsr_cache(p, get_lsr_cache(p) & ~val);
262}
263
264/* This handles soft CTS/RTS */
265#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
266#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
267#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
268#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
269#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
270
271#endif
272
273#ifndef BFIN_UART_TX_FIFO_SIZE
274# define BFIN_UART_TX_FIFO_SIZE 2
275#endif
276
277#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index d27600c262c2..f8568a31d0ab 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -100,6 +100,10 @@ struct sport_register {
100}; 100};
101#undef __BFP 101#undef __BFP
102 102
103struct bfin_snd_platform_data {
104 const unsigned short *pin_req;
105};
106
103#define bfin_read_sport_rx32(base) \ 107#define bfin_read_sport_rx32(base) \
104({ \ 108({ \
105 struct sport_register *__mmrs = (void *)base; \ 109 struct sport_register *__mmrs = (void *)base; \
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
new file mode 100644
index 000000000000..e767d649dfc4
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -0,0 +1,45 @@
1/*
2 * bfin_twi.h - interface to Blackfin TWIs
3 *
4 * Copyright 2005-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BFIN_TWI_H__
10#define __ASM_BFIN_TWI_H__
11
12#include <linux/types.h>
13
14/*
15 * All Blackfin system MMRs are padded to 32bits even if the register
16 * itself is only 16bits. So use a helper macro to streamline this.
17 */
18#define __BFP(m) u16 m; u16 __pad_##m
19
20/*
21 * bfin twi registers layout
22 */
23struct bfin_twi_regs {
24 __BFP(clkdiv);
25 __BFP(control);
26 __BFP(slave_ctl);
27 __BFP(slave_stat);
28 __BFP(slave_addr);
29 __BFP(master_ctl);
30 __BFP(master_stat);
31 __BFP(master_addr);
32 __BFP(int_stat);
33 __BFP(int_mask);
34 __BFP(fifo_ctl);
35 __BFP(fifo_stat);
36 u32 __pad[20];
37 __BFP(xmt_data8);
38 __BFP(xmt_data16);
39 __BFP(rcv_data8);
40 __BFP(rcv_data16);
41};
42
43#undef __BFP
44
45#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 3f7ef4d97791..8a0fed16058f 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -25,9 +25,7 @@
25#include <asm-generic/bitops/const_hweight.h> 25#include <asm-generic/bitops/const_hweight.h>
26#include <asm-generic/bitops/lock.h> 26#include <asm-generic/bitops/lock.h>
27 27
28#include <asm-generic/bitops/ext2-non-atomic.h>
29#include <asm-generic/bitops/ext2-atomic.h> 28#include <asm-generic/bitops/ext2-atomic.h>
30#include <asm-generic/bitops/minix.h>
31 29
32#ifndef CONFIG_SMP 30#ifndef CONFIG_SMP
33#include <linux/irqflags.h> 31#include <linux/irqflags.h>
@@ -108,10 +106,15 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
108#define smp_mb__before_clear_bit() barrier() 106#define smp_mb__before_clear_bit() barrier()
109#define smp_mb__after_clear_bit() barrier() 107#define smp_mb__after_clear_bit() barrier()
110 108
109#define test_bit __skip_test_bit
111#include <asm-generic/bitops/non-atomic.h> 110#include <asm-generic/bitops/non-atomic.h>
111#undef test_bit
112 112
113#endif /* CONFIG_SMP */ 113#endif /* CONFIG_SMP */
114 114
115/* Needs to be after test_bit and friends */
116#include <asm-generic/bitops/le.h>
117
115/* 118/*
116 * hweightN: returns the hamming weight (i.e. the number 119 * hweightN: returns the hamming weight (i.e. the number
117 * of bits set) of a N-bit word 120 * of bits set) of a N-bit word
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index bd0641a267f1..568885a2c286 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -7,6 +7,8 @@
7#ifndef __ARCH_BLACKFIN_CACHE_H 7#ifndef __ARCH_BLACKFIN_CACHE_H
8#define __ARCH_BLACKFIN_CACHE_H 8#define __ARCH_BLACKFIN_CACHE_H
9 9
10#include <linux/linkage.h> /* for asmlinkage */
11
10/* 12/*
11 * Bytes per L1 cache line 13 * Bytes per L1 cache line
12 * Blackfin loads 32 bytes for cache 14 * Blackfin loads 32 bytes for cache
diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h
new file mode 100644
index 000000000000..03255df6c1ea
--- /dev/null
+++ b/arch/blackfin/include/asm/cachectl.h
@@ -0,0 +1,20 @@
1/*
2 * based on the mips/cachectl.h
3 *
4 * Copyright 2010 Analog Devices Inc.
5 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#ifndef _ASM_CACHECTL
11#define _ASM_CACHECTL
12
13/*
14 * Options for cacheflush system call
15 */
16#define ICACHE (1<<0) /* flush instruction cache */
17#define DCACHE (1<<1) /* writeback and flush data cache */
18#define BCACHE (ICACHE|DCACHE) /* flush both caches */
19
20#endif /* _ASM_CACHECTL */
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 2666ff8ea952..9a5b2c572ebf 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -11,6 +11,9 @@
11 11
12#include <asm/blackfin.h> /* for SSYNC() */ 12#include <asm/blackfin.h> /* for SSYNC() */
13#include <asm/sections.h> /* for _ramend */ 13#include <asm/sections.h> /* for _ramend */
14#ifdef CONFIG_SMP
15#include <asm/smp.h>
16#endif
14 17
15extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 18extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
16extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 19extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
@@ -36,8 +39,13 @@ extern void blackfin_invalidate_entire_icache(void);
36 39
37static inline void flush_icache_range(unsigned start, unsigned end) 40static inline void flush_icache_range(unsigned start, unsigned end)
38{ 41{
39#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 42#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
40 blackfin_dcache_flush_range(start, end); 43 if (end <= physical_mem_end)
44 blackfin_dcache_flush_range(start, end);
45#endif
46#if defined(CONFIG_BFIN_L2_WRITEBACK)
47 if (start >= L2_START && end <= L2_START + L2_LENGTH)
48 blackfin_dcache_flush_range(start, end);
41#endif 49#endif
42 50
43 /* Make sure all write buffers in the data side of the core 51 /* Make sure all write buffers in the data side of the core
@@ -49,9 +57,17 @@ static inline void flush_icache_range(unsigned start, unsigned end)
49 * the pipeline. 57 * the pipeline.
50 */ 58 */
51 SSYNC(); 59 SSYNC();
52#if defined(CONFIG_BFIN_ICACHE) 60#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
53 blackfin_icache_flush_range(start, end); 61 if (end <= physical_mem_end) {
54 flush_icache_range_others(start, end); 62 blackfin_icache_flush_range(start, end);
63 flush_icache_range_others(start, end);
64 }
65#endif
66#if defined(CONFIG_BFIN_L2_ICACHEABLE)
67 if (start >= L2_START && end <= L2_START + L2_LENGTH) {
68 blackfin_icache_flush_range(start, end);
69 flush_icache_range_others(start, end);
70 }
55#endif 71#endif
56} 72}
57 73
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
index 6c39d94b44d0..59af63c0c2be 100644
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -172,16 +172,19 @@
172#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val) 172#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
173#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) 173#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
174#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val) 174#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
175#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
176#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val) 175#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
177#if 0 176#if 0
178#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */ 177#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
179#endif 178#endif
180#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
181#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val) 179#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
182#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
183#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val) 180#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
184 181
182#if !ANOMALY_05000481
183#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
184#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
185#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
186#endif
187
185/* Event/Interrupt Registers*/ 188/* Event/Interrupt Registers*/
186 189
187#define bfin_read_EVT0() bfin_read32(EVT0) 190#define bfin_read_EVT0() bfin_read32(EVT0)
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index 16883e582e3c..05043786da21 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -10,11 +10,8 @@
10 10
11#include <linux/percpu.h> 11#include <linux/percpu.h>
12 12
13struct task_struct;
14
15struct blackfin_cpudata { 13struct blackfin_cpudata {
16 struct cpu cpu; 14 struct cpu cpu;
17 struct task_struct *idle;
18 unsigned int imemctl; 15 unsigned int imemctl;
19 unsigned int dmemctl; 16 unsigned int dmemctl;
20}; 17};
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index e3f0f4c49819..823679011457 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -52,20 +52,32 @@
52 52
53#define bfin_read(addr) \ 53#define bfin_read(addr) \
54({ \ 54({ \
55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ 55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ 56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ 57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
58 ({ BUG(); 0; }); \ 58 ({ BUG(); 0; }); \
59}) 59})
60#define bfin_write(addr, val) \ 60#define bfin_write(addr, val) \
61({ \ 61do { \
62 switch (sizeof(*(addr))) { \ 62 switch (sizeof(*(addr))) { \
63 case 1: bfin_write8(addr, val); break; \ 63 case 1: bfin_write8(addr, val); break; \
64 case 2: bfin_write16(addr, val); break; \ 64 case 2: bfin_write16(addr, val); break; \
65 case 4: bfin_write32(addr, val); break; \ 65 case 4: bfin_write32(addr, val); break; \
66 default: BUG(); \ 66 default: BUG(); \
67 } \ 67 } \
68}) 68} while (0)
69
70#define bfin_write_or(addr, bits) \
71do { \
72 typeof(addr) __addr = (addr); \
73 bfin_write(__addr, bfin_read(__addr) | (bits)); \
74} while (0)
75
76#define bfin_write_and(addr, bits) \
77do { \
78 typeof(addr) __addr = (addr); \
79 bfin_write(__addr, bfin_read(__addr) & (bits)); \
80} while (0)
69 81
70#endif /* __ASSEMBLY__ */ 82#endif /* __ASSEMBLY__ */
71 83
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index eedf3ca65ba2..d9dbc1a53534 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -14,40 +14,7 @@
14#include <asm/blackfin.h> 14#include <asm/blackfin.h>
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm-generic/dma.h> 16#include <asm-generic/dma.h>
17 17#include <asm/bfin_dma.h>
18/* DMA_CONFIG Masks */
19#define DMAEN 0x0001 /* DMA Channel Enable */
20#define WNR 0x0002 /* Channel Direction (W/R*) */
21#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
22#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
23#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
24#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
25#define RESTART 0x0020 /* DMA Buffer Clear */
26#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
27#define DI_EN 0x0080 /* Data Interrupt Enable */
28#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
29#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
30#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
31#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
32#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
33#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
34#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
35#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
36#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
37#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
38#define NDSIZE 0x0f00 /* Next Descriptor Size */
39#define DMAFLOW 0x7000 /* Flow Control */
40#define DMAFLOW_STOP 0x0000 /* Stop Mode */
41#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
42#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
43#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
44#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
45
46/* DMA_IRQ_STATUS Masks */
47#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
48#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
49#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
50#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
51 18
52/*------------------------- 19/*-------------------------
53 * config reg bits value 20 * config reg bits value
@@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
149* DMA API's 116* DMA API's
150*******************************************************************************/ 117*******************************************************************************/
151extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; 118extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
152extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS]; 119extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
153extern int channel2irq(unsigned int channel); 120extern int channel2irq(unsigned int channel);
154 121
155static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) 122static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index efcc3aebeae4..edf2a2ad5183 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,8 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#include <mach/pll.h>
13
12/* PLL_CTL Masks */ 14/* PLL_CTL Masks */
13#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 15#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
14#define PLL_OFF 0x0002 /* PLL Not Powered */ 16#define PLL_OFF 0x0002 /* PLL Not Powered */
@@ -123,6 +125,9 @@ void unset_dram_srfs(void);
123 125
124#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) 126#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
125 127
128#ifdef CONFIG_CPU_FREQ
129#define CPUFREQ_CPU 0
130#endif
126struct bfin_dpmc_platform_data { 131struct bfin_dpmc_platform_data {
127 const unsigned int *tuple_tab; 132 const unsigned int *tuple_tab;
128 unsigned short tabsize; 133 unsigned short tabsize;
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
index a6886f6e4819..4104d5783e2c 100644
--- a/arch/blackfin/include/asm/entry.h
+++ b/arch/blackfin/include/asm/entry.h
@@ -15,14 +15,6 @@
15#define LFLUSH_I_AND_D 0x00000808 15#define LFLUSH_I_AND_D 0x00000808
16#define LSIGTRAP 5 16#define LSIGTRAP 5
17 17
18/* process bits for task_struct.flags */
19#define PF_TRACESYS_OFF 3
20#define PF_TRACESYS_BIT 5
21#define PF_PTRACED_OFF 3
22#define PF_PTRACED_BIT 4
23#define PF_DTRACE_OFF 1
24#define PF_DTRACE_BIT 5
25
26/* 18/*
27 * NOTE! The single-stepping code assumes that all interrupt handlers 19 * NOTE! The single-stepping code assumes that all interrupt handlers
28 * start by saving SYSCFG on the stack with their first instruction. 20 * start by saving SYSCFG on the stack with their first instruction.
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index c722acdda0d3..38657dac1235 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -193,4 +193,22 @@ uint16_t get_enabled_gptimers(void);
193uint32_t get_gptimer_status(unsigned int group); 193uint32_t get_gptimer_status(unsigned int group);
194void set_gptimer_status(unsigned int group, uint32_t value); 194void set_gptimer_status(unsigned int group, uint32_t value);
195 195
196/*
197 * All Blackfin system MMRs are padded to 32bits even if the register
198 * itself is only 16bits. So use a helper macro to streamline this.
199 */
200#define __BFP(m) u16 m; u16 __pad_##m
201
202/*
203 * bfin timer registers layout
204 */
205struct bfin_gptimer_regs {
206 __BFP(config);
207 u32 counter;
208 u32 period;
209 u32 width;
210};
211
212#undef __BFP
213
196#endif 214#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 234fbac17ec1..dccae26805b0 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,148 +7,48 @@
7#ifndef _BFIN_IO_H 7#ifndef _BFIN_IO_H
8#define _BFIN_IO_H 8#define _BFIN_IO_H
9 9
10#ifdef __KERNEL__
11
12#ifndef __ASSEMBLY__
13#include <linux/types.h>
14#endif
15#include <linux/compiler.h> 10#include <linux/compiler.h>
16 11#include <linux/types.h>
17/* 12#include <asm/byteorder.h>
18 * These are for ISA/PCI shared memory _only_ and should never be used 13
19 * on any other type of memory, including Zorro memory. They are meant to 14#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
20 * access the bus in the bus byte order which is little-endian!. 15static inline type __raw_read##size(const volatile void __iomem *addr) \
21 * 16{ \
22 * readX/writeX() are used to access memory mapped devices. On some 17 unsigned int val; \
23 * architectures the memory mapped IO stuff needs to be accessed 18 int tmp; \
24 * differently. On the bfin architecture, we just read/write the 19 __asm__ __volatile__ ( \
25 * memory location directly. 20 "cli %1;" \
26 */ 21 "NOP; NOP; SSYNC;" \
27#ifndef __ASSEMBLY__ 22 "%0 = "#asm" [%2] "#asm_sign";" \
28 23 "sti %1;" \
29static inline unsigned char readb(const volatile void __iomem *addr) 24 : "=d"(val), "=d"(tmp) \
30{ 25 : "a"(addr) \
31 unsigned int val; 26 ); \
32 int tmp; 27 return (type) val; \
33
34 __asm__ __volatile__ (
35 "cli %1;"
36 "NOP; NOP; SSYNC;"
37 "%0 = b [%2] (z);"
38 "sti %1;"
39 : "=d"(val), "=d"(tmp)
40 : "a"(addr)
41 );
42
43 return (unsigned char) val;
44}
45
46static inline unsigned short readw(const volatile void __iomem *addr)
47{
48 unsigned int val;
49 int tmp;
50
51 __asm__ __volatile__ (
52 "cli %1;"
53 "NOP; NOP; SSYNC;"
54 "%0 = w [%2] (z);"
55 "sti %1;"
56 : "=d"(val), "=d"(tmp)
57 : "a"(addr)
58 );
59
60 return (unsigned short) val;
61}
62
63static inline unsigned int readl(const volatile void __iomem *addr)
64{
65 unsigned int val;
66 int tmp;
67
68 __asm__ __volatile__ (
69 "cli %1;"
70 "NOP; NOP; SSYNC;"
71 "%0 = [%2];"
72 "sti %1;"
73 : "=d"(val), "=d"(tmp)
74 : "a"(addr)
75 );
76
77 return val;
78} 28}
79 29DECLARE_BFIN_RAW_READX(b, u8, b, (z))
80#endif /* __ASSEMBLY__ */ 30#define __raw_readb __raw_readb
81 31DECLARE_BFIN_RAW_READX(w, u16, w, (z))
82#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) 32#define __raw_readw __raw_readw
83#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) 33DECLARE_BFIN_RAW_READX(l, u32, , )
84#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) 34#define __raw_readl __raw_readl
85
86#define __raw_readb readb
87#define __raw_readw readw
88#define __raw_readl readl
89#define __raw_writeb writeb
90#define __raw_writew writew
91#define __raw_writel writel
92#define memset_io(a, b, c) memset((void *)(a), (b), (c))
93#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
94#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
95
96/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
97#define __io(port) ((void *)(unsigned long)(port))
98
99#define inb(port) readb(__io(port))
100#define inw(port) readw(__io(port))
101#define inl(port) readl(__io(port))
102#define outb(x, port) writeb(x, __io(port))
103#define outw(x, port) writew(x, __io(port))
104#define outl(x, port) writel(x, __io(port))
105
106#define inb_p(port) inb(__io(port))
107#define inw_p(port) inw(__io(port))
108#define inl_p(port) inl(__io(port))
109#define outb_p(x, port) outb(x, __io(port))
110#define outw_p(x, port) outw(x, __io(port))
111#define outl_p(x, port) outl(x, __io(port))
112
113#define ioread8_rep(a, d, c) readsb(a, d, c)
114#define ioread16_rep(a, d, c) readsw(a, d, c)
115#define ioread32_rep(a, d, c) readsl(a, d, c)
116#define iowrite8_rep(a, s, c) writesb(a, s, c)
117#define iowrite16_rep(a, s, c) writesw(a, s, c)
118#define iowrite32_rep(a, s, c) writesl(a, s, c)
119
120#define ioread8(x) readb(x)
121#define ioread16(x) readw(x)
122#define ioread32(x) readl(x)
123#define iowrite8(val, x) writeb(val, x)
124#define iowrite16(val, x) writew(val, x)
125#define iowrite32(val, x) writel(val, x)
126
127/**
128 * I/O write barrier
129 *
130 * Ensure ordering of I/O space writes. This will make sure that writes
131 * following the barrier will arrive after all previous writes.
132 */
133#define mmiowb() do { SSYNC(); wmb(); } while (0)
134
135#define IO_SPACE_LIMIT 0xffffffff
136
137/* Values for nocacheflag and cmode */
138#define IOMAP_NOCACHE_SER 1
139
140#ifndef __ASSEMBLY__
141 35
142extern void outsb(unsigned long port, const void *addr, unsigned long count); 36extern void outsb(unsigned long port, const void *addr, unsigned long count);
143extern void outsw(unsigned long port, const void *addr, unsigned long count); 37extern void outsw(unsigned long port, const void *addr, unsigned long count);
144extern void outsw_8(unsigned long port, const void *addr, unsigned long count); 38extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
145extern void outsl(unsigned long port, const void *addr, unsigned long count); 39extern void outsl(unsigned long port, const void *addr, unsigned long count);
40#define outsb outsb
41#define outsw outsw
42#define outsl outsl
146 43
147extern void insb(unsigned long port, void *addr, unsigned long count); 44extern void insb(unsigned long port, void *addr, unsigned long count);
148extern void insw(unsigned long port, void *addr, unsigned long count); 45extern void insw(unsigned long port, void *addr, unsigned long count);
149extern void insw_8(unsigned long port, void *addr, unsigned long count); 46extern void insw_8(unsigned long port, void *addr, unsigned long count);
150extern void insl(unsigned long port, void *addr, unsigned long count); 47extern void insl(unsigned long port, void *addr, unsigned long count);
151extern void insl_16(unsigned long port, void *addr, unsigned long count); 48extern void insl_16(unsigned long port, void *addr, unsigned long count);
49#define insb insb
50#define insw insw
51#define insl insl
152 52
153extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); 53extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
154extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); 54extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
158extern void dma_insw(unsigned long port, void *addr, unsigned short count); 58extern void dma_insw(unsigned long port, void *addr, unsigned short count);
159extern void dma_insl(unsigned long port, void *addr, unsigned short count); 59extern void dma_insl(unsigned long port, void *addr, unsigned short count);
160 60
161static inline void readsl(const void __iomem *addr, void *buf, int len) 61/**
162{ 62 * I/O write barrier
163 insl((unsigned long)addr, buf, len); 63 *
164} 64 * Ensure ordering of I/O space writes. This will make sure that writes
165 65 * following the barrier will arrive after all previous writes.
166static inline void readsw(const void __iomem *addr, void *buf, int len)
167{
168 insw((unsigned long)addr, buf, len);
169}
170
171static inline void readsb(const void __iomem *addr, void *buf, int len)
172{
173 insb((unsigned long)addr, buf, len);
174}
175
176static inline void writesl(const void __iomem *addr, const void *buf, int len)
177{
178 outsl((unsigned long)addr, buf, len);
179}
180
181static inline void writesw(const void __iomem *addr, const void *buf, int len)
182{
183 outsw((unsigned long)addr, buf, len);
184}
185
186static inline void writesb(const void __iomem *addr, const void *buf, int len)
187{
188 outsb((unsigned long)addr, buf, len);
189}
190
191/*
192 * Map some physical address range into the kernel address space.
193 */
194static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
195 int cacheflag)
196{
197 return (void __iomem *)physaddr;
198}
199
200/*
201 * Unmap a ioremap()ed region again
202 */
203static inline void iounmap(void *addr)
204{
205}
206
207/*
208 * __iounmap unmaps nearly everything, so be careful
209 * it doesn't free currently pointer/page tables anymore but it
210 * wans't used anyway and might be added later.
211 */
212static inline void __iounmap(void *addr, unsigned long size)
213{
214}
215
216/*
217 * Set new cache mode for some kernel address space.
218 * The caller must push data for that range itself, if such data may already
219 * be in the cache.
220 */ 66 */
221static inline void kernel_set_cachemode(void *addr, unsigned long size, 67#define mmiowb() do { SSYNC(); wmb(); } while (0)
222 int cmode)
223{
224}
225
226static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
227{
228 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
229}
230static inline void __iomem *ioremap_nocache(unsigned long physaddr,
231 unsigned long size)
232{
233 return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
234}
235 68
236extern void blkfin_inv_cache_all(void); 69#include <asm-generic/io.h>
237 70
238#endif 71#endif
239
240#define ioport_map(port, nr) ((void __iomem*)(port))
241#define ioport_unmap(addr)
242
243/* Pages to physical address... */
244#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT)
245
246#define phys_to_virt(vaddr) ((void *) (vaddr))
247#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
248
249#define virt_to_bus virt_to_phys
250#define bus_to_virt phys_to_virt
251
252/*
253 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
254 * access
255 */
256#define xlate_dev_mem_ptr(p) __va(p)
257
258/*
259 * Convert a virtual cached pointer to an uncached pointer
260 */
261#define xlate_dev_kmem_ptr(p) p
262
263#endif /* __KERNEL__ */
264
265#endif /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index d3b40449ca0e..9e0cc0e2534f 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -34,11 +34,12 @@
34#include <asm/bitops.h> 34#include <asm/bitops.h>
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37#include <asm/bitsperlong.h>
37 38
38#define IPIPE_ARCH_STRING "1.12-00" 39#define IPIPE_ARCH_STRING "1.16-01"
39#define IPIPE_MAJOR_NUMBER 1 40#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 12 41#define IPIPE_MINOR_NUMBER 16
41#define IPIPE_PATCH_NUMBER 0 42#define IPIPE_PATCH_NUMBER 1
42 43
43#ifdef CONFIG_SMP 44#ifdef CONFIG_SMP
44#error "I-pipe/blackfin: SMP not implemented" 45#error "I-pipe/blackfin: SMP not implemented"
@@ -49,31 +50,25 @@
49#define prepare_arch_switch(next) \ 50#define prepare_arch_switch(next) \
50do { \ 51do { \
51 ipipe_schedule_notify(current, next); \ 52 ipipe_schedule_notify(current, next); \
52 local_irq_disable_hw(); \ 53 hard_local_irq_disable(); \
53} while (0) 54} while (0)
54 55
55#define task_hijacked(p) \ 56#define task_hijacked(p) \
56 ({ \ 57 ({ \
57 int __x__ = __ipipe_root_domain_p; \ 58 int __x__ = __ipipe_root_domain_p; \
58 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
59 if (__x__) \ 59 if (__x__) \
60 local_irq_enable_hw(); \ 60 hard_local_irq_enable(); \
61 !__x__; \ 61 !__x__; \
62 }) 62 })
63 63
64struct ipipe_domain; 64struct ipipe_domain;
65 65
66struct ipipe_sysinfo { 66struct ipipe_sysinfo {
67 67 int sys_nr_cpus; /* Number of CPUs on board */
68 int ncpus; /* Number of CPUs on board */ 68 int sys_hrtimer_irq; /* hrtimer device IRQ */
69 u64 cpufreq; /* CPU frequency (in Hz) */ 69 u64 sys_hrtimer_freq; /* hrtimer device frequency */
70 70 u64 sys_hrclock_freq; /* hrclock device frequency */
71 /* Arch-dependent block */ 71 u64 sys_cpu_freq; /* CPU frequency (Hz) */
72
73 struct {
74 unsigned tmirq; /* Timer tick IRQ */
75 u64 tmfreq; /* Timer frequency */
76 } archdep;
77}; 72};
78 73
79#define ipipe_read_tsc(t) \ 74#define ipipe_read_tsc(t) \
@@ -115,9 +110,19 @@ void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
115void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, 110void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
116 unsigned irq); 111 unsigned irq);
117 112
118#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq)) 113#define __ipipe_enable_irq(irq) \
114 do { \
115 struct irq_desc *desc = irq_to_desc(irq); \
116 struct irq_chip *chip = get_irq_desc_chip(desc); \
117 chip->irq_unmask(&desc->irq_data); \
118 } while (0)
119 119
120#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) 120#define __ipipe_disable_irq(irq) \
121 do { \
122 struct irq_desc *desc = irq_to_desc(irq); \
123 struct irq_chip *chip = get_irq_desc_chip(desc); \
124 chip->irq_mask(&desc->irq_data); \
125 } while (0)
121 126
122static inline int __ipipe_check_tickdev(const char *devname) 127static inline int __ipipe_check_tickdev(const char *devname)
123{ 128{
@@ -128,12 +133,11 @@ void __ipipe_enable_pipeline(void);
128 133
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 134#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130 135
131#define __ipipe_sync_pipeline ___ipipe_sync_pipeline 136void ___ipipe_sync_pipeline(void);
132void ___ipipe_sync_pipeline(unsigned long syncmask);
133 137
134void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); 138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
135 139
136int __ipipe_get_irq_priority(unsigned irq); 140int __ipipe_get_irq_priority(unsigned int irq);
137 141
138void __ipipe_serial_debug(const char *fmt, ...); 142void __ipipe_serial_debug(const char *fmt, ...);
139 143
@@ -152,7 +156,10 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
152 return ffs(ul) - 1; 156 return ffs(ul) - 1;
153} 157}
154 158
155#define __ipipe_run_irqtail() /* Must be a macro */ \ 159#define __ipipe_do_root_xirq(ipd, irq) \
160 ((ipd)->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)))
161
162#define __ipipe_run_irqtail(irq) /* Must be a macro */ \
156 do { \ 163 do { \
157 unsigned long __pending; \ 164 unsigned long __pending; \
158 CSYNC(); \ 165 CSYNC(); \
@@ -164,42 +171,8 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
164 } \ 171 } \
165 } while (0) 172 } while (0)
166 173
167#define __ipipe_run_isr(ipd, irq) \
168 do { \
169 if (!__ipipe_pipeline_head_p(ipd)) \
170 local_irq_enable_hw(); \
171 if (ipd == ipipe_root_domain) { \
172 if (unlikely(ipipe_virtual_irq_p(irq))) { \
173 irq_enter(); \
174 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
175 irq_exit(); \
176 } else \
177 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
178 } else { \
179 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
180 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
181 /* Attempt to exit the outer interrupt level before \
182 * starting the deferred IRQ processing. */ \
183 __ipipe_run_irqtail(); \
184 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
185 } \
186 local_irq_disable_hw(); \
187 } while (0)
188
189#define __ipipe_syscall_watched_p(p, sc) \ 174#define __ipipe_syscall_watched_p(p, sc) \
190 (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls) 175 (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls)
191
192void ipipe_init_irq_threads(void);
193
194int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
195
196#ifdef CONFIG_TICKSOURCE_CORETMR
197#define IRQ_SYSTMR IRQ_CORETMR
198#define IRQ_PRIOTMR IRQ_CORETMR
199#else
200#define IRQ_SYSTMR IRQ_TIMER0
201#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
202#endif
203 176
204#ifdef CONFIG_BF561 177#ifdef CONFIG_BF561
205#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) 178#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
@@ -219,11 +192,11 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219 192
220#define task_hijacked(p) 0 193#define task_hijacked(p) 0
221#define ipipe_trap_notify(t, r) 0 194#define ipipe_trap_notify(t, r) 0
195#define __ipipe_root_tick_p(regs) 1
222 196
223#define ipipe_init_irq_threads() do { } while (0) 197#endif /* !CONFIG_IPIPE */
224#define ipipe_start_irq_thread(irq, desc) 0
225 198
226#ifndef CONFIG_TICKSOURCE_GPTMR0 199#ifdef CONFIG_TICKSOURCE_CORETMR
227#define IRQ_SYSTMR IRQ_CORETMR 200#define IRQ_SYSTMR IRQ_CORETMR
228#define IRQ_PRIOTMR IRQ_CORETMR 201#define IRQ_PRIOTMR IRQ_CORETMR
229#else 202#else
@@ -231,10 +204,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
231#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 204#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
232#endif 205#endif
233 206
234#define __ipipe_root_tick_p(regs) 1
235
236#endif /* !CONFIG_IPIPE */
237
238#define ipipe_update_tick_evtdev(evtdev) do { } while (0) 207#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
239 208
240#endif /* !__ASM_BLACKFIN_IPIPE_H */ 209#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 00409201d9ed..84a4ffd36747 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -24,8 +24,10 @@
24 24
25#ifdef CONFIG_IPIPE 25#ifdef CONFIG_IPIPE
26 26
27#include <asm/bitsperlong.h>
28#include <mach/irq.h>
29
27#define IPIPE_NR_XIRQS NR_IRQS 30#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29 31
30/* Blackfin-specific, per-cpu pipeline status */ 32/* Blackfin-specific, per-cpu pipeline status */
31#define IPIPE_SYNCDEFER_FLAG 15 33#define IPIPE_SYNCDEFER_FLAG 15
@@ -42,11 +44,14 @@
42#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4) 44#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
43#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5) 45#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
44#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6) 46#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
45#define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP 47#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7)
48#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN
46#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1) 49#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
47 50
48#define IPIPE_TIMER_IRQ IRQ_CORETMR 51#define IPIPE_TIMER_IRQ IRQ_CORETMR
49 52
53#define __IPIPE_FEATURE_SYSINFO_V2 1
54
50#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
51 56
52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 57extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
@@ -63,6 +68,8 @@ void __ipipe_unlock_root(void);
63 68
64#endif /* !__ASSEMBLY__ */ 69#endif /* !__ASSEMBLY__ */
65 70
71#define __IPIPE_FEATURE_SYSINFO_V2 1
72
66#endif /* CONFIG_IPIPE */ 73#endif /* CONFIG_IPIPE */
67 74
68#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */ 75#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index 7fbe42307b9a..ee73f79aef10 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -10,6 +10,16 @@
10#include <linux/types.h> 10#include <linux/types.h>
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12 12
13/* init functions only */
14extern int __init init_arch_irq(void);
15extern void init_exception_vectors(void);
16extern void __init program_IAR(void);
17#ifdef init_mach_irq
18extern void __init init_mach_irq(void);
19#else
20# define init_mach_irq()
21#endif
22
13/* BASE LEVEL interrupt handler routines */ 23/* BASE LEVEL interrupt handler routines */
14asmlinkage void evt_exception(void); 24asmlinkage void evt_exception(void);
15asmlinkage void trap(void); 25asmlinkage void trap(void);
@@ -37,4 +47,19 @@ extern void return_from_exception(void);
37extern int bfin_request_exception(unsigned int exception, void (*handler)(void)); 47extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
38extern int bfin_free_exception(unsigned int exception, void (*handler)(void)); 48extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
39 49
50extern asmlinkage void lower_to_irq14(void);
51extern asmlinkage void bfin_return_from_exception(void);
52extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
53extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
54
55struct irq_data;
56extern void bfin_handle_irq(unsigned irq);
57extern void bfin_ack_noop(struct irq_data *);
58extern void bfin_internal_mask_irq(unsigned int irq);
59extern void bfin_internal_unmask_irq(unsigned int irq);
60
61struct irq_desc;
62extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
63extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
64
40#endif 65#endif
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 813a1af3e865..b4bbb75a9e15 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -8,12 +8,11 @@
8#ifndef __ASM_BFIN_IRQFLAGS_H__ 8#ifndef __ASM_BFIN_IRQFLAGS_H__
9#define __ASM_BFIN_IRQFLAGS_H__ 9#define __ASM_BFIN_IRQFLAGS_H__
10 10
11#include <mach/blackfin.h>
12
11#ifdef CONFIG_SMP 13#ifdef CONFIG_SMP
12# include <asm/pda.h> 14# include <asm/pda.h>
13# include <asm/processor.h> 15# include <asm/processor.h>
14/* Forward decl needed due to cdef inter dependencies */
15static inline uint32_t __pure bfin_dspid(void);
16# define blackfin_core_id() (bfin_dspid() & 0xff)
17# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask 16# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
18#else 17#else
19extern unsigned long bfin_irq_flags; 18extern unsigned long bfin_irq_flags;
@@ -31,186 +30,256 @@ static inline unsigned long bfin_cli(void)
31 return flags; 30 return flags;
32} 31}
33 32
34#ifdef CONFIG_IPIPE
35
36#include <linux/compiler.h>
37#include <linux/ipipe_base.h>
38#include <linux/ipipe_trace.h>
39
40#ifdef CONFIG_DEBUG_HWERR 33#ifdef CONFIG_DEBUG_HWERR
41# define bfin_no_irqs 0x3f 34# define bfin_no_irqs 0x3f
42#else 35#else
43# define bfin_no_irqs 0x1f 36# define bfin_no_irqs 0x1f
44#endif 37#endif
45 38
46#define raw_local_irq_disable() \ 39/*****************************************************************************/
47 do { \ 40/*
48 ipipe_check_context(ipipe_root_domain); \ 41 * Hard, untraced CPU interrupt flag manipulation and access.
49 __ipipe_stall_root(); \ 42 */
50 barrier(); \ 43static inline void __hard_local_irq_disable(void)
51 } while (0) 44{
45 bfin_cli();
46}
52 47
53#define raw_local_irq_enable() \ 48static inline void __hard_local_irq_enable(void)
54 do { \ 49{
55 barrier(); \ 50 bfin_sti(bfin_irq_flags);
56 ipipe_check_context(ipipe_root_domain); \ 51}
57 __ipipe_unstall_root(); \
58 } while (0)
59 52
60#define raw_local_save_flags_ptr(x) \ 53static inline unsigned long hard_local_save_flags(void)
61 do { \ 54{
62 *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \ 55 return bfin_read_IMASK();
63 } while (0) 56}
64 57
65#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x)) 58static inline unsigned long __hard_local_irq_save(void)
59{
60 unsigned long flags;
61 flags = bfin_cli();
62#ifdef CONFIG_DEBUG_HWERR
63 bfin_sti(0x3f);
64#endif
65 return flags;
66}
66 67
67#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs) 68static inline int hard_irqs_disabled_flags(unsigned long flags)
69{
70 return (flags & ~0x3f) == 0;
71}
68 72
69#define raw_local_irq_save_ptr(x) \ 73static inline int hard_irqs_disabled(void)
70 do { \ 74{
71 *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \ 75 unsigned long flags = hard_local_save_flags();
72 barrier(); \ 76 return hard_irqs_disabled_flags(flags);
73 } while (0) 77}
74 78
75#define raw_local_irq_save(x) \ 79static inline void __hard_local_irq_restore(unsigned long flags)
76 do { \ 80{
77 ipipe_check_context(ipipe_root_domain); \ 81 if (!hard_irqs_disabled_flags(flags))
78 raw_local_irq_save_ptr(&(x)); \ 82 __hard_local_irq_enable();
79 } while (0) 83}
80 84
81static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) 85/*****************************************************************************/
86/*
87 * Interrupt pipe handling.
88 */
89#ifdef CONFIG_IPIPE
90
91#include <linux/compiler.h>
92#include <linux/ipipe_trace.h>
93/*
94 * Way too many inter-deps between low-level headers in this port, so
95 * we redeclare the required bits we cannot pick from
96 * <asm/ipipe_base.h> to prevent circular dependencies.
97 */
98void __ipipe_stall_root(void);
99void __ipipe_unstall_root(void);
100unsigned long __ipipe_test_root(void);
101unsigned long __ipipe_test_and_stall_root(void);
102void __ipipe_restore_root(unsigned long flags);
103
104#ifdef CONFIG_IPIPE_DEBUG_CONTEXT
105struct ipipe_domain;
106extern struct ipipe_domain ipipe_root;
107void ipipe_check_context(struct ipipe_domain *ipd);
108#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root)
109#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */
110#define __check_irqop_context(ipd) do { } while (0)
111#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */
112
113/*
114 * Interrupt pipe interface to linux/irqflags.h.
115 */
116static inline void arch_local_irq_disable(void)
82{ 117{
83 /* 118 __check_irqop_context();
84 * Merge virtual and real interrupt mask bits into a single 119 __ipipe_stall_root();
85 * 32bit word. 120 barrier();
86 */
87 return (real & ~(1 << 31)) | ((virt != 0) << 31);
88} 121}
89 122
90static inline int raw_demangle_irq_bits(unsigned long *x) 123static inline void arch_local_irq_enable(void)
91{ 124{
92 int virt = (*x & (1 << 31)) != 0; 125 barrier();
93 *x &= ~(1L << 31); 126 __check_irqop_context();
94 return virt; 127 __ipipe_unstall_root();
95} 128}
96 129
97static inline void local_irq_disable_hw_notrace(void) 130static inline unsigned long arch_local_save_flags(void)
98{ 131{
99 bfin_cli(); 132 return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
100} 133}
101 134
102static inline void local_irq_enable_hw_notrace(void) 135static inline int arch_irqs_disabled_flags(unsigned long flags)
103{ 136{
104 bfin_sti(bfin_irq_flags); 137 return flags == bfin_no_irqs;
105} 138}
106 139
107#define local_save_flags_hw(flags) \ 140static inline unsigned long arch_local_irq_save(void)
108 do { \ 141{
109 (flags) = bfin_read_IMASK(); \ 142 unsigned long flags;
110 } while (0)
111 143
112#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0) 144 __check_irqop_context();
145 flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
146 barrier();
113 147
114#define irqs_disabled_hw() \ 148 return flags;
115 ({ \ 149}
116 unsigned long flags; \
117 local_save_flags_hw(flags); \
118 irqs_disabled_flags_hw(flags); \
119 })
120 150
121static inline void local_irq_save_ptr_hw(unsigned long *flags) 151static inline void arch_local_irq_restore(unsigned long flags)
122{ 152{
123 *flags = bfin_cli(); 153 __check_irqop_context();
124#ifdef CONFIG_DEBUG_HWERR 154 __ipipe_restore_root(flags == bfin_no_irqs);
125 bfin_sti(0x3f);
126#endif
127} 155}
128 156
129#define local_irq_save_hw_notrace(flags) \ 157static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
130 do { \ 158{
131 local_irq_save_ptr_hw(&(flags)); \ 159 /*
132 } while (0) 160 * Merge virtual and real interrupt mask bits into a single
161 * 32bit word.
162 */
163 return (real & ~(1 << 31)) | ((virt != 0) << 31);
164}
133 165
134static inline void local_irq_restore_hw_notrace(unsigned long flags) 166static inline int arch_demangle_irq_bits(unsigned long *x)
135{ 167{
136 if (!irqs_disabled_flags_hw(flags)) 168 int virt = (*x & (1 << 31)) != 0;
137 local_irq_enable_hw_notrace(); 169 *x &= ~(1L << 31);
170 return virt;
138} 171}
139 172
173/*
174 * Interface to various arch routines that may be traced.
175 */
140#ifdef CONFIG_IPIPE_TRACE_IRQSOFF 176#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
141# define local_irq_disable_hw() \ 177static inline void hard_local_irq_disable(void)
142 do { \ 178{
143 if (!irqs_disabled_hw()) { \ 179 if (!hard_irqs_disabled()) {
144 local_irq_disable_hw_notrace(); \ 180 __hard_local_irq_disable();
145 ipipe_trace_begin(0x80000000); \ 181 ipipe_trace_begin(0x80000000);
146 } \ 182 }
147 } while (0) 183}
148# define local_irq_enable_hw() \
149 do { \
150 if (irqs_disabled_hw()) { \
151 ipipe_trace_end(0x80000000); \
152 local_irq_enable_hw_notrace(); \
153 } \
154 } while (0)
155# define local_irq_save_hw(flags) \
156 do { \
157 local_save_flags_hw(flags); \
158 if (!irqs_disabled_flags_hw(flags)) { \
159 local_irq_disable_hw_notrace(); \
160 ipipe_trace_begin(0x80000001); \
161 } \
162 } while (0)
163# define local_irq_restore_hw(flags) \
164 do { \
165 if (!irqs_disabled_flags_hw(flags)) { \
166 ipipe_trace_end(0x80000001); \
167 local_irq_enable_hw_notrace(); \
168 } \
169 } while (0)
170#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
171# define local_irq_disable_hw() local_irq_disable_hw_notrace()
172# define local_irq_enable_hw() local_irq_enable_hw_notrace()
173# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags)
174# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags)
175#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
176 184
177#else /* CONFIG_IPIPE */ 185static inline void hard_local_irq_enable(void)
186{
187 if (hard_irqs_disabled()) {
188 ipipe_trace_end(0x80000000);
189 __hard_local_irq_enable();
190 }
191}
178 192
179static inline void raw_local_irq_disable(void) 193static inline unsigned long hard_local_irq_save(void)
180{ 194{
181 bfin_cli(); 195 unsigned long flags = hard_local_save_flags();
196 if (!hard_irqs_disabled_flags(flags)) {
197 __hard_local_irq_disable();
198 ipipe_trace_begin(0x80000001);
199 }
200 return flags;
182} 201}
183static inline void raw_local_irq_enable(void) 202
203static inline void hard_local_irq_restore(unsigned long flags)
184{ 204{
185 bfin_sti(bfin_irq_flags); 205 if (!hard_irqs_disabled_flags(flags)) {
206 ipipe_trace_end(0x80000001);
207 __hard_local_irq_enable();
208 }
186} 209}
187 210
188#define raw_local_save_flags(flags) do { (flags) = bfin_read_IMASK(); } while (0) 211#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
212# define hard_local_irq_disable() __hard_local_irq_disable()
213# define hard_local_irq_enable() __hard_local_irq_enable()
214# define hard_local_irq_save() __hard_local_irq_save()
215# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
216#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
189 217
190#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) 218#define hard_local_irq_save_cond() hard_local_irq_save()
219#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags)
191 220
192static inline unsigned long __raw_local_irq_save(void) 221#else /* !CONFIG_IPIPE */
193{
194 unsigned long flags = bfin_cli();
195#ifdef CONFIG_DEBUG_HWERR
196 bfin_sti(0x3f);
197#endif
198 return flags;
199}
200#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
201 222
202#define local_irq_save_hw(flags) raw_local_irq_save(flags) 223/*
203#define local_irq_restore_hw(flags) raw_local_irq_restore(flags) 224 * Direct interface to linux/irqflags.h.
204#define local_irq_enable_hw() raw_local_irq_enable() 225 */
205#define local_irq_disable_hw() raw_local_irq_disable() 226#define arch_local_save_flags() hard_local_save_flags()
206#define irqs_disabled_hw() irqs_disabled() 227#define arch_local_irq_save(flags) __hard_local_irq_save()
228#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
229#define arch_local_irq_enable() __hard_local_irq_enable()
230#define arch_local_irq_disable() __hard_local_irq_disable()
231#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
232#define arch_irqs_disabled() hard_irqs_disabled()
233
234/*
235 * Interface to various arch routines that may be traced.
236 */
237#define hard_local_irq_save() __hard_local_irq_save()
238#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
239#define hard_local_irq_enable() __hard_local_irq_enable()
240#define hard_local_irq_disable() __hard_local_irq_disable()
241#define hard_local_irq_save_cond() hard_local_save_flags()
242#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0)
207 243
208#endif /* !CONFIG_IPIPE */ 244#endif /* !CONFIG_IPIPE */
209 245
210static inline void raw_local_irq_restore(unsigned long flags) 246#ifdef CONFIG_SMP
211{ 247#define hard_local_irq_save_smp() hard_local_irq_save()
212 if (!raw_irqs_disabled_flags(flags)) 248#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags)
213 raw_local_irq_enable(); 249#else
214} 250#define hard_local_irq_save_smp() hard_local_save_flags()
251#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0)
252#endif
253
254/*
255 * Remap the arch-neutral IRQ state manipulation macros to the
256 * blackfin-specific hard_local_irq_* API.
257 */
258#define local_irq_save_hw(flags) \
259 do { \
260 (flags) = hard_local_irq_save(); \
261 } while (0)
262#define local_irq_restore_hw(flags) \
263 do { \
264 hard_local_irq_restore(flags); \
265 } while (0)
266#define local_irq_disable_hw() \
267 do { \
268 hard_local_irq_disable(); \
269 } while (0)
270#define local_irq_enable_hw() \
271 do { \
272 hard_local_irq_enable(); \
273 } while (0)
274#define local_irq_save_hw_notrace(flags) \
275 do { \
276 (flags) = __hard_local_irq_save(); \
277 } while (0)
278#define local_irq_restore_hw_notrace(flags) \
279 do { \
280 __hard_local_irq_restore(flags); \
281 } while (0)
282
283#define irqs_disabled_hw() hard_irqs_disabled()
215 284
216#endif 285#endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index 8651afe12990..aaf884591b07 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -103,7 +103,12 @@ static inline void arch_kgdb_breakpoint(void)
103 asm("EXCPT 2;"); 103 asm("EXCPT 2;");
104} 104}
105#define BREAK_INSTR_SIZE 2 105#define BREAK_INSTR_SIZE 2
106#define CACHE_FLUSH_IS_SAFE 1 106#ifdef CONFIG_SMP
107# define CACHE_FLUSH_IS_SAFE 0
108#else
109# define CACHE_FLUSH_IS_SAFE 1
110#endif
111#define GDB_ADJUSTS_BREAK_OFFSET
107#define HW_INST_WATCHPOINT_NUM 6 112#define HW_INST_WATCHPOINT_NUM 6
108#define HW_WATCHPOINT_NUM 8 113#define HW_WATCHPOINT_NUM 8
109#define TYPE_INST_WATCHPOINT 0 114#define TYPE_INST_WATCHPOINT 0
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index e1a9b4624f91..3828c70e7a2e 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -97,8 +97,8 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next
97} 97}
98 98
99#ifdef CONFIG_IPIPE 99#ifdef CONFIG_IPIPE
100#define lock_mm_switch(flags) local_irq_save_hw_cond(flags) 100#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
101#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags) 101#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
102#else 102#else
103#define lock_mm_switch(flags) do { (void)(flags); } while (0) 103#define lock_mm_switch(flags) do { (void)(flags); } while (0)
104#define unlock_mm_switch(flags) do { (void)(flags); } while (0) 104#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
@@ -205,9 +205,9 @@ static inline void destroy_context(struct mm_struct *mm)
205} 205}
206 206
207#define ipipe_mm_switch_protect(flags) \ 207#define ipipe_mm_switch_protect(flags) \
208 local_irq_save_hw_cond(flags) 208 flags = hard_local_irq_save_cond()
209 209
210#define ipipe_mm_switch_unprotect(flags) \ 210#define ipipe_mm_switch_unprotect(flags) \
211 local_irq_restore_hw_cond(flags) 211 hard_local_irq_restore_cond(flags)
212 212
213#endif 213#endif
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
new file mode 100644
index 000000000000..3d2b1716322f
--- /dev/null
+++ b/arch/blackfin/include/asm/perf_event.h
@@ -0,0 +1 @@
#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index aea880274de7..8af7772e84cc 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -14,7 +14,7 @@
14#define current_text_addr() ({ __label__ _l; _l: &&_l;}) 14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15 15
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17#include <asm/blackfin.h> 17#include <mach/blackfin.h>
18 18
19static inline unsigned long rdusp(void) 19static inline unsigned long rdusp(void)
20{ 20{
@@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
134 return bfin_read_DSPID(); 134 return bfin_read_DSPID();
135} 135}
136 136
137#define blackfin_core_id() (bfin_dspid() & 0xff)
138
137static inline uint32_t __pure bfin_compiled_revid(void) 139static inline uint32_t __pure bfin_compiled_revid(void)
138{ 140{
139#if defined(CONFIG_BF_REV_0_0) 141#if defined(CONFIG_BF_REV_0_0)
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index aaa1c6c2bc19..7854d4367c15 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -102,17 +102,15 @@ struct pt_regs {
102/* user_mode returns true if only one bit is set in IPEND, other than the 102/* user_mode returns true if only one bit is set in IPEND, other than the
103 master interrupt enable. */ 103 master interrupt enable. */
104#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) 104#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
105#define instruction_pointer(regs) ((regs)->pc)
106#define user_stack_pointer(regs) ((regs)->usp)
107#define profile_pc(regs) instruction_pointer(regs)
108extern void show_regs(struct pt_regs *); 105extern void show_regs(struct pt_regs *);
109 106
110#define arch_has_single_step() (1) 107#define arch_has_single_step() (1)
111extern void user_enable_single_step(struct task_struct *child);
112extern void user_disable_single_step(struct task_struct *child);
113/* common code demands this function */ 108/* common code demands this function */
114#define ptrace_disable(child) user_disable_single_step(child) 109#define ptrace_disable(child) user_disable_single_step(child)
115 110
111extern int is_user_addr_valid(struct task_struct *child,
112 unsigned long start, unsigned long len);
113
116/* 114/*
117 * Get the address of the live pt_regs for the specified task. 115 * Get the address of the live pt_regs for the specified task.
118 * These are saved onto the top kernel stack when the process 116 * These are saved onto the top kernel stack when the process
@@ -127,6 +125,8 @@ extern void user_disable_single_step(struct task_struct *child);
127 ((unsigned long)task_stack_page(task) + \ 125 ((unsigned long)task_stack_page(task) + \
128 (THREAD_SIZE - sizeof(struct pt_regs))) 126 (THREAD_SIZE - sizeof(struct pt_regs)))
129 127
128#include <asm-generic/ptrace.h>
129
130#endif /* __KERNEL__ */ 130#endif /* __KERNEL__ */
131 131
132#endif /* __ASSEMBLY__ */ 132#endif /* __ASSEMBLY__ */
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
index 94a4a12e3bf2..a0cb0caff152 100644
--- a/arch/blackfin/include/asm/serial.h
+++ b/arch/blackfin/include/asm/serial.h
@@ -1,2 +1 @@
1#include <asm-generic/serial.h> #include <asm-generic/serial.h>
2#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
index f5b537967116..af6c0aa79bae 100644
--- a/arch/blackfin/include/asm/smp.h
+++ b/arch/blackfin/include/asm/smp.h
@@ -17,7 +17,12 @@
17 17
18#define raw_smp_processor_id() blackfin_core_id() 18#define raw_smp_processor_id() blackfin_core_id()
19 19
20extern char coreb_trampoline_start, coreb_trampoline_end; 20extern void bfin_relocate_coreb_l1_mem(void);
21
22#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
23asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
24extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
25#endif
21 26
22struct corelock_slot { 27struct corelock_slot {
23 int lock; 28 int lock;
@@ -34,7 +39,7 @@ extern unsigned long dcache_invld_count[NR_CPUS];
34void smp_icache_flush_range_others(unsigned long start, 39void smp_icache_flush_range_others(unsigned long start,
35 unsigned long end); 40 unsigned long end);
36#ifdef CONFIG_HOTPLUG_CPU 41#ifdef CONFIG_HOTPLUG_CPU
37void coreb_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 42void coreb_die(void);
38void cpu_die(void); 43void cpu_die(void);
39void platform_cpu_die(void); 44void platform_cpu_die(void);
40int __cpu_disable(void); 45int __cpu_disable(void);
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1942ccfedbe0..1f286e71c21f 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
17asmlinkage void __raw_spin_lock_asm(volatile int *ptr); 17asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
18asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); 18asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
19asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); 19asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
20asmlinkage void arch_read_lock_asm(volatile int *ptr); 20asmlinkage void __raw_read_lock_asm(volatile int *ptr);
21asmlinkage int arch_read_trylock_asm(volatile int *ptr); 21asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
22asmlinkage void arch_read_unlock_asm(volatile int *ptr); 22asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
23asmlinkage void arch_write_lock_asm(volatile int *ptr); 23asmlinkage void __raw_write_lock_asm(volatile int *ptr);
24asmlinkage int arch_write_trylock_asm(volatile int *ptr); 24asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
25asmlinkage void arch_write_unlock_asm(volatile int *ptr); 25asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
26 26
27static inline int arch_spin_is_locked(arch_spinlock_t *lock) 27static inline int arch_spin_is_locked(arch_spinlock_t *lock)
28{ 28{
@@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
64 64
65static inline void arch_read_lock(arch_rwlock_t *rw) 65static inline void arch_read_lock(arch_rwlock_t *rw)
66{ 66{
67 arch_read_lock_asm(&rw->lock); 67 __raw_read_lock_asm(&rw->lock);
68} 68}
69 69
70#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
71
70static inline int arch_read_trylock(arch_rwlock_t *rw) 72static inline int arch_read_trylock(arch_rwlock_t *rw)
71{ 73{
72 return arch_read_trylock_asm(&rw->lock); 74 return __raw_read_trylock_asm(&rw->lock);
73} 75}
74 76
75static inline void arch_read_unlock(arch_rwlock_t *rw) 77static inline void arch_read_unlock(arch_rwlock_t *rw)
76{ 78{
77 arch_read_unlock_asm(&rw->lock); 79 __raw_read_unlock_asm(&rw->lock);
78} 80}
79 81
80static inline void arch_write_lock(arch_rwlock_t *rw) 82static inline void arch_write_lock(arch_rwlock_t *rw)
81{ 83{
82 arch_write_lock_asm(&rw->lock); 84 __raw_write_lock_asm(&rw->lock);
83} 85}
84 86
87#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
88
85static inline int arch_write_trylock(arch_rwlock_t *rw) 89static inline int arch_write_trylock(arch_rwlock_t *rw)
86{ 90{
87 return arch_write_trylock_asm(&rw->lock); 91 return __raw_write_trylock_asm(&rw->lock);
88} 92}
89 93
90static inline void arch_write_unlock(arch_rwlock_t *rw) 94static inline void arch_write_unlock(arch_rwlock_t *rw)
91{ 95{
92 arch_write_unlock_asm(&rw->lock); 96 __raw_write_unlock_asm(&rw->lock);
93} 97}
94 98
95#define arch_spin_relax(lock) cpu_relax() 99#define arch_spin_relax(lock) cpu_relax()
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index dde19b1d25f5..44bd0cced725 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -19,11 +19,11 @@
19 * Force strict CPU ordering. 19 * Force strict CPU ordering.
20 */ 20 */
21#define nop() __asm__ __volatile__ ("nop;\n\t" : : ) 21#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
22#define mb() __asm__ __volatile__ ("" : : : "memory") 22#define smp_mb() mb()
23#define rmb() __asm__ __volatile__ ("" : : : "memory") 23#define smp_rmb() rmb()
24#define wmb() __asm__ __volatile__ ("" : : : "memory") 24#define smp_wmb() wmb()
25#define set_mb(var, value) do { (void) xchg(&var, value); } while (0) 25#define set_mb(var, value) do { var = value; mb(); } while (0)
26#define read_barrier_depends() do { } while(0) 26#define smp_read_barrier_depends() read_barrier_depends()
27 27
28#ifdef CONFIG_SMP 28#ifdef CONFIG_SMP
29asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); 29asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
@@ -37,16 +37,16 @@ asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
37 unsigned long new, unsigned long old); 37 unsigned long new, unsigned long old);
38 38
39#ifdef __ARCH_SYNC_CORE_DCACHE 39#ifdef __ARCH_SYNC_CORE_DCACHE
40# define smp_mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) 40/* Force Core data cache coherence */
41# define smp_rmb() do { barrier(); smp_check_barrier(); } while (0) 41# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
42# define smp_wmb() do { barrier(); smp_mark_barrier(); } while (0) 42# define rmb() do { barrier(); smp_check_barrier(); } while (0)
43#define smp_read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) 43# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
44 44# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
45#else 45#else
46# define smp_mb() barrier() 46# define mb() barrier()
47# define smp_rmb() barrier() 47# define rmb() barrier()
48# define smp_wmb() barrier() 48# define wmb() barrier()
49#define smp_read_barrier_depends() barrier() 49# define read_barrier_depends() do { } while (0)
50#endif 50#endif
51 51
52static inline unsigned long __xchg(unsigned long x, volatile void *ptr, 52static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
@@ -99,10 +99,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
99 99
100#else /* !CONFIG_SMP */ 100#else /* !CONFIG_SMP */
101 101
102#define smp_mb() barrier() 102#define mb() barrier()
103#define smp_rmb() barrier() 103#define rmb() barrier()
104#define smp_wmb() barrier() 104#define wmb() barrier()
105#define smp_read_barrier_depends() do { } while(0) 105#define read_barrier_depends() do { } while (0)
106 106
107struct __xchg_dummy { 107struct __xchg_dummy {
108 unsigned long a[100]; 108 unsigned long a[100];
@@ -117,7 +117,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
117 unsigned long tmp = 0; 117 unsigned long tmp = 0;
118 unsigned long flags; 118 unsigned long flags;
119 119
120 local_irq_save_hw(flags); 120 flags = hard_local_irq_save();
121 121
122 switch (size) { 122 switch (size) {
123 case 1: 123 case 1:
@@ -139,7 +139,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
139 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); 139 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
140 break; 140 break;
141 } 141 }
142 local_irq_restore_hw(flags); 142 hard_local_irq_restore(flags);
143 return tmp; 143 return tmp;
144} 144}
145 145
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
index 9fe0da612c09..70c4e511cae6 100644
--- a/arch/blackfin/include/asm/traps.h
+++ b/arch/blackfin/include/asm/traps.h
@@ -57,7 +57,7 @@
57#define HWC_x3(level) \ 57#define HWC_x3(level) \
58 "External Memory Addressing Error\n" 58 "External Memory Addressing Error\n"
59#define EXC_0x04(level) \ 59#define EXC_0x04(level) \
60 "Unimplmented exception occured\n" \ 60 "Unimplmented exception occurred\n" \
61 level " - Maybe you forgot to install a custom exception handler?\n" 61 level " - Maybe you forgot to install a custom exception handler?\n"
62#define HWC_x12(level) \ 62#define HWC_x12(level) \
63 "Performance Monitor Overflow\n" 63 "Performance Monitor Overflow\n"
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 14fcd254b185..0ccba60b9ccf 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -392,8 +392,15 @@
392#define __NR_fanotify_init 371 392#define __NR_fanotify_init 371
393#define __NR_fanotify_mark 372 393#define __NR_fanotify_mark 372
394#define __NR_prlimit64 373 394#define __NR_prlimit64 373
395#define __NR_cacheflush 374
396#define __NR_name_to_handle_at 375
397#define __NR_open_by_handle_at 376
398#define __NR_clock_adjtime 377
399#define __NR_syncfs 378
400#define __NR_setns 379
401#define __NR_sendmmsg 380
395 402
396#define __NR_syscall 374 403#define __NR_syscall 381
397#define NR_syscalls __NR_syscall 404#define NR_syscalls __NR_syscall
398 405
399/* Old optional stuff no one actually uses */ 406/* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
new file mode 100644
index 000000000000..cab14e911dc2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -0,0 +1,57 @@
1/*
2 * Common Blackfin IRQ definitions (i.e. the CEC)
3 *
4 * Copyright 2005-2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#ifndef _MACH_COMMON_IRQ_H_
10#define _MACH_COMMON_IRQ_H_
11
12/*
13 * Core events interrupt source definitions
14 *
15 * Event Source Event Name
16 * Emulation EMU 0 (highest priority)
17 * Reset RST 1
18 * NMI NMI 2
19 * Exception EVX 3
20 * Reserved -- 4
21 * Hardware Error IVHW 5
22 * Core Timer IVTMR 6
23 * Peripherals IVG7 7
24 * Peripherals IVG8 8
25 * Peripherals IVG9 9
26 * Peripherals IVG10 10
27 * Peripherals IVG11 11
28 * Peripherals IVG12 12
29 * Peripherals IVG13 13
30 * Softirq IVG14 14
31 * System Call IVG15 15 (lowest priority)
32 */
33
34/* The ABSTRACT IRQ definitions */
35#define IRQ_EMU 0 /* Emulation */
36#define IRQ_RST 1 /* reset */
37#define IRQ_NMI 2 /* Non Maskable */
38#define IRQ_EVX 3 /* Exception */
39#define IRQ_UNUSED 4 /* - unused interrupt */
40#define IRQ_HWERR 5 /* Hardware Error */
41#define IRQ_CORETMR 6 /* Core timer */
42
43#define BFIN_IRQ(x) ((x) + 7)
44
45#define IVG7 7
46#define IVG8 8
47#define IVG9 9
48#define IVG10 10
49#define IVG11 11
50#define IVG12 12
51#define IVG13 13
52#define IVG14 14
53#define IVG15 15
54
55#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
56
57#endif
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644
index 000000000000..382178b361af
--- /dev/null
+++ b/arch/blackfin/include/mach-common/pll.h
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_COMMON_PLL_H
8#define _MACH_COMMON_PLL_H
9
10#ifndef __ASSEMBLY__
11
12#include <asm/blackfin.h>
13#include <asm/irqflags.h>
14
15#ifndef bfin_iwr_restore
16static inline void
17bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
18{
19#ifdef SIC_IWR
20 bfin_write_SIC_IWR(iwr0);
21#else
22 bfin_write_SIC_IWR0(iwr0);
23# ifdef SIC_IWR1
24 bfin_write_SIC_IWR1(iwr1);
25# endif
26# ifdef SIC_IWR2
27 bfin_write_SIC_IWR2(iwr2);
28# endif
29#endif
30}
31#endif
32
33#ifndef bfin_iwr_save
34static inline void
35bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
36 unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
37{
38#ifdef SIC_IWR
39 *iwr0 = bfin_read_SIC_IWR();
40#else
41 *iwr0 = bfin_read_SIC_IWR0();
42# ifdef SIC_IWR1
43 *iwr1 = bfin_read_SIC_IWR1();
44# endif
45# ifdef SIC_IWR2
46 *iwr2 = bfin_read_SIC_IWR2();
47# endif
48#endif
49 bfin_iwr_restore(niwr0, niwr1, niwr2);
50}
51#endif
52
53static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
54{
55 unsigned long flags, iwr0, iwr1, iwr2;
56
57 if (val == bfin_read_PLL_CTL())
58 return;
59
60 flags = hard_local_irq_save();
61 /* Enable the PLL Wakeup bit in SIC IWR */
62 bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
63
64 bfin_write16(addr, val);
65 SSYNC();
66 asm("IDLE;");
67
68 bfin_iwr_restore(iwr0, iwr1, iwr2);
69 hard_local_irq_restore(flags);
70}
71
72/* Writing to PLL_CTL initiates a PLL relock sequence */
73static inline void bfin_write_PLL_CTL(unsigned int val)
74{
75 _bfin_write_pll_relock(PLL_CTL, val);
76}
77
78/* Writing to VR_CTL initiates a PLL relock sequence */
79static inline void bfin_write_VR_CTL(unsigned int val)
80{
81 _bfin_write_pll_relock(VR_CTL, val);
82}
83
84#endif
85
86#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
new file mode 100644
index 000000000000..9f78a761c40a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-a.h
@@ -0,0 +1,25 @@
1/*
2 * Port A Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_A__
6#define __BFIN_PERIPHERAL_PORT_A__
7
8#define PA0 (1 << 0)
9#define PA1 (1 << 1)
10#define PA2 (1 << 2)
11#define PA3 (1 << 3)
12#define PA4 (1 << 4)
13#define PA5 (1 << 5)
14#define PA6 (1 << 6)
15#define PA7 (1 << 7)
16#define PA8 (1 << 8)
17#define PA9 (1 << 9)
18#define PA10 (1 << 10)
19#define PA11 (1 << 11)
20#define PA12 (1 << 12)
21#define PA13 (1 << 13)
22#define PA14 (1 << 14)
23#define PA15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
new file mode 100644
index 000000000000..b81702f09ec6
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-b.h
@@ -0,0 +1,25 @@
1/*
2 * Port B Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_B__
6#define __BFIN_PERIPHERAL_PORT_B__
7
8#define PB0 (1 << 0)
9#define PB1 (1 << 1)
10#define PB2 (1 << 2)
11#define PB3 (1 << 3)
12#define PB4 (1 << 4)
13#define PB5 (1 << 5)
14#define PB6 (1 << 6)
15#define PB7 (1 << 7)
16#define PB8 (1 << 8)
17#define PB9 (1 << 9)
18#define PB10 (1 << 10)
19#define PB11 (1 << 11)
20#define PB12 (1 << 12)
21#define PB13 (1 << 13)
22#define PB14 (1 << 14)
23#define PB15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
new file mode 100644
index 000000000000..3cc665e0ba08
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-c.h
@@ -0,0 +1,25 @@
1/*
2 * Port C Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_C__
6#define __BFIN_PERIPHERAL_PORT_C__
7
8#define PC0 (1 << 0)
9#define PC1 (1 << 1)
10#define PC2 (1 << 2)
11#define PC3 (1 << 3)
12#define PC4 (1 << 4)
13#define PC5 (1 << 5)
14#define PC6 (1 << 6)
15#define PC7 (1 << 7)
16#define PC8 (1 << 8)
17#define PC9 (1 << 9)
18#define PC10 (1 << 10)
19#define PC11 (1 << 11)
20#define PC12 (1 << 12)
21#define PC13 (1 << 13)
22#define PC14 (1 << 14)
23#define PC15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
new file mode 100644
index 000000000000..868c6a01f1b2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-d.h
@@ -0,0 +1,25 @@
1/*
2 * Port D Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_D__
6#define __BFIN_PERIPHERAL_PORT_D__
7
8#define PD0 (1 << 0)
9#define PD1 (1 << 1)
10#define PD2 (1 << 2)
11#define PD3 (1 << 3)
12#define PD4 (1 << 4)
13#define PD5 (1 << 5)
14#define PD6 (1 << 6)
15#define PD7 (1 << 7)
16#define PD8 (1 << 8)
17#define PD9 (1 << 9)
18#define PD10 (1 << 10)
19#define PD11 (1 << 11)
20#define PD12 (1 << 12)
21#define PD13 (1 << 13)
22#define PD14 (1 << 14)
23#define PD15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
new file mode 100644
index 000000000000..c88b0d0dd443
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-e.h
@@ -0,0 +1,25 @@
1/*
2 * Port E Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_E__
6#define __BFIN_PERIPHERAL_PORT_E__
7
8#define PE0 (1 << 0)
9#define PE1 (1 << 1)
10#define PE2 (1 << 2)
11#define PE3 (1 << 3)
12#define PE4 (1 << 4)
13#define PE5 (1 << 5)
14#define PE6 (1 << 6)
15#define PE7 (1 << 7)
16#define PE8 (1 << 8)
17#define PE9 (1 << 9)
18#define PE10 (1 << 10)
19#define PE11 (1 << 11)
20#define PE12 (1 << 12)
21#define PE13 (1 << 13)
22#define PE14 (1 << 14)
23#define PE15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
new file mode 100644
index 000000000000..d6af20633278
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-f.h
@@ -0,0 +1,25 @@
1/*
2 * Port F Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_F__
6#define __BFIN_PERIPHERAL_PORT_F__
7
8#define PF0 (1 << 0)
9#define PF1 (1 << 1)
10#define PF2 (1 << 2)
11#define PF3 (1 << 3)
12#define PF4 (1 << 4)
13#define PF5 (1 << 5)
14#define PF6 (1 << 6)
15#define PF7 (1 << 7)
16#define PF8 (1 << 8)
17#define PF9 (1 << 9)
18#define PF10 (1 << 10)
19#define PF11 (1 << 11)
20#define PF12 (1 << 12)
21#define PF13 (1 << 13)
22#define PF14 (1 << 14)
23#define PF15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
new file mode 100644
index 000000000000..09355d333c0e
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-g.h
@@ -0,0 +1,25 @@
1/*
2 * Port G Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_G__
6#define __BFIN_PERIPHERAL_PORT_G__
7
8#define PG0 (1 << 0)
9#define PG1 (1 << 1)
10#define PG2 (1 << 2)
11#define PG3 (1 << 3)
12#define PG4 (1 << 4)
13#define PG5 (1 << 5)
14#define PG6 (1 << 6)
15#define PG7 (1 << 7)
16#define PG8 (1 << 8)
17#define PG9 (1 << 9)
18#define PG10 (1 << 10)
19#define PG11 (1 << 11)
20#define PG12 (1 << 12)
21#define PG13 (1 << 13)
22#define PG14 (1 << 14)
23#define PG15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
new file mode 100644
index 000000000000..fa3910c6fbd4
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-h.h
@@ -0,0 +1,25 @@
1/*
2 * Port H Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_H__
6#define __BFIN_PERIPHERAL_PORT_H__
7
8#define PH0 (1 << 0)
9#define PH1 (1 << 1)
10#define PH2 (1 << 2)
11#define PH3 (1 << 3)
12#define PH4 (1 << 4)
13#define PH5 (1 << 5)
14#define PH6 (1 << 6)
15#define PH7 (1 << 7)
16#define PH8 (1 << 8)
17#define PH9 (1 << 9)
18#define PH10 (1 << 10)
19#define PH11 (1 << 11)
20#define PH12 (1 << 12)
21#define PH13 (1 << 13)
22#define PH14 (1 << 14)
23#define PH15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
new file mode 100644
index 000000000000..f176f08af624
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-i.h
@@ -0,0 +1,25 @@
1/*
2 * Port I Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_I__
6#define __BFIN_PERIPHERAL_PORT_I__
7
8#define PI0 (1 << 0)
9#define PI1 (1 << 1)
10#define PI2 (1 << 2)
11#define PI3 (1 << 3)
12#define PI4 (1 << 4)
13#define PI5 (1 << 5)
14#define PI6 (1 << 6)
15#define PI7 (1 << 7)
16#define PI8 (1 << 8)
17#define PI9 (1 << 9)
18#define PI10 (1 << 10)
19#define PI11 (1 << 11)
20#define PI12 (1 << 12)
21#define PI13 (1 << 13)
22#define PI14 (1 << 14)
23#define PI15 (1 << 15)
24
25#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
new file mode 100644
index 000000000000..924123ecec5a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-j.h
@@ -0,0 +1,25 @@
1/*
2 * Port J Masks
3 */
4
5#ifndef __BFIN_PERIPHERAL_PORT_J__
6#define __BFIN_PERIPHERAL_PORT_J__
7
8#define PJ0 (1 << 0)
9#define PJ1 (1 << 1)
10#define PJ2 (1 << 2)
11#define PJ3 (1 << 3)
12#define PJ4 (1 << 4)
13#define PJ5 (1 << 5)
14#define PJ6 (1 << 6)
15#define PJ7 (1 << 7)
16#define PJ8 (1 << 8)
17#define PJ9 (1 << 9)
18#define PJ10 (1 << 10)
19#define PJ11 (1 << 11)
20#define PJ12 (1 << 12)
21#define PJ13 (1 << 13)
22#define PJ14 (1 << 14)
23#define PJ15 (1 << 15)
24
25#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 07:43:28 -0400