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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-20 19:42:36 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-20 19:42:36 -0500
commitbfc7249cc293deac8f2678b7ec3d2407b68c0a33 (patch)
tree6a73d533cc72fbc583ca1af46defe7d3c26d2751 /arch/arm
parenta4e1328a9d20ccf4a9e5a19fce172e6deb2a33e2 (diff)
parentf1e9203e2366164b832d8a6ce10134de8c575178 (diff)
Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/mmp2-brownstone.dts2
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi29
-rw-r--r--arch/arm/boot/dts/pxa168-aspenite.dts2
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi27
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts2
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi28
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi12
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi12
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi12
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi12
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi12
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi12
-rw-r--r--arch/arm/mach-mmp/Kconfig12
-rw-r--r--arch/arm/mach-mmp/mmp-dt.c57
-rw-r--r--arch/arm/mach-mmp/mmp2-dt.c26
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c23
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c6
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c6
19 files changed, 152 insertions, 143 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6a3d9a6c4497..91bd5bd62857 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -177,6 +177,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
177dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 177dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
178dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 178dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
179dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb 179dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
180dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
181 pxa910-dkb.dtb \
182 mmp2-brownstone.dtb
180dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 183dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
181dtb-$(CONFIG_ARCH_MXC) += \ 184dtb-$(CONFIG_ARCH_MXC) += \
182 imx1-ads.dtb \ 185 imx1-ads.dtb \
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
index 7f70a39459f6..350208c5e1ed 100644
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "mmp2.dtsi" 11#include "mmp2.dtsi"
12 12
13/ { 13/ {
14 model = "Marvell MMP2 Brownstone Development Board"; 14 model = "Marvell MMP2 Brownstone Development Board";
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 4e8b08c628c7..766bbb8495b6 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -7,7 +7,8 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9 9
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include <dt-bindings/clock/marvell,mmp2.h>
11 12
12/ { 13/ {
13 aliases { 14 aliases {
@@ -135,6 +136,8 @@
135 compatible = "mrvl,mmp-uart"; 136 compatible = "mrvl,mmp-uart";
136 reg = <0xd4030000 0x1000>; 137 reg = <0xd4030000 0x1000>;
137 interrupts = <27>; 138 interrupts = <27>;
139 clocks = <&soc_clocks MMP2_CLK_UART0>;
140 resets = <&soc_clocks MMP2_CLK_UART0>;
138 status = "disabled"; 141 status = "disabled";
139 }; 142 };
140 143
@@ -142,6 +145,8 @@
142 compatible = "mrvl,mmp-uart"; 145 compatible = "mrvl,mmp-uart";
143 reg = <0xd4017000 0x1000>; 146 reg = <0xd4017000 0x1000>;
144 interrupts = <28>; 147 interrupts = <28>;
148 clocks = <&soc_clocks MMP2_CLK_UART1>;
149 resets = <&soc_clocks MMP2_CLK_UART1>;
145 status = "disabled"; 150 status = "disabled";
146 }; 151 };
147 152
@@ -149,6 +154,8 @@
149 compatible = "mrvl,mmp-uart"; 154 compatible = "mrvl,mmp-uart";
150 reg = <0xd4018000 0x1000>; 155 reg = <0xd4018000 0x1000>;
151 interrupts = <24>; 156 interrupts = <24>;
157 clocks = <&soc_clocks MMP2_CLK_UART2>;
158 resets = <&soc_clocks MMP2_CLK_UART2>;
152 status = "disabled"; 159 status = "disabled";
153 }; 160 };
154 161
@@ -156,6 +163,8 @@
156 compatible = "mrvl,mmp-uart"; 163 compatible = "mrvl,mmp-uart";
157 reg = <0xd4016000 0x1000>; 164 reg = <0xd4016000 0x1000>;
158 interrupts = <46>; 165 interrupts = <46>;
166 clocks = <&soc_clocks MMP2_CLK_UART3>;
167 resets = <&soc_clocks MMP2_CLK_UART3>;
159 status = "disabled"; 168 status = "disabled";
160 }; 169 };
161 170
@@ -168,6 +177,8 @@
168 #gpio-cells = <2>; 177 #gpio-cells = <2>;
169 interrupts = <49>; 178 interrupts = <49>;
170 interrupt-names = "gpio_mux"; 179 interrupt-names = "gpio_mux";
180 clocks = <&soc_clocks MMP2_CLK_GPIO>;
181 resets = <&soc_clocks MMP2_CLK_GPIO>;
171 interrupt-controller; 182 interrupt-controller;
172 #interrupt-cells = <1>; 183 #interrupt-cells = <1>;
173 ranges; 184 ranges;
@@ -201,6 +212,8 @@
201 compatible = "mrvl,mmp-twsi"; 212 compatible = "mrvl,mmp-twsi";
202 reg = <0xd4011000 0x1000>; 213 reg = <0xd4011000 0x1000>;
203 interrupts = <7>; 214 interrupts = <7>;
215 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
216 resets = <&soc_clocks MMP2_CLK_TWSI0>;
204 #address-cells = <1>; 217 #address-cells = <1>;
205 #size-cells = <0>; 218 #size-cells = <0>;
206 mrvl,i2c-fast-mode; 219 mrvl,i2c-fast-mode;
@@ -211,6 +224,8 @@
211 compatible = "mrvl,mmp-twsi"; 224 compatible = "mrvl,mmp-twsi";
212 reg = <0xd4025000 0x1000>; 225 reg = <0xd4025000 0x1000>;
213 interrupts = <58>; 226 interrupts = <58>;
227 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
228 resets = <&soc_clocks MMP2_CLK_TWSI1>;
214 status = "disabled"; 229 status = "disabled";
215 }; 230 };
216 231
@@ -220,8 +235,20 @@
220 interrupts = <1 0>; 235 interrupts = <1 0>;
221 interrupt-names = "rtc 1Hz", "rtc alarm"; 236 interrupt-names = "rtc 1Hz", "rtc alarm";
222 interrupt-parent = <&intcmux5>; 237 interrupt-parent = <&intcmux5>;
238 clocks = <&soc_clocks MMP2_CLK_RTC>;
239 resets = <&soc_clocks MMP2_CLK_RTC>;
223 status = "disabled"; 240 status = "disabled";
224 }; 241 };
225 }; 242 };
243
244 soc_clocks: clocks{
245 compatible = "marvell,mmp2-clock";
246 reg = <0xd4050000 0x1000>,
247 <0xd4282800 0x400>,
248 <0xd4015000 0x1000>;
249 reg-names = "mpmu", "apmu", "apbc";
250 #clock-cells = <1>;
251 #reset-cells = <1>;
252 };
226 }; 253 };
227}; 254};
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
index e762facb3fa4..0a988b3fb248 100644
--- a/arch/arm/boot/dts/pxa168-aspenite.dts
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "pxa168.dtsi" 11#include "pxa168.dtsi"
12 12
13/ { 13/ {
14 model = "Marvell PXA168 Aspenite Development Board"; 14 model = "Marvell PXA168 Aspenite Development Board";
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 975dad21ac38..b899e25cbb1b 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -7,7 +7,8 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9 9
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include <dt-bindings/clock/marvell,pxa168.h>
11 12
12/ { 13/ {
13 aliases { 14 aliases {
@@ -59,6 +60,8 @@
59 compatible = "mrvl,mmp-uart"; 60 compatible = "mrvl,mmp-uart";
60 reg = <0xd4017000 0x1000>; 61 reg = <0xd4017000 0x1000>;
61 interrupts = <27>; 62 interrupts = <27>;
63 clocks = <&soc_clocks PXA168_CLK_UART0>;
64 resets = <&soc_clocks PXA168_CLK_UART0>;
62 status = "disabled"; 65 status = "disabled";
63 }; 66 };
64 67
@@ -66,6 +69,8 @@
66 compatible = "mrvl,mmp-uart"; 69 compatible = "mrvl,mmp-uart";
67 reg = <0xd4018000 0x1000>; 70 reg = <0xd4018000 0x1000>;
68 interrupts = <28>; 71 interrupts = <28>;
72 clocks = <&soc_clocks PXA168_CLK_UART1>;
73 resets = <&soc_clocks PXA168_CLK_UART1>;
69 status = "disabled"; 74 status = "disabled";
70 }; 75 };
71 76
@@ -73,6 +78,8 @@
73 compatible = "mrvl,mmp-uart"; 78 compatible = "mrvl,mmp-uart";
74 reg = <0xd4026000 0x1000>; 79 reg = <0xd4026000 0x1000>;
75 interrupts = <29>; 80 interrupts = <29>;
81 clocks = <&soc_clocks PXA168_CLK_UART2>;
82 resets = <&soc_clocks PXA168_CLK_UART2>;
76 status = "disabled"; 83 status = "disabled";
77 }; 84 };
78 85
@@ -84,6 +91,8 @@
84 gpio-controller; 91 gpio-controller;
85 #gpio-cells = <2>; 92 #gpio-cells = <2>;
86 interrupts = <49>; 93 interrupts = <49>;
94 clocks = <&soc_clocks PXA168_CLK_GPIO>;
95 resets = <&soc_clocks PXA168_CLK_GPIO>;
87 interrupt-names = "gpio_mux"; 96 interrupt-names = "gpio_mux";
88 interrupt-controller; 97 interrupt-controller;
89 #interrupt-cells = <1>; 98 #interrupt-cells = <1>;
@@ -110,6 +119,8 @@
110 compatible = "mrvl,mmp-twsi"; 119 compatible = "mrvl,mmp-twsi";
111 reg = <0xd4011000 0x1000>; 120 reg = <0xd4011000 0x1000>;
112 interrupts = <7>; 121 interrupts = <7>;
122 clocks = <&soc_clocks PXA168_CLK_TWSI0>;
123 resets = <&soc_clocks PXA168_CLK_TWSI0>;
113 mrvl,i2c-fast-mode; 124 mrvl,i2c-fast-mode;
114 status = "disabled"; 125 status = "disabled";
115 }; 126 };
@@ -118,6 +129,8 @@
118 compatible = "mrvl,mmp-twsi"; 129 compatible = "mrvl,mmp-twsi";
119 reg = <0xd4025000 0x1000>; 130 reg = <0xd4025000 0x1000>;
120 interrupts = <58>; 131 interrupts = <58>;
132 clocks = <&soc_clocks PXA168_CLK_TWSI1>;
133 resets = <&soc_clocks PXA168_CLK_TWSI1>;
121 status = "disabled"; 134 status = "disabled";
122 }; 135 };
123 136
@@ -126,8 +139,20 @@
126 reg = <0xd4010000 0x1000>; 139 reg = <0xd4010000 0x1000>;
127 interrupts = <5 6>; 140 interrupts = <5 6>;
128 interrupt-names = "rtc 1Hz", "rtc alarm"; 141 interrupt-names = "rtc 1Hz", "rtc alarm";
142 clocks = <&soc_clocks PXA168_CLK_RTC>;
143 resets = <&soc_clocks PXA168_CLK_RTC>;
129 status = "disabled"; 144 status = "disabled";
130 }; 145 };
131 }; 146 };
147
148 soc_clocks: clocks{
149 compatible = "marvell,pxa168-clock";
150 reg = <0xd4050000 0x1000>,
151 <0xd4282800 0x400>,
152 <0xd4015000 0x1000>;
153 reg-names = "mpmu", "apmu", "apbc";
154 #clock-cells = <1>;
155 #reset-cells = <1>;
156 };
132 }; 157 };
133}; 158};
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index 595492aa5053..c82f2810ec73 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/dts-v1/; 10/dts-v1/;
11/include/ "pxa910.dtsi" 11#include "pxa910.dtsi"
12 12
13/ { 13/ {
14 model = "Marvell PXA910 DKB Development Board"; 14 model = "Marvell PXA910 DKB Development Board";
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 0247c622f580..0868f6729be1 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -7,7 +7,8 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9 9
10/include/ "skeleton.dtsi" 10#include "skeleton.dtsi"
11#include <dt-bindings/clock/marvell,pxa910.h>
11 12
12/ { 13/ {
13 aliases { 14 aliases {
@@ -71,6 +72,8 @@
71 compatible = "mrvl,mmp-uart"; 72 compatible = "mrvl,mmp-uart";
72 reg = <0xd4017000 0x1000>; 73 reg = <0xd4017000 0x1000>;
73 interrupts = <27>; 74 interrupts = <27>;
75 clocks = <&soc_clocks PXA910_CLK_UART0>;
76 resets = <&soc_clocks PXA910_CLK_UART0>;
74 status = "disabled"; 77 status = "disabled";
75 }; 78 };
76 79
@@ -78,6 +81,8 @@
78 compatible = "mrvl,mmp-uart"; 81 compatible = "mrvl,mmp-uart";
79 reg = <0xd4018000 0x1000>; 82 reg = <0xd4018000 0x1000>;
80 interrupts = <28>; 83 interrupts = <28>;
84 clocks = <&soc_clocks PXA910_CLK_UART1>;
85 resets = <&soc_clocks PXA910_CLK_UART1>;
81 status = "disabled"; 86 status = "disabled";
82 }; 87 };
83 88
@@ -85,6 +90,8 @@
85 compatible = "mrvl,mmp-uart"; 90 compatible = "mrvl,mmp-uart";
86 reg = <0xd4036000 0x1000>; 91 reg = <0xd4036000 0x1000>;
87 interrupts = <59>; 92 interrupts = <59>;
93 clocks = <&soc_clocks PXA910_CLK_UART2>;
94 resets = <&soc_clocks PXA910_CLK_UART2>;
88 status = "disabled"; 95 status = "disabled";
89 }; 96 };
90 97
@@ -97,6 +104,8 @@
97 #gpio-cells = <2>; 104 #gpio-cells = <2>;
98 interrupts = <49>; 105 interrupts = <49>;
99 interrupt-names = "gpio_mux"; 106 interrupt-names = "gpio_mux";
107 clocks = <&soc_clocks PXA910_CLK_GPIO>;
108 resets = <&soc_clocks PXA910_CLK_GPIO>;
100 interrupt-controller; 109 interrupt-controller;
101 #interrupt-cells = <1>; 110 #interrupt-cells = <1>;
102 ranges; 111 ranges;
@@ -124,6 +133,8 @@
124 #size-cells = <0>; 133 #size-cells = <0>;
125 reg = <0xd4011000 0x1000>; 134 reg = <0xd4011000 0x1000>;
126 interrupts = <7>; 135 interrupts = <7>;
136 clocks = <&soc_clocks PXA910_CLK_TWSI0>;
137 resets = <&soc_clocks PXA910_CLK_TWSI0>;
127 mrvl,i2c-fast-mode; 138 mrvl,i2c-fast-mode;
128 status = "disabled"; 139 status = "disabled";
129 }; 140 };
@@ -134,6 +145,8 @@
134 #size-cells = <0>; 145 #size-cells = <0>;
135 reg = <0xd4037000 0x1000>; 146 reg = <0xd4037000 0x1000>;
136 interrupts = <54>; 147 interrupts = <54>;
148 clocks = <&soc_clocks PXA910_CLK_TWSI1>;
149 resets = <&soc_clocks PXA910_CLK_TWSI1>;
137 status = "disabled"; 150 status = "disabled";
138 }; 151 };
139 152
@@ -142,8 +155,21 @@
142 reg = <0xd4010000 0x1000>; 155 reg = <0xd4010000 0x1000>;
143 interrupts = <5 6>; 156 interrupts = <5 6>;
144 interrupt-names = "rtc 1Hz", "rtc alarm"; 157 interrupt-names = "rtc 1Hz", "rtc alarm";
158 clocks = <&soc_clocks PXA910_CLK_RTC>;
159 resets = <&soc_clocks PXA910_CLK_RTC>;
145 status = "disabled"; 160 status = "disabled";
146 }; 161 };
147 }; 162 };
163
164 soc_clocks: clocks{
165 compatible = "marvell,pxa910-clock";
166 reg = <0xd4050000 0x1000>,
167 <0xd4282800 0x400>,
168 <0xd4015000 0x1000>,
169 <0xd403b000 0x1000>;
170 reg-names = "mpmu", "apmu", "apbc", "apbcp";
171 #clock-cells = <1>;
172 #reset-cells = <1>;
173 };
148 }; 174 };
149}; 175};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e3ab942fd148..7b4099fcf817 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -188,19 +188,11 @@
188 "apb0_ir1", "apb0_keypad"; 188 "apb0_ir1", "apb0_keypad";
189 }; 189 };
190 190
191 apb1_mux: apb1_mux@01c20058 { 191 apb1: clk@01c20058 {
192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
194 reg = <0x01c20058 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
196 clock-output-names = "apb1_mux";
197 };
198
199 apb1: apb1@01c20058 {
200 #clock-cells = <0>; 192 #clock-cells = <0>;
201 compatible = "allwinner,sun4i-a10-apb1-clk"; 193 compatible = "allwinner,sun4i-a10-apb1-clk";
202 reg = <0x01c20058 0x4>; 194 reg = <0x01c20058 0x4>;
203 clocks = <&apb1_mux>; 195 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
204 clock-output-names = "apb1"; 196 clock-output-names = "apb1";
205 }; 197 };
206 198
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 81ad4b94e812..1b76667f3182 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -176,19 +176,11 @@
176 "apb0_ir", "apb0_keypad"; 176 "apb0_ir", "apb0_keypad";
177 }; 177 };
178 178
179 apb1_mux: apb1_mux@01c20058 { 179 apb1: clk@01c20058 {
180 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
182 reg = <0x01c20058 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
184 clock-output-names = "apb1_mux";
185 };
186
187 apb1: apb1@01c20058 {
188 #clock-cells = <0>; 180 #clock-cells = <0>;
189 compatible = "allwinner,sun4i-a10-apb1-clk"; 181 compatible = "allwinner,sun4i-a10-apb1-clk";
190 reg = <0x01c20058 0x4>; 182 reg = <0x01c20058 0x4>;
191 clocks = <&apb1_mux>; 183 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
192 clock-output-names = "apb1"; 184 clock-output-names = "apb1";
193 }; 185 };
194 186
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index b131068f4f35..c35217ea1f64 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -161,19 +161,11 @@
161 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; 161 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
162 }; 162 };
163 163
164 apb1_mux: apb1_mux@01c20058 { 164 apb1: clk@01c20058 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
167 reg = <0x01c20058 0x4>;
168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux";
170 };
171
172 apb1: apb1@01c20058 {
173 #clock-cells = <0>; 165 #clock-cells = <0>;
174 compatible = "allwinner,sun4i-a10-apb1-clk"; 166 compatible = "allwinner,sun4i-a10-apb1-clk";
175 reg = <0x01c20058 0x4>; 167 reg = <0x01c20058 0x4>;
176 clocks = <&apb1_mux>; 168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
177 clock-output-names = "apb1"; 169 clock-output-names = "apb1";
178 }; 170 };
179 171
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index a400172a8a52..f47156b6572b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -229,19 +229,11 @@
229 "apb1_daudio1"; 229 "apb1_daudio1";
230 }; 230 };
231 231
232 apb2_mux: apb2_mux@01c20058 { 232 apb2: clk@01c20058 {
233 #clock-cells = <0>; 233 #clock-cells = <0>;
234 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 234 compatible = "allwinner,sun4i-a10-apb1-clk";
235 reg = <0x01c20058 0x4>; 235 reg = <0x01c20058 0x4>;
236 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 236 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
237 clock-output-names = "apb2_mux";
238 };
239
240 apb2: apb2@01c20058 {
241 #clock-cells = <0>;
242 compatible = "allwinner,sun6i-a31-apb2-div-clk";
243 reg = <0x01c20058 0x4>;
244 clocks = <&apb2_mux>;
245 clock-output-names = "apb2"; 237 clock-output-names = "apb2";
246 }; 238 };
247 239
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82a524ce28ad..e21ce5992d56 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -236,19 +236,11 @@
236 "apb0_iis2", "apb0_keypad"; 236 "apb0_iis2", "apb0_keypad";
237 }; 237 };
238 238
239 apb1_mux: apb1_mux@01c20058 { 239 apb1: clk@01c20058 {
240 #clock-cells = <0>;
241 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
242 reg = <0x01c20058 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
244 clock-output-names = "apb1_mux";
245 };
246
247 apb1: apb1@01c20058 {
248 #clock-cells = <0>; 240 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-apb1-clk"; 241 compatible = "allwinner,sun4i-a10-apb1-clk";
250 reg = <0x01c20058 0x4>; 242 reg = <0x01c20058 0x4>;
251 clocks = <&apb1_mux>; 243 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
252 clock-output-names = "apb1"; 244 clock-output-names = "apb1";
253 }; 245 };
254 246
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6086adbf9d74..0746cd1024d7 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -189,19 +189,11 @@
189 "apb1_daudio0", "apb1_daudio1"; 189 "apb1_daudio0", "apb1_daudio1";
190 }; 190 };
191 191
192 apb2_mux: apb2_mux_clk@01c20058 { 192 apb2: clk@01c20058 {
193 #clock-cells = <0>; 193 #clock-cells = <0>;
194 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 194 compatible = "allwinner,sun4i-a10-apb1-clk";
195 reg = <0x01c20058 0x4>; 195 reg = <0x01c20058 0x4>;
196 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 196 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
197 clock-output-names = "apb2_mux";
198 };
199
200 apb2: apb2_clk@01c20058 {
201 #clock-cells = <0>;
202 compatible = "allwinner,sun6i-a31-apb2-div-clk";
203 reg = <0x01c20058 0x4>;
204 clocks = <&apb2_mux>;
205 clock-output-names = "apb2"; 197 clock-output-names = "apb2";
206 }; 198 };
207 199
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index ebdba87b9671..fdbfadf00c84 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -86,11 +86,12 @@ config MACH_GPLUGD
86 86
87config MACH_MMP_DT 87config MACH_MMP_DT
88 bool "Support MMP (ARMv5) platforms from device tree" 88 bool "Support MMP (ARMv5) platforms from device tree"
89 select CPU_PXA168
90 select CPU_PXA910
91 select USE_OF 89 select USE_OF
92 select PINCTRL 90 select PINCTRL
93 select PINCTRL_SINGLE 91 select PINCTRL_SINGLE
92 select COMMON_CLK
93 select ARCH_HAS_RESET_CONTROLLER
94 select CPU_MOHAWK
94 help 95 help
95 Include support for Marvell MMP2 based platforms using 96 Include support for Marvell MMP2 based platforms using
96 the device tree. Needn't select any other machine while 97 the device tree. Needn't select any other machine while
@@ -99,10 +100,12 @@ config MACH_MMP_DT
99config MACH_MMP2_DT 100config MACH_MMP2_DT
100 bool "Support MMP2 (ARMv7) platforms from device tree" 101 bool "Support MMP2 (ARMv7) platforms from device tree"
101 depends on !CPU_MOHAWK 102 depends on !CPU_MOHAWK
102 select CPU_MMP2
103 select USE_OF 103 select USE_OF
104 select PINCTRL 104 select PINCTRL
105 select PINCTRL_SINGLE 105 select PINCTRL_SINGLE
106 select COMMON_CLK
107 select ARCH_HAS_RESET_CONTROLLER
108 select CPU_PJ4
106 help 109 help
107 Include support for Marvell MMP2 based platforms using 110 Include support for Marvell MMP2 based platforms using
108 the device tree. 111 the device tree.
@@ -111,21 +114,18 @@ endmenu
111 114
112config CPU_PXA168 115config CPU_PXA168
113 bool 116 bool
114 select COMMON_CLK
115 select CPU_MOHAWK 117 select CPU_MOHAWK
116 help 118 help
117 Select code specific to PXA168 119 Select code specific to PXA168
118 120
119config CPU_PXA910 121config CPU_PXA910
120 bool 122 bool
121 select COMMON_CLK
122 select CPU_MOHAWK 123 select CPU_MOHAWK
123 help 124 help
124 Select code specific to PXA910 125 Select code specific to PXA910
125 126
126config CPU_MMP2 127config CPU_MMP2
127 bool 128 bool
128 select COMMON_CLK
129 select CPU_PJ4 129 select CPU_PJ4
130 help 130 help
131 Select code specific to MMP2. MMP2 is ARMv7 compatible. 131 Select code specific to MMP2. MMP2 is ARMv7 compatible.
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index cca529ceecb7..b2296c9309b8 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -11,63 +11,42 @@
11 11
12#include <linux/irqchip.h> 12#include <linux/irqchip.h>
13#include <linux/of_platform.h> 13#include <linux/of_platform.h>
14#include <linux/clk-provider.h>
14#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
15#include <asm/mach/time.h> 16#include <asm/mach/time.h>
17#include <asm/hardware/cache-tauros2.h>
16 18
17#include "common.h" 19#include "common.h"
18 20
19extern void __init mmp_dt_init_timer(void); 21extern void __init mmp_dt_init_timer(void);
20 22
21static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = { 23static const char *pxa168_dt_board_compat[] __initdata = {
22 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL), 24 "mrvl,pxa168-aspenite",
23 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL), 25 NULL,
24 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
25 OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
26 OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
27 OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
28 OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
29 {}
30}; 26};
31 27
32static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = { 28static const char *pxa910_dt_board_compat[] __initdata = {
33 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL), 29 "mrvl,pxa910-dkb",
34 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL), 30 NULL,
35 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
36 OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
37 OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
38 OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
39 OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
40 {}
41}; 31};
42 32
43static void __init pxa168_dt_init(void) 33static void __init mmp_init_time(void)
44{
45 of_platform_populate(NULL, of_default_bus_match_table,
46 pxa168_auxdata_lookup, NULL);
47}
48
49static void __init pxa910_dt_init(void)
50{ 34{
51 of_platform_populate(NULL, of_default_bus_match_table, 35#ifdef CONFIG_CACHE_TAUROS2
52 pxa910_auxdata_lookup, NULL); 36 tauros2_init(0);
37#endif
38 mmp_dt_init_timer();
39 of_clk_init(NULL);
53} 40}
54 41
55static const char *mmp_dt_board_compat[] __initdata = {
56 "mrvl,pxa168-aspenite",
57 "mrvl,pxa910-dkb",
58 NULL,
59};
60
61DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") 42DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
62 .map_io = mmp_map_io, 43 .map_io = mmp_map_io,
63 .init_time = mmp_dt_init_timer, 44 .init_time = mmp_init_time,
64 .init_machine = pxa168_dt_init, 45 .dt_compat = pxa168_dt_board_compat,
65 .dt_compat = mmp_dt_board_compat,
66MACHINE_END 46MACHINE_END
67 47
68DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") 48DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
69 .map_io = mmp_map_io, 49 .map_io = mmp_map_io,
70 .init_time = mmp_dt_init_timer, 50 .init_time = mmp_init_time,
71 .init_machine = pxa910_dt_init, 51 .dt_compat = pxa910_dt_board_compat,
72 .dt_compat = mmp_dt_board_compat,
73MACHINE_END 52MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 023cb453f157..998c0f533abc 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -12,29 +12,22 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/irqchip.h> 13#include <linux/irqchip.h>
14#include <linux/of_platform.h> 14#include <linux/of_platform.h>
15#include <linux/clk-provider.h>
15#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
16#include <asm/mach/time.h> 17#include <asm/mach/time.h>
18#include <asm/hardware/cache-tauros2.h>
17 19
18#include "common.h" 20#include "common.h"
19 21
20extern void __init mmp_dt_init_timer(void); 22extern void __init mmp_dt_init_timer(void);
21 23
22static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = { 24static void __init mmp_init_time(void)
23 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
24 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
25 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
26 OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
27 OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
28 OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
29 OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
30 OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
31 {}
32};
33
34static void __init mmp2_dt_init(void)
35{ 25{
36 of_platform_populate(NULL, of_default_bus_match_table, 26#ifdef CONFIG_CACHE_TAUROS2
37 mmp2_auxdata_lookup, NULL); 27 tauros2_init(0);
28#endif
29 mmp_dt_init_timer();
30 of_clk_init(NULL);
38} 31}
39 32
40static const char *mmp2_dt_board_compat[] __initdata = { 33static const char *mmp2_dt_board_compat[] __initdata = {
@@ -44,7 +37,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
44 37
45DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") 38DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
46 .map_io = mmp_map_io, 39 .map_io = mmp_map_io,
47 .init_time = mmp_dt_init_timer, 40 .init_time = mmp_init_time,
48 .init_machine = mmp2_dt_init,
49 .dt_compat = mmp2_dt_board_compat, 41 .dt_compat = mmp2_dt_board_compat,
50MACHINE_END 42MACHINE_END
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 5c5ebb4db5f7..644ff3231bb8 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -111,6 +111,7 @@ static struct clk dpll3_ck;
111 111
112static const char *dpll3_ck_parent_names[] = { 112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck", 113 "sys_ck",
114 "sys_ck",
114}; 115};
115 116
116static const struct clk_ops dpll3_ck_ops = { 117static const struct clk_ops dpll3_ck_ops = {
@@ -733,6 +734,10 @@ static const char *corex2_fck_parent_names[] = {
733DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL); 734DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
734DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops); 735DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
735 736
737static const char *cpefuse_fck_parent_names[] = {
738 "sys_ck",
739};
740
736static struct clk cpefuse_fck; 741static struct clk cpefuse_fck;
737 742
738static struct clk_hw_omap cpefuse_fck_hw = { 743static struct clk_hw_omap cpefuse_fck_hw = {
@@ -744,7 +749,7 @@ static struct clk_hw_omap cpefuse_fck_hw = {
744 .clkdm_name = "core_l4_clkdm", 749 .clkdm_name = "core_l4_clkdm",
745}; 750};
746 751
747DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops); 752DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
748 753
749static struct clk csi2_96m_fck; 754static struct clk csi2_96m_fck;
750 755
@@ -775,7 +780,7 @@ static struct clk_hw_omap d2d_26m_fck_hw = {
775 .clkdm_name = "d2d_clkdm", 780 .clkdm_name = "d2d_clkdm",
776}; 781};
777 782
778DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops); 783DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
779 784
780static struct clk des1_ick; 785static struct clk des1_ick;
781 786
@@ -1046,7 +1051,7 @@ static struct clk_hw_omap dss2_alwon_fck_hw = {
1046 .clkdm_name = "dss_clkdm", 1051 .clkdm_name = "dss_clkdm",
1047}; 1052};
1048 1053
1049DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops); 1054DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
1050 1055
1051static struct clk dss_96m_fck; 1056static struct clk dss_96m_fck;
1052 1057
@@ -1368,7 +1373,7 @@ DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1368static struct clk wkup_l4_ick; 1373static struct clk wkup_l4_ick;
1369 1374
1370DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm"); 1375DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1371DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops); 1376DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
1372 1377
1373static struct clk gpio1_ick; 1378static struct clk gpio1_ick;
1374 1379
@@ -1862,7 +1867,7 @@ static struct clk_hw_omap hecc_ck_hw = {
1862 .clkdm_name = "core_l3_clkdm", 1867 .clkdm_name = "core_l3_clkdm",
1863}; 1868};
1864 1869
1865DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops); 1870DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
1866 1871
1867static struct clk hsotgusb_fck_am35xx; 1872static struct clk hsotgusb_fck_am35xx;
1868 1873
@@ -1875,7 +1880,7 @@ static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1875 .clkdm_name = "core_l3_clkdm", 1880 .clkdm_name = "core_l3_clkdm",
1876}; 1881};
1877 1882
1878DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops); 1883DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
1879 1884
1880static struct clk hsotgusb_ick_3430es1; 1885static struct clk hsotgusb_ick_3430es1;
1881 1886
@@ -2411,7 +2416,7 @@ static struct clk_hw_omap modem_fck_hw = {
2411 .clkdm_name = "d2d_clkdm", 2416 .clkdm_name = "d2d_clkdm",
2412}; 2417};
2413 2418
2414DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops); 2419DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2415 2420
2416static struct clk mspro_fck; 2421static struct clk mspro_fck;
2417 2422
@@ -2710,7 +2715,7 @@ static struct clk_hw_omap sr1_fck_hw = {
2710 .clkdm_name = "wkup_clkdm", 2715 .clkdm_name = "wkup_clkdm",
2711}; 2716};
2712 2717
2713DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops); 2718DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2714 2719
2715static struct clk sr2_fck; 2720static struct clk sr2_fck;
2716 2721
@@ -2724,7 +2729,7 @@ static struct clk_hw_omap sr2_fck_hw = {
2724 .clkdm_name = "wkup_clkdm", 2729 .clkdm_name = "wkup_clkdm",
2725}; 2730};
2726 2731
2727DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops); 2732DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2728 2733
2729static struct clk sr_l4_ick; 2734static struct clk sr_l4_ick;
2730 2735
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 20e120d071dd..c2da2a0fe5ad 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -474,7 +474,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
474 */ 474 */
475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, 475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long *best_parent_rate, 476 unsigned long *best_parent_rate,
477 struct clk **best_parent_clk) 477 struct clk_hw **best_parent_clk)
478{ 478{
479 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 479 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
480 struct dpll_data *dd; 480 struct dpll_data *dd;
@@ -488,10 +488,10 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
488 488
489 if (__clk_get_rate(dd->clk_bypass) == rate && 489 if (__clk_get_rate(dd->clk_bypass) == rate &&
490 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 490 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
491 *best_parent_clk = dd->clk_bypass; 491 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
492 } else { 492 } else {
493 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate); 493 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
494 *best_parent_clk = dd->clk_ref; 494 *best_parent_clk = __clk_get_hw(dd->clk_ref);
495 } 495 }
496 496
497 *best_parent_rate = rate; 497 *best_parent_rate = rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 535822fcf4bb..0e58e5a85d53 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -223,7 +223,7 @@ out:
223 */ 223 */
224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, 224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long *best_parent_rate, 225 unsigned long *best_parent_rate,
226 struct clk **best_parent_clk) 226 struct clk_hw **best_parent_clk)
227{ 227{
228 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 228 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
229 struct dpll_data *dd; 229 struct dpll_data *dd;
@@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
237 237
238 if (__clk_get_rate(dd->clk_bypass) == rate && 238 if (__clk_get_rate(dd->clk_bypass) == rate &&
239 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 239 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
240 *best_parent_clk = dd->clk_bypass; 240 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
241 } else { 241 } else {
242 rate = omap4_dpll_regm4xen_round_rate(hw, rate, 242 rate = omap4_dpll_regm4xen_round_rate(hw, rate,
243 best_parent_rate); 243 best_parent_rate);
244 *best_parent_clk = dd->clk_ref; 244 *best_parent_clk = __clk_get_hw(dd->clk_ref);
245 } 245 }
246 246
247 *best_parent_rate = rate; 247 *best_parent_rate = rate;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 05:14:40 -0400