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-rw-r--r--Documentation/clk.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4415-clock.txt38
-rw-r--r--Documentation/devicetree/bindings/clock/exynos7-clock.txt93
-rw-r--r--Documentation/devicetree/bindings/clock/marvell,mmp2.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/marvell,pxa168.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/marvell,pxa910.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt18
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt31
-rw-r--r--MAINTAINERS3
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/mmp2-brownstone.dts2
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi29
-rw-r--r--arch/arm/boot/dts/pxa168-aspenite.dts2
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi27
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts2
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi28
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi12
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi12
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi12
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi12
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi12
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi12
-rw-r--r--arch/arm/mach-mmp/Kconfig12
-rw-r--r--arch/arm/mach-mmp/mmp-dt.c57
-rw-r--r--arch/arm/mach-mmp/mmp2-dt.c26
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c23
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c6
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c6
-rw-r--r--arch/mips/alchemy/common/clock.c10
-rw-r--r--drivers/clk/at91/clk-programmable.c4
-rw-r--r--drivers/clk/bcm/clk-kona.c4
-rw-r--r--drivers/clk/clk-composite.c9
-rw-r--r--drivers/clk/clk-mux.c2
-rw-r--r--drivers/clk/clk-s2mps11.c2
-rw-r--r--drivers/clk/clk.c42
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c72
-rw-r--r--drivers/clk/mmp/Makefile7
-rw-r--r--drivers/clk/mmp/clk-frac.c74
-rw-r--r--drivers/clk/mmp/clk-gate.c133
-rw-r--r--drivers/clk/mmp/clk-mix.c513
-rw-r--r--drivers/clk/mmp/clk-mmp2.c6
-rw-r--r--drivers/clk/mmp/clk-of-mmp2.c334
-rw-r--r--drivers/clk/mmp/clk-of-pxa168.c279
-rw-r--r--drivers/clk/mmp/clk-of-pxa910.c301
-rw-r--r--drivers/clk/mmp/clk-pxa168.c6
-rw-r--r--drivers/clk/mmp/clk-pxa910.c6
-rw-r--r--drivers/clk/mmp/clk.c192
-rw-r--r--drivers/clk/mmp/clk.h226
-rw-r--r--drivers/clk/mmp/reset.c99
-rw-r--r--drivers/clk/mmp/reset.h31
-rw-r--r--drivers/clk/pxa/Makefile1
-rw-r--r--drivers/clk/pxa/clk-pxa.c45
-rw-r--r--drivers/clk/pxa/clk-pxa.h9
-rw-r--r--drivers/clk/pxa/clk-pxa25x.c273
-rw-r--r--drivers/clk/pxa/clk-pxa27x.c9
-rw-r--r--drivers/clk/qcom/clk-pll.c2
-rw-r--r--drivers/clk/qcom/clk-rcg.c20
-rw-r--r--drivers/clk/qcom/clk-rcg2.c28
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-mmc-phase.c154
-rw-r--r--drivers/clk/rockchip/clk-pll.c81
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c79
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c246
-rw-r--r--drivers/clk/rockchip/clk.c20
-rw-r--r--drivers/clk/rockchip/clk.h45
-rw-r--r--drivers/clk/samsung/Makefile2
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c33
-rw-r--r--drivers/clk/samsung/clk-exynos4.c2
-rw-r--r--drivers/clk/samsung/clk-exynos4415.c1144
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c185
-rw-r--r--drivers/clk/samsung/clk-exynos7.c743
-rw-r--r--drivers/clk/samsung/clk-pll.c25
-rw-r--r--drivers/clk/samsung/clk-pll.h4
-rw-r--r--drivers/clk/samsung/clk.c102
-rw-r--r--drivers/clk/samsung/clk.h43
-rw-r--r--drivers/clk/shmobile/clk-div6.c113
-rw-r--r--drivers/clk/sunxi/Makefile1
-rw-r--r--drivers/clk/sunxi/clk-a20-gmac.c7
-rw-r--r--drivers/clk/sunxi/clk-factors.c6
-rw-r--r--drivers/clk/sunxi/clk-factors.h3
-rw-r--r--drivers/clk/sunxi/clk-mod0.c1
-rw-r--r--drivers/clk/sunxi/clk-sun6i-ar100.c4
-rw-r--r--drivers/clk/sunxi/clk-sun8i-mbus.c1
-rw-r--r--drivers/clk/sunxi/clk-sun9i-core.c271
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c85
-rw-r--r--include/dt-bindings/clock/exynos4415.h360
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h92
-rw-r--r--include/dt-bindings/clock/marvell,mmp2.h74
-rw-r--r--include/dt-bindings/clock/marvell,pxa168.h57
-rw-r--r--include/dt-bindings/clock/marvell,pxa910.h54
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h13
-rw-r--r--include/linux/clk-provider.h8
-rw-r--r--include/linux/clk/ti.h4
94 files changed, 6663 insertions, 690 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 1fee72f4d331..4ff84623d5e1 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -74,7 +74,7 @@ the operations defined in clk.h:
74 long (*determine_rate)(struct clk_hw *hw, 74 long (*determine_rate)(struct clk_hw *hw,
75 unsigned long rate, 75 unsigned long rate,
76 unsigned long *best_parent_rate, 76 unsigned long *best_parent_rate,
77 struct clk **best_parent_clk); 77 struct clk_hw **best_parent_clk);
78 int (*set_parent)(struct clk_hw *hw, u8 index); 78 int (*set_parent)(struct clk_hw *hw, u8 index);
79 u8 (*get_parent)(struct clk_hw *hw); 79 u8 (*get_parent)(struct clk_hw *hw);
80 int (*set_rate)(struct clk_hw *hw, 80 int (*set_rate)(struct clk_hw *hw,
diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
new file mode 100644
index 000000000000..847d98bae8cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
@@ -0,0 +1,38 @@
1* Samsung Exynos4415 Clock Controller
2
3The Exynos4415 clock controller generates and supplies clock to various
4consumer devices within the Exynos4415 SoC.
5
6Required properties:
7
8- compatible: should be one of the following:
9 - "samsung,exynos4415-cmu" - for the main system clocks controller
10 (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
11 - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
12 Controller (DMC) domain clock controller.
13
14- reg: physical base address of the controller and length of memory mapped
15 region.
16
17- #clock-cells: should be 1.
18
19Each clock is assigned an identifier and client nodes can use this identifier
20to specify the clock which they consume.
21
22All available clocks are defined as preprocessor macros in
23dt-bindings/clock/exynos4415.h header and can be used in device
24tree sources.
25
26Example 1: An example of a clock controller node is listed below.
27
28 cmu: clock-controller@10030000 {