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authorArnd Bergmann <arnd@arndb.de>2014-07-26 06:01:10 -0400
committerArnd Bergmann <arnd@arndb.de>2014-07-26 06:01:27 -0400
commit96bda115ec552ff75319f85828f6c333d101b401 (patch)
treee30895f65413fdf8fd91c026faad1a3fb54b0653 /arch/arm
parent8e5655cd4f7e140ceb24705f913406e9f56b7d54 (diff)
parentf1ff47454bb2fe0d5644f981679d1bea532816fd (diff)
Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung S5PV210 DT support for v3.17" from Kukjin Kim: - support common clock framework for s5pv210 clock - add generic PHY driver on s5pv210 to support it via DT - add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards - remove board files from mach-s5pv210 and unused codes - enable multiplatform for s5pv210 * tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: clk: samsung: s5pv210: Remove legacy board support ARM: SAMSUNG: Remove remaining legacy code gpio: samsung: Remove legacy support of S5PV210 ARM: S5PV210: Enable multi-platform build support cpufreq: s5pv210: Make the driver multiplatform aware ARM: S5PV210: Register cpufreq platform device ARM: S5PV210: move debug-macro.S into the common space ARM: S5PV210: Untie PM support from legacy code ARM: S5PV210: Remove support for board files ARM: dts: Add Device tree for s5pc110/s5pv210 boards ARM: dts: Add Device tree for s5pv210 SoC ARM: S5PV210: Add board file for boot using Device Tree phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver clk: samsung: Add S5PV210 Audio Subsystem clock driver ARM: SAMSUNG: Remove legacy clock code serial: samsung: Remove support for legacy clock code cpufreq: s3c24xx: Remove some dead code ARM: S5PV210: Migrate clock handling to Common Clock Framework clk: samsung: Add clock driver for S5PV210 and compatible SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig22
-rw-r--r--arch/arm/Kconfig.debug12
-rw-r--r--arch/arm/Makefile4
-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/s5pv210-aquila.dts392
-rw-r--r--arch/arm/boot/dts/s5pv210-goni.dts449
-rw-r--r--arch/arm/boot/dts/s5pv210-pinctrl.dtsi839
-rw-r--r--arch/arm/boot/dts/s5pv210-smdkc110.dts78
-rw-r--r--arch/arm/boot/dts/s5pv210-smdkv210.dts238
-rw-r--r--arch/arm/boot/dts/s5pv210-torbreck.dts92
-rw-r--r--arch/arm/boot/dts/s5pv210.dtsi633
-rw-r--r--arch/arm/include/debug/s5pv210.S (renamed from arch/arm/mach-s5pv210/include/mach/debug-macro.S)23
-rw-r--r--arch/arm/mach-exynos/pm.c1
-rw-r--r--arch/arm/mach-s3c24xx/common.c2
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2412.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-h1940.c5
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2413.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2416.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2443.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-vstms.c1
-rw-r--r--arch/arm/mach-s3c24xx/s3c2410.c6
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c6
-rw-r--r--arch/arm/mach-s3c24xx/s3c2442.c1
-rw-r--r--arch/arm/mach-s3c24xx/s3c244x.c6
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-hmt.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-ncp.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6400.c1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c1
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c1
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c1
-rw-r--r--arch/arm/mach-s5pv210/Kconfig197
-rw-r--r--arch/arm/mach-s5pv210/Makefile29
-rw-r--r--arch/arm/mach-s5pv210/Makefile.boot2
-rw-r--r--arch/arm/mach-s5pv210/clock.c1365
-rw-r--r--arch/arm/mach-s5pv210/common.c279
-rw-r--r--arch/arm/mach-s5pv210/common.h21
-rw-r--r--arch/arm/mach-s5pv210/dev-audio.c246
-rw-r--r--arch/arm/mach-s5pv210/dma.c130
-rw-r--r--arch/arm/mach-s5pv210/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pv210/include/mach/gpio.h140
-rw-r--r--arch/arm/mach-s5pv210/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h137
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h158
-rw-r--r--arch/arm/mach-s5pv210/include/mach/memory.h27
-rw-r--r--arch/arm/mach-s5pv210/include/mach/pm-core.h46
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-gpio.h41
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-irq.h18
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c687
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c916
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c159
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c337
-rw-r--r--arch/arm/mach-s5pv210/mach-torbreck.c135
-rw-r--r--arch/arm/mach-s5pv210/pm.c147
-rw-r--r--arch/arm/mach-s5pv210/s5pv210.c77
-rw-r--r--arch/arm/mach-s5pv210/setup-fb-24bpp.c49
-rw-r--r--arch/arm/mach-s5pv210/setup-fimc.c43
-rw-r--r--arch/arm/mach-s5pv210/setup-i2c0.c28
-rw-r--r--arch/arm/mach-s5pv210/setup-i2c1.c28
-rw-r--r--arch/arm/mach-s5pv210/setup-i2c2.c28
-rw-r--r--arch/arm/mach-s5pv210/setup-ide.c39
-rw-r--r--arch/arm/mach-s5pv210/setup-keypad.c24
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci-gpio.c103
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c34
-rw-r--r--arch/arm/mach-s5pv210/setup-usb-phy.c95
-rw-r--r--arch/arm/mach-s5pv210/sleep.S (renamed from arch/arm/plat-samsung/s5p-sleep.S)19
-rw-r--r--arch/arm/plat-samsung/Kconfig143
-rw-r--r--arch/arm/plat-samsung/Makefile15
-rw-r--r--arch/arm/plat-samsung/clock-clksrc.c212
-rw-r--r--arch/arm/plat-samsung/clock.c539
-rw-r--r--arch/arm/plat-samsung/cpu.c3
-rw-r--r--arch/arm/plat-samsung/devs.c330
-rw-r--r--arch/arm/plat-samsung/include/plat/camport.h28
-rw-r--r--arch/arm/plat-samsung/include/plat/clock-clksrc.h83
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h152
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h13
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h42
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-core.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/fimc-core.h51
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h64
-rw-r--r--arch/arm/plat-samsung/include/plat/hdmi.h16
-rw-r--r--arch/arm/plat-samsung/include/plat/irqs.h72
-rw-r--r--arch/arm/plat-samsung/include/plat/mfc.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/pll.h323
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h65
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h47
-rw-r--r--arch/arm/plat-samsung/include/plat/tv-core.h44
-rw-r--r--arch/arm/plat-samsung/init.c1
-rw-r--r--arch/arm/plat-samsung/pm-gpio.c4
-rw-r--r--arch/arm/plat-samsung/s5p-clock.c294
-rw-r--r--arch/arm/plat-samsung/s5p-dev-mfc.c81
-rw-r--r--arch/arm/plat-samsung/s5p-dev-uart.c88
-rw-r--r--arch/arm/plat-samsung/s5p-irq-eint.c221
-rw-r--r--arch/arm/plat-samsung/s5p-irq-gpioint.c218
-rw-r--r--arch/arm/plat-samsung/s5p-irq-pm.c92
-rw-r--r--arch/arm/plat-samsung/s5p-irq.c31
-rw-r--r--arch/arm/plat-samsung/s5p-pm.c40
103 files changed, 2956 insertions, 9090 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 03a302267ea4..f505f9ec792d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -744,25 +744,6 @@ config ARCH_S3C64XX
744 help 744 help
745 Samsung S3C64XX series based systems 745 Samsung S3C64XX series based systems
746 746
747config ARCH_S5PV210
748 bool "Samsung S5PV210/S5PC110"
749 select ARCH_HAS_HOLES_MEMORYMODEL
750 select ARCH_SPARSEMEM_ENABLE
751 select ATAGS
752 select CLKDEV_LOOKUP
753 select CLKSRC_SAMSUNG_PWM
754 select CPU_V7
755 select GENERIC_CLOCKEVENTS
756 select GPIO_SAMSUNG
757 select HAVE_S3C2410_I2C if I2C
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
759 select HAVE_S3C_RTC if RTC_CLASS
760 select NEED_MACH_GPIO_H
761 select NEED_MACH_MEMORY_H
762 select SAMSUNG_ATAGS
763 help
764 Samsung S5PV210/S5PC110 series based systems
765
766config ARCH_DAVINCI 747config ARCH_DAVINCI
767 bool "TI DaVinci" 748 bool "TI DaVinci"
768 select ARCH_HAS_HOLES_MEMORYMODEL 749 select ARCH_HAS_HOLES_MEMORYMODEL
@@ -1500,7 +1481,8 @@ config ARM_PSCI
1500config ARCH_NR_GPIO 1481config ARCH_NR_GPIO
1501 int 1482 int
1502 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1483 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1503 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX 1484 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1485 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1504 default 416 if ARCH_SUNXI 1486 default 416 if ARCH_SUNXI
1505 default 392 if ARCH_U8500 1487 default 392 if ARCH_U8500
1506 default 352 if ARCH_VT8500 1488 default 352 if ARCH_VT8500
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9cce733ba241..640770c7b6d2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -617,6 +617,7 @@ choice
617 depends on PLAT_SAMSUNG 617 depends on PLAT_SAMSUNG
618 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 618 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
619 select DEBUG_S3C24XX_UART if ARCH_S3C24XX 619 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
620 select DEBUG_S5PV210_UART if ARCH_S5PV210
620 bool "Use Samsung S3C UART 0 for low-level debug" 621 bool "Use Samsung S3C UART 0 for low-level debug"
621 help 622 help
622 Say Y here if you want the debug print routines to direct 623 Say Y here if you want the debug print routines to direct
@@ -627,6 +628,7 @@ choice
627 depends on PLAT_SAMSUNG 628 depends on PLAT_SAMSUNG
628 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 629 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
629 select DEBUG_S3C24XX_UART if ARCH_S3C24XX 630 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
631 select DEBUG_S5PV210_UART if ARCH_S5PV210
630 bool "Use Samsung S3C UART 1 for low-level debug" 632 bool "Use Samsung S3C UART 1 for low-level debug"
631 help 633 help
632 Say Y here if you want the debug print routines to direct 634 Say Y here if you want the debug print routines to direct
@@ -637,6 +639,7 @@ choice
637 depends on PLAT_SAMSUNG 639 depends on PLAT_SAMSUNG
638 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 640 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
639 select DEBUG_S3C24XX_UART if ARCH_S3C24XX 641 select DEBUG_S3C24XX_UART if ARCH_S3C24XX
642 select DEBUG_S5PV210_UART if ARCH_S5PV210
640 bool "Use Samsung S3C UART 2 for low-level debug" 643 bool "Use Samsung S3C UART 2 for low-level debug"
641 help 644 help
642 Say Y here if you want the debug print routines to direct 645 Say Y here if you want the debug print routines to direct
@@ -644,8 +647,9 @@ choice
644 by the boot-loader before use. 647 by the boot-loader before use.
645 648
646 config DEBUG_S3C_UART3 649 config DEBUG_S3C_UART3
647 depends on PLAT_SAMSUNG && ARCH_EXYNOS 650 depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210)
648 select DEBUG_EXYNOS_UART 651 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
652 select DEBUG_S5PV210_UART if ARCH_S5PV210
649 bool "Use Samsung S3C UART 3 for low-level debug" 653 bool "Use Samsung S3C UART 3 for low-level debug"
650 help 654 help
651 Say Y here if you want the debug print routines to direct 655 Say Y here if you want the debug print routines to direct
@@ -945,6 +949,9 @@ config DEBUG_S3C2410_UART
945config DEBUG_S3C24XX_UART 949config DEBUG_S3C24XX_UART
946 bool 950 bool
947 951
952config DEBUG_S5PV210_UART
953 bool
954
948config DEBUG_OMAP2PLUS_UART 955config DEBUG_OMAP2PLUS_UART
949 bool 956 bool
950 depends on ARCH_OMAP2PLUS 957 depends on ARCH_OMAP2PLUS
@@ -1005,6 +1012,7 @@ config DEBUG_LL_INCLUDE
1005 default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM 1012 default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
1006 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 1013 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
1007 default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART 1014 default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
1015 default "debug/s5pv210.S" if DEBUG_S5PV210_UART
1008 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 1016 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
1009 default "debug/sti.S" if DEBUG_STI_UART 1017 default "debug/sti.S" if DEBUG_STI_UART
1010 default "debug/tegra.S" if DEBUG_TEGRA_UART 1018 default "debug/tegra.S" if DEBUG_TEGRA_UART
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c3a032405e3a..a1e21e81b7aa 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -210,11 +210,11 @@ machine-$(CONFIG_PLAT_SPEAR) += spear
210plat-$(CONFIG_ARCH_EXYNOS) += samsung 210plat-$(CONFIG_ARCH_EXYNOS) += samsung
211plat-$(CONFIG_ARCH_OMAP) += omap 211plat-$(CONFIG_ARCH_OMAP) += omap
212plat-$(CONFIG_ARCH_S3C64XX) += samsung 212plat-$(CONFIG_ARCH_S3C64XX) += samsung
213plat-$(CONFIG_ARCH_S5PV210) += samsung
213plat-$(CONFIG_PLAT_IOP) += iop 214plat-$(CONFIG_PLAT_IOP) += iop
214plat-$(CONFIG_PLAT_ORION) += orion 215plat-$(CONFIG_PLAT_ORION) += orion
215plat-$(CONFIG_PLAT_PXA) += pxa 216plat-$(CONFIG_PLAT_PXA) += pxa
216plat-$(CONFIG_PLAT_S3C24XX) += samsung 217plat-$(CONFIG_PLAT_S3C24XX) += samsung
217plat-$(CONFIG_PLAT_S5P) += samsung
218plat-$(CONFIG_PLAT_VERSATILE) += versatile 218plat-$(CONFIG_PLAT_VERSATILE) += versatile
219 219
220ifeq ($(CONFIG_ARCH_EBSA110),y) 220ifeq ($(CONFIG_ARCH_EBSA110),y)
@@ -238,7 +238,7 @@ MACHINE :=
238endif 238endif
239 239
240machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) 240machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
241platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y)) 241platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
242 242
243ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y) 243ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
244ifeq ($(KBUILD_SRC),) 244ifeq ($(KBUILD_SRC),)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 67c59dc2d23a..3c08b79e825d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -318,6 +318,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \
318dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 318dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
319dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 319dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
320 s3c6410-smdk6410.dtb 320 s3c6410-smdk6410.dtb
321dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
322 s5pv210-goni.dtb \
323 s5pv210-smdkc110.dtb \
324 s5pv210-smdkv210.dtb \
325 s5pv210-torbreck.dtb
321dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ 326dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
322 r8a7740-armadillo800eva.dtb \ 327 r8a7740-armadillo800eva.dtb \
323 r8a7778-bockw.dtb \ 328 r8a7778-bockw.dtb \
diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts
new file mode 100644
index 000000000000..aa31b84a707a
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-aquila.dts
@@ -0,0 +1,392 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Board device tree source for Samsung Aquila board.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16/dts-v1/;
17#include <dt-bindings/input/input.h>
18#include "s5pv210.dtsi"
19
20/ {
21 model = "Samsung Aquila based on S5PC110";
22 compatible = "samsung,aquila", "samsung,s5pv210";
23
24 aliases {
25 i2c3 = &i2c_pmic;
26 };
27
28 chosen {
29 bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk";
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x30000000 0x05000000
35 0x40000000 0x18000000>;
36 };
37
38 regulators {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 vtf_reg: fixed-regulator@0 {
44 compatible = "regulator-fixed";
45 reg = <0>;
46 regulator-name = "V_TF_2.8V";
47 regulator-min-microvolt = <2800000>;
48 regulator-max-microvolt = <2800000>;
49 gpios = <&mp05 4 0>;
50 enable-active-high;
51 };
52
53 pda_reg: fixed-regulator@1 {
54 compatible = "regulator-fixed";
55 regulator-name = "VCC_1.8V_PDA";
56 regulator-min-microvolt = <1800000>;
57 regulator-max-microvolt = <1800000>;
58 reg = <1>;
59 };
60
61 bat_reg: fixed-regulator@2 {
62 compatible = "regulator-fixed";
63 regulator-name = "V_BAT";
64 regulator-min-microvolt = <3700000>;
65 regulator-max-microvolt = <3700000>;
66 reg = <2>;
67 };
68 };
69
70 i2c_pmic: i2c-pmic {
71 compatible = "i2c-gpio";
72 gpios = <&gpj4 0 0>, /* sda */
73 <&gpj4 3 0>; /* scl */
74 i2c-gpio,delay-us = <2>; /* ~100 kHz */
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 pmic@66 {
79 compatible = "national,lp3974";
80 reg = <0x66>;
81
82 max8998,pmic-buck1-default-dvs-idx = <0>;
83 max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
84 <&gph0 4 0>;
85 max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
86 <1200000>, <1200000>;
87
88 max8998,pmic-buck2-default-dvs-idx = <0>;
89 max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
90 max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
91
92 regulators {
93 ldo2_reg: LDO2 {
94 regulator-name = "VALIVE_1.1V";
95 regulator-min-microvolt = <1100000>;
96 regulator-max-microvolt = <1100000>;
97 regulator-always-on;
98 };
99
100 ldo3_reg: LDO3 {
101 regulator-name = "VUSB+MIPI_1.1V";
102 regulator-min-microvolt = <1100000>;
103 regulator-max-microvolt = <1100000>;
104 regulator-always-on;
105 };
106
107 ldo4_reg: LDO4 {
108 regulator-name = "VADC_3.3V";
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 };
112
113 ldo5_reg: LDO5 {
114 regulator-name = "VTF_2.8V";
115 regulator-min-microvolt = <2800000>;
116 regulator-max-microvolt = <2800000>;
117 regulator-always-on;
118 };
119
120 ldo6_reg: LDO6 {
121 regulator-name = "VCC_3.3V";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 regulator-always-on;
125 };
126
127 ldo7_reg: LDO7 {
128 regulator-name = "VCC_3.0V";
129 regulator-min-microvolt = <3000000>;
130 regulator-max-microvolt = <3000000>;
131 regulator-always-on;
132 regulator-boot-on;
133 };
134
135 ldo8_reg: LDO8 {
136 regulator-name = "VUSB+VDAC_3.3V";
137 regulator-min-microvolt = <3300000>;
138 regulator-max-microvolt = <3300000>;
139 regulator-always-on;
140 };
141
142 ldo9_reg: LDO9 {
143 regulator-name = "VCC+VCAM_2.8V";
144 regulator-min-microvolt = <2800000>;
145 regulator-max-microvolt = <2800000>;
146 regulator-always-on;
147 };
148
149 ldo10_reg: LDO10 {
150 regulator-name = "VPLL_1.1V";
151 regulator-min-microvolt = <1100000>;
152 regulator-max-microvolt = <1100000>;
153 regulator-always-on;
154 regulator-boot-on;
155 };
156
157 ldo11_reg: LDO11 {
158 regulator-name = "CAM_IO_2.8V";
159 regulator-min-microvolt = <2800000>;
160 regulator-max-microvolt = <2800000>;
161 regulator-always-on;
162 };
163
164 ldo12_reg: LDO12 {
165 regulator-name = "CAM_ISP_1.2V";
166 regulator-min-microvolt = <1200000>;
167 regulator-max-microvolt = <1200000>;
168 regulator-always-on;
169 };
170
171 ldo13_reg: LDO13 {
172 regulator-name = "CAM_A_2.8V";
173 regulator-min-microvolt = <2800000>;
174 regulator-max-microvolt = <2800000>;
175 regulator-always-on;
176 };
177
178 ldo14_reg: LDO14 {
179 regulator-name = "CAM_CIF_1.8V";
180 regulator-min-microvolt = <1800000>;
181 regulator-max-microvolt = <1800000>;
182 regulator-always-on;
183 };
184
185 ldo15_reg: LDO15 {
186 regulator-name = "CAM_AF_3.3V";
187 regulator-min-microvolt = <3300000>;
188 regulator-max-microvolt = <3300000>;
189 regulator-always-on;
190 };
191
192 ldo16_reg: LDO16 {
193 regulator-name = "VMIPI_1.8V";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <1800000>;
196 regulator-always-on;
197 };
198
199 ldo17_reg: LDO17 {
200 regulator-name = "CAM_8M_1.8V";
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <1800000>;
203 regulator-always-on;
204 };
205
206 buck1_reg: BUCK1 {
207 regulator-name = "VARM_1.2V";
208 regulator-min-microvolt = <1200000>;
209 regulator-max-microvolt = <1200000>;
210 regulator-always-on;
211 };
212
213 buck2_reg: BUCK2 {
214 regulator-name = "VINT_1.2V";
215 regulator-min-microvolt = <1200000>;
216 regulator-max-microvolt = <1200000>;
217 regulator-always-on;
218 };
219
220 buck3_reg: BUCK3 {
221 regulator-name = "VCC_1.8V";
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <1800000>;
224 regulator-always-on;
225 };
226
227 buck4_reg: BUCK4 {
228 regulator-name = "CAM_CORE_1.2V";
229 regulator-min-microvolt = <1200000>;
230 regulator-max-microvolt = <1200000>;
231 regulator-always-on;
232 };
233
234 vichg_reg: ENVICHG {
235 regulator-name = "VICHG";
236 };
237
238 safeout1_reg: ESAFEOUT1 {
239 regulator-name = "SAFEOUT1";
240 regulator-always-on;
241 };
242
243 safeout2_reg: ESAFEOUT2 {
244 regulator-name = "SAFEOUT2";
245 regulator-boot-on;
246 };
247 };
248 };
249
250 };
251
252 gpio-keys {
253 compatible = "gpio-keys";
254
255 power-key {
256 gpios = <&gph2 6 1>;
257 linux,code = <KEY_POWER>;
258 label = "power";
259 debounce-interval = <1>;
260 gpio-key,wakeup;
261 };
262 };
263};
264
265&xusbxti {
266 clock-frequency = <24000000>;
267};
268
269&keypad {
270 linux,input-no-autorepeat;
271 linux,input-wakeup;
272 samsung,keypad-num-rows = <3>;
273 samsung,keypad-num-columns = <3>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
276 <&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
277 status = "okay";
278
279 key_1 {
280 keypad,row = <0>;
281 keypad,column = <1>;
282 linux,code = <KEY_CONNECT>;
283 };
284
285 key_2 {
286 keypad,row = <0>;
287 keypad,column = <2>;
288 linux,code = <KEY_BACK>;
289 };
290
291 key_3 {
292 keypad,row = <1>;
293 keypad,column = <1>;
294 linux,code = <KEY_CAMERA_FOCUS>;
295 };
296
297 key_4 {
298 keypad,row = <1>;
299 keypad,column = <2>;
300 linux,code = <KEY_VOLUMEUP>;
301 };
302
303 key_5 {
304 keypad,row = <2>;
305 keypad,column = <1>;
306 linux,code = <KEY_CAMERA>;
307 };
308
309 key_6 {
310 keypad,row = <2>;
311 keypad,column = <2>;
312 linux,code = <KEY_VOLUMEDOWN>;
313 };
314};
315
316&uart0 {
317 status = "okay";
318};
319
320&uart1 {
321 status = "okay";
322};
323
324&uart2 {
325 status = "okay";
326};
327
328&uart3 {
329 status = "okay";
330};
331
332&sdhci0 {
333 bus-width = <4>;
334 non-removable;
335 status = "okay";
336 vmmc-supply = <&ldo5_reg>;
337 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
338 pinctrl-names = "default";
339};
340
341&sdhci2 {
342 bus-width = <4>;
343 cd-gpios = <&gph3 4 1>;
344 vmmc-supply = <&vtf_reg>;
345 cd-inverted;
346 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>;
347 pinctrl-names = "default";
348 status = "okay";
349};
350
351&onenand {
352 status = "okay";
353};
354
355&hsotg {
356 vusb_a-supply = <&ldo3_reg>;
357 vusb_d-supply = <&ldo8_reg>;
358 status = "okay";
359};
360
361&usbphy {
362 status = "okay";
363};
364
365&fimd {
366 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
367 pinctrl-names = "default";
368 status = "okay";
369
370 display-timings {
371 native-mode = <&timing0>;
372 timing0: timing {
373 clock-frequency = <0>;
374 hactive = <800>;
375 vactive = <480>;
376 hfront-porch = <16>;
377 hback-porch = <16>;
378 hsync-len = <2>;
379 vback-porch = <3>;
380 vfront-porch = <28>;
381 vsync-len = <1>;
382 };
383 };
384};
385
386&pinctrl0 {
387 t_flash_detect: t-flash-detect {
388 samsung,pins = "gph3-4";
389 samsung,pin-function = <0>;
390 samsung,pin-pud = <0>;
391 };
392};
diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
new file mode 100644
index 000000000000..6387c77a6f7b
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -0,0 +1,449 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Board device tree source for Samsung Goni board.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16/dts-v1/;
17#include <dt-bindings/input/input.h>
18#include "s5pv210.dtsi"
19
20/ {
21 model = "Samsung Goni based on S5PC110";
22 compatible = "samsung,goni", "samsung,s5pv210";
23
24 aliases {
25 i2c3 = &i2c_pmic;
26 };
27
28 chosen {
29 bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk";
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x30000000 0x05000000
35 0x40000000 0x10000000
36 0x50000000 0x08000000>;
37 };
38
39 regulators {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 vtf_reg: fixed-regulator@0 {
45 compatible = "regulator-fixed";
46 regulator-name = "V_TF_2.8V";
47 regulator-min-microvolt = <2800000>;
48 regulator-max-microvolt = <2800000>;
49 reg = <0>;
50 gpios = <&mp05 4 0>;
51 enable-active-high;
52 };
53
54 pda_reg: fixed-regulator@1 {
55 compatible = "regulator-fixed";
56 regulator-name = "VCC_1.8V_PDA";
57 regulator-min-microvolt = <1800000>;
58 regulator-max-microvolt = <1800000>;
59 reg = <1>;
60 };
61
62 bat_reg: fixed-regulator@2 {
63 compatible = "regulator-fixed";
64 regulator-name = "V_BAT";
65 regulator-min-microvolt = <3700000>;
66 regulator-max-microvolt = <3700000>;
67 reg = <2>;
68 };
69
70 tsp_reg: fixed-regulator@3 {
71 compatible = "regulator-fixed";
72 regulator-name = "TSP_VDD";
73 regulator-min-microvolt = <2800000>;
74 regulator-max-microvolt = <2800000>;
75 reg = <3>;
76 gpios = <&gpj1 3 0>;
77 enable-active-high;
78 };
79 };
80
81 i2c_pmic: i2c-pmic {
82 compatible = "i2c-gpio";
83 gpios = <&gpj4 0 0>, /* sda */
84 <&gpj4 3 0>; /* scl */
85 i2c-gpio,delay-us = <2>; /* ~100 kHz */
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 pmic@66 {
90 compatible = "national,lp3974";
91 reg = <0x66>;
92
93 max8998,pmic-buck1-default-dvs-idx = <0>;
94 max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
95 <&gph0 4 0>;
96 max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
97 <1200000>, <1200000>;
98
99 max8998,pmic-buck2-default-dvs-idx = <0>;
100 max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
101 max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
102
103 regulators {
104 ldo2_reg: LDO2 {
105 regulator-name = "VALIVE_1.1V";
106 regulator-min-microvolt = <1100000>;
107 regulator-max-microvolt = <1100000>;
108 regulator-always-on;
109 };
110
111 ldo3_reg: LDO3 {
112 regulator-name = "VUSB+MIPI_1.1V";
113 regulator-min-microvolt = <1100000>;
114 regulator-max-microvolt = <1100000>;
115 regulator-always-on;
116 };
117
118 ldo4_reg: LDO4 {
119 regulator-name = "VADC_3.3V";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
122 };
123
124 ldo5_reg: LDO5 {
125 regulator-name = "VTF_2.8V";
126 regulator-min-microvolt = <2800000>;
127 regulator-max-microvolt = <2800000>;
128 };
129
130 ldo6_reg: LDO6 {
131 regulator-name = "VCC_3.3V";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 };
135
136 ldo7_reg: LDO7 {
137 regulator-name = "VLCD_1.8V";
138 regulator-min-microvolt = <1800000>;
139 regulator-max-microvolt = <1800000>;
140 regulator-always-on;
141 };
142
143 ldo8_reg: LDO8 {
144 regulator-name = "VUSB+VDAC_3.3V";
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
147 };
148
149 ldo9_reg: LDO9 {
150 regulator-name = "VCC+VCAM_2.8V";
151 regulator-min-microvolt = <2800000>;
152 regulator-max-microvolt = <2800000>;
153 };
154
155 ldo10_reg: LDO10 {
156 regulator-name = "VPLL_1.1V";
157 regulator-min-microvolt = <1100000>;
158 regulator-max-microvolt = <1100000>;
159 regulator-boot-on;
160 };
161
162 ldo11_reg: LDO11 {
163 regulator-name = "CAM_IO_2.8V";
164 regulator-min-microvolt = <2800000>;
165 regulator-max-microvolt = <2800000>;
166 };
167
168 ldo12_reg: LDO12 {
169 regulator-name = "CAM_ISP_1.2V";
170 regulator-min-microvolt = <1200000>;
171 regulator-max-microvolt = <1200000>;
172 };
173
174 ldo13_reg: LDO13 {
175 regulator-name = "CAM_A_2.8V";
176 regulator-min-microvolt = <2800000>;
177 regulator-max-microvolt = <2800000>;
178 };
179
180 ldo14_reg: LDO14 {
181 regulator-name = "CAM_CIF_1.8V";
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <1800000>;
184 };
185
186 ldo15_reg: LDO15 {
187 regulator-name = "CAM_AF_3.3V";
188 regulator-min-microvolt = <3300000>;
189 regulator-max-microvolt = <3300000>;
190 };
191
192 ldo16_reg: LDO16 {
193 regulator-name = "VMIPI_1.8V";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <1800000>;
196 };
197
198 ldo17_reg: LDO17 {
199 regulator-name = "CAM_8M_1.8V";
200 regulator-min-microvolt = <1800000>;
201 regulator-max-microvolt = <1800000>;
202 regulator-always-on;
203 };
204
205 buck1_reg: BUCK1 {
206 regulator-name = "VARM_1.2V";
207 regulator-min-microvolt = <1200000>;
208 regulator-max-microvolt = <1200000>;
209 };
210
211 buck2_reg: BUCK2 {
212 regulator-name = "VINT_1.2V";
213 regulator-min-microvolt = <1200000>;
214 regulator-max-microvolt = <1200000>;
215 };
216
217 buck3_reg: BUCK3 {
218 regulator-name = "VCC_1.8V";
219 regulator-min-microvolt = <1800000>;
220 regulator-max-microvolt = <1800000>;
221 regulator-always-on;
222 };
223
224 buck4_reg: BUCK4 {
225 regulator-name = "CAM_CORE_1.2V";
226 regulator-min-microvolt = <1200000>;
227 regulator-max-microvolt = <1200000>;
228 regulator-always-on;
229 };
230 };
231 };
232 };
233
234 gpio-keys {
235 compatible = "gpio-keys";
236
237 power-key {
238 gpios = <&gph2 6 1>;
239 linux,code = <KEY_POWER>;
240 label = "power";
241 debounce-interval = <1>;
242 gpio-key,wakeup;
243 };
244 };
245};
246
247&xusbxti {
248 clock-frequency = <24000000>;
249};
250
251&keypad {
252 linux,input-no-autorepeat;
253 linux,input-wakeup;
254 samsung,keypad-num-rows = <3>;
255 samsung,keypad-num-columns = <3>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
258 <&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
259 status = "okay";
260
261 key_1 {
262 keypad,row = <0>;
263 keypad,column = <1>;
264 linux,code = <KEY_CONNECT>;
265 };
266
267 key_2 {
268 keypad,row = <0>;
269 keypad,column = <2>;
270 linux,code = <KEY_BACK>;
271 };
272
273 key_3 {
274 keypad,row = <1>;
275 keypad,column = <1>;
276 linux,code = <KEY_CAMERA_FOCUS>;
277 };
278
279 key_4 {
280 keypad,row = <1>;
281 keypad,column = <2>;
282 linux,code = <KEY_VOLUMEUP>;
283 };
284
285 key_5 {
286 keypad,row = <2>;
287 keypad,column = <1>;
288 linux,code = <KEY_CAMERA>;
289 };
290
291 key_6 {
292 keypad,row = <2>;
293 keypad,column = <2>;
294 linux,code = <KEY_VOLUMEDOWN>;
295 };
296};
297
298&uart0 {
299 status = "okay";
300};
301
302&uart1 {
303 status = "okay";
304};
305
306&uart2 {
307 status = "okay";
308};
309
310&uart3 {
311 status = "okay";
312};
313
314&sdhci0 {
315 bus-width = <4>;
316 non-removable;
317 vmmc-supply = <&ldo5_reg>;
318 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
319 pinctrl-names = "default";
320 status = "okay";
321};
322
323&sdhci2 {
324 bus-width = <4>;
325 cd-gpios = <&gph3 4 1>;
326 vmmc-supply = <&vtf_reg>;
327 cd-inverted;
328 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
329 pinctrl-names = "default";
330 status = "okay";
331};
332
333&hsotg {
334 vusb_a-supply = <&ldo3_reg>;
335 vusb_d-supply = <&ldo8_reg>;
336 status = "okay";
337};
338
339&usbphy {
340 status = "okay";
341};
342
343&i2c2 {
344 samsung,i2c-sda-delay = <100>;
345 samsung,i2c-max-bus-freq = <400000>;
346 samsung,i2c-slave-addr = <0x10>;
347 status = "okay";
348
349 tsp@4a {
350 compatible = "atmel,maxtouch";
351 reg = <0x4a>;
352 interrupt-parent = <&gpj0>;
353 interrupts = <5 2>;
354
355 atmel,x-line = <17>;
356 atmel,y-line = <11>;
357 atmel,x-size = <800>;
358 atmel,y-size = <480>;
359 atmel,burst-length = <0x21>;
360 atmel,threshold = <0x28>;
361 atmel,orientation = <1>;
362
363 vdd-supply = <&tsp_reg>;
364 };
365};
366
367&i2c0 {
368 samsung,i2c-sda-delay = <100>;
369 samsung,i2c-max-bus-freq = <100000>;
370 samsung,i2c-slave-addr = <0x10>;
371 status = "okay";
372
373 noon010pc30: sensor@30 {
374 compatible = "siliconfile,noon010pc30";
375 reg = <0x30>;
376 vddio-supply = <&ldo11_reg>;
377 vdda-supply = <&ldo13_reg>;
378 vdd_core-supply = <&ldo14_reg>;
379
380 clock-frequency = <16000000>;
381 clocks = <&clock_cam 0>;
382 clock-names = "mclk";
383 nreset-gpios = <&gpb 2 0>;
384 nstby-gpios = <&gpb 0 0>;
385
386 port {
387 noon010pc30_ep: endpoint {
388 remote-endpoint = <&fimc0_ep>;
389 bus-width = <8>;
390 hsync-active = <0>;
391 vsync-active = <1>;
392 pclk-sample = <1>;
393 };
394 };
395 };
396};
397
398&camera {
399 pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>;
400 pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>;
401 pinctrl-names = "default", "idle";
402
403 parallel-ports {
404 #address-cells = <1>;
405 #size-cells = <0>;
406
407 /* camera A input */
408 port@1 {
409 reg = <1>;
410 fimc0_ep: endpoint {
411 remote-endpoint = <&noon010pc30_ep>;
412 bus-width = <8>;
413 hsync-active = <1>;
414 vsync-active = <1>;
415 pclk-sample = <0>;
416 };
417 };
418 };
419};
420
421&fimd {
422 pinctrl-0 = <&lcd_clk &lcd_data24>;
423 pinctrl-names = "default";
424 status = "okay";
425
426 display-timings {
427 native-mode = <&timing0>;
428 timing0: timing {
429 /* 480x800@55Hz */
430 clock-frequency = <23439570>;
431 hactive = <480>;
432 hfront-porch = <16>;
433 hback-porch = <16>;
434 hsync-len = <2>;
435 vactive = <800>;
436 vback-porch = <2>;
437 vfront-porch = <28>;
438 vsync-len = <1>;
439 hsync-active = <0>;
440 vsync-active = <0>;
441 de-active = <0>;
442 pixelclk-active = <0>;
443 };
444 };
445};
446
447&onenand {
448 status = "okay";
449};
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
new file mode 100644
index 000000000000..8c714088e3c6
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
@@ -0,0 +1,839 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22&pinctrl0 {
23 gpa0: gpa0 {
24 gpio-controller;
25 #gpio-cells = <2>;
26
27 interrupt-controller;
28 #interrupt-cells = <2>;
29 };
30
31 gpa1: gpa1 {
32 gpio-controller;
33 #gpio-cells = <2>;
34
35 interrupt-controller;
36 #interrupt-cells = <2>;
37 };
38
39 gpb: gpb {
40 gpio-controller;
41 #gpio-cells = <2>;
42
43 interrupt-controller;
44 #interrupt-cells = <2>;
45 };
46
47 gpc0: gpc0 {
48 gpio-controller;
49 #gpio-cells = <2>;
50
51 interrupt-controller;
52 #interrupt-cells = <2>;
53 };
54
55 gpc1: gpc1 {
56 gpio-controller;
57 #gpio-cells = <2>;
58
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 };
62
63 gpd0: gpd0 {
64 gpio-controller;
65 #gpio-cells = <2>;
66
67 interrupt-controller;
68 #interrupt-cells = <2>;
69 };
70
71 gpd1: gpd1 {
72 gpio-controller;
73 #gpio-cells = <2>;
74
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 };
78
79 gpe0: gpe0 {
80 gpio-controller;
81 #gpio-cells = <2>;
82
83 interrupt-controller;
84 #interrupt-cells = <2>;
85 };
86
87 gpe1: gpe1 {
88 gpio-controller;
89 #gpio-cells = <2>;
90
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 };
94
95 gpf0: gpf0 {
96 gpio-controller;
97 #gpio-cells = <2>;
98
99 interrupt-controller;
100 #interrupt-cells = <2>;
101 };
102
103 gpf1: gpf1 {
104 gpio-controller;
105 #gpio-cells = <2>;
106
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 };
110
111 gpf2: gpf2 {
112 gpio-controller;
113 #gpio-cells = <2>;
114
115 interrupt-controller;
116 #interrupt-cells = <2>;
117 };
118
119 gpf3: gpf3 {
120 gpio-controller;
121 #gpio-cells = <2>;
122
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 };
126
127 gpg0: gpg0 {
128 gpio-controller;
129 #gpio-cells = <2>;
130
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 gpg1: gpg1 {
136 gpio-controller;
137 #gpio-cells = <2>;
138
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 };
142
143 gpg2: gpg2 {
144 gpio-controller;
145 #gpio-cells = <2>;
146
147 interrupt-controller;
148 #interrupt-cells = <2>;
149 };
150
151 gpg3: gpg3 {
152 gpio-controller;
153 #gpio-cells = <2>;
154
155 interrupt-controller;
156 #interrupt-cells = <2>;
157 };
158
159 gpj0: gpj0 {
160 gpio-controller;
161 #gpio-cells = <2>;
162
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 };
166
167 gpj1: gpj1 {
168 gpio-controller;
169 #gpio-cells = <2>;
170
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpj2: gpj2 {
176 gpio-controller;
177 #gpio-cells = <2>;
178
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
182
183 gpj3: gpj3 {
184 gpio-controller;
185 #gpio-cells = <2>;
186
187 interrupt-controller;
188 #interrupt-cells = <2>;
189 };
190
191 gpj4: gpj4 {
192 gpio-controller;
193 #gpio-cells = <2>;
194
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 gpgi: gpgi {
200 gpio-controller;
201 #gpio-cells = <2>;
202 };
203
204 mp01: mp01 {
205 gpio-controller;
206 #gpio-cells = <2>;
207 };
208
209 mp02: mp02 {
210 gpio-controller;
211 #gpio-cells = <2>;
212 };
213
214 mp03: mp03 {
215 gpio-controller;
216 #gpio-cells = <2>;
217 };
218
219 mp04: mp04 {
220 gpio-controller;
221 #gpio-cells = <2>;
222 };
223
224 mp05: mp05 {
225 gpio-controller;
226 #gpio-cells = <2>;
227 };
228
229 mp06: mp06 {
230 gpio-controller;
231 #gpio-cells = <2>;
232 };
233
234 mp07: mp07 {
235 gpio-controller;
236 #gpio-cells = <2>;
237 };
238
239 gph0: gph0 {
240 gpio-controller;
241 interrupt-controller;
242 interrupt-parent = <&vic0>;
243 interrupts = <0>, <1>, <2>, <3>,
244 <4>, <5>, <6>, <7>;
245 #gpio-cells = <2>;
246 #interrupt-cells = <2>;
247 };
248
249 gph1: gph1 {
250 gpio-controller;
251 interrupt-controller;
252 interrupt-parent = <&vic0>;
253 interrupts = <8>, <9>, <10>, <11>,
254 <12>, <13>, <14>, <15>;
255 #gpio-cells = <2>;
256 #interrupt-cells = <2>;
257 };
258
259 gph2: gph2 {
260 gpio-controller;
261 #gpio-cells = <2>;
262 #interrupt-cells = <2>;
263 };
264
265 gph3: gph3 {
266 gpio-controller;
267 #gpio-cells = <2>;
268 #interrupt-cells = <2>;
269 };
270
271 uart0_data: uart0-data {
272 samsung,pins = "gpa0-0", "gpa0-1";
273 samsung,pin-function = <2>;
274 samsung,pin-pud = <0>;
275 samsung,pin-drv = <0>;
276 };
277
278 uart0_fctl: uart0-fctl {
279 samsung,pins = "gpa0-2", "gpa0-3";
280 samsung,pin-function = <2>;
281 samsung,pin-pud = <0>;
282 samsung,pin-drv = <0>;
283 };
284
285 uart1_data: uart1-data {
286 samsung,pins = "gpa0-4", "gpa0-5";
287 samsung,pin-function = <2>;
288 samsung,pin-pud = <0>;
289 samsung,pin-drv = <0>;
290 };
291
292 uart1_fctl: uart1-fctl {
293 samsung,pins = "gpa0-6", "gpa0-7";
294 samsung,pin-function = <2>;
295 samsung,pin-pud = <0>;
296 samsung,pin-drv = <0>;
297 };
298
299 uart2_data: uart2-data {
300 samsung,pins = "gpa1-0", "gpa1-1";
301 samsung,pin-function = <2>;
302 samsung,pin-pud = <0>;
303 samsung,pin-drv = <0>;
304 };
305
306 uart2_fctl: uart2-fctl {
307 samsung,pins = "gpa1-2", "gpa1-3";
308 samsung,pin-function = <3>;
309 samsung,pin-pud = <0>;
310 samsung,pin-drv = <0>;
311 };
312
313 uart3_data: uart3-data {
314 samsung,pins = "gpa1-2", "gpa1-3";
315 samsung,pin-function = <2>;
316 samsung,pin-pud = <0>;
317 samsung,pin-drv = <0>;
318 };
319
320 uart_audio: uart-audio {
321 samsung,pins = "gpa1-2", "gpa1-3";
322 samsung,pin-function = <4>;
323 samsung,pin-pud = <0>;
324 samsung,pin-drv = <0>;
325 };
326
327 spi0_bus: spi0-bus {
328 samsung,pins = "gpb-0", "gpb-2", "gpb-3";
329 samsung,pin-function = <2>;
330 samsung,pin-pud = <2>;
331 samsung,pin-drv = <0>;
332 };
333
334 spi1_bus: spi1-bus {
335 samsung,pins = "gpb-4", "gpb-6", "gpb-7";
336 samsung,pin-function = <2>;
337 samsung,pin-pud = <2>;
338 samsung,pin-drv = <0>;
339 };
340
341 i2s0_bus: i2s0-bus {
342 samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
343 "gpi-4", "gpi-5", "gpi-6";
344 samsung,pin-function = <2>;
345 samsung,pin-pud = <0>;
346 samsung,pin-drv = <0>;
347 };
348
349 i2s1_bus: i2s1-bus {
350 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
351 "gpc0-4";
352 samsung,pin-function = <2>;
353 samsung,pin-pud = <0>;
354 samsung,pin-drv = <0>;
355 };
356
357 i2s2_bus: i2s2-bus {
358 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
359 "gpc1-4";
360 samsung,pin-function = <4>;
361 samsung,pin-pud = <0>;
362 samsung,pin-drv = <0>;
363 };
364
365 pcm1_bus: pcm1-bus {
366 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
367 "gpc0-4";
368 samsung,pin-function = <3>;
369 samsung,pin-pud = <0>;
370 samsung,pin-drv = <0>;
371 };
372
373 ac97_bus: ac97-bus {
374 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
375 "gpc0-4";
376 samsung,pin-function = <4>;
377 samsung,pin-pud = <0>;
378 samsung,pin-drv = <0>;
379 };
380
381 i2s2_bus: i2s2-bus {
382 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
383 "gpc1-4";
384 samsung,pin-function = <2>;
385 samsung,pin-pud = <0>;
386 samsung,pin-drv = <0>;
387 };
388
389 pcm2_bus: pcm2-bus {
390 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
391 "gpc1-4";
392 samsung,pin-function = <3>;
393 samsung,pin-pud = <0>;
394 samsung,pin-drv = <0>;
395 };
396
397 spdif_bus: spdif-bus {
398 samsung,pins = "gpc1-0", "gpc1-1";
399 samsung,pin-function = <4>;
400 samsung,pin-pud = <0>;
401 samsung,pin-drv = <0>;
402 };
403
404 spi2_bus: spi2-bus {
405 samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
406 samsung,pin-function = <5>;
407 samsung,pin-pud = <2>;
408 samsung,pin-drv = <0>;
409 };
410
411 i2c0_bus: i2c0-bus {
412 samsung,pins = "gpd1-0", "gpd1-1";
413 samsung,pin-function = <2>;
414 samsung,pin-pud = <2>;
415 samsung,pin-drv = <0>;
416 };
417
418 i2c1_bus: i2c1-bus {
419 samsung,pins = "gpd1-2", "gpd1-3";
420 samsung,pin-function = <2>;
421 samsung,pin-pud = <2>;
422 samsung,pin-drv = <0>;
423 };
424
425 i2c2_bus: i2c2-bus {
426 samsung,pins = "gpd1-4", "gpd1-5";
427 samsung,pin-function = <2>;
428 samsung,pin-pud = <2>;
429 samsung,pin-drv = <0>;
430 };
431
432 pwm0_out: pwm0-out {
433 samsung,pins = "gpd0-0";
434 samsung,pin-function = <2>;
435 samsung,pin-pud = <0>;
436 samsung,pin-drv = <0>;
437 };
438
439 pwm1_out: pwm1-out {
440 samsung,pins = "gpd0-1";
441 samsung,pin-function = <2>;
442 samsung,pin-pud = <0>;
443 samsung,pin-drv = <0>;
444 };
445
446 pwm2_out: pwm2-out {
447 samsung,pins = "gpd0-2";
448 samsung,pin-function = <2>;
449 samsung,pin-pud = <0>;
450 samsung,pin-drv = <0>;
451 };
452
453 pwm3_out: pwm3-out {
454 samsung,pins = "gpd0-3";
455 samsung,pin-function = <2>;
456 samsung,pin-pud = <0>;
457 samsung,pin-drv = <0>;
458 };
459
460 keypad_row0: keypad-row-0 {
461 samsung,pins = "gph3-0";
462 samsung,pin-function = <3>;
463 samsung,pin-pud = <0>;
464 samsung,pin-drv = <0>;
465 };
466
467 keypad_row1: keypad-row-1 {
468 samsung,pins = "gph3-1";
469 samsung,pin-function = <3>;
470 samsung,pin-pud = <0>;
471 samsung,pin-drv = <0>;
472 };
473
474 keypad_row2: keypad-row-2 {
475 samsung,pins = "gph3-2";
476 samsung,pin-function = <3>;
477 samsung,pin-pud = <0>;
478 samsung,pin-drv = <0>;
479 };
480
481 keypad_row3: keypad-row-3 {
482 samsung,pins = "gph3-3";
483 samsung,pin-function = <3>;
484 samsung,pin-pud = <0>;
485 samsung,pin-drv = <0>;
486 };
487
488 keypad_row4: keypad-row-4 {
489 samsung,pins = "gph3-4";
490 samsung,pin-function = <3>;
491 samsung,pin-pud = <0>;
492 samsung,pin-drv = <0>;
493 };
494
495 keypad_row5: keypad-row-5 {
496 samsung,pins = "gph3-5";
497 samsung,pin-function = <3>;
498 samsung,pin-pud = <0>;
499 samsung,pin-drv = <0>;
500 };
501
502 keypad_row6: keypad-row-6 {
503 samsung,pins = "gph3-6";
504 samsung,pin-function = <3>;
505 samsung,pin-pud = <0>;
506 samsung,pin-drv = <0>;
507 };
508
509 keypad_row7: keypad-row-7 {
510 samsung,pins = "gph3-7";
511 samsung,pin-function = <3>;
512 samsung,pin-pud = <0>;
513 samsung,pin-drv = <0>;
514 };
515
516 keypad_col0: keypad-col-0 {
517 samsung,pins = "gph2-0";
518 samsung,pin-function = <3>;
519 samsung,pin-pud = <0>;
520 samsung,pin-drv = <0>;
521 };
522
523 keypad_col1: keypad-col-1 {
524 samsung,pins = "gph2-1";
525 samsung,pin-function = <3>;
526 samsung,pin-pud = <0>;
527 samsung,pin-drv = <0>;
528 };
529
530 keypad_col2: keypad-col-2 {
531 samsung,pins = "gph2-2";
532 samsung,pin-function = <3>;
533 samsung,pin-pud = <0>;
534 samsung,pin-drv = <0>;
535 };
536
537 keypad_col3: keypad-col-3 {
538 samsung,pins = "gph2-3";
539 samsung,pin-function = <3>;
540 samsung,pin-pud = <0>;
541 samsung,pin-drv = <0>;
542 };
543
544 keypad_col4: keypad-col-4 {
545 samsung,pins = "gph2-4";
546 samsung,pin-function = <3>;
547 samsung,pin-pud = <0>;
548 samsung,pin-drv = <0>;
549 };
550
551 keypad_col5: keypad-col-5 {
552 samsung,pins = "gph2-5";
553 samsung,pin-function = <3>;
554 samsung,pin-pud = <0>;
555 samsung,pin-drv = <0>;
556 };
557
558 keypad_col6: keypad-col-6 {
559 samsung,pins = "gph2-6";
560 samsung,pin-function = <3>;
561 samsung,pin-pud = <0>;
562 samsung,pin-drv = <0>;
563 };
564
565 keypad_col7: keypad-col-7 {
566 samsung,pins = "gph2-7";
567 samsung,pin-function = <3>;
568 samsung,pin-pud = <0>;
569 samsung,pin-drv = <0>;
570 };
571
572 sd0_clk: sd0-clk {
573 samsung,pins = "gpg0-0";
574 samsung,pin-function = <2>;
575 samsung,pin-pud = <0>;
576 samsung,pin-drv = <3>;
577 };
578
579 sd0_cmd: sd0-cmd {
580 samsung,pins = "gpg0-1";
581 samsung,pin-function = <2>;
582 samsung,pin-pud = <0>;
583 samsung,pin-drv = <3>;
584 };
585
586 sd0_cd: sd0-cd {
587 samsung,pins = "gpg0-2";
588 samsung,pin-function = <2>;
589 samsung,pin-pud = <2>;
590 samsung,pin-drv = <3>;
591 };
592
593 sd0_bus1: sd0-bus-width1 {
594 samsung,pins = "gpg0-3";
595 samsung,pin-function = <2>;
596 samsung,pin-pud = <2>;
597 samsung,pin-drv = <3>;
598 };
599
600 sd0_bus4: sd0-bus-width4 {
601 samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6";
602 samsung,pin-function = <2>;
603 samsung,pin-pud = <2>;
604 samsung,pin-drv = <3>;
605 };
606
607 sd0_bus8: sd0-bus-width8 {
608 samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
609 samsung,pin-function = <3>;
610 samsung,pin-pud = <2>;
611 samsung,pin-drv = <3>;
612 };
613
614 sd1_clk: sd1-clk {
615 samsung,pins = "gpg1-0";
616 samsung,pin-function = <2>;
617 samsung,pin-pud = <0>;
618 samsung,pin-drv = <3>;
619 };
620
621 sd1_cmd: sd1-cmd {
622 samsung,pins = "gpg1-1";
623 samsung,pin-function = <2>;
624 samsung,pin-pud = <0>;
625 samsung,pin-drv = <3>;
626 };
627
628 sd1_cd: sd1-cd {
629 samsung,pins = "gpg1-2";
630 samsung,pin-function = <2>;
631 samsung,pin-pud = <2>;
632 samsung,pin-drv = <3>;
633 };
634
635 sd1_bus1: sd1-bus-width1 {
636 samsung,pins = "gpg1-3";
637 samsung,pin-function = <2>;
638 samsung,pin-pud = <2>;
639 samsung,pin-drv = <3>;
640 };
641
642 sd1_bus4: sd1-bus-width4 {
643 samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
644 samsung,pin-function = <2>;
645 samsung,pin-pud = <2>;
646 samsung,pin-drv = <3>;
647 };
648
649 sd2_clk: sd2-clk {
650 samsung,pins = "gpg2-0";
651 samsung,pin-function = <2>;
652 samsung,pin-pud = <0>;
653 samsung,pin-drv = <3>;
654 };
655
656 sd2_cmd: sd2-cmd {
657 samsung,pins = "gpg2-1";
658 samsung,pin-function = <2>;
659 samsung,pin-pud = <0>;
660 samsung,pin-drv = <3>;
661 };
662
663 sd2_cd: sd2-cd {
664 samsung,pins = "gpg2-2";
665 samsung,pin-function = <2>;
666 samsung,pin-pud = <2>;
667 samsung,pin-drv = <3>;
668 };
669
670 sd2_bus1: sd2-bus-width1 {
671 samsung,pins = "gpg2-3";
672 samsung,pin-function = <2>;
673 samsung,pin-pud = <2>;
674 samsung,pin-drv = <3>;
675 };
676
677 sd2_bus4: sd2-bus-width4 {
678 samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6";
679 samsung,pin-function = <2>;
680 samsung,pin-pud = <2>;
681 samsung,pin-drv = <3>;
682 };
683
684 sd2_bus8: sd2-bus-width8 {
685 samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
686 samsung,pin-function = <3>;
687 samsung,pin-pud = <2>;
688 samsung,pin-drv = <3>;
689 };
690
691 sd3_clk: sd3-clk {
692 samsung,pins = "gpg3-0";
693 samsung,pin-function = <2>;
694 samsung,pin-pud = <0>;
695 samsung,pin-drv = <3>;
696 };
697
698 sd3_cmd: sd3-cmd {
699 samsung,pins = "gpg3-1";
700 samsung,pin-function = <2>;
701 samsung,pin-pud = <0>;
702 samsung,pin-drv = <3>;
703 };
704
705 sd3_cd: sd3-cd {
706 samsung,pins = "gpg3-2";
707 samsung,pin-function = <2>;
708 samsung,pin-pud = <2>;
709 samsung,pin-drv = <3>;
710 };
711
712 sd3_bus1: sd3-bus-width1 {
713 samsung,pins = "gpg3-3";
714 samsung,pin-function = <2>;
715 samsung,pin-pud = <2>;
716 samsung,pin-drv = <3>;
717 };
718
719 sd3_bus4: sd3-bus-width4 {
720 samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
721 samsung,pin-function = <2>;
722 samsung,pin-pud = <2>;
723 samsung,pin-drv = <3>;
724 };
725
726 eint0: ext-int0 {
727 samsung,pins = "gph0-0";
728 samsung,pin-function = <0xf>;
729 samsung,pin-pud = <0>;
730 samsung,pin-drv = <0>;
731 };
732
733 eint8: ext-int8 {
734 samsung,pins = "gph1-0";
735 samsung,pin-function = <0xf>;
736 samsung,pin-pud = <0>;
737 samsung,pin-drv = <0>;
738 };
739
740 eint15: ext-int15 {
741 samsung,pins = "gph1-7";
742 samsung,pin-function = <0xf>;
743 samsung,pin-pud = <0>;
744 samsung,pin-drv = <0>;
745 };
746
747 eint16: ext-int16 {
748 samsung,pins = "gph2-0";
749 samsung,pin-function = <0xf>;
750 samsung,pin-pud = <0>;
751 samsung,pin-drv = <0>;
752 };
753
754 eint31: ext-int31 {
755 samsung,pins = "gph3-7";
756 samsung,pin-function = <0xf>;
757 samsung,pin-pud = <0>;
758 samsung,pin-drv = <0>;
759 };
760
761 cam_port_a_io: cam-port-a-io {
762 samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
763 "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
764 "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4";
765 samsung,pin-function = <2>;
766 samsung,pin-pud = <0>;
767 samsung,pin-drv = <0>;
768 };
769
770 cam_port_a_clk_active: cam-port-a-clk-active {
771 samsung,pins = "gpe1-3";
772 samsung,pin-function = <2>;
773 samsung,pin-pud = <0>;
774 samsung,pin-drv = <3>;
775 };
776
777 cam_port_a_clk_idle: cam-port-a-clk-idle {
778 samsung,pins = "gpe1-3";
779 samsung,pin-function = <0>;
780 samsung,pin-pud = <1>;
781 samsung,pin-drv = <0>;
782 };
783
784 cam_port_b_io: cam-port-b-io {
785 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
786 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
787 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
788 samsung,pin-function = <3>;
789 samsung,pin-pud = <0>;
790 samsung,pin-drv = <0>;
791 };
792
793 cam_port_b_clk_active: cam-port-b-clk-active {
794 samsung,pins = "gpj1-3";
795 samsung,pin-function = <3>;
796 samsung,pin-pud = <0>;
797 samsung,pin-drv = <3>;
798 };
799
800 cam_port_b_clk_idle: cam-port-b-clk-idle {
801 samsung,pins = "gpj1-3";
802 samsung,pin-function = <0>;
803 samsung,pin-pud = <1>;
804 samsung,pin-drv = <0>;
805 };
806
807 lcd_ctrl: lcd-ctrl {
808 samsung,pins = "gpd0-0", "gpd0-1";
809 samsung,pin-function = <3>;
810 samsung,pin-pud = <0>;
811 samsung,pin-drv = <0>;
812 };
813
814 lcd_sync: lcd-sync {
815 samsung,pins = "gpf0-0", "gpf0-1";
816 samsung,pin-function = <2>;
817 samsung,pin-pud = <0>;
818 samsung,pin-drv = <0>;
819 };
820
821 lcd_clk: lcd-clk {
822 samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
823 samsung,pin-function = <2>;
824 samsung,pin-pud = <0>;
825 samsung,pin-drv = <0>;
826 };
827
828 lcd_data24: lcd-data-width24 {
829 samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
830 "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
831 "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
832 "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
833 "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
834 "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
835 samsung,pin-function = <2>;
836 samsung,pin-pud = <0>;
837 samsung,pin-drv = <0>;
838 };
839};
diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts
new file mode 100644
index 000000000000..1eedab7ffe94
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts
@@ -0,0 +1,78 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Board device tree source for YIC System SMDC110 board.
10 *
11 * NOTE: This file is completely based on original board file for mach-smdkc110
12 * available in Linux 3.15 and intends to provide equivalent level of hardware
13 * support. Due to lack of hardware, _no_ testing has been performed.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20/dts-v1/;
21#include <dt-bindings/input/input.h>
22#include "s5pv210.dtsi"
23
24/ {
25 model = "YIC System SMDKC110 based on S5PC110";
26 compatible = "yic,smdkc110", "samsung,s5pv210";
27
28 chosen {
29 bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x20000000 0x20000000>;
35 };
36};
37
38&xusbxti {
39 clock-frequency = <24000000>;
40};
41
42&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 status = "okay";
48};
49
50&uart2 {
51 status = "okay";
52};
53
54&uart3 {
55 status = "okay";
56};
57
58&rtc {
59 status = "okay";
60};
61
62&i2c0 {
63 status = "okay";
64
65 audio-codec@1b {
66 compatible = "wlf,wm8580";
67 reg = <0x1b>;
68 };
69
70 eeprom@50 {
71 compatible = "atmel,24c08";
72 reg = <0x50>;
73 };
74};
75
76&i2s0 {
77 status = "okay";
78};
diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts
new file mode 100644
index 000000000000..cb8521899ec8
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts
@@ -0,0 +1,238 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Board device tree source for YIC System SMDV210 board.
10 *
11 * NOTE: This file is completely based on original board file for mach-smdkv210
12 * available in Linux 3.15 and intends to provide equivalent level of hardware
13 * support. Due to lack of hardware, _no_ testing has been performed.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20/dts-v1/;
21#include <dt-bindings/input/input.h>
22#include "s5pv210.dtsi"
23
24/ {
25 model = "YIC System SMDKV210 based on S5PV210";
26 compatible = "yic,smdkv210", "samsung,s5pv210";
27
28 chosen {
29 bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x20000000 0x40000000>;
35 };
36
37 ethernet@18000000 {
38 compatible = "davicom,dm9000";
39 reg = <0xA8000000 0x2 0xA8000002 0x2>;
40 interrupt-parent = <&gph1>;
41 interrupts = <1 4>;
42 local-mac-address = [00 00 de ad be ef];
43 davicom,no-eeprom;
44 };
45
46 backlight {
47 compatible = "pwm-backlight";
48 pwms = <&pwm 3 5000000 0>;
49 brightness-levels = <0 4 8 16 32 64 128 255>;
50 default-brightness-level = <6>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&pwm3_out>;
53 };
54};
55
56&xusbxti {
57 clock-frequency = <24000000>;
58};
59
60&keypad {
61 linux,input-no-autorepeat;
62 linux,input-wakeup;
63 samsung,keypad-num-rows = <8>;
64 samsung,keypad-num-columns = <8>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
67 <&keypad_row3>, <&keypad_row4>, <&keypad_row5>,
68 <&keypad_row6>, <&keypad_row7>,
69 <&keypad_col0>, <&keypad_col1>, <&keypad_col2>,
70 <&keypad_col3>, <&keypad_col4>, <&keypad_col5>,
71 <&keypad_col6>, <&keypad_col7>;
72 status = "okay";
73
74 key_1 {
75 keypad,row = <0>;
76 keypad,column = <3>;
77 linux,code = <KEY_1>;
78 };
79
80 key_2 {
81 keypad,row = <0>;
82 keypad,column = <4>;
83 linux,code = <KEY_2>;
84 };
85
86 key_3 {
87 keypad,row = <0>;
88 keypad,column = <5>;
89 linux,code = <KEY_3>;
90 };
91
92 key_4 {
93 keypad,row = <0>;
94 keypad,column = <6>;
95 linux,code = <KEY_4>;
96 };
97
98 key_5 {
99 keypad,row = <0
100 >;
101 keypad,column = <7>;
102 linux,code = <KEY_5>;
103 };
104
105 key_6 {
106 keypad,row = <1>;
107 keypad,column = <3>;
108 linux,code = <KEY_A>;
109 };
110 key_7 {
111 keypad,row = <1>;
112 keypad,column = <4>;
113 linux,code = <KEY_B>;
114 };
115
116 key_8 {
117 keypad,row = <1>;
118 keypad,column = <5>;
119 linux,code = <KEY_C>;
120 };
121
122 key_9 {
123 keypad,row = <1>;
124 keypad,column = <6>;
125 linux,code = <KEY_D>;
126 };
127
128 key_10 {
129 keypad,row = <1>;
130 keypad,column = <7>;
131 linux,code = <KEY_E>;
132 };
133};
134
135&uart0 {
136 status = "okay";
137};
138
139&uart1 {
140 status = "okay";
141};
142
143&uart2 {
144 status = "okay";
145};
146
147&uart3 {
148 status = "okay";
149};
150
151&rtc {
152 status = "okay";
153};
154
155&sdhci0 {
156 bus-width = <4>;
157 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
158 pinctrl-names = "default";
159 status = "okay";
160};
161
162&sdhci1 {
163 bus-width = <4>;
164 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
165 pinctrl-names = "default";
166 status = "okay";
167};
168
169&sdhci2 {
170 bus-width = <4>;
171 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
172 pinctrl-names = "default";
173 status = "okay";
174};
175
176&sdhci3 {
177 bus-width = <4>;
178 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
179 pinctrl-names = "default";
180 status = "okay";
181};
182
183&hsotg {
184 status = "okay";
185};
186
187&usbphy {
188 status = "okay";
189};
190
191&fimd {
192 pinctrl-0 = <&lcd_clk &lcd_data24>;
193 pinctrl-names = "default";
194 status = "okay";
195
196 display-timings {
197 native-mode = <&timing0>;
198
199 timing0: timing@0 {
200 /* 800x480@60Hz */
201 clock-frequency = <24373920>;
202 hactive = <800>;
203 vactive = <480>;
204 hfront-porch = <8>;
205 hback-porch = <13>;
206 hsync-len = <3>;
207 vback-porch = <7>;
208 vfront-porch = <5>;
209 vsync-len = <1>;
210 hsync-active = <0>;
211 vsync-active = <0>;
212 de-active = <1>;
213 pixelclk-active = <1>;
214 };
215 };
216};
217
218&pwm {
219 samsung,pwm-outputs = <3>;
220};
221
222&i2c0 {
223 status = "okay";
224
225 audio-codec@1b {
226 compatible = "wlf,wm8580";
227 reg = <0x1b>;
228 };
229
230 eeprom@50 {
231 compatible = "atmel,24c08";
232 reg = <0x50>;
233 };
234};
235
236&i2s0 {
237 status = "okay";
238};
diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts
new file mode 100644
index 000000000000..622599fd2cfa
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210-torbreck.dts
@@ -0,0 +1,92 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Board device tree source for Torbreck board.
10 *
11 * NOTE: This file is completely based on original board file for mach-torbreck
12 * available in Linux 3.15 and intends to provide equivalent level of hardware
13 * support. Due to lack of hardware, _no_ testing has been performed.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20/dts-v1/;
21#include <dt-bindings/input/input.h>
22#include "s5pv210.dtsi"
23
24/ {
25 model = "aESOP Torbreck based on S5PV210";
26 compatible = "aesop,torbreck", "samsung,s5pv210";
27
28 chosen {
29 bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x20000000 0x20000000>;
35 };
36};
37
38&xusbxti {
39 clock-frequency = <24000000>;
40};
41
42&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 status = "okay";
48};
49
50&uart2 {
51 status = "okay";
52};
53
54&uart3 {
55 status = "okay";
56};
57
58&rtc {
59 status = "okay";
60};
61
62&sdhci0 {
63 bus-width = <4>;
64 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
65 pinctrl-names = "default";
66 status = "okay";
67};
68
69&sdhci1 {
70 bus-width = <4>;
71 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
72 pinctrl-names = "default";
73 status = "okay";
74};
75
76&sdhci2 {
77 bus-width = <4>;
78 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
79 pinctrl-names = "default";
80 status = "okay";
81};
82
83&sdhci3 {
84 bus-width = <4>;
85 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
86 pinctrl-names = "default";
87 status = "okay";
88};
89
90&i2s0 {
91 status = "okay";
92};
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
new file mode 100644
index 000000000000..8344a0ee2b86
--- /dev/null
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -0,0 +1,633 @@
1/*
2 * Samsung's S5PV210 SoC device tree source
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
5 *
6 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
7 * Tomasz Figa <t.figa@samsung.com>
8 *
9 * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22#include "skeleton.dtsi"
23#include <dt-bindings/clock/s5pv210.h>
24#include <dt-bindings/clock/s5pv210-audss.h>
25
26/ {
27 aliases {
28 csis0 = &csis0;
29 fimc0 = &fimc0;
30 fimc1 = &fimc1;
31 fimc2 = &fimc2;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
34 i2c2 = &i2c2;
35 i2s0 = &i2s0;
36 i2s1 = &i2s1;
37 i2s2 = &i2s2;
38 pinctrl0 = &pinctrl0;
39 spi0 = &spi0;
40 spi1 = &spi1;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a8";
50 reg = <0>;
51 };
52 };
53
54 soc {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges;
59
60 external-clocks {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 xxti: oscillator@0 {
66 compatible = "fixed-clock";
67 reg = <0>;
68 clock-frequency = <0>;
69 clock-output-names = "xxti";
70 #clock-cells = <0>;
71 };
72
73 xusbxti: oscillator@1 {
74 compatible = "fixed-clock";
75 reg = <1>;
76 clock-frequency = <0>;
77 clock-output-names = "xusbxti";
78 #clock-cells = <0>;
79 };
80 };
81
82 onenand: onenand@b0000000 {
83 compatible = "samsung,s5pv210-onenand";
84 reg = <0xb0600000 0x2000>,
85 <0xb0000000 0x20000>,
86 <0xb0040000 0x20000>;
87 interrupt-parent = <&vic1>;
88 interrupts = <31>;
89 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
90 clock-names = "bus", "onenand";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 status = "disabled";
94 };
95
96 chipid@e0000000 {
97 compatible = "samsung,s5pv210-chipid";
98 reg = <0xe0000000 0x1000>;
99 };
100
101 clocks: clock-controller@e0100000 {
102 compatible = "samsung,s5pv210-clock", "simple-bus";
103 reg = <0xe0100000 0x10000>;
104 clock-names = "xxti", "xusbxti";
105 clocks = <&xxti>, <&xusbxti>;
106 #clock-cells = <1>;
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 pmu_syscon: syscon@e0108000 {
112 compatible = "samsung-s5pv210-pmu", "syscon";
113 reg = <0xe0108000 0x8000>;
114 };
115 };
116
117 pinctrl0: pinctrl@e0200000 {
118 compatible = "samsung,s5pv210-pinctrl";
119 reg = <0xe0200000 0x1000>;
120 interrupt-parent = <&vic0>;
121 interrupts = <30>;
122
123 wakeup-interrupt-controller {
124 compatible = "samsung,exynos4210-wakeup-eint";
125 interrupts = <16>;
126 interrupt-parent = <&vic0>;
127 };
128 };
129
130 amba {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "arm,amba-bus";
134 ranges;
135
136 pdma0: dma@e0900000 {
137 compatible = "arm,pl330", "arm,primecell";
138 reg = <0xe0900000 0x1000>;
139 interrupt-parent = <&vic0>;
140 interrupts = <19>;
141 clocks = <&clocks CLK_PDMA0>;
142 clock-names = "apb_pclk";
143 #dma-cells = <1>;
144 #dma-channels = <8>;
145 #dma-requests = <32>;
146 };
147
148 pdma1: dma@e0a00000 {
149 compatible = "arm,pl330", "arm,primecell";
150 reg = <0xe0a00000 0x1000>;
151 interrupt-parent = <&vic0>;
152 interrupts = <20>;
153 clocks = <&clocks CLK_PDMA1>;
154 clock-names = "apb_pclk";
155 #dma-cells = <1>;
156 #dma-channels = <8>;
157 #dma-requests = <32>;
158 };
159 };
160
161 spi0: spi@e1300000 {
162 compatible = "samsung,s5pv210-spi";
163 reg = <0xe1300000 0x1000>;
164 interrupt-parent = <&vic1>;
165 interrupts = <15>;
166 dmas = <&pdma0 7>, <&pdma0 6>;
167 dma-names = "tx", "rx";
168 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
169 clock-names = "spi", "spi_busclk0";
170 pinctrl-names = "default";
171 pinctrl-0 = <&spi0_bus>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 status = "disabled";
175 };
176
177 spi1: spi@e1400000 {
178 compatible = "samsung,s5pv210-spi";
179 reg = <0xe1400000 0x1000>;
180 interrupt-parent = <&vic1>;
181 interrupts = <16>;
182 dmas = <&pdma1 7>, <&pdma1 6>;
183 dma-names = "tx", "rx";
184 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
185 clock-names = "spi", "spi_busclk0";
186 pinctrl-names = "default";
187 pinctrl-0 = <&spi1_bus>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 status = "disabled";
191 };
192
193 keypad: keypad@e1600000 {
194 compatible = "samsung,s5pv210-keypad";
195 reg = <0xe1600000 0x1000>;
196 interrupt-parent = <&vic2>;
197 interrupts = <25>;
198 clocks = <&clocks CLK_KEYIF>;
199 clock-names = "keypad";
200 status = "disabled";
201 };
202
203 i2c0: i2c@e1800000 {
204 compatible = "samsung,s3c2440-i2c";
205 reg = <0xe1800000 0x1000>;
206 interrupt-parent = <&vic1>;
207 interrupts = <14>;
208 clocks = <&clocks CLK_I2C0>;
209 clock-names = "i2c";
210 pinctrl-names = "default";
211 pinctrl-0 = <&i2c0_bus>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 status = "disabled";
215 };
216
217 i2c2: i2c@e1a00000 {
218 compatible = "samsung,s3c2440-i2c";
219 reg = <0xe1a00000 0x1000>;
220 interrupt-parent = <&vic1>;
221 interrupts = <19>;
222 clocks = <&clocks CLK_I2C2>;
223 clock-names = "i2c";
224 pinctrl-0 = <&i2c2_bus>;
225 pinctrl-names = "default";
226 #address-cells = <1>;
227 #size-cells = <0>;
228 status = "disabled";
229 };
230
231 audio-subsystem {
232 compatible = "samsung,s5pv210-audss", "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
235 ranges;
236
237 clk_audss: clock-controller@eee10000 {
238 compatible = "samsung,s5pv210-audss-clock";
239 reg = <0xeee10000 0x1000>;
240 clock-names = "hclk", "xxti",
241 "fout_epll",
242 "sclk_audio0";
243 clocks = <&clocks DOUT_HCLKP>, <&xxti>,
244 <&clocks FOUT_EPLL>,
245 <&clocks SCLK_AUDIO0>;
246 #clock-cells = <1>;
247 };
248
249 i2s0: i2s@eee30000 {
250 compatible = "samsung,s5pv210-i2s";
251 reg = <0xeee30000 0x1000>;
252 interrupt-parent = <&vic2>;
253 interrupts = <16>;
254 dma-names = "rx", "tx", "tx-sec";
255 dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>;
256 clock-names = "iis",
257 "i2s_opclk0",
258 "i2s_opclk1";
259 clocks = <&clk_audss CLK_I2S>,
260 <&clk_audss CLK_I2S>,
261 <&clk_audss CLK_DOUT_AUD_BUS>;
262 samsung,idma-addr = <0xc0010000>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&i2s0_bus>;
265 #sound-dai-cells = <0>;
266 status = "disabled";
267 };
268 };
269
270 i2s1: i2s@e2100000 {
271 compatible = "samsung,s3c6410-i2s";
272 reg = <0xe2100000 0x1000>;
273 interrupt-parent = <&vic2>;
274 interrupts = <17>;
275 dma-names = "rx", "tx";
276 dmas = <&pdma1 12>, <&pdma1 13>;
277 clock-names = "iis", "i2s_opclk0";
278 clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2s1_bus>;
281 #sound-dai-cells = <0>;
282 status = "disabled";
283 };
284
285 i2s2: i2s@e2a00000 {
286 compatible = "samsung,s3c6410-i2s";
287 reg = <0xe2a00000 0x1000>;
288 interrupt-parent = <&vic2>;
289 interrupts = <18>;
290 dma-names = "rx", "tx";
291 dmas = <&pdma1 14>, <&pdma1 15>;
292 clock-names = "iis", "i2s_opclk0";
293 clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&i2s2_bus>;
296 #sound-dai-cells = <0>;
297 status = "disabled";
298 };
299
300 pwm: pwm@e2500000 {
301 compatible = "samsung,s5pc100-pwm";
302 reg = <0xe2500000 0x1000>;
303 interrupt-parent = <&vic0>;
304 interrupts = <21>, <22>, <23>, <24>, <25>;
305 clock-names = "timers";
306 clocks = <&clocks CLK_PWM>;
307 #pwm-cells = <3>;
308 };
309
310 watchdog: watchdog@e2700000 {
311 compatible = "samsung,s3c2410-wdt";
312 reg = <0xe2700000 0x1000>;
313 interrupt-parent = <&vic0>;
314 interrupts = <26>;
315 clock-names = "watchdog";
316 clocks = <&clocks CLK_WDT>;
317 };
318
319 rtc: rtc@e2800000 {
320 compatible = "samsung,s3c6410-rtc";
321 reg = <0xe2800000 0x100>;
322 interrupt-parent = <&vic0>;
323 interrupts = <28>, <29>;
324 clocks = <&clocks CLK_RTC>;
325 clock-names = "rtc";
326 status = "disabled";
327 };
328
329 uart0: serial@e2900000 {
330 compatible = "samsung,s5pv210-uart";
331 reg = <0xe2900000 0x400>;
332 interrupt-parent = <&vic1>;
333 interrupts = <10>;
334 clock-names = "uart", "clk_uart_baud0",
335 "clk_uart_baud1";
336 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
337 <&clocks SCLK_UART0>;
338 status = "disabled";
339 };
340
341 uart1: serial@e2900400 {
342 compatible = "samsung,s5pv210-uart";
343 reg = <0xe2900400 0x400>;
344 interrupt-parent = <&vic1>;
345 interrupts = <11>;
346 clock-names = "uart", "clk_uart_baud0",
347 "clk_uart_baud1";
348 clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
349 <&clocks SCLK_UART1>;
350 status = "disabled";
351 };
352
353 uart2: serial@e2900800 {
354 compatible = "samsung,s5pv210-uart";
355 reg = <0xe2900800 0x400>;
356 interrupt-parent = <&vic1>;
357 interrupts = <12>;
358 clock-names = "uart", "clk_uart_baud0",
359 "clk_uart_baud1";
360 clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
361 <&clocks SCLK_UART2>;
362 status = "disabled";
363 };
364
365 uart3: serial@e2900c00 {
366 compatible = "samsung,s5pv210-uart";
367 reg = <0xe2900c00 0x400>;
368 interrupt-parent = <&vic1>;
369 interrupts = <13>;
370 clock-names = "uart", "clk_uart_baud0",
371 "clk_uart_baud1";
372 clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>,
373 <&clocks SCLK_UART3>;
374 status = "disabled";
375 };
376
377 sdhci0: sdhci@eb000000 {
378 compatible = "samsung,s3c6410-sdhci";
379 reg = <0xeb000000 0x100000>;
380 interrupt-parent = <&vic1>;
381 interrupts = <26>;
382 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
383 clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>,
384 <&clocks SCLK_MMC0>;
385 status = "disabled";
386 };
387
388 sdhci1: sdhci@eb100000 {
389 compatible = "samsung,s3c6410-sdhci";
390 reg = <0xeb100000 0x100000>;
391 interrupt-parent = <&vic1>;
392 interrupts = <27>;
393 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
394 clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>,
395 <&clocks SCLK_MMC1>;
396 status = "disabled";
397 };
398
399 sdhci2: sdhci@eb200000 {
400 compatible = "samsung,s3c6410-sdhci";
401 reg = <0xeb200000 0x100000>;
402 interrupt-parent = <&vic1>;
403 interrupts = <28>;
404 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
405 clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>,
406 <&clocks SCLK_MMC2>;
407 status = "disabled";
408 };
409
410 sdhci3: sdhci@eb300000 {
411 compatible = "samsung,s3c6410-sdhci";
412 reg = <0xeb300000 0x100000>;
413 interrupt-parent = <&vic3>;
414 interrupts = <2>;
415 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3";
416 clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>,
417 <&clocks SCLK_MMC3>;
418 status = "disabled";
419 };
420
421 hsotg: hsotg@ec000000 {
422 compatible = "samsung,s3c6400-hsotg";
423 reg = <0xec000000 0x20000>;
424 interrupt-parent = <&vic1>;
425 interrupts = <24>;
426 clocks = <&clocks CLK_USB_OTG>;
427 clock-names = "otg";
428 phy-names = "usb2-phy";
429 phys = <&usbphy 0>;
430 status = "disabled";
431 };
432
433 usbphy: usbphy@ec100000 {
434 compatible = "samsung,s5pv210-usb2-phy";
435 reg = <0xec100000 0x100>;
436 samsung,pmureg-phandle = <&pmu_syscon>;
437 clocks = <&clocks CLK_USB_OTG>, <&xusbxti>;
438 clock-names = "phy", "ref";
439 #phy-cells = <1>;
440 status = "disabled";
441 };
442
443 ehci: ehci@ec200000 {
444 compatible = "samsung,exynos4210-ehci";
445 reg = <0xec200000 0x100>;
446 interrupts = <23>;
447 interrupt-parent = <&vic1>;
448 clocks = <&clocks CLK_USB_HOST>;
449 clock-names = "usbhost";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 status = "disabled";
453
454 port@0 {
455 reg = <0>;
456 phys = <&usbphy 1>;
457 };
458 };
459
460 ohci: ohci@ec300000 {
461 compatible = "samsung,exynos4210-ohci";
462 reg = <0xec300000 0x100>;
463 interrupts = <23>;
464 clocks = <&clocks CLK_USB_HOST>;
465 clock-names = "usbhost";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469
470 port@0 {
471 reg = <0>;
472 phys = <&usbphy 1>;
473 };
474 };
475
476 mfc: codec@f1700000 {
477 compatible = "samsung,mfc-v5";
478 reg = <0xf1700000 0x10000>;
479 interrupt-parent = <&vic2>;
480 interrupts = <14>;
481 clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>;
482 clock-names = "sclk_mfc", "mfc";
483 };
484
485 vic0: interrupt-controller@f2000000 {
486 compatible = "arm,pl192-vic";
487 interrupt-controller;
488 reg = <0xf2000000 0x1000>;
489 #interrupt-cells = <1>;
490 };
491
492 vic1: interrupt-controller@f2100000 {
493 compatible = "arm,pl192-vic";
494 interrupt-controller;
495 reg = <0xf2100000 0x1000>;
496 #interrupt-cells = <1>;
497 };
498
499 vic2: interrupt-controller@f2200000 {
500 compatible = "arm,pl192-vic";
501 interrupt-controller;
502 reg = <0xf2200000 0x1000>;
503 #interrupt-cells = <1>;
504 };
505
506 vic3: interrupt-controller@f2300000 {
507 compatible = "arm,pl192-vic";
508 interrupt-controller;
509 reg = <0xf2300000 0x1000>;
510 #interrupt-cells = <1>;
511 };
512
513 fimd: fimd@f8000000 {
514 compatible = "samsung,exynos4210-fimd";
515 interrupt-parent = <&vic2>;
516 reg = <0xf8000000 0x20000>;
517 interrupt-names = "fifo", "vsync", "lcd_sys";
518 interrupts = <0>, <1>, <2>;
519 clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>;
520 clock-names = "sclk_fimd", "fimd";
521 status = "disabled";
522 };
523
524 g2d: g2d@fa000000 {
525 compatible = "samsung,s5pv210-g2d";
526 reg = <0xfa000000 0x1000>;
527 interrupt-parent = <&vic2>;
528 interrupts = <9>;
529 clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>;
530 clock-names = "sclk_fimg2d", "fimg2d";
531 };
532
533 mdma1: mdma@fa200000 {
534 compatible = "arm,pl330", "arm,primecell";
535 reg = <0xfa200000 0x1000>;
536 interrupt-parent = <&vic0>;
537 interrupts = <18>;
538 clocks = <&clocks CLK_MDMA>;
539 clock-names = "apb_pclk";
540 #dma-cells = <1>;
541 #dma-channels = <8>;
542 #dma-requests = <1>;
543 };
544
545 i2c1: i2c@fab00000 {
546 compatible = "samsung,s3c2440-i2c";
547 reg = <0xfab00000 0x1000>;
548 interrupt-parent = <&vic2>;
549 interrupts = <13>;
550 clocks = <&clocks CLK_I2C1>;
551 clock-names = "i2c";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c1_bus>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 status = "disabled";
557 };
558
559 camera: camera {
560 compatible = "samsung,fimc", "simple-bus";
561 pinctrl-names = "default";
562 pinctrl-0 = <>;
563 clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
564 clock-names = "sclk_cam0", "sclk_cam1";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges;
568
569 clock_cam: clock-controller {
570 #clock-cells = <1>;
571 };
572
573 csis0: csis@fa600000 {
574 compatible = "samsung,s5pv210-csis";
575 reg = <0xfa600000 0x4000>;
576 interrupt-parent = <&vic2>;
577 interrupts = <29>;
578 clocks = <&clocks CLK_CSIS>,
579 <&clocks SCLK_CSIS>;
580 clock-names = "clk_csis",
581 "sclk_csis";
582 bus-width = <4>;
583 status = "disabled";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 };
587
588 fimc0: fimc@fb200000 {
589 compatible = "samsung,s5pv210-fimc";
590 reg = <0xfb200000 0x1000>;
591 interrupts = <5>;
592 interrupt-parent = <&vic2>;
593 clocks = <&clocks CLK_FIMC0>,
594 <&clocks SCLK_FIMC0>;
595 clock-names = "fimc",
596 "sclk_fimc";
597 samsung,pix-limits = <4224 8192 1920 4224>;
598 samsung,mainscaler-ext;
599 samsung,cam-if;
600 };
601
602 fimc1: fimc@fb300000 {
603 compatible = "samsung,s5pv210-fimc";
604 reg = <0xfb300000 0x1000>;
605 interrupt-parent = <&vic2>;
606 interrupts = <6>;
607 clocks = <&clocks CLK_FIMC1>,
608 <&clocks SCLK_FIMC1>;
609 clock-names = "fimc",
610 "sclk_fimc";
611 samsung,pix-limits = <4224 8192 1920 4224>;
612 samsung,mainscaler-ext;
613 samsung,cam-if;
614 };
615
616 fimc2: fimc@fb400000 {
617 compatible = "samsung,s5pv210-fimc";
618 reg = <0xfb400000 0x1000>;
619 interrupt-parent = <&vic2>;
620 interrupts = <7>;
621 clocks = <&clocks CLK_FIMC2>,
622 <&clocks SCLK_FIMC2>;
623 clock-names = "fimc",
624 "sclk_fimc";
625 samsung,pix-limits = <4224 8192 1920 4224>;
626 samsung,mainscaler-ext;
627 samsung,lcd-wb;
628 };
629 };
630 };
631};
632
633#include "s5pv210-pinctrl.dtsi"
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/include/debug/s5pv210.S
index 30b511a580aa..4f1a73e2c1a1 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/s5pv210.S
@@ -1,9 +1,6 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/debug-macro.S 1/*
2 * 2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 * 4 *
8 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
@@ -12,8 +9,9 @@
12 9
13/* pull in the relevant register and map files. */ 10/* pull in the relevant register and map files. */
14 11
15#include <linux/serial_s3c.h> 12#define S3C_ADDR_BASE 0xF6000000
16#include <mach/map.h> 13#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
14#define S5PV210_PA_UART 0xe2900000
17 15
18 /* note, for the boot process to work we have to keep the UART 16 /* note, for the boot process to work we have to keep the UART
19 * virtual address aligned to an 1MiB boundary for the L1 17 * virtual address aligned to an 1MiB boundary for the L1
@@ -22,8 +20,8 @@
22 */ 20 */
23 21
24 .macro addruart, rp, rv, tmp 22 .macro addruart, rp, rv, tmp
25 ldr \rp, = S3C_PA_UART 23 ldr \rp, =S5PV210_PA_UART
26 ldr \rv, = S3C_VA_UART 24 ldr \rv, =S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0 25#if CONFIG_DEBUG_S3C_UART != 0
28 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) 26 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
29 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) 27 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
@@ -33,9 +31,4 @@
33#define fifo_full fifo_full_s5pv210 31#define fifo_full fifo_full_s5pv210
34#define fifo_level fifo_level_s5pv210 32#define fifo_level fifo_level_s5pv210
35 33
36/* include the reset of the code which will do the work, we're only
37 * compiling for a single cpu processor type so the default of s3c2440
38 * will be fine with us.
39 */
40
41#include <debug/samsung.S> 34#include <debug/samsung.S>
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index bcb96be1efee..c4c6d98ada52 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -28,7 +28,6 @@
28#include <asm/suspend.h> 28#include <asm/suspend.h>
29 29
30#include <plat/pm-common.h> 30#include <plat/pm-common.h>
31#include <plat/pll.h>
32#include <plat/regs-srom.h> 31#include <plat/regs-srom.h>
33 32
34#include <mach/map.h> 33#include <mach/map.h>
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index c0763b837745..44fa95df9262 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -49,9 +49,7 @@
49 49
50#include <plat/cpu.h> 50#include <plat/cpu.h>
51#include <plat/devs.h> 51#include <plat/devs.h>
52#include <plat/clock.h>
53#include <plat/cpu-freq.h> 52#include <plat/cpu-freq.h>
54#include <plat/pll.h>
55#include <plat/pwm-core.h> 53#include <plat/pwm-core.h>
56#include <plat/watchdog-reset.h> 54#include <plat/watchdog-reset.h>
57 55
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index bd064c05c473..28b13951de87 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -29,7 +29,6 @@
29 29
30#include <plat/cpu.h> 30#include <plat/cpu.h>
31#include <plat/cpu-freq-core.h> 31#include <plat/cpu-freq-core.h>
32#include <plat/clock.h>
33 32
34#include <mach/s3c2412.h> 33#include <mach/s3c2412.h>
35 34
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index fbf5487ae5d1..c9a99bbad545 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -60,7 +60,6 @@
60#include <plat/cpu.h> 60#include <plat/cpu.h>
61#include <plat/devs.h> 61#include <plat/devs.h>
62#include <plat/gpio-cfg.h> 62#include <plat/gpio-cfg.h>
63#include <plat/pll.h>
64#include <plat/pm.h> 63#include <plat/pm.h>
65#include <plat/samsung-time.h> 64#include <plat/samsung-time.h>
66 65
@@ -73,6 +72,10 @@
73 72
74#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END)) 73#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
75 74
75#define S3C24XX_PLL_MDIV_SHIFT (12)
76#define S3C24XX_PLL_PDIV_SHIFT (4)
77#define S3C24XX_PLL_SDIV_SHIFT (0)
78
76static struct map_desc h1940_iodesc[] __initdata = { 79static struct map_desc h1940_iodesc[] __initdata = {
77 [0] = { 80 [0] = {
78 .virtual = (unsigned long)H1940_LATCH, 81 .virtual = (unsigned long)H1940_LATCH,
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index e81ea82c55f9..e647b47244a9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -48,7 +48,6 @@
48#include <linux/mtd/partitions.h> 48#include <linux/mtd/partitions.h>
49 49
50#include <plat/gpio-cfg.h> 50#include <plat/gpio-cfg.h>
51#include <plat/clock.h>
52#include <plat/devs.h> 51#include <plat/devs.h>
53#include <plat/cpu.h> 52#include <plat/cpu.h>
54#include <plat/pm.h> 53#include <plat/pm.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index fb3b80e44595..10726bf84920 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -43,7 +43,6 @@
43#include <mach/gpio-samsung.h> 43#include <mach/gpio-samsung.h>
44#include <mach/fb.h> 44#include <mach/fb.h>
45 45
46#include <plat/clock.h>
47#include <plat/devs.h> 46#include <plat/devs.h>
48#include <plat/cpu.h> 47#include <plat/cpu.h>
49#include <plat/samsung-time.h> 48#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index fa6f30d23601..24189e8e8560 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -44,7 +44,6 @@
44#include <linux/platform_data/i2c-s3c2410.h> 44#include <linux/platform_data/i2c-s3c2410.h>
45 45
46#include <plat/gpio-cfg.h> 46#include <plat/gpio-cfg.h>
47#include <plat/clock.h>
48#include <plat/devs.h> 47#include <plat/devs.h>
49#include <plat/cpu.h> 48#include <plat/cpu.h>
50#include <linux/platform_data/mtd-nand-s3c2410.h> 49#include <linux/platform_data/mtd-nand-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index ef5d5ea33182..0ed77614dcfe 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,7 +38,6 @@
38#include <mach/fb.h> 38#include <mach/fb.h>
39#include <linux/platform_data/i2c-s3c2410.h> 39#include <linux/platform_data/i2c-s3c2410.h>
40 40
41#include <plat/clock.h>
42#include <plat/devs.h> 41#include <plat/devs.h>
43#include <plat/cpu.h> 42#include <plat/cpu.h>
44#include <plat/samsung-time.h> 43#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 9104c2be36c9..9d4f64750698 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -42,7 +42,6 @@
42#include <linux/platform_data/i2c-s3c2410.h> 42#include <linux/platform_data/i2c-s3c2410.h>
43#include <linux/platform_data/mtd-nand-s3c2410.h> 43#include <linux/platform_data/mtd-nand-s3c2410.h>
44 44
45#include <plat/clock.h>
46#include <plat/devs.h> 45#include <plat/devs.h>
47#include <plat/cpu.h> 46#include <plat/cpu.h>
48#include <plat/samsung-time.h> 47#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 7eab88829883..5ffe828cd659 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -41,8 +41,6 @@
41 41
42#include <plat/cpu.h> 42#include <plat/cpu.h>
43#include <plat/devs.h> 43#include <plat/devs.h>
44#include <plat/clock.h>
45#include <plat/pll.h>
46#include <plat/pm.h> 44#include <plat/pm.h>
47#include <plat/watchdog-reset.h> 45#include <plat/watchdog-reset.h>
48 46
@@ -83,10 +81,6 @@ void __init s3c2410_map_io(void)
83 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); 81 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
84} 82}
85 83
86void __init_or_cpufreq s3c2410_setup_clocks(void)
87{
88}
89
90struct bus_type s3c2410_subsys = { 84struct bus_type s3c2410_subsys = {
91 .name = "s3c2410-core", 85 .name = "s3c2410-core",
92 .dev_name = "s3c2410-core", 86 .dev_name = "s3c2410-core",
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index d49f52fbc842..569f3f5a6c71 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -37,12 +37,10 @@
37#include <mach/regs-clock.h> 37#include <mach/regs-clock.h>
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
39 39
40#include <plat/clock.h>
41#include <plat/cpu.h> 40#include <plat/cpu.h>
42#include <plat/cpu-freq.h> 41#include <plat/cpu-freq.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/nand-core.h> 43#include <plat/nand-core.h>
45#include <plat/pll.h>
46#include <plat/pm.h> 44#include <plat/pm.h>
47#include <plat/regs-spi.h> 45#include <plat/regs-spi.h>
48 46
@@ -171,10 +169,6 @@ void __init s3c2412_map_io(void)
171 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); 169 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
172} 170}
173 171
174void __init_or_cpufreq s3c2412_setup_clocks(void)
175{
176}
177
178/* need to register the subsystem before we actually register the device, and 172/* need to register the subsystem before we actually register the device, and
179 * we also need to ensure that it has been initialised before any of the 173 * we also need to ensure that it has been initialised before any of the
180 * drivers even try to use it (even if not on an s3c2412 based system) 174 * drivers even try to use it (even if not on an s3c2412 based system)
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index fb9da2b603a2..7b043349f1c8 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -43,7 +43,6 @@
43 43
44#include <mach/regs-clock.h> 44#include <mach/regs-clock.h>
45 45
46#include <plat/clock.h>
47#include <plat/cpu.h> 46#include <plat/cpu.h>
48#include <plat/pm.h> 47#include <plat/pm.h>
49 48
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 4a64bcc9eb51..d1c3e65785a1 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -38,11 +38,9 @@
38#include <mach/regs-clock.h> 38#include <mach/regs-clock.h>
39#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
40 40
41#include <plat/clock.h>
42#include <plat/devs.h> 41#include <plat/devs.h>
43#include <plat/cpu.h> 42#include <plat/cpu.h>
44#include <plat/pm.h> 43#include <plat/pm.h>
45#include <plat/pll.h>
46#include <plat/nand-core.h> 44#include <plat/nand-core.h>
47#include <plat/watchdog-reset.h> 45#include <plat/watchdog-reset.h>
48 46
@@ -78,10 +76,6 @@ void __init s3c244x_map_io(void)
78 s3c2410_device_dclk.name = "s3c2440-dclk"; 76 s3c2410_device_dclk.name = "s3c2440-dclk";
79} 77}
80 78
81void __init_or_cpufreq s3c244x_setup_clocks(void)
82{
83}
84
85/* Since the S3C2442 and S3C2440 share items, put both subsystems here */ 79/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
86 80
87struct bus_type s3c2440_subsys = { 81struct bus_type s3c2440_subsys = {
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 55eb6a69655b..60576dfbea8d 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -45,7 +45,6 @@
45#include <linux/platform_data/i2c-s3c2410.h> 45#include <linux/platform_data/i2c-s3c2410.h>
46#include <plat/fb.h> 46#include <plat/fb.h>
47 47
48#include <plat/clock.h>
49#include <plat/devs.h> 48#include <plat/devs.h>
50#include <plat/cpu.h> 49#include <plat/cpu.h>
51#include <mach/regs-gpio.h> 50#include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 4b0199fff9f5..fe116334afda 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -58,7 +58,6 @@
58#include <linux/platform_data/spi-s3c64xx.h> 58#include <linux/platform_data/spi-s3c64xx.h>
59 59
60#include <plat/keypad.h> 60#include <plat/keypad.h>
61#include <plat/clock.h>
62#include <plat/devs.h> 61#include <plat/devs.h>
63#include <plat/cpu.h> 62#include <plat/cpu.h>
64#include <plat/adc.h> 63#include <plat/adc.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 72cee08c8bf5..19e8feb908fd 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -39,7 +39,6 @@
39#include <plat/fb.h> 39#include <plat/fb.h>
40#include <linux/platform_data/mtd-nand-s3c2410.h> 40#include <linux/platform_data/mtd-nand-s3c2410.h>
41 41
42#include <plat/clock.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/cpu.h> 43#include <plat/cpu.h>
45#include <plat/samsung-time.h> 44#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 67f06a9ae656..4bae7dc49eea 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -40,7 +40,6 @@
40#include <linux/platform_data/i2c-s3c2410.h> 40#include <linux/platform_data/i2c-s3c2410.h>
41#include <plat/fb.h> 41#include <plat/fb.h>
42 42
43#include <plat/clock.h>
44#include <plat/devs.h> 43#include <plat/devs.h>
45#include <plat/cpu.h> 44#include <plat/cpu.h>
46#include <plat/samsung-time.h> 45#include <plat/samsung-time.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 78dd6f73c072..b3d13537a7f0 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -28,7 +28,6 @@
28#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
29#include <mach/gpio-samsung.h> 29#include <mach/gpio-samsung.h>
30 30
31#include <plat/clock.h>
32#include <plat/cpu.h> 31#include <plat/cpu.h>
33#include <plat/devs.h> 32#include <plat/devs.h>
34#include <linux/platform_data/i2c-s3c2410.h> 33#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index c85d1cbe769f..910749768340 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -30,7 +30,6 @@
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/map.h> 31#include <mach/map.h>
32 32
33#include <plat/clock.h>
34#include <plat/devs.h> 33#include <plat/devs.h>
35#include <plat/cpu.h> 34#include <plat/cpu.h>
36#include <linux/platform_data/i2c-s3c2410.h> 35#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index c6a8b2ab0240..1dc86d76b530 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -63,7 +63,6 @@
63#include <plat/fb.h> 63#include <plat/fb.h>
64#include <plat/gpio-cfg.h> 64#include <plat/gpio-cfg.h>
65 65
66#include <plat/clock.h>
67#include <plat/devs.h> 66#include <plat/devs.h>
68#include <plat/cpu.h> 67#include <plat/cpu.h>
69#include <plat/adc.h> 68#include <plat/adc.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 8c42807bf579..1ce48c54cd9c 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -39,7 +39,6 @@
39 39
40#include <plat/cpu.h> 40#include <plat/cpu.h>
41#include <plat/devs.h> 41#include <plat/devs.h>
42#include <plat/clock.h>
43#include <plat/sdhci.h> 42#include <plat/sdhci.h>
44#include <plat/iic-core.h> 43#include <plat/iic-core.h>
45#include <plat/onenand-core.h> 44#include <plat/onenand-core.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 5be3f09bac92..b2a7930548d9 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -40,7 +40,6 @@
40 40
41#include <plat/cpu.h> 41#include <plat/cpu.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/clock.h>
44#include <plat/sdhci.h> 43#include <plat/sdhci.h>
45#include <plat/ata-core.h> 44#include <plat/ata-core.h>
46#include <plat/adc-core.h> 45#include <plat/adc-core.h>
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index f60f2862856d..330bfc8fcd52 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -7,193 +7,28 @@
7 7
8# Configuration options for the S5PV210/S5PC110 8# Configuration options for the S5PV210/S5PC110
9 9
10config ARCH_S5PV210
11 bool "Samsung S5PV210/S5PC110" if ARCH_MULTI_V7
12 select ARCH_HAS_HOLES_MEMORYMODEL
13 select ARCH_REQUIRE_GPIOLIB
14 select ARM_VIC
15 select CLKSRC_SAMSUNG_PWM
16 select COMMON_CLK_SAMSUNG
17 select HAVE_S3C2410_I2C if I2C
18 select HAVE_S3C2410_WATCHDOG if WATCHDOG
19 select HAVE_S3C_RTC if RTC_CLASS
20 select PINCTRL
21 select PINCTRL_EXYNOS
22 help
23 Samsung S5PV210/S5PC110 series based systems
24
10if ARCH_S5PV210 25if ARCH_S5PV210
11 26
12config CPU_S5PV210 27config CPU_S5PV210
13 bool 28 def_bool y
14 select ARM_AMBA 29 select ARM_AMBA
15 select PL330_DMA if DMADEVICES 30 select PL330_DMA if DMADEVICES
16 select S5P_EXT_INT
17 select S5P_PM if PM
18 select S5P_SLEEP if PM
19 help 31 help
20 Enable S5PV210 CPU support 32 Enable S5PV210 CPU support
21 33
22config S5PV210_SETUP_I2C1
23 bool
24 help
25 Common setup code for i2c bus 1.
26
27config S5PV210_SETUP_I2C2
28 bool
29 help
30 Common setup code for i2c bus 2.
31
32config S5PV210_SETUP_IDE
33 bool
34 help
35 Common setup code for S5PV210 IDE GPIO configurations
36
37config S5PV210_SETUP_FB_24BPP
38 bool
39 help
40 Common setup code for S5PV210 with an 24bpp RGB display helper.
41
42config S5PV210_SETUP_KEYPAD
43 bool
44 help
45 Common setup code for keypad.
46
47config S5PV210_SETUP_SDHCI
48 bool
49 select S5PV210_SETUP_SDHCI_GPIO
50 help
51 Internal helper functions for S5PV210 based SDHCI systems
52
53config S5PV210_SETUP_SDHCI_GPIO
54 bool
55 help
56 Common setup code for SDHCI gpio.
57
58config S5PV210_SETUP_FIMC
59 bool
60 help
61 Common setup code for the camera interfaces.
62
63config S5PV210_SETUP_SPI
64 bool
65 help
66 Common setup code for SPI GPIO configurations.
67
68config S5PV210_SETUP_USB_PHY
69 bool
70 help
71 Common setup code for USB PHY controller
72
73menu "S5PC110 Machines"
74
75config MACH_AQUILA
76 bool "Aquila"
77 select CPU_S5PV210
78 select S3C_DEV_FB
79 select S3C_DEV_HSMMC
80 select S3C_DEV_HSMMC1
81 select S3C_DEV_HSMMC2
82 select S5PV210_SETUP_FB_24BPP
83 select S5PV210_SETUP_SDHCI
84 select S5PV210_SETUP_USB_PHY
85 select S5P_DEV_FIMC0
86 select S5P_DEV_FIMC1
87 select S5P_DEV_FIMC2
88 select S5P_DEV_ONENAND
89 help
90 Machine support for the Samsung Aquila target based on S5PC110 SoC
91
92config MACH_GONI
93 bool "GONI"
94 select CPU_S5PV210
95 select S3C_DEV_FB
96 select S3C_DEV_HSMMC
97 select S3C_DEV_HSMMC1
98 select S3C_DEV_HSMMC2
99 select S3C_DEV_I2C1
100 select S3C_DEV_I2C2
101 select S3C_DEV_USB_HSOTG
102 select S5PV210_SETUP_FB_24BPP
103 select S5PV210_SETUP_FIMC
104 select S5PV210_SETUP_I2C1
105 select S5PV210_SETUP_I2C2
106 select S5PV210_SETUP_KEYPAD
107 select S5PV210_SETUP_SDHCI
108 select S5PV210_SETUP_USB_PHY
109 select S5P_DEV_FIMC0
110 select S5P_DEV_FIMC1
111 select S5P_DEV_FIMC2
112 select S5P_DEV_MFC
113 select S5P_DEV_ONENAND
114 select S5P_DEV_TV
115 select S5P_GPIO_INT
116 select SAMSUNG_DEV_KEYPAD
117 help
118 Machine support for Samsung GONI board
119 S5PC110(MCP) is one of package option of S5PV210
120
121config MACH_SMDKC110
122 bool "SMDKC110"
123 select CPU_S5PV210
124 select S3C_DEV_I2C1
125 select S3C_DEV_I2C2
126 select S3C_DEV_RTC
127 select S3C_DEV_WDT
128 select S5PV210_SETUP_I2C1
129 select S5PV210_SETUP_I2C2
130 select S5PV210_SETUP_IDE
131 select S5P_DEV_FIMC0
132 select S5P_DEV_FIMC1
133 select S5P_DEV_FIMC2
134 select S5P_DEV_MFC
135 select SAMSUNG_DEV_IDE
136 help
137 Machine support for Samsung SMDKC110
138 S5PC110(MCP) is one of package option of S5PV210
139
140endmenu
141
142menu "S5PV210 Machines"
143
144config MACH_SMDKV210
145 bool "SMDKV210"
146 select CPU_S5PV210
147 select S3C_DEV_FB
148 select S3C_DEV_HSMMC
149 select S3C_DEV_HSMMC1
150 select S3C_DEV_HSMMC2
151 select S3C_DEV_HSMMC3
152 select S3C_DEV_I2C1
153 select S3C_DEV_I2C2
154 select S3C_DEV_RTC
155 select S3C_DEV_USB_HSOTG
156 select S3C_DEV_WDT
157 select S5PV210_SETUP_FB_24BPP
158 select S5PV210_SETUP_I2C1
159 select S5PV210_SETUP_I2C2
160 select S5PV210_SETUP_IDE
161 select S5PV210_SETUP_KEYPAD
162 select S5PV210_SETUP_SDHCI
163 select S5PV210_SETUP_USB_PHY
164 select S5P_DEV_FIMC0
165 select S5P_DEV_FIMC1
166 select S5P_DEV_FIMC2
167 select S5P_DEV_JPEG
168 select S5P_DEV_MFC
169 select SAMSUNG_DEV_ADC
170 select SAMSUNG_DEV_BACKLIGHT
171 select SAMSUNG_DEV_IDE
172 select SAMSUNG_DEV_KEYPAD
173 select SAMSUNG_DEV_PWM
174 select SAMSUNG_DEV_TS
175 help
176 Machine support for Samsung SMDKV210
177
178config MACH_TORBRECK
179 bool "Torbreck"
180 select ARCH_SPARSEMEM_ENABLE
181 select CPU_S5PV210
182 select S3C_DEV_HSMMC
183 select S3C_DEV_HSMMC1
184 select S3C_DEV_HSMMC2
185 select S3C_DEV_HSMMC3
186 select S3C_DEV_I2C1
187 select S3C_DEV_I2C2
188 select S3C_DEV_RTC
189 select S3C_DEV_WDT
190 select S5PV210_SETUP_I2C1
191 select S5PV210_SETUP_I2C2
192 select S5PV210_SETUP_SDHCI
193 select SAMSUNG_DEV_IDE
194 help
195 Machine support for aESOP Torbreck
196
197endmenu
198
199endif 34endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 1c4e41998a10..7dc2d0e25a83 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -5,6 +5,8 @@
5# 5#
6# Licensed under GPLv2 6# Licensed under GPLv2
7 7
8ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
9
8obj-y := 10obj-y :=
9obj-m := 11obj-m :=
10obj-n := 12obj-n :=
@@ -12,31 +14,8 @@ obj- :=
12 14
13# Core 15# Core
14 16
15obj-y += common.o clock.o 17obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
16
17obj-$(CONFIG_PM) += pm.o
18
19obj-y += dma.o
20 18
21# machine support 19# machine support
22 20
23obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o 21obj-y += s5pv210.o
24obj-$(CONFIG_MACH_GONI) += mach-goni.o
25obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
26obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
27obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
28
29# device support
30
31obj-y += dev-audio.o
32
33obj-y += setup-i2c0.o
34obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
35obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
36obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
37obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
38obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
39obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
40obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
41obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o
42obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5pv210/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
deleted file mode 100644
index ca463724a3df..000000000000
--- a/arch/arm/mach-s5pv210/clock.c
+++ /dev/null
@@ -1,1365 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/map.h>
24
25#include <plat/cpu-freq.h>
26#include <mach/regs-clock.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/pll.h>
30#include <plat/s5p-clock.h>
31#include <plat/clock-clksrc.h>
32
33#include "common.h"
34
35static unsigned long xtal;
36
37static struct clksrc_clk clk_mout_apll = {
38 .clk = {
39 .name = "mout_apll",
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static struct clksrc_clk clk_mout_epll = {
46 .clk = {
47 .name = "mout_epll",
48 },
49 .sources = &clk_src_epll,
50 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
51};
52
53static struct clksrc_clk clk_mout_mpll = {
54 .clk = {
55 .name = "mout_mpll",
56 },
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59};
60
61static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
64};
65
66static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
69};
70
71static struct clksrc_clk clk_armclk = {
72 .clk = {
73 .name = "armclk",
74 },
75 .sources = &clkset_armclk,
76 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
77 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
78};
79
80static struct clksrc_clk clk_hclk_msys = {
81 .clk = {
82 .name = "hclk_msys",
83 .parent = &clk_armclk.clk,
84 },
85 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
86};
87
88static struct clksrc_clk clk_pclk_msys = {
89 .clk = {
90 .name = "pclk_msys",
91 .parent = &clk_hclk_msys.clk,
92 },
93 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
94};
95
96static struct clksrc_clk clk_sclk_a2m = {
97 .clk = {
98 .name = "sclk_a2m",
99 .parent = &clk_mout_apll.clk,
100 },
101 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
102};
103
104static struct clk *clkset_hclk_sys_list[] = {
105 [0] = &clk_mout_mpll.clk,
106 [1] = &clk_sclk_a2m.clk,
107};
108
109static struct clksrc_sources clkset_hclk_sys = {
110 .sources = clkset_hclk_sys_list,
111 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
112};
113
114static struct clksrc_clk clk_hclk_dsys = {
115 .clk = {
116 .name = "hclk_dsys",
117 },
118 .sources = &clkset_hclk_sys,
119 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
120 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
121};
122
123static struct clksrc_clk clk_pclk_dsys = {
124 .clk = {
125 .name = "pclk_dsys",
126 .parent = &clk_hclk_dsys.clk,
127 },
128 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
129};
130
131static struct clksrc_clk clk_hclk_psys = {
132 .clk = {
133 .name = "hclk_psys",
134 },
135 .sources = &clkset_hclk_sys,
136 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
137 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
138};
139
140static struct clksrc_clk clk_pclk_psys = {
141 .clk = {
142 .name = "pclk_psys",
143 .parent = &clk_hclk_psys.clk,
144 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
146};
147
148static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
149{
150 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
151}
152
153static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
154{
155 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
156}
157
158static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
159{
160 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
161}
162
163static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
164{
165 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
166}
167
168static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
169{
170 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
171}
172
173static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
174{
175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
176}
177
178static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
179{
180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
181}
182
183static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
184{
185 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
186}
187
188static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m",
190 .rate = 27000000,
191};
192
193static struct clk clk_sclk_hdmiphy = {
194 .name = "sclk_hdmiphy",
195};
196
197static struct clk clk_sclk_usbphy0 = {
198 .name = "sclk_usbphy0",
199};
200
201static struct clk clk_sclk_usbphy1 = {
202 .name = "sclk_usbphy1",
203};
204
205static struct clk clk_pcmcdclk0 = {
206 .name = "pcmcdclk",
207};
208
209static struct clk clk_pcmcdclk1 = {
210 .name = "pcmcdclk",
211};
212
213static struct clk clk_pcmcdclk2 = {
214 .name = "pcmcdclk",
215};
216
217static struct clk *clkset_vpllsrc_list[] = {
218 [0] = &clk_fin_vpll,
219 [1] = &clk_sclk_hdmi27m,
220};
221
222static struct clksrc_sources clkset_vpllsrc = {
223 .sources = clkset_vpllsrc_list,
224 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
225};
226
227static struct clksrc_clk clk_vpllsrc = {
228 .clk = {
229 .name = "vpll_src",
230 .enable = s5pv210_clk_mask0_ctrl,
231 .ctrlbit = (1 << 7),
232 },
233 .sources = &clkset_vpllsrc,
234 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
235};
236
237static struct clk *clkset_sclk_vpll_list[] = {
238 [0] = &clk_vpllsrc.clk,
239 [1] = &clk_fout_vpll,
240};
241
242static struct clksrc_sources clkset_sclk_vpll = {
243 .sources = clkset_sclk_vpll_list,
244 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
245};
246
247static struct clksrc_clk clk_sclk_vpll = {
248 .clk = {
249 .name = "sclk_vpll",
250 },
251 .sources = &clkset_sclk_vpll,
252 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
253};
254
255static struct clk *clkset_moutdmc0src_list[] = {
256 [0] = &clk_sclk_a2m.clk,
257 [1] = &clk_mout_mpll.clk,
258 [2] = NULL,
259 [3] = NULL,
260};
261
262static struct clksrc_sources clkset_moutdmc0src = {
263 .sources = clkset_moutdmc0src_list,
264 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
265};
266
267static struct clksrc_clk clk_mout_dmc0 = {
268 .clk = {
269 .name = "mout_dmc0",
270 },
271 .sources = &clkset_moutdmc0src,
272 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
273};
274
275static struct clksrc_clk clk_sclk_dmc0 = {
276 .clk = {
277 .name = "sclk_dmc0",
278 .parent = &clk_mout_dmc0.clk,
279 },
280 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
281};
282
283static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
284{
285 return clk_get_rate(clk->parent) / 2;
286}
287
288static struct clk_ops clk_hclk_imem_ops = {
289 .get_rate = s5pv210_clk_imem_get_rate,
290};
291
292static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
293{
294 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
295}
296
297static struct clk_ops clk_fout_apll_ops = {
298 .get_rate = s5pv210_clk_fout_apll_get_rate,
299};
300
301static struct clk init_clocks_off[] = {
302 {
303 .name = "rot",
304 .parent = &clk_hclk_dsys.clk,
305 .enable = s5pv210_clk_ip0_ctrl,
306 .ctrlbit = (1<<29),
307 }, {
308 .name = "fimc",
309 .devname = "s5pv210-fimc.0",
310 .parent = &clk_hclk_dsys.clk,
311 .enable = s5pv210_clk_ip0_ctrl,
312 .ctrlbit = (1 << 24),
313 }, {
314 .name = "fimc",
315 .devname = "s5pv210-fimc.1",
316 .parent = &clk_hclk_dsys.clk,
317 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 25),
319 }, {
320 .name = "fimc",
321 .devname = "s5pv210-fimc.2",
322 .parent = &clk_hclk_dsys.clk,
323 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 26),
325 }, {
326 .name = "jpeg",
327 .parent = &clk_hclk_dsys.clk,
328 .enable = s5pv210_clk_ip0_ctrl,
329 .ctrlbit = (1 << 28),
330 }, {
331 .name = "mfc",
332 .devname = "s5p-mfc",
333 .parent = &clk_pclk_psys.clk,
334 .enable = s5pv210_clk_ip0_ctrl,
335 .ctrlbit = (1 << 16),
336 }, {
337 .name = "dac",
338 .devname = "s5p-sdo",
339 .parent = &clk_hclk_dsys.clk,
340 .enable = s5pv210_clk_ip1_ctrl,
341 .ctrlbit = (1 << 10),
342 }, {
343 .name = "mixer",
344 .devname = "s5p-mixer",
345 .parent = &clk_hclk_dsys.clk,
346 .enable = s5pv210_clk_ip1_ctrl,
347 .ctrlbit = (1 << 9),
348 }, {
349 .name = "vp",
350 .devname = "s5p-mixer",
351 .parent = &clk_hclk_dsys.clk,
352 .enable = s5pv210_clk_ip1_ctrl,
353 .ctrlbit = (1 << 8),
354 }, {
355 .name = "hdmi",
356 .devname = "s5pv210-hdmi",
357 .parent = &clk_hclk_dsys.clk,
358 .enable = s5pv210_clk_ip1_ctrl,
359 .ctrlbit = (1 << 11),
360 }, {
361 .name = "hdmiphy",
362 .devname = "s5pv210-hdmi",
363 .enable = s5pv210_clk_hdmiphy_ctrl,
364 .ctrlbit = (1 << 0),
365 }, {
366 .name = "dacphy",
367 .devname = "s5p-sdo",
368 .enable = exynos4_clk_dac_ctrl,
369 .ctrlbit = (1 << 0),
370 }, {
371 .name = "otg",
372 .parent = &clk_hclk_psys.clk,
373 .enable = s5pv210_clk_ip1_ctrl,
374 .ctrlbit = (1<<16),
375 }, {
376 .name = "usb-host",
377 .parent = &clk_hclk_psys.clk,
378 .enable = s5pv210_clk_ip1_ctrl,
379 .ctrlbit = (1<<17),
380 }, {
381 .name = "lcd",
382 .parent = &clk_hclk_dsys.clk,
383 .enable = s5pv210_clk_ip1_ctrl,
384 .ctrlbit = (1<<0),
385 }, {
386 .name = "cfcon",
387 .parent = &clk_hclk_psys.clk,
388 .enable = s5pv210_clk_ip1_ctrl,
389 .ctrlbit = (1<<25),
390 }, {
391 .name = "systimer",
392 .parent = &clk_pclk_psys.clk,
393 .enable = s5pv210_clk_ip3_ctrl,
394 .ctrlbit = (1<<16),
395 }, {
396 .name = "watchdog",
397 .parent = &clk_pclk_psys.clk,
398 .enable = s5pv210_clk_ip3_ctrl,
399 .ctrlbit = (1<<22),
400 }, {
401 .name = "rtc",
402 .parent = &clk_pclk_psys.clk,
403 .enable = s5pv210_clk_ip3_ctrl,
404 .ctrlbit = (1<<15),
405 }, {
406 .name = "i2c",
407 .devname = "s3c2440-i2c.0",
408 .parent = &clk_pclk_psys.clk,
409 .enable = s5pv210_clk_ip3_ctrl,
410 .ctrlbit = (1<<7),
411 }, {
412 .name = "i2c",
413 .devname = "s3c2440-i2c.1",
414 .parent = &clk_pclk_psys.clk,
415 .enable = s5pv210_clk_ip3_ctrl,
416 .ctrlbit = (1 << 10),
417 }, {
418 .name = "i2c",
419 .devname = "s3c2440-i2c.2",
420 .parent = &clk_pclk_psys.clk,
421 .enable = s5pv210_clk_ip3_ctrl,
422 .ctrlbit = (1<<9),
423 }, {
424 .name = "i2c",
425 .devname = "s3c2440-hdmiphy-i2c",
426 .parent = &clk_pclk_psys.clk,
427 .enable = s5pv210_clk_ip3_ctrl,
428 .ctrlbit = (1 << 11),
429 }, {
430 .name = "spi",
431 .devname = "s5pv210-spi.0",
432 .parent = &clk_pclk_psys.clk,
433 .enable = s5pv210_clk_ip3_ctrl,
434 .ctrlbit = (1<<12),
435 }, {
436 .name = "spi",
437 .devname = "s5pv210-spi.1",
438 .parent = &clk_pclk_psys.clk,
439 .enable = s5pv210_clk_ip3_ctrl,
440 .ctrlbit = (1<<13),
441 }, {
442 .name = "spi",
443 .devname = "s5pv210-spi.2",
444 .parent = &clk_pclk_psys.clk,
445 .enable = s5pv210_clk_ip3_ctrl,
446 .ctrlbit = (1<<14),
447 }, {
448 .name = "timers",
449 .parent = &clk_pclk_psys.clk,
450 .enable = s5pv210_clk_ip3_ctrl,
451 .ctrlbit = (1<<23),
452 }, {
453 .name = "adc",
454 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<24),
457 }, {
458 .name = "keypad",
459 .parent = &clk_pclk_psys.clk,
460 .enable = s5pv210_clk_ip3_ctrl,
461 .ctrlbit = (1<<21),
462 }, {
463 .name = "iis",
464 .devname = "samsung-i2s.0",
465 .parent = &clk_p,
466 .enable = s5pv210_clk_ip3_ctrl,
467 .ctrlbit = (1<<4),
468 }, {
469 .name = "iis",
470 .devname = "samsung-i2s.1",
471 .parent = &clk_p,
472 .enable = s5pv210_clk_ip3_ctrl,
473 .ctrlbit = (1 << 5),
474 }, {
475 .name = "iis",
476 .devname = "samsung-i2s.2",
477 .parent = &clk_p,
478 .enable = s5pv210_clk_ip3_ctrl,
479 .ctrlbit = (1 << 6),
480 }, {
481 .name = "spdif",
482 .parent = &clk_p,
483 .enable = s5pv210_clk_ip3_ctrl,
484 .ctrlbit = (1 << 0),
485 },
486};
487
488static struct clk init_clocks[] = {
489 {
490 .name = "hclk_imem",
491 .parent = &clk_hclk_msys.clk,
492 .ctrlbit = (1 << 5),
493 .enable = s5pv210_clk_ip0_ctrl,
494 .ops = &clk_hclk_imem_ops,
495 }, {
496 .name = "uart",
497 .devname = "s5pv210-uart.0",
498 .parent = &clk_pclk_psys.clk,
499 .enable = s5pv210_clk_ip3_ctrl,
500 .ctrlbit = (1 << 17),
501 }, {
502 .name = "uart",
503 .devname = "s5pv210-uart.1",
504 .parent = &clk_pclk_psys.clk,
505 .enable = s5pv210_clk_ip3_ctrl,
506 .ctrlbit = (1 << 18),
507 }, {
508 .name = "uart",
509 .devname = "s5pv210-uart.2",
510 .parent = &clk_pclk_psys.clk,
511 .enable = s5pv210_clk_ip3_ctrl,
512 .ctrlbit = (1 << 19),
513 }, {
514 .name = "uart",
515 .devname = "s5pv210-uart.3",
516 .parent = &clk_pclk_psys.clk,
517 .enable = s5pv210_clk_ip3_ctrl,
518 .ctrlbit = (1 << 20),
519 }, {
520 .name = "sromc",
521 .parent = &clk_hclk_psys.clk,
522 .enable = s5pv210_clk_ip1_ctrl,
523 .ctrlbit = (1 << 26),
524 },
525};
526
527static struct clk clk_hsmmc0 = {
528 .name = "hsmmc",
529 .devname = "s3c-sdhci.0",
530 .parent = &clk_hclk_psys.clk,
531 .enable = s5pv210_clk_ip2_ctrl,
532 .ctrlbit = (1<<16),
533};
534
535static struct clk clk_hsmmc1 = {
536 .name = "hsmmc",
537 .devname = "s3c-sdhci.1",
538 .parent = &clk_hclk_psys.clk,
539 .enable = s5pv210_clk_ip2_ctrl,
540 .ctrlbit = (1<<17),
541};
542
543static struct clk clk_hsmmc2 = {
544 .name = "hsmmc",
545 .devname = "s3c-sdhci.2",
546 .parent = &clk_hclk_psys.clk,
547 .enable = s5pv210_clk_ip2_ctrl,
548 .ctrlbit = (1<<18),
549};
550
551static struct clk clk_hsmmc3 = {
552 .name = "hsmmc",
553 .devname = "s3c-sdhci.3",
554 .parent = &clk_hclk_psys.clk,
555 .enable = s5pv210_clk_ip2_ctrl,
556 .ctrlbit = (1<<19),
557};
558
559static struct clk clk_pdma0 = {
560 .name = "pdma0",
561 .parent = &clk_hclk_psys.clk,
562 .enable = s5pv210_clk_ip0_ctrl,
563 .ctrlbit = (1 << 3),
564};
565
566static struct clk clk_pdma1 = {
567 .name = "pdma1",
568 .parent = &clk_hclk_psys.clk,
569 .enable = s5pv210_clk_ip0_ctrl,
570 .ctrlbit = (1 << 4),
571};
572
573static struct clk *clkset_uart_list[] = {
574 [6] = &clk_mout_mpll.clk,
575 [7] = &clk_mout_epll.clk,
576};
577
578static struct clksrc_sources clkset_uart = {
579 .sources = clkset_uart_list,
580 .nr_sources = ARRAY_SIZE(clkset_uart_list),
581};
582
583static struct clk *clkset_group1_list[] = {
584 [0] = &clk_sclk_a2m.clk,
585 [1] = &clk_mout_mpll.clk,
586 [2] = &clk_mout_epll.clk,
587 [3] = &clk_sclk_vpll.clk,
588};
589
590static struct clksrc_sources clkset_group1 = {
591 .sources = clkset_group1_list,
592 .nr_sources = ARRAY_SIZE(clkset_group1_list),
593};
594
595static struct clk *clkset_sclk_onenand_list[] = {
596 [0] = &clk_hclk_psys.clk,
597 [1] = &clk_hclk_dsys.clk,
598};
599
600static struct clksrc_sources clkset_sclk_onenand = {
601 .sources = clkset_sclk_onenand_list,
602 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
603};
604
605static struct clk *clkset_sclk_dac_list[] = {
606 [0] = &clk_sclk_vpll.clk,
607 [1] = &clk_sclk_hdmiphy,
608};
609
610static struct clksrc_sources clkset_sclk_dac = {
611 .sources = clkset_sclk_dac_list,
612 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
613};
614
615static struct clksrc_clk clk_sclk_dac = {
616 .clk = {
617 .name = "sclk_dac",
618 .enable = s5pv210_clk_mask0_ctrl,
619 .ctrlbit = (1 << 2),
620 },
621 .sources = &clkset_sclk_dac,
622 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
623};
624
625static struct clksrc_clk clk_sclk_pixel = {
626 .clk = {
627 .name = "sclk_pixel",
628 .parent = &clk_sclk_vpll.clk,
629 },
630 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
631};
632
633static struct clk *clkset_sclk_hdmi_list[] = {
634 [0] = &clk_sclk_pixel.clk,
635 [1] = &clk_sclk_hdmiphy,
636};
637
638static struct clksrc_sources clkset_sclk_hdmi = {
639 .sources = clkset_sclk_hdmi_list,
640 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
641};
642
643static struct clksrc_clk clk_sclk_hdmi = {
644 .clk = {
645 .name = "sclk_hdmi",
646 .enable = s5pv210_clk_mask0_ctrl,
647 .ctrlbit = (1 << 0),
648 },
649 .sources = &clkset_sclk_hdmi,
650 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
651};
652
653static struct clk *clkset_sclk_mixer_list[] = {
654 [0] = &clk_sclk_dac.clk,
655 [1] = &clk_sclk_hdmi.clk,
656};
657
658static struct clksrc_sources clkset_sclk_mixer = {
659 .sources = clkset_sclk_mixer_list,
660 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
661};
662
663static struct clksrc_clk clk_sclk_mixer = {
664 .clk = {
665 .name = "sclk_mixer",
666 .enable = s5pv210_clk_mask0_ctrl,
667 .ctrlbit = (1 << 1),
668 },
669 .sources = &clkset_sclk_mixer,
670 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
671};
672
673static struct clksrc_clk *sclk_tv[] = {
674 &clk_sclk_dac,
675 &clk_sclk_pixel,
676 &clk_sclk_hdmi,
677 &clk_sclk_mixer,
678};
679
680static struct clk *clkset_sclk_audio0_list[] = {
681 [0] = &clk_ext_xtal_mux,
682 [1] = &clk_pcmcdclk0,
683 [2] = &clk_sclk_hdmi27m,
684 [3] = &clk_sclk_usbphy0,
685 [4] = &clk_sclk_usbphy1,
686 [5] = &clk_sclk_hdmiphy,
687 [6] = &clk_mout_mpll.clk,
688 [7] = &clk_mout_epll.clk,
689 [8] = &clk_sclk_vpll.clk,
690};
691
692static struct clksrc_sources clkset_sclk_audio0 = {
693 .sources = clkset_sclk_audio0_list,
694 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
695};
696
697static struct clksrc_clk clk_sclk_audio0 = {
698 .clk = {
699 .name = "sclk_audio",
700 .devname = "soc-audio.0",
701 .enable = s5pv210_clk_mask0_ctrl,
702 .ctrlbit = (1 << 24),
703 },
704 .sources = &clkset_sclk_audio0,
705 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
706 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
707};
708
709static struct clk *clkset_sclk_audio1_list[] = {
710 [0] = &clk_ext_xtal_mux,
711 [1] = &clk_pcmcdclk1,
712 [2] = &clk_sclk_hdmi27m,
713 [3] = &clk_sclk_usbphy0,
714 [4] = &clk_sclk_usbphy1,
715 [5] = &clk_sclk_hdmiphy,
716 [6] = &clk_mout_mpll.clk,
717 [7] = &clk_mout_epll.clk,
718 [8] = &clk_sclk_vpll.clk,
719};
720
721static struct clksrc_sources clkset_sclk_audio1 = {
722 .sources = clkset_sclk_audio1_list,
723 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
724};
725
726static struct clksrc_clk clk_sclk_audio1 = {
727 .clk = {
728 .name = "sclk_audio",
729 .devname = "soc-audio.1",
730 .enable = s5pv210_clk_mask0_ctrl,
731 .ctrlbit = (1 << 25),
732 },
733 .sources = &clkset_sclk_audio1,
734 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
735 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
736};
737
738static struct clk *clkset_sclk_audio2_list[] = {
739 [0] = &clk_ext_xtal_mux,
740 [1] = &clk_pcmcdclk0,
741 [2] = &clk_sclk_hdmi27m,
742 [3] = &clk_sclk_usbphy0,
743 [4] = &clk_sclk_usbphy1,
744 [5] = &clk_sclk_hdmiphy,
745 [6] = &clk_mout_mpll.clk,
746 [7] = &clk_mout_epll.clk,
747 [8] = &clk_sclk_vpll.clk,
748};
749
750static struct clksrc_sources clkset_sclk_audio2 = {
751 .sources = clkset_sclk_audio2_list,
752 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
753};
754
755static struct clksrc_clk clk_sclk_audio2 = {
756 .clk = {
757 .name = "sclk_audio",
758 .devname = "soc-audio.2",
759 .enable = s5pv210_clk_mask0_ctrl,
760 .ctrlbit = (1 << 26),
761 },
762 .sources = &clkset_sclk_audio2,
763 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
764 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
765};
766
767static struct clk *clkset_sclk_spdif_list[] = {
768 [0] = &clk_sclk_audio0.clk,
769 [1] = &clk_sclk_audio1.clk,
770 [2] = &clk_sclk_audio2.clk,
771};
772
773static struct clksrc_sources clkset_sclk_spdif = {
774 .sources = clkset_sclk_spdif_list,
775 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
776};
777
778static struct clksrc_clk clk_sclk_spdif = {
779 .clk = {
780 .name = "sclk_spdif",
781 .enable = s5pv210_clk_mask0_ctrl,
782 .ctrlbit = (1 << 27),
783 .ops = &s5p_sclk_spdif_ops,
784 },
785 .sources = &clkset_sclk_spdif,
786 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
787};
788
789static struct clk *clkset_group2_list[] = {
790 [0] = &clk_ext_xtal_mux,
791 [1] = &clk_xusbxti,
792 [2] = &clk_sclk_hdmi27m,
793 [3] = &clk_sclk_usbphy0,
794 [4] = &clk_sclk_usbphy1,
795 [5] = &clk_sclk_hdmiphy,
796 [6] = &clk_mout_mpll.clk,
797 [7] = &clk_mout_epll.clk,
798 [8] = &clk_sclk_vpll.clk,
799};
800
801static struct clksrc_sources clkset_group2 = {
802 .sources = clkset_group2_list,
803 .nr_sources = ARRAY_SIZE(clkset_group2_list),
804};
805
806static struct clksrc_clk clksrcs[] = {
807 {
808 .clk = {
809 .name = "sclk_dmc",
810 },
811 .sources = &clkset_group1,
812 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
813 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
814 }, {
815 .clk = {
816 .name = "sclk_onenand",
817 },
818 .sources = &clkset_sclk_onenand,
819 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
820 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
821 }, {
822 .clk = {
823 .name = "sclk_fimc",
824 .devname = "s5pv210-fimc.0",
825 .enable = s5pv210_clk_mask1_ctrl,
826 .ctrlbit = (1 << 2),
827 },
828 .sources = &clkset_group2,
829 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
830 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
831 }, {
832 .clk = {
833 .name = "sclk_fimc",
834 .devname = "s5pv210-fimc.1",
835 .enable = s5pv210_clk_mask1_ctrl,
836 .ctrlbit = (1 << 3),
837 },
838 .sources = &clkset_group2,
839 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
840 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
841 }, {
842 .clk = {
843 .name = "sclk_fimc",
844 .devname = "s5pv210-fimc.2",
845 .enable = s5pv210_clk_mask1_ctrl,
846 .ctrlbit = (1 << 4),
847 },
848 .sources = &clkset_group2,
849 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
850 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
851 }, {
852 .clk = {
853 .name = "sclk_cam0",
854 .enable = s5pv210_clk_mask0_ctrl,
855 .ctrlbit = (1 << 3),
856 },
857 .sources = &clkset_group2,
858 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
859 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
860 }, {
861 .clk = {
862 .name = "sclk_cam1",
863 .enable = s5pv210_clk_mask0_ctrl,
864 .ctrlbit = (1 << 4),
865 },
866 .sources = &clkset_group2,
867 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
868 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
869 }, {
870 .clk = {
871 .name = "sclk_fimd",
872 .enable = s5pv210_clk_mask0_ctrl,
873 .ctrlbit = (1 << 5),
874 },
875 .sources = &clkset_group2,
876 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
877 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
878 }, {
879 .clk = {
880 .name = "sclk_mfc",
881 .devname = "s5p-mfc",
882 .enable = s5pv210_clk_ip0_ctrl,
883 .ctrlbit = (1 << 16),
884 },
885 .sources = &clkset_group1,
886 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
887 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
888 }, {
889 .clk = {
890 .name = "sclk_g2d",
891 .enable = s5pv210_clk_ip0_ctrl,
892 .ctrlbit = (1 << 12),
893 },
894 .sources = &clkset_group1,
895 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
896 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
897 }, {
898 .clk = {
899 .name = "sclk_g3d",
900 .enable = s5pv210_clk_ip0_ctrl,
901 .ctrlbit = (1 << 8),
902 },
903 .sources = &clkset_group1,
904 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
905 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
906 }, {
907 .clk = {
908 .name = "sclk_csis",
909 .enable = s5pv210_clk_mask0_ctrl,
910 .ctrlbit = (1 << 6),
911 },
912 .sources = &clkset_group2,
913 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
914 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
915 }, {
916 .clk = {
917 .name = "sclk_pwi",
918 .enable = s5pv210_clk_mask0_ctrl,
919 .ctrlbit = (1 << 29),
920 },
921 .sources = &clkset_group2,
922 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
923 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
924 }, {
925 .clk = {
926 .name = "sclk_pwm",
927 .enable = s5pv210_clk_mask0_ctrl,
928 .ctrlbit = (1 << 19),
929 },
930 .sources = &clkset_group2,
931 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
932 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
933 },
934};
935
936static struct clksrc_clk clk_sclk_uart0 = {
937 .clk = {
938 .name = "uclk1",
939 .devname = "s5pv210-uart.0",
940 .enable = s5pv210_clk_mask0_ctrl,
941 .ctrlbit = (1 << 12),
942 },
943 .sources = &clkset_uart,
944 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
945 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
946};
947
948static struct clksrc_clk clk_sclk_uart1 = {
949 .clk = {
950 .name = "uclk1",
951 .devname = "s5pv210-uart.1",
952 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 13),
954 },
955 .sources = &clkset_uart,
956 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
957 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
958};
959
960static struct clksrc_clk clk_sclk_uart2 = {
961 .clk = {
962 .name = "uclk1",
963 .devname = "s5pv210-uart.2",
964 .enable = s5pv210_clk_mask0_ctrl,
965 .ctrlbit = (1 << 14),
966 },
967 .sources = &clkset_uart,
968 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
969 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
970};
971
972static struct clksrc_clk clk_sclk_uart3 = {
973 .clk = {
974 .name = "uclk1",
975 .devname = "s5pv210-uart.3",
976 .enable = s5pv210_clk_mask0_ctrl,
977 .ctrlbit = (1 << 15),
978 },
979 .sources = &clkset_uart,
980 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
981 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
982};
983
984static struct clksrc_clk clk_sclk_mmc0 = {
985 .clk = {
986 .name = "sclk_mmc",
987 .devname = "s3c-sdhci.0",
988 .enable = s5pv210_clk_mask0_ctrl,
989 .ctrlbit = (1 << 8),
990 },
991 .sources = &clkset_group2,
992 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
993 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
994};
995
996static struct clksrc_clk clk_sclk_mmc1 = {
997 .clk = {
998 .name = "sclk_mmc",
999 .devname = "s3c-sdhci.1",
1000 .enable = s5pv210_clk_mask0_ctrl,
1001 .ctrlbit = (1 << 9),
1002 },
1003 .sources = &clkset_group2,
1004 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1005 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1006};
1007
1008static struct clksrc_clk clk_sclk_mmc2 = {
1009 .clk = {
1010 .name = "sclk_mmc",
1011 .devname = "s3c-sdhci.2",
1012 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 10),
1014 },
1015 .sources = &clkset_group2,
1016 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1017 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1018};
1019
1020static struct clksrc_clk clk_sclk_mmc3 = {
1021 .clk = {
1022 .name = "sclk_mmc",
1023 .devname = "s3c-sdhci.3",
1024 .enable = s5pv210_clk_mask0_ctrl,
1025 .ctrlbit = (1 << 11),
1026 },
1027 .sources = &clkset_group2,
1028 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1029 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1030};
1031
1032static struct clksrc_clk clk_sclk_spi0 = {
1033 .clk = {
1034 .name = "sclk_spi",
1035 .devname = "s5pv210-spi.0",
1036 .enable = s5pv210_clk_mask0_ctrl,
1037 .ctrlbit = (1 << 16),
1038 },
1039 .sources = &clkset_group2,
1040 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1041 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1042 };
1043
1044static struct clksrc_clk clk_sclk_spi1 = {
1045 .clk = {
1046 .name = "sclk_spi",
1047 .devname = "s5pv210-spi.1",
1048 .enable = s5pv210_clk_mask0_ctrl,
1049 .ctrlbit = (1 << 17),
1050 },
1051 .sources = &clkset_group2,
1052 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1053 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1054 };
1055
1056
1057static struct clksrc_clk *clksrc_cdev[] = {
1058 &clk_sclk_uart0,
1059 &clk_sclk_uart1,
1060 &clk_sclk_uart2,
1061 &clk_sclk_uart3,
1062 &clk_sclk_mmc0,
1063 &clk_sclk_mmc1,
1064 &clk_sclk_mmc2,
1065 &clk_sclk_mmc3,
1066 &clk_sclk_spi0,
1067 &clk_sclk_spi1,
1068};
1069
1070static struct clk *clk_cdev[] = {
1071 &clk_hsmmc0,
1072 &clk_hsmmc1,
1073 &clk_hsmmc2,
1074 &clk_hsmmc3,
1075 &clk_pdma0,
1076 &clk_pdma1,
1077};
1078
1079/* Clock initialisation code */
1080static struct clksrc_clk *sysclks[] = {
1081 &clk_mout_apll,
1082 &clk_mout_epll,
1083 &clk_mout_mpll,
1084 &clk_armclk,
1085 &clk_hclk_msys,
1086 &clk_sclk_a2m,
1087 &clk_hclk_dsys,
1088 &clk_hclk_psys,
1089 &clk_pclk_msys,
1090 &clk_pclk_dsys,
1091 &clk_pclk_psys,
1092 &clk_vpllsrc,
1093 &clk_sclk_vpll,
1094 &clk_mout_dmc0,
1095 &clk_sclk_dmc0,
1096 &clk_sclk_audio0,
1097 &clk_sclk_audio1,
1098 &clk_sclk_audio2,
1099 &clk_sclk_spdif,
1100};
1101
1102static u32 epll_div[][6] = {
1103 { 48000000, 0, 48, 3, 3, 0 },
1104 { 96000000, 0, 48, 3, 2, 0 },
1105 { 144000000, 1, 72, 3, 2, 0 },
1106 { 192000000, 0, 48, 3, 1, 0 },
1107 { 288000000, 1, 72, 3, 1, 0 },
1108 { 32750000, 1, 65, 3, 4, 35127 },
1109 { 32768000, 1, 65, 3, 4, 35127 },
1110 { 45158400, 0, 45, 3, 3, 10355 },
1111 { 45000000, 0, 45, 3, 3, 10355 },
1112 { 45158000, 0, 45, 3, 3, 10355 },
1113 { 49125000, 0, 49, 3, 3, 9961 },
1114 { 49152000, 0, 49, 3, 3, 9961 },
1115 { 67737600, 1, 67, 3, 3, 48366 },
1116 { 67738000, 1, 67, 3, 3, 48366 },
1117 { 73800000, 1, 73, 3, 3, 47710 },
1118 { 73728000, 1, 73, 3, 3, 47710 },
1119 { 36000000, 1, 32, 3, 4, 0 },
1120 { 60000000, 1, 60, 3, 3, 0 },
1121 { 72000000, 1, 72, 3, 3, 0 },
1122 { 80000000, 1, 80, 3, 3, 0 },
1123 { 84000000, 0, 42, 3, 2, 0 },
1124 { 50000000, 0, 50, 3, 3, 0 },
1125};
1126
1127static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1128{
1129 unsigned int epll_con, epll_con_k;
1130 unsigned int i;
1131
1132 /* Return if nothing changed */
1133 if (clk->rate == rate)
1134 return 0;
1135
1136 epll_con = __raw_readl(S5P_EPLL_CON);
1137 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1138
1139 epll_con_k &= ~PLL46XX_KDIV_MASK;
1140 epll_con &= ~(1 << 27 |
1141 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1142 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1143 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1144
1145 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1146 if (epll_div[i][0] == rate) {
1147 epll_con_k |= epll_div[i][5] << 0;
1148 epll_con |= (epll_div[i][1] << 27 |
1149 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1150 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1151 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1152 break;
1153 }
1154 }
1155
1156 if (i == ARRAY_SIZE(epll_div)) {
1157 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1158 __func__);
1159 return -EINVAL;
1160 }
1161
1162 __raw_writel(epll_con, S5P_EPLL_CON);
1163 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1164
1165 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1166 clk->rate, rate);
1167
1168 clk->rate = rate;
1169
1170 return 0;
1171}
1172
1173static struct clk_ops s5pv210_epll_ops = {
1174 .set_rate = s5pv210_epll_set_rate,
1175 .get_rate = s5p_epll_get_rate,
1176};
1177
1178static u32 vpll_div[][5] = {
1179 { 54000000, 3, 53, 3, 0 },
1180 { 108000000, 3, 53, 2, 0 },
1181};
1182
1183static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
1184{
1185 return clk->rate;
1186}
1187
1188static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
1189{
1190 unsigned int vpll_con;
1191 unsigned int i;
1192
1193 /* Return if nothing changed */
1194 if (clk->rate == rate)
1195 return 0;
1196
1197 vpll_con = __raw_readl(S5P_VPLL_CON);
1198 vpll_con &= ~(0x1 << 27 | \
1199 PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
1200 PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
1201 PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
1202
1203 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1204 if (vpll_div[i][0] == rate) {
1205 vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
1206 vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
1207 vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
1208 vpll_con |= vpll_div[i][4] << 27;
1209 break;
1210 }
1211 }
1212
1213 if (i == ARRAY_SIZE(vpll_div)) {
1214 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1215 __func__);
1216 return -EINVAL;
1217 }
1218
1219 __raw_writel(vpll_con, S5P_VPLL_CON);
1220
1221 /* Wait for VPLL lock */
1222 while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
1223 continue;
1224
1225 clk->rate = rate;
1226 return 0;
1227}
1228static struct clk_ops s5pv210_vpll_ops = {
1229 .get_rate = s5pv210_vpll_get_rate,
1230 .set_rate = s5pv210_vpll_set_rate,
1231};
1232
1233void __init_or_cpufreq s5pv210_setup_clocks(void)
1234{
1235 struct clk *xtal_clk;
1236 unsigned long vpllsrc;
1237 unsigned long armclk;
1238 unsigned long hclk_msys;
1239 unsigned long hclk_dsys;
1240 unsigned long hclk_psys;
1241 unsigned long pclk_msys;
1242 unsigned long pclk_dsys;
1243 unsigned long pclk_psys;
1244 unsigned long apll;
1245 unsigned long mpll;
1246 unsigned long epll;
1247 unsigned long vpll;
1248 unsigned int ptr;
1249 u32 clkdiv0, clkdiv1;
1250
1251 /* Set functions for clk_fout_epll */
1252 clk_fout_epll.enable = s5p_epll_enable;
1253 clk_fout_epll.ops = &s5pv210_epll_ops;
1254
1255 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1256
1257 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1258 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1259
1260 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1261 __func__, clkdiv0, clkdiv1);
1262
1263 xtal_clk = clk_get(NULL, "xtal");
1264 BUG_ON(IS_ERR(xtal_clk));
1265
1266 xtal = clk_get_rate(xtal_clk);
1267 clk_put(xtal_clk);
1268
1269 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1270
1271 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1272 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1273 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1274 __raw_readl(S5P_EPLL_CON1), pll_4600);
1275 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1276 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1277
1278 clk_fout_apll.ops = &clk_fout_apll_ops;
1279 clk_fout_mpll.rate = mpll;
1280 clk_fout_epll.rate = epll;
1281 clk_fout_vpll.ops = &s5pv210_vpll_ops;
1282 clk_fout_vpll.rate = vpll;
1283
1284 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1285 apll, mpll, epll, vpll);
1286
1287 armclk = clk_get_rate(&clk_armclk.clk);
1288 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1289 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1290 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1291 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1292 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1293 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1294
1295 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1296 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1297 armclk, hclk_msys, hclk_dsys, hclk_psys,
1298 pclk_msys, pclk_dsys, pclk_psys);
1299
1300 clk_f.rate = armclk;
1301 clk_h.rate = hclk_psys;
1302 clk_p.rate = pclk_psys;
1303
1304 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1305 s3c_set_clksrc(&clksrcs[ptr], true);
1306}
1307
1308static struct clk *clks[] __initdata = {
1309 &clk_sclk_hdmi27m,
1310 &clk_sclk_hdmiphy,
1311 &clk_sclk_usbphy0,
1312 &clk_sclk_usbphy1,
1313 &clk_pcmcdclk0,
1314 &clk_pcmcdclk1,
1315 &clk_pcmcdclk2,
1316};
1317
1318static struct clk_lookup s5pv210_clk_lookup[] = {
1319 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
1320 CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
1321 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1322 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1323 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1324 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1325 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1326 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1327 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1328 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1329 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1330 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1331 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1332 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1333 CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1334 CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1335 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1336 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1337};
1338
1339void __init s5pv210_register_clocks(void)
1340{
1341 int ptr;
1342
1343 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1344
1345 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1346 s3c_register_clksrc(sysclks[ptr], 1);
1347
1348 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1349 s3c_register_clksrc(sclk_tv[ptr], 1);
1350
1351 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1352 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1353
1354 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1355 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1356
1357 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1358 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1359 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1360
1361 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1362 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1363 s3c_disable_clocks(clk_cdev[ptr], 1);
1364
1365}
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
deleted file mode 100644
index 7024dcd0e40a..000000000000
--- a/arch/arm/mach-s5pv210/common.c
+++ /dev/null
@@ -1,279 +0,0 @@
1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for S5PV210
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/device.h>
22#include <clocksource/samsung_pwm.h>
23#include <linux/platform_device.h>
24#include <linux/sched.h>
25#include <linux/dma-mapping.h>
26#include <linux/serial_core.h>
27#include <linux/serial_s3c.h>
28
29#include <asm/proc-fns.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
34#include <mach/map.h>
35#include <mach/regs-clock.h>
36
37#include <plat/cpu.h>
38#include <plat/clock.h>
39#include <plat/devs.h>
40#include <plat/sdhci.h>
41#include <plat/adc-core.h>
42#include <plat/ata-core.h>
43#include <plat/fb-core.h>
44#include <plat/fimc-core.h>
45#include <plat/iic-core.h>
46#include <plat/keypad-core.h>
47#include <plat/pwm-core.h>
48#include <plat/tv-core.h>
49#include <plat/spi-core.h>
50
51#include "common.h"
52
53static const char name_s5pv210[] = "S5PV210/S5PC110";
54
55static struct cpu_table cpu_ids[] __initdata = {
56 {
57 .idcode = S5PV210_CPU_ID,
58 .idmask = S5PV210_CPU_MASK,
59 .map_io = s5pv210_map_io,
60 .init_clocks = s5pv210_init_clocks,
61 .init_uarts = s5pv210_init_uarts,
62 .init = s5pv210_init,
63 .name = name_s5pv210,
64 },
65};
66
67/* Initial IO mappings */
68
69static struct map_desc s5pv210_iodesc[] __initdata = {
70 {
71 .virtual = (unsigned long)S5P_VA_CHIPID,
72 .pfn = __phys_to_pfn(S5PV210_PA_CHIPID),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
76 .virtual = (unsigned long)S3C_VA_SYS,
77 .pfn = __phys_to_pfn(S5PV210_PA_SYSCON),
78 .length = SZ_64K,
79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)S3C_VA_TIMER,
82 .pfn = __phys_to_pfn(S5PV210_PA_TIMER),
83 .length = SZ_16K,
84 .type = MT_DEVICE,
85 }, {
86 .virtual = (unsigned long)S3C_VA_WATCHDOG,
87 .pfn = __phys_to_pfn(S5PV210_PA_WATCHDOG),
88 .length = SZ_4K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (unsigned long)S5P_VA_SROMC,
92 .pfn = __phys_to_pfn(S5PV210_PA_SROMC),
93 .length = SZ_4K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = (unsigned long)S5P_VA_SYSTIMER,
97 .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = (unsigned long)S5P_VA_GPIO,
102 .pfn = __phys_to_pfn(S5PV210_PA_GPIO),
103 .length = SZ_4K,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (unsigned long)VA_VIC0,
107 .pfn = __phys_to_pfn(S5PV210_PA_VIC0),
108 .length = SZ_16K,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (unsigned long)VA_VIC1,
112 .pfn = __phys_to_pfn(S5PV210_PA_VIC1),
113 .length = SZ_16K,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (unsigned long)VA_VIC2,
117 .pfn = __phys_to_pfn(S5PV210_PA_VIC2),
118 .length = SZ_16K,
119 .type = MT_DEVICE,
120 }, {
121 .virtual = (unsigned long)VA_VIC3,
122 .pfn = __phys_to_pfn(S5PV210_PA_VIC3),
123 .length = SZ_16K,
124 .type = MT_DEVICE,
125 }, {
126 .virtual = (unsigned long)S3C_VA_UART,
127 .pfn = __phys_to_pfn(S3C_PA_UART),
128 .length = SZ_512K,
129 .type = MT_DEVICE,
130 }, {
131 .virtual = (unsigned long)S5P_VA_DMC0,
132 .pfn = __phys_to_pfn(S5PV210_PA_DMC0),
133 .length = SZ_4K,
134 .type = MT_DEVICE,
135 }, {
136 .virtual = (unsigned long)S5P_VA_DMC1,
137 .pfn = __phys_to_pfn(S5PV210_PA_DMC1),
138 .length = SZ_4K,
139 .type = MT_DEVICE,
140 }, {
141 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
142 .pfn =__phys_to_pfn(S5PV210_PA_HSPHY),
143 .length = SZ_4K,
144 .type = MT_DEVICE,
145 }
146};
147
148void s5pv210_restart(enum reboot_mode mode, const char *cmd)
149{
150 __raw_writel(0x1, S5P_SWRESET);
151}
152
153static struct samsung_pwm_variant s5pv210_pwm_variant = {
154 .bits = 32,
155 .div_base = 0,
156 .has_tint_cstat = true,
157 .tclk_mask = (1 << 5),
158};
159
160void __init samsung_set_timer_source(unsigned int event, unsigned int source)
161{
162 s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
163 s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
164}
165
166void __init samsung_timer_init(void)
167{
168 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
169 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
170 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
171 };
172
173 samsung_pwm_clocksource_init(S3C_VA_TIMER,
174 timer_irqs, &s5pv210_pwm_variant);
175}
176
177/*
178 * s5pv210_map_io
179 *
180 * register the standard cpu IO areas
181 */
182
183void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
184{
185 /* initialize the io descriptors we need for initialization */
186 iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
187 if (mach_desc)
188 iotable_init(mach_desc, size);
189
190 /* detect cpu id and rev. */
191 s5p_init_cpu(S5P_VA_CHIPID);
192
193 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
194
195 samsung_pwm_set_platdata(&s5pv210_pwm_variant);
196}
197
198void __init s5pv210_map_io(void)
199{
200 /* initialise device information early */
201 s5pv210_default_sdhci0();
202 s5pv210_default_sdhci1();
203 s5pv210_default_sdhci2();
204 s5pv210_default_sdhci3();
205
206 s3c_adc_setname("samsung-adc-v3");
207
208 s3c_cfcon_setname("s5pv210-pata");
209
210 s3c_fimc_setname(0, "s5pv210-fimc");
211 s3c_fimc_setname(1, "s5pv210-fimc");
212 s3c_fimc_setname(2, "s5pv210-fimc");
213
214 /* the i2c devices are directly compatible with s3c2440 */
215 s3c_i2c0_setname("s3c2440-i2c");
216 s3c_i2c1_setname("s3c2440-i2c");
217 s3c_i2c2_setname("s3c2440-i2c");
218
219 s3c_fb_setname("s5pv210-fb");
220
221 /* Use s5pv210-keypad instead of samsung-keypad */
222 samsung_keypad_setname("s5pv210-keypad");
223
224 /* setup TV devices */
225 s5p_hdmi_setname("s5pv210-hdmi");
226
227 s3c64xx_spi_setname("s5pv210-spi");
228}
229
230void __init s5pv210_init_clocks(int xtal)
231{
232 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
233
234 s3c24xx_register_baseclocks(xtal);
235 s5p_register_clocks(xtal);
236 s5pv210_register_clocks();
237 s5pv210_setup_clocks();
238}
239
240void __init s5pv210_init_irq(void)
241{
242 u32 vic[4]; /* S5PV210 supports 4 VIC */
243
244 /* All the VICs are fully populated. */
245 vic[0] = ~0;
246 vic[1] = ~0;
247 vic[2] = ~0;
248 vic[3] = ~0;
249
250 s5p_init_irq(vic, ARRAY_SIZE(vic));
251}
252
253struct bus_type s5pv210_subsys = {
254 .name = "s5pv210-core",
255 .dev_name = "s5pv210-core",
256};
257
258static struct device s5pv210_dev = {
259 .bus = &s5pv210_subsys,
260};
261
262static int __init s5pv210_core_init(void)
263{
264 return subsys_system_register(&s5pv210_subsys, NULL);
265}
266core_initcall(s5pv210_core_init);
267
268int __init s5pv210_init(void)
269{
270 printk(KERN_INFO "S5PV210: Initializing architecture\n");
271 return device_register(&s5pv210_dev);
272}
273
274/* uart registration process */
275
276void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
277{
278 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
279}
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index fe1beb54e548..2ad387c1ecf0 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -12,19 +12,12 @@
12#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H 12#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
13#define __ARCH_ARM_MACH_S5PV210_COMMON_H 13#define __ARCH_ARM_MACH_S5PV210_COMMON_H
14 14
15#include <linux/reboot.h> 15#ifdef CONFIG_PM_SLEEP
16 16u32 exynos_get_eint_wake_mask(void);
17void s5pv210_init_io(struct map_desc *mach_desc, int size); 17void s5pv210_cpu_resume(void);
18void s5pv210_init_irq(void); 18void s5pv210_pm_init(void);
19 19#else
20void s5pv210_register_clocks(void); 20static inline void s5pv210_pm_init(void) {}
21void s5pv210_setup_clocks(void); 21#endif
22
23void s5pv210_restart(enum reboot_mode mode, const char *cmd);
24
25extern int s5pv210_init(void);
26extern void s5pv210_map_io(void);
27extern void s5pv210_init_clocks(int xtal);
28extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29 22
30#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */ 23#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
deleted file mode 100644
index 2d67361ef431..000000000000
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ /dev/null
@@ -1,246 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <linux/platform_data/asoc-s3c.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22#define S5PV210_AUDSS_INT_MEM (0xC0000000)
23
24static int s5pv210_cfg_i2s(struct platform_device *pdev)
25{
26 /* configure GPIO for i2s port */
27 switch (pdev->id) {
28 case 0:
29 s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
30 break;
31 case 1:
32 s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
33 break;
34 case 2:
35 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
36 break;
37 default:
38 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
39 return -EINVAL;
40 }
41
42 return 0;
43}
44
45static struct s3c_audio_pdata i2sv5_pdata = {
46 .cfg_gpio = s5pv210_cfg_i2s,
47 .type = {
48 .i2s = {
49 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
50 | QUIRK_NEED_RSTCLR,
51 .idma_addr = S5PV210_AUDSS_INT_MEM,
52 },
53 },
54};
55
56static struct resource s5pv210_iis0_resource[] = {
57 [0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256),
58 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
59 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
60 [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
61};
62
63struct platform_device s5pv210_device_iis0 = {
64 .name = "samsung-i2s",
65 .id = 0,
66 .num_resources = ARRAY_SIZE(s5pv210_iis0_resource),
67 .resource = s5pv210_iis0_resource,
68 .dev = {
69 .platform_data = &i2sv5_pdata,
70 },
71};
72
73static struct s3c_audio_pdata i2sv3_pdata = {
74 .cfg_gpio = s5pv210_cfg_i2s,
75};
76
77static struct resource s5pv210_iis1_resource[] = {
78 [0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256),
79 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
80 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
81};
82
83struct platform_device s5pv210_device_iis1 = {
84 .name = "samsung-i2s",
85 .id = 1,
86 .num_resources = ARRAY_SIZE(s5pv210_iis1_resource),
87 .resource = s5pv210_iis1_resource,
88 .dev = {
89 .platform_data = &i2sv3_pdata,
90 },
91};
92
93static struct resource s5pv210_iis2_resource[] = {
94 [0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256),
95 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
96 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
97};
98
99struct platform_device s5pv210_device_iis2 = {
100 .name = "samsung-i2s",
101 .id = 2,
102 .num_resources = ARRAY_SIZE(s5pv210_iis2_resource),
103 .resource = s5pv210_iis2_resource,
104 .dev = {
105 .platform_data = &i2sv3_pdata,
106 },
107};
108
109/* PCM Controller platform_devices */
110
111static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
112{
113 switch (pdev->id) {
114 case 0:
115 s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
116 break;
117 case 1:
118 s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
119 break;
120 case 2:
121 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
122 break;
123 default:
124 printk(KERN_DEBUG "Invalid PCM Controller number!");
125 return -EINVAL;
126 }
127
128 return 0;
129}
130
131static struct s3c_audio_pdata s3c_pcm_pdata = {
132 .cfg_gpio = s5pv210_pcm_cfg_gpio,
133};
134
135static struct resource s5pv210_pcm0_resource[] = {
136 [0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256),
137 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
138 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
139};
140
141struct platform_device s5pv210_device_pcm0 = {
142 .name = "samsung-pcm",
143 .id = 0,
144 .num_resources = ARRAY_SIZE(s5pv210_pcm0_resource),
145 .resource = s5pv210_pcm0_resource,
146 .dev = {
147 .platform_data = &s3c_pcm_pdata,
148 },
149};
150
151static struct resource s5pv210_pcm1_resource[] = {
152 [0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256),
153 [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
154 [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
155};
156
157struct platform_device s5pv210_device_pcm1 = {
158 .name = "samsung-pcm",
159 .id = 1,
160 .num_resources = ARRAY_SIZE(s5pv210_pcm1_resource),
161 .resource = s5pv210_pcm1_resource,
162 .dev = {
163 .platform_data = &s3c_pcm_pdata,
164 },
165};
166
167static struct resource s5pv210_pcm2_resource[] = {
168 [0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256),
169 [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
170 [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
171};
172
173struct platform_device s5pv210_device_pcm2 = {
174 .name = "samsung-pcm",
175 .id = 2,
176 .num_resources = ARRAY_SIZE(s5pv210_pcm2_resource),
177 .resource = s5pv210_pcm2_resource,
178 .dev = {
179 .platform_data = &s3c_pcm_pdata,
180 },
181};
182
183/* AC97 Controller platform devices */
184
185static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
186{
187 return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
188}
189
190static struct resource s5pv210_ac97_resource[] = {
191 [0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256),
192 [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
193 [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
194 [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
195 [4] = DEFINE_RES_IRQ(IRQ_AC97),
196};
197
198static struct s3c_audio_pdata s3c_ac97_pdata = {
199 .cfg_gpio = s5pv210_ac97_cfg_gpio,
200};
201
202static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32);
203
204struct platform_device s5pv210_device_ac97 = {
205 .name = "samsung-ac97",
206 .id = -1,
207 .num_resources = ARRAY_SIZE(s5pv210_ac97_resource),
208 .resource = s5pv210_ac97_resource,
209 .dev = {
210 .platform_data = &s3c_ac97_pdata,
211 .dma_mask = &s5pv210_ac97_dmamask,
212 .coherent_dma_mask = DMA_BIT_MASK(32),
213 },
214};
215
216/* S/PDIF Controller platform_device */
217
218static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
219{
220 s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
221
222 return 0;
223}
224
225static struct resource s5pv210_spdif_resource[] = {
226 [0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256),
227 [1] = DEFINE_RES_DMA(DMACH_SPDIF),
228};
229
230static struct s3c_audio_pdata samsung_spdif_pdata = {
231 .cfg_gpio = s5pv210_spdif_cfg_gpio,
232};
233
234static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
235
236struct platform_device s5pv210_device_spdif = {
237 .name = "samsung-spdif",
238 .id = -1,
239 .num_resources = ARRAY_SIZE(s5pv210_spdif_resource),
240 .resource = s5pv210_spdif_resource,
241 .dev = {
242 .platform_data = &samsung_spdif_pdata,
243 .dma_mask = &s5pv210_spdif_dmamask,
244 .coherent_dma_mask = DMA_BIT_MASK(32),
245 },
246};
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
deleted file mode 100644
index b8337e248b09..000000000000
--- a/arch/arm/mach-s5pv210/dma.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
29#include <plat/devs.h>
30#include <plat/irqs.h>
31
32#include <mach/map.h>
33#include <mach/irqs.h>
34#include <mach/dma.h>
35
36static u8 pdma0_peri[] = {
37 DMACH_UART0_RX,
38 DMACH_UART0_TX,
39 DMACH_UART1_RX,
40 DMACH_UART1_TX,
41 DMACH_UART2_RX,
42 DMACH_UART2_TX,
43 DMACH_UART3_RX,
44 DMACH_UART3_TX,
45 DMACH_MAX,
46 DMACH_I2S0_RX,
47 DMACH_I2S0_TX,
48 DMACH_I2S0S_TX,
49 DMACH_I2S1_RX,
50 DMACH_I2S1_TX,
51 DMACH_MAX,
52 DMACH_MAX,
53 DMACH_SPI0_RX,
54 DMACH_SPI0_TX,
55 DMACH_SPI1_RX,
56 DMACH_SPI1_TX,
57 DMACH_MAX,
58 DMACH_MAX,
59 DMACH_AC97_MICIN,
60 DMACH_AC97_PCMIN,
61 DMACH_AC97_PCMOUT,
62 DMACH_MAX,
63 DMACH_PWM,
64 DMACH_SPDIF,
65};
66
67static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
68 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
69 .peri_id = pdma0_peri,
70};
71
72static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
73 S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
74
75static u8 pdma1_peri[] = {
76 DMACH_UART0_RX,
77 DMACH_UART0_TX,
78 DMACH_UART1_RX,
79 DMACH_UART1_TX,
80 DMACH_UART2_RX,
81 DMACH_UART2_TX,
82 DMACH_UART3_RX,
83 DMACH_UART3_TX,
84 DMACH_MAX,
85 DMACH_I2S0_RX,
86 DMACH_I2S0_TX,
87 DMACH_I2S0S_TX,
88 DMACH_I2S1_RX,
89 DMACH_I2S1_TX,
90 DMACH_I2S2_RX,
91 DMACH_I2S2_TX,
92 DMACH_SPI0_RX,
93 DMACH_SPI0_TX,
94 DMACH_SPI1_RX,
95 DMACH_SPI1_TX,
96 DMACH_MAX,
97 DMACH_MAX,
98 DMACH_PCM0_RX,
99 DMACH_PCM0_TX,
100 DMACH_PCM1_RX,
101 DMACH_PCM1_TX,
102 DMACH_MSM_REQ0,
103 DMACH_MSM_REQ1,
104 DMACH_MSM_REQ2,
105 DMACH_MSM_REQ3,
106 DMACH_PCM2_RX,
107 DMACH_PCM2_TX,
108};
109
110static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
111 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
112 .peri_id = pdma1_peri,
113};
114
115static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
116 S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
117
118static int __init s5pv210_dma_init(void)
119{
120 dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
121 dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
122 amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
123
124 dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
125 dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
126 amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
127
128 return 0;
129}
130arch_initcall(s5pv210_dma_init);
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h
deleted file mode 100644
index 201842a3769e..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
deleted file mode 100644
index 6c8b903c02e4..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
17
18/* GPIO bank sizes */
19#define S5PV210_GPIO_A0_NR (8)
20#define S5PV210_GPIO_A1_NR (4)
21#define S5PV210_GPIO_B_NR (8)
22#define S5PV210_GPIO_C0_NR (5)
23#define S5PV210_GPIO_C1_NR (5)
24#define S5PV210_GPIO_D0_NR (4)
25#define S5PV210_GPIO_D1_NR (6)
26#define S5PV210_GPIO_E0_NR (8)
27#define S5PV210_GPIO_E1_NR (5)
28#define S5PV210_GPIO_F0_NR (8)
29#define S5PV210_GPIO_F1_NR (8)
30#define S5PV210_GPIO_F2_NR (8)
31#define S5PV210_GPIO_F3_NR (6)
32#define S5PV210_GPIO_G0_NR (7)
33#define S5PV210_GPIO_G1_NR (7)
34#define S5PV210_GPIO_G2_NR (7)
35#define S5PV210_GPIO_G3_NR (7)
36#define S5PV210_GPIO_H0_NR (8)
37#define S5PV210_GPIO_H1_NR (8)
38#define S5PV210_GPIO_H2_NR (8)
39#define S5PV210_GPIO_H3_NR (8)
40#define S5PV210_GPIO_I_NR (7)
41#define S5PV210_GPIO_J0_NR (8)
42#define S5PV210_GPIO_J1_NR (6)
43#define S5PV210_GPIO_J2_NR (8)
44#define S5PV210_GPIO_J3_NR (8)
45#define S5PV210_GPIO_J4_NR (5)
46
47#define S5PV210_GPIO_MP01_NR (8)
48#define S5PV210_GPIO_MP02_NR (4)
49#define S5PV210_GPIO_MP03_NR (8)
50#define S5PV210_GPIO_MP04_NR (8)
51#define S5PV210_GPIO_MP05_NR (8)
52
53/* GPIO bank numbers */
54
55/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
56 * space for debugging purposes so that any accidental
57 * change from one gpio bank to another can be caught.
58*/
59
60#define S5PV210_GPIO_NEXT(__gpio) \
61 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
62
63enum s5p_gpio_number {
64 S5PV210_GPIO_A0_START = 0,
65 S5PV210_GPIO_A1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A0),
66 S5PV210_GPIO_B_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_A1),
67 S5PV210_GPIO_C0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_B),
68 S5PV210_GPIO_C1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C0),
69 S5PV210_GPIO_D0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_C1),
70 S5PV210_GPIO_D1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D0),
71 S5PV210_GPIO_E0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_D1),
72 S5PV210_GPIO_E1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E0),
73 S5PV210_GPIO_F0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_E1),
74 S5PV210_GPIO_F1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F0),
75 S5PV210_GPIO_F2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F1),
76 S5PV210_GPIO_F3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F2),
77 S5PV210_GPIO_G0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_F3),
78 S5PV210_GPIO_G1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G0),
79 S5PV210_GPIO_G2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G1),
80 S5PV210_GPIO_G3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G2),
81 S5PV210_GPIO_H0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_G3),
82 S5PV210_GPIO_H1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H0),
83 S5PV210_GPIO_H2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H1),
84 S5PV210_GPIO_H3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H2),
85 S5PV210_GPIO_I_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_H3),
86 S5PV210_GPIO_J0_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_I),
87 S5PV210_GPIO_J1_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J0),
88 S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
89 S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
90 S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
91 S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
92 S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
93 S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
94 S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
95 S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
96};
97
98/* S5PV210 GPIO number definitions */
99#define S5PV210_GPA0(_nr) (S5PV210_GPIO_A0_START + (_nr))
100#define S5PV210_GPA1(_nr) (S5PV210_GPIO_A1_START + (_nr))
101#define S5PV210_GPB(_nr) (S5PV210_GPIO_B_START + (_nr))
102#define S5PV210_GPC0(_nr) (S5PV210_GPIO_C0_START + (_nr))
103#define S5PV210_GPC1(_nr) (S5PV210_GPIO_C1_START + (_nr))
104#define S5PV210_GPD0(_nr) (S5PV210_GPIO_D0_START + (_nr))
105#define S5PV210_GPD1(_nr) (S5PV210_GPIO_D1_START + (_nr))
106#define S5PV210_GPE0(_nr) (S5PV210_GPIO_E0_START + (_nr))
107#define S5PV210_GPE1(_nr) (S5PV210_GPIO_E1_START + (_nr))
108#define S5PV210_GPF0(_nr) (S5PV210_GPIO_F0_START + (_nr))
109#define S5PV210_GPF1(_nr) (S5PV210_GPIO_F1_START + (_nr))
110#define S5PV210_GPF2(_nr) (S5PV210_GPIO_F2_START + (_nr))
111#define S5PV210_GPF3(_nr) (S5PV210_GPIO_F3_START + (_nr))
112#define S5PV210_GPG0(_nr) (S5PV210_GPIO_G0_START + (_nr))
113#define S5PV210_GPG1(_nr) (S5PV210_GPIO_G1_START + (_nr))
114#define S5PV210_GPG2(_nr) (S5PV210_GPIO_G2_START + (_nr))
115#define S5PV210_GPG3(_nr) (S5PV210_GPIO_G3_START + (_nr))
116#define S5PV210_GPH0(_nr) (S5PV210_GPIO_H0_START + (_nr))
117#define S5PV210_GPH1(_nr) (S5PV210_GPIO_H1_START + (_nr))
118#define S5PV210_GPH2(_nr) (S5PV210_GPIO_H2_START + (_nr))
119#define S5PV210_GPH3(_nr) (S5PV210_GPIO_H3_START + (_nr))
120#define S5PV210_GPI(_nr) (S5PV210_GPIO_I_START + (_nr))
121#define S5PV210_GPJ0(_nr) (S5PV210_GPIO_J0_START + (_nr))
122#define S5PV210_GPJ1(_nr) (S5PV210_GPIO_J1_START + (_nr))
123#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
124#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
125#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
126#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
127#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
128#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
129#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr))
130#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr))
131
132/* the end of the S5PV210 specific gpios */
133#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
134#define S3C_GPIO_END S5PV210_GPIO_END
135
136/* define the number of gpios we need to the one after the MP05() range */
137#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \
138 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
139
140#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/hardware.h b/arch/arm/mach-s5pv210/include/mach/hardware.h
deleted file mode 100644
index fada7a392d09..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/hardware.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
deleted file mode 100644
index 5e0de3a31f3d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/irqs.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0: System, DMA, Timer */
19
20#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
21#define IRQ_BATF S5P_IRQ_VIC0(17)
22#define IRQ_MDMA S5P_IRQ_VIC0(18)
23#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
24#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
25#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
26#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
27#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
28#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
29#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
30#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
31#define IRQ_WDT S5P_IRQ_VIC0(27)
32#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
33#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
34#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
35#define IRQ_FIMC3 S5P_IRQ_VIC0(31)
36
37/* VIC1: ARM, Power, Memory, Connectivity, Storage */
38
39#define IRQ_PMU S5P_IRQ_VIC1(0)
40#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
41#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
42#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
43#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
44#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
45#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
46#define IRQ_ONENAND S5P_IRQ_VIC1(7)
47#define IRQ_NFC S5P_IRQ_VIC1(8)
48#define IRQ_CFCON S5P_IRQ_VIC1(9)
49#define IRQ_UART0 S5P_IRQ_VIC1(10)
50#define IRQ_UART1 S5P_IRQ_VIC1(11)
51#define IRQ_UART2 S5P_IRQ_VIC1(12)
52#define IRQ_UART3 S5P_IRQ_VIC1(13)
53#define IRQ_IIC S5P_IRQ_VIC1(14)
54#define IRQ_SPI0 S5P_IRQ_VIC1(15)
55#define IRQ_SPI1 S5P_IRQ_VIC1(16)
56#define IRQ_SPI2 S5P_IRQ_VIC1(17)
57#define IRQ_IRDA S5P_IRQ_VIC1(18)
58#define IRQ_IIC2 S5P_IRQ_VIC1(19)
59#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20)
60#define IRQ_HSIRX S5P_IRQ_VIC1(21)
61#define IRQ_HSITX S5P_IRQ_VIC1(22)
62#define IRQ_UHOST S5P_IRQ_VIC1(23)
63#define IRQ_OTG S5P_IRQ_VIC1(24)
64#define IRQ_MSM S5P_IRQ_VIC1(25)
65#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
66#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
67#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
68#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29)
69#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
70#define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31)
71
72/* VIC2: Multimedia, Audio, Security */
73
74#define IRQ_LCD0 S5P_IRQ_VIC2(0)
75#define IRQ_LCD1 S5P_IRQ_VIC2(1)
76#define IRQ_LCD2 S5P_IRQ_VIC2(2)
77#define IRQ_LCD3 S5P_IRQ_VIC2(3)
78#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
79#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
80#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
81#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
82#define IRQ_JPEG S5P_IRQ_VIC2(8)
83#define IRQ_2D S5P_IRQ_VIC2(9)
84#define IRQ_3D S5P_IRQ_VIC2(10)
85#define IRQ_MIXER S5P_IRQ_VIC2(11)
86#define IRQ_HDMI S5P_IRQ_VIC2(12)
87#define IRQ_IIC1 S5P_IRQ_VIC2(13)
88#define IRQ_MFC S5P_IRQ_VIC2(14)
89#define IRQ_SDO S5P_IRQ_VIC2(15)
90#define IRQ_I2S0 S5P_IRQ_VIC2(16)
91#define IRQ_I2S1 S5P_IRQ_VIC2(17)
92#define IRQ_I2S2 S5P_IRQ_VIC2(18)
93#define IRQ_AC97 S5P_IRQ_VIC2(19)
94#define IRQ_PCM0 S5P_IRQ_VIC2(20)
95#define IRQ_PCM1 S5P_IRQ_VIC2(21)
96#define IRQ_SPDIF S5P_IRQ_VIC2(22)
97#define IRQ_ADC S5P_IRQ_VIC2(23)
98#define IRQ_PENDN S5P_IRQ_VIC2(24)
99#define IRQ_TC IRQ_PENDN
100#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
101#define IRQ_CG S5P_IRQ_VIC2(26)
102#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
103#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
104#define IRQ_PCM2 S5P_IRQ_VIC2(29)
105#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
106#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
107
108/* VIC3: Etc */
109
110#define IRQ_IPC S5P_IRQ_VIC3(0)
111#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
112#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
113#define IRQ_CEC S5P_IRQ_VIC3(3)
114#define IRQ_TSI S5P_IRQ_VIC3(4)
115#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
116#define IRQ_MDNIE1 S5P_IRQ_VIC3(6)
117#define IRQ_MDNIE2 S5P_IRQ_VIC3(7)
118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
120
121#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
122#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
123
124/* GPIO interrupt */
125#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
126#define S5P_GPIOINT_GROUP_MAXNR 22
127
128/* Set the default NR_IRQS */
129#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
130
131/* Compatibility */
132#define IRQ_LCD_FIFO IRQ_LCD0
133#define IRQ_LCD_VSYNC IRQ_LCD1
134#define IRQ_LCD_SYSTEM IRQ_LCD2
135#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS
136
137#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
deleted file mode 100644
index 763929aca52d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ /dev/null
@@ -1,158 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5PV210_PA_SDRAM 0x20000000
20
21#define S5PV210_PA_SROM_BANK5 0xA8000000
22
23#define S5PC110_PA_ONENAND 0xB0000000
24#define S5PC110_PA_ONENAND_DMA 0xB0600000
25
26#define S5PV210_PA_CHIPID 0xE0000000
27
28#define S5PV210_PA_SYSCON 0xE0100000
29
30#define S5PV210_PA_GPIO 0xE0200000
31
32#define S5PV210_PA_SPDIF 0xE1100000
33
34#define S5PV210_PA_SPI0 0xE1300000
35#define S5PV210_PA_SPI1 0xE1400000
36
37#define S5PV210_PA_KEYPAD 0xE1600000
38
39#define S5PV210_PA_ADC 0xE1700000
40
41#define S5PV210_PA_IIC0 0xE1800000
42#define S5PV210_PA_IIC1 0xFAB00000
43#define S5PV210_PA_IIC2 0xE1A00000
44
45#define S5PV210_PA_AC97 0xE2200000
46
47#define S5PV210_PA_PCM0 0xE2300000
48#define S5PV210_PA_PCM1 0xE1200000
49#define S5PV210_PA_PCM2 0xE2B00000
50
51#define S5PV210_PA_TIMER 0xE2500000
52#define S5PV210_PA_SYSTIMER 0xE2600000
53#define S5PV210_PA_WATCHDOG 0xE2700000
54#define S5PV210_PA_RTC 0xE2800000
55
56#define S5PV210_PA_UART 0xE2900000
57
58#define S5PV210_PA_SROMC 0xE8000000
59
60#define S5PV210_PA_CFCON 0xE8200000
61
62#define S5PV210_PA_MFC 0xF1700000
63
64#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
65
66#define S5PV210_PA_HSOTG 0xEC000000
67#define S5PV210_PA_HSPHY 0xEC100000
68
69#define S5PV210_PA_IIS0 0xEEE30000
70#define S5PV210_PA_IIS1 0xE2100000
71#define S5PV210_PA_IIS2 0xE2A00000
72
73#define S5PV210_PA_DMC0 0xF0000000
74#define S5PV210_PA_DMC1 0xF1400000
75
76#define S5PV210_PA_VIC0 0xF2000000
77#define S5PV210_PA_VIC1 0xF2100000
78#define S5PV210_PA_VIC2 0xF2200000
79#define S5PV210_PA_VIC3 0xF2300000
80
81#define S5PV210_PA_FB 0xF8000000
82
83#define S5PV210_PA_MDMA 0xFA200000
84#define S5PV210_PA_PDMA0 0xE0900000
85#define S5PV210_PA_PDMA1 0xE0A00000
86
87#define S5PV210_PA_MIPI_CSIS 0xFA600000
88
89#define S5PV210_PA_FIMC0 0xFB200000
90#define S5PV210_PA_FIMC1 0xFB300000
91#define S5PV210_PA_FIMC2 0xFB400000
92
93#define S5PV210_PA_JPEG 0xFB600000
94
95#define S5PV210_PA_SDO 0xF9000000
96#define S5PV210_PA_VP 0xF9100000
97#define S5PV210_PA_MIXER 0xF9200000
98#define S5PV210_PA_HDMI 0xFA100000
99#define S5PV210_PA_IIC_HDMIPHY 0xFA900000
100
101/* Compatibiltiy Defines */
102
103#define S3C_PA_FB S5PV210_PA_FB
104#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
105#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
106#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
107#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
108#define S3C_PA_IIC S5PV210_PA_IIC0
109#define S3C_PA_IIC1 S5PV210_PA_IIC1
110#define S3C_PA_IIC2 S5PV210_PA_IIC2
111#define S3C_PA_RTC S5PV210_PA_RTC
112#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
113#define S3C_PA_WDT S5PV210_PA_WATCHDOG
114#define S3C_PA_SPI0 S5PV210_PA_SPI0
115#define S3C_PA_SPI1 S5PV210_PA_SPI1
116
117#define S5P_PA_CHIPID S5PV210_PA_CHIPID
118#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
119#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
120#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
121#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
122#define S5P_PA_MFC S5PV210_PA_MFC
123#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY
124
125#define S5P_PA_SDO S5PV210_PA_SDO
126#define S5P_PA_VP S5PV210_PA_VP
127#define S5P_PA_MIXER S5PV210_PA_MIXER
128#define S5P_PA_HDMI S5PV210_PA_HDMI
129
130#define S5P_PA_ONENAND S5PC110_PA_ONENAND
131#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
132#define S5P_PA_SDRAM S5PV210_PA_SDRAM
133#define S5P_PA_SROMC S5PV210_PA_SROMC
134#define S5P_PA_SYSCON S5PV210_PA_SYSCON
135#define S5P_PA_TIMER S5PV210_PA_TIMER
136
137#define S5P_PA_JPEG S5PV210_PA_JPEG
138
139#define SAMSUNG_PA_ADC S5PV210_PA_ADC
140#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
141#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
142#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER
143
144/* UART */
145
146#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
147
148#define S3C_PA_UART S5PV210_PA_UART
149
150#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
151#define S5P_PA_UART0 S5P_PA_UART(0)
152#define S5P_PA_UART1 S5P_PA_UART(1)
153#define S5P_PA_UART2 S5P_PA_UART(2)
154#define S5P_PA_UART3 S5P_PA_UART(3)
155
156#define S5P_SZ_UART SZ_256
157
158#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h
deleted file mode 100644
index 2d3cfa221d5f..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/memory.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/memory.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x20000000)
17
18/*
19 * Sparsemem support
20 * Physical memory can be located from 0x20000000 to 0x7fffffff,
21 * so MAX_PHYSMEM_BITS is 31.
22 */
23
24#define MAX_PHYSMEM_BITS 31
25#define SECTION_SIZE_BITS 28
26
27#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
deleted file mode 100644
index eba8aea63ed8..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18static inline void s3c_pm_debug_init_uart(void)
19{
20 /* nothing here yet */
21}
22
23static inline void s3c_pm_arch_prepare_irqs(void)
24{
25 __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
26 __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
27}
28
29static inline void s3c_pm_arch_stop_clocks(void)
30{
31 /* nothing here yet */
32}
33
34static inline void s3c_pm_arch_show_resume_irqs(void)
35{
36 /* nothing here yet */
37}
38
39static inline void s3c_pm_arch_update_uart(void __iomem *regs,
40 struct pm_uart_save *save)
41{
42 /* nothing here yet */
43}
44
45static inline void s3c_pm_restored_gpios(void) { }
46static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index e345584d4c34..b14ffcd7f6cc 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -13,7 +13,7 @@
13#ifndef __ASM_ARCH_REGS_CLOCK_H 13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__ 14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15 15
16#include <mach/map.h> 16#include <plat/map-base.h>
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19 19
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
deleted file mode 100644
index de0c89976078..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV210 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18#define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00)
19#define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4))
20
21#define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
22#define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4))
23
24#define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00)
25#define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4))
26
27#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40)
28#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4))
29
30#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
31
32#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
33
34#define EINT_MODE S3C_GPIO_SFN(0xf)
35
36#define EINT_GPIO_0(x) S5PV210_GPH0(x)
37#define EINT_GPIO_1(x) S5PV210_GPH1(x)
38#define EINT_GPIO_2(x) S5PV210_GPH2(x)
39#define EINT_GPIO_3(x) S5PV210_GPH3(x)
40
41#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
deleted file mode 100644
index d8bc1e6c7aaa..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
deleted file mode 100644
index cc37edacda26..000000000000
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ /dev/null
@@ -1,687 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-aquila.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <linux/fb.h>
17#include <linux/i2c.h>
18#include <linux/i2c-gpio.h>
19#include <linux/mfd/max8998.h>
20#include <linux/mfd/wm8994/pdata.h>
21#include <linux/regulator/fixed.h>
22#include <linux/gpio_keys.h>
23#include <linux/input.h>
24#include <linux/gpio.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/setup.h>
29#include <asm/mach-types.h>
30
31#include <video/samsung_fimd.h>
32#include <mach/map.h>
33#include <mach/regs-clock.h>
34
35#include <plat/gpio-cfg.h>
36#include <plat/devs.h>
37#include <plat/cpu.h>
38#include <plat/fb.h>
39#include <plat/fimc-core.h>
40#include <plat/sdhci.h>
41#include <plat/samsung-time.h>
42
43#include "common.h"
44
45/* Following are default values for UCON, ULCON and UFCON UART registers */
46#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
47 S3C2410_UCON_RXILEVEL | \
48 S3C2410_UCON_TXIRQMODE | \
49 S3C2410_UCON_RXIRQMODE | \
50 S3C2410_UCON_RXFIFO_TOI | \
51 S3C2443_UCON_RXERR_IRQEN)
52
53#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
54
55#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
56
57static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
58 [0] = {
59 .hwport = 0,
60 .flags = 0,
61 .ucon = AQUILA_UCON_DEFAULT,
62 .ulcon = AQUILA_ULCON_DEFAULT,
63 /*
64 * Actually UART0 can support 256 bytes fifo, but aquila board
65 * supports 128 bytes fifo because of initial chip bug
66 */
67 .ufcon = AQUILA_UFCON_DEFAULT |
68 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
69 },
70 [1] = {
71 .hwport = 1,
72 .flags = 0,
73 .ucon = AQUILA_UCON_DEFAULT,
74 .ulcon = AQUILA_ULCON_DEFAULT,
75 .ufcon = AQUILA_UFCON_DEFAULT |
76 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
77 },
78 [2] = {
79 .hwport = 2,
80 .flags = 0,
81 .ucon = AQUILA_UCON_DEFAULT,
82 .ulcon = AQUILA_ULCON_DEFAULT,
83 .ufcon = AQUILA_UFCON_DEFAULT |
84 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
85 },
86 [3] = {
87 .hwport = 3,
88 .flags = 0,
89 .ucon = AQUILA_UCON_DEFAULT,
90 .ulcon = AQUILA_ULCON_DEFAULT,
91 .ufcon = AQUILA_UFCON_DEFAULT |
92 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
93 },
94};
95
96/* Frame Buffer */
97static struct s3c_fb_pd_win aquila_fb_win0 = {
98 .max_bpp = 32,
99 .default_bpp = 16,
100 .xres = 480,
101 .yres = 800,
102};
103
104static struct s3c_fb_pd_win aquila_fb_win1 = {
105 .max_bpp = 32,
106 .default_bpp = 16,
107 .xres = 480,
108 .yres = 800,
109};
110
111static struct fb_videomode aquila_lcd_timing = {
112 .left_margin = 16,
113 .right_margin = 16,
114 .upper_margin = 3,
115 .lower_margin = 28,
116 .hsync_len = 2,
117 .vsync_len = 2,
118 .xres = 480,
119 .yres = 800,
120};
121
122static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
123 .win[0] = &aquila_fb_win0,
124 .win[1] = &aquila_fb_win1,
125 .vtiming = &aquila_lcd_timing,
126 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
127 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
128 VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
129 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
130};
131
132/* MAX8998 regulators */
133#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
134
135static struct regulator_init_data aquila_ldo2_data = {
136 .constraints = {
137 .name = "VALIVE_1.1V",
138 .min_uV = 1100000,
139 .max_uV = 1100000,
140 .apply_uV = 1,
141 .always_on = 1,
142 .state_mem = {
143 .enabled = 1,
144 },
145 },
146};
147
148static struct regulator_init_data aquila_ldo3_data = {
149 .constraints = {
150 .name = "VUSB+MIPI_1.1V",
151 .min_uV = 1100000,
152 .max_uV = 1100000,
153 .apply_uV = 1,
154 .always_on = 1,
155 },
156};
157
158static struct regulator_init_data aquila_ldo4_data = {
159 .constraints = {
160 .name = "VDAC_3.3V",
161 .min_uV = 3300000,
162 .max_uV = 3300000,
163 .apply_uV = 1,
164 },
165};
166
167static struct regulator_init_data aquila_ldo5_data = {
168 .constraints = {
169 .name = "VTF_2.8V",
170 .min_uV = 2800000,
171 .max_uV = 2800000,
172 .apply_uV = 1,
173 },
174};
175
176static struct regulator_init_data aquila_ldo6_data = {
177 .constraints = {
178 .name = "VCC_3.3V",
179 .min_uV = 3300000,
180 .max_uV = 3300000,
181 .apply_uV = 1,
182 },
183};
184
185static struct regulator_init_data aquila_ldo7_data = {
186 .constraints = {
187 .name = "VCC_3.0V",
188 .min_uV = 3000000,
189 .max_uV = 3000000,
190 .apply_uV = 1,
191 .boot_on = 1,
192 .always_on = 1,
193 },
194};
195
196static struct regulator_init_data aquila_ldo8_data = {
197 .constraints = {
198 .name = "VUSB+VADC_3.3V",
199 .min_uV = 3300000,
200 .max_uV = 3300000,
201 .apply_uV = 1,
202 .always_on = 1,
203 },
204};
205
206static struct regulator_init_data aquila_ldo9_data = {
207 .constraints = {
208 .name = "VCC+VCAM_2.8V",
209 .min_uV = 2800000,
210 .max_uV = 2800000,
211 .apply_uV = 1,
212 .always_on = 1,
213 },
214};
215
216static struct regulator_init_data aquila_ldo10_data = {
217 .constraints = {
218 .name = "VPLL_1.1V",
219 .min_uV = 1100000,
220 .max_uV = 1100000,
221 .apply_uV = 1,
222 .boot_on = 1,
223 },
224};
225
226static struct regulator_init_data aquila_ldo11_data = {
227 .constraints = {
228 .name = "CAM_IO_2.8V",
229 .min_uV = 2800000,
230 .max_uV = 2800000,
231 .apply_uV = 1,
232 .always_on = 1,
233 },
234};
235
236static struct regulator_init_data aquila_ldo12_data = {
237 .constraints = {
238 .name = "CAM_ISP_1.2V",
239 .min_uV = 1200000,
240 .max_uV = 1200000,
241 .apply_uV = 1,
242 .always_on = 1,
243 },
244};
245
246static struct regulator_init_data aquila_ldo13_data = {
247 .constraints = {
248 .name = "CAM_A_2.8V",
249 .min_uV = 2800000,
250 .max_uV = 2800000,
251 .apply_uV = 1,
252 .always_on = 1,
253 },
254};
255
256static struct regulator_init_data aquila_ldo14_data = {
257 .constraints = {
258 .name = "CAM_CIF_1.8V",
259 .min_uV = 1800000,
260 .max_uV = 1800000,
261 .apply_uV = 1,
262 .always_on = 1,
263 },
264};
265
266static struct regulator_init_data aquila_ldo15_data = {
267 .constraints = {
268 .name = "CAM_AF_3.3V",
269 .min_uV = 3300000,
270 .max_uV = 3300000,
271 .apply_uV = 1,
272 .always_on = 1,
273 },
274};
275
276static struct regulator_init_data aquila_ldo16_data = {
277 .constraints = {
278 .name = "VMIPI_1.8V",
279 .min_uV = 1800000,
280 .max_uV = 1800000,
281 .apply_uV = 1,
282 .always_on = 1,
283 },
284};
285
286static struct regulator_init_data aquila_ldo17_data = {
287 .constraints = {
288 .name = "CAM_8M_1.8V",
289 .min_uV = 1800000,
290 .max_uV = 1800000,
291 .apply_uV = 1,
292 .always_on = 1,
293 },
294};
295
296/* BUCK */
297static struct regulator_consumer_supply buck1_consumer =
298 REGULATOR_SUPPLY("vddarm", NULL);
299
300static struct regulator_consumer_supply buck2_consumer =
301 REGULATOR_SUPPLY("vddint", NULL);
302
303static struct regulator_init_data aquila_buck1_data = {
304 .constraints = {
305 .name = "VARM_1.2V",
306 .min_uV = 1200000,
307 .max_uV = 1200000,
308 .apply_uV = 1,
309 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
310 REGULATOR_CHANGE_STATUS,
311 },
312 .num_consumer_supplies = 1,
313 .consumer_supplies = &buck1_consumer,
314};
315
316static struct regulator_init_data aquila_buck2_data = {
317 .constraints = {
318 .name = "VINT_1.2V",
319 .min_uV = 1200000,
320 .max_uV = 1200000,
321 .apply_uV = 1,
322 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
323 REGULATOR_CHANGE_STATUS,
324 },
325 .num_consumer_supplies = 1,
326 .consumer_supplies = &buck2_consumer,
327};
328
329static struct regulator_init_data aquila_buck3_data = {
330 .constraints = {
331 .name = "VCC_1.8V",
332 .min_uV = 1800000,
333 .max_uV = 1800000,
334 .apply_uV = 1,
335 .state_mem = {
336 .enabled = 1,
337 },
338 },
339};
340
341static struct regulator_init_data aquila_buck4_data = {
342 .constraints = {
343 .name = "CAM_CORE_1.2V",
344 .min_uV = 1200000,
345 .max_uV = 1200000,
346 .apply_uV = 1,
347 .always_on = 1,
348 },
349};
350
351static struct max8998_regulator_data aquila_regulators[] = {
352 { MAX8998_LDO2, &aquila_ldo2_data },
353 { MAX8998_LDO3, &aquila_ldo3_data },
354 { MAX8998_LDO4, &aquila_ldo4_data },
355 { MAX8998_LDO5, &aquila_ldo5_data },
356 { MAX8998_LDO6, &aquila_ldo6_data },
357 { MAX8998_LDO7, &aquila_ldo7_data },
358 { MAX8998_LDO8, &aquila_ldo8_data },
359 { MAX8998_LDO9, &aquila_ldo9_data },
360 { MAX8998_LDO10, &aquila_ldo10_data },
361 { MAX8998_LDO11, &aquila_ldo11_data },
362 { MAX8998_LDO12, &aquila_ldo12_data },
363 { MAX8998_LDO13, &aquila_ldo13_data },
364 { MAX8998_LDO14, &aquila_ldo14_data },
365 { MAX8998_LDO15, &aquila_ldo15_data },
366 { MAX8998_LDO16, &aquila_ldo16_data },
367 { MAX8998_LDO17, &aquila_ldo17_data },
368 { MAX8998_BUCK1, &aquila_buck1_data },
369 { MAX8998_BUCK2, &aquila_buck2_data },
370 { MAX8998_BUCK3, &aquila_buck3_data },
371 { MAX8998_BUCK4, &aquila_buck4_data },
372};
373
374static struct max8998_platform_data aquila_max8998_pdata = {
375 .num_regulators = ARRAY_SIZE(aquila_regulators),
376 .regulators = aquila_regulators,
377 .buck1_set1 = S5PV210_GPH0(3),
378 .buck1_set2 = S5PV210_GPH0(4),
379 .buck2_set3 = S5PV210_GPH0(5),
380 .buck1_voltage = { 1200000, 1200000, 1200000, 1200000 },
381 .buck2_voltage = { 1200000, 1200000 },
382};
383#endif
384
385static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
386 REGULATOR_SUPPLY("DBVDD", "5-001a"),
387 REGULATOR_SUPPLY("AVDD2", "5-001a"),
388 REGULATOR_SUPPLY("CPVDD", "5-001a"),
389};
390
391static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
392 REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
393 REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
394};
395
396static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
397 .constraints = {
398 .always_on = 1,
399 },
400 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
401 .consumer_supplies = wm8994_fixed_voltage0_supplies,
402};
403
404static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
405 .constraints = {
406 .always_on = 1,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
409 .consumer_supplies = wm8994_fixed_voltage1_supplies,
410};
411
412static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
413 .supply_name = "VCC_1.8V_PDA",
414 .microvolts = 1800000,
415 .gpio = -EINVAL,
416 .init_data = &wm8994_fixed_voltage0_init_data,
417};
418
419static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
420 .supply_name = "V_BAT",
421 .microvolts = 3700000,
422 .gpio = -EINVAL,
423 .init_data = &wm8994_fixed_voltage1_init_data,
424};
425
426static struct platform_device wm8994_fixed_voltage0 = {
427 .name = "reg-fixed-voltage",
428 .id = 0,
429 .dev = {
430 .platform_data = &wm8994_fixed_voltage0_config,
431 },
432};
433
434static struct platform_device wm8994_fixed_voltage1 = {
435 .name = "reg-fixed-voltage",
436 .id = 1,
437 .dev = {
438 .platform_data = &wm8994_fixed_voltage1_config,
439 },
440};
441
442static struct regulator_consumer_supply wm8994_avdd1_supply =
443 REGULATOR_SUPPLY("AVDD1", "5-001a");
444
445static struct regulator_consumer_supply wm8994_dcvdd_supply =
446 REGULATOR_SUPPLY("DCVDD", "5-001a");
447
448static struct regulator_init_data wm8994_ldo1_data = {
449 .constraints = {
450 .name = "AVDD1_3.0V",
451 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
452 },
453 .num_consumer_supplies = 1,
454 .consumer_supplies = &wm8994_avdd1_supply,
455};
456
457static struct regulator_init_data wm8994_ldo2_data = {
458 .constraints = {
459 .name = "DCVDD_1.0V",
460 },
461 .num_consumer_supplies = 1,
462 .consumer_supplies = &wm8994_dcvdd_supply,
463};
464
465static struct wm8994_pdata wm8994_platform_data = {
466 /* configure gpio1 function: 0x0001(Logic level input/output) */
467 .gpio_defaults[0] = 0x0001,
468 /* configure gpio3/4/5/7 function for AIF2 voice */
469 .gpio_defaults[2] = 0x8100,
470 .gpio_defaults[3] = 0x8100,
471 .gpio_defaults[4] = 0x8100,
472 .gpio_defaults[6] = 0x0100,
473 /* configure gpio8/9/10/11 function for AIF3 BT */
474 .gpio_defaults[7] = 0x8100,
475 .gpio_defaults[8] = 0x0100,
476 .gpio_defaults[9] = 0x0100,
477 .gpio_defaults[10] = 0x0100,
478 .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
479 .ldo[1] = { 0, &wm8994_ldo2_data },
480};
481
482/* GPIO I2C PMIC */
483#define AP_I2C_GPIO_PMIC_BUS_4 4
484static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
485 .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */
486 .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */
487};
488
489static struct platform_device aquila_i2c_gpio_pmic = {
490 .name = "i2c-gpio",
491 .id = AP_I2C_GPIO_PMIC_BUS_4,
492 .dev = {
493 .platform_data = &aquila_i2c_gpio_pmic_data,
494 },
495};
496
497static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
498#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
499 {
500 /* 0xCC when SRAD = 0 */
501 I2C_BOARD_INFO("max8998", 0xCC >> 1),
502 .platform_data = &aquila_max8998_pdata,
503 },
504#endif
505};
506
507/* GPIO I2C AP 1.8V */
508#define AP_I2C_GPIO_BUS_5 5
509static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
510 .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
511 .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
512};
513
514static struct platform_device aquila_i2c_gpio5 = {
515 .name = "i2c-gpio",
516 .id = AP_I2C_GPIO_BUS_5,
517 .dev = {
518 .platform_data = &aquila_i2c_gpio5_data,
519 },
520};
521
522static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
523 {
524 /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
525 I2C_BOARD_INFO("wm8994", 0x1a),
526 .platform_data = &wm8994_platform_data,
527 },
528};
529
530/* PMIC Power button */
531static struct gpio_keys_button aquila_gpio_keys_table[] = {
532 {
533 .code = KEY_POWER,
534 .gpio = S5PV210_GPH2(6),
535 .desc = "gpio-keys: KEY_POWER",
536 .type = EV_KEY,
537 .active_low = 1,
538 .wakeup = 1,
539 .debounce_interval = 1,
540 },
541};
542
543static struct gpio_keys_platform_data aquila_gpio_keys_data = {
544 .buttons = aquila_gpio_keys_table,
545 .nbuttons = ARRAY_SIZE(aquila_gpio_keys_table),
546};
547
548static struct platform_device aquila_device_gpiokeys = {
549 .name = "gpio-keys",
550 .dev = {
551 .platform_data = &aquila_gpio_keys_data,
552 },
553};
554
555static void __init aquila_pmic_init(void)
556{
557 /* AP_PMIC_IRQ: EINT7 */
558 s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
559 s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
560
561 /* nPower: EINT22 */
562 s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
563 s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
564}
565
566/* MoviNAND */
567static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
568 .max_width = 4,
569 .cd_type = S3C_SDHCI_CD_PERMANENT,
570};
571
572/* Wireless LAN */
573static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
574 .max_width = 4,
575 .cd_type = S3C_SDHCI_CD_EXTERNAL,
576 /* ext_cd_{init,cleanup} callbacks will be added later */
577};
578
579/* External Flash */
580#define AQUILA_EXT_FLASH_EN S5PV210_MP05(4)
581#define AQUILA_EXT_FLASH_CD S5PV210_GPH3(4)
582static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
583 .max_width = 4,
584 .cd_type = S3C_SDHCI_CD_GPIO,
585 .ext_cd_gpio = AQUILA_EXT_FLASH_CD,
586 .ext_cd_gpio_invert = 1,
587};
588
589static void aquila_setup_sdhci(void)
590{
591 gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
592
593 s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
594 s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
595 s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
596};
597
598/* Audio device */
599static struct platform_device aquila_device_audio = {
600 .name = "smdk-audio",
601 .id = -1,
602};
603
604static struct platform_device *aquila_devices[] __initdata = {
605 &aquila_i2c_gpio_pmic,
606 &aquila_i2c_gpio5,
607 &aquila_device_gpiokeys,
608 &aquila_device_audio,
609 &s3c_device_fb,
610 &s5p_device_onenand,
611 &s3c_device_hsmmc0,
612 &s3c_device_hsmmc1,
613 &s3c_device_hsmmc2,
614 &s5p_device_fimc0,
615 &s5p_device_fimc1,
616 &s5p_device_fimc2,
617 &s5p_device_fimc_md,
618 &s5pv210_device_iis0,
619 &wm8994_fixed_voltage0,
620 &wm8994_fixed_voltage1,
621};
622
623static void __init aquila_sound_init(void)
624{
625 unsigned int gpio;
626
627 /* CODEC_XTAL_EN
628 *
629 * The Aquila board have a oscillator which provide main clock
630 * to WM8994 codec. The oscillator provide 24MHz clock to WM8994
631 * clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
632 * */
633 gpio = S5PV210_GPH3(2); /* XEINT_26 */
634 gpio_request(gpio, "CODEC_XTAL_EN");
635 s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
636 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
637
638 /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
639 * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
640 * because it needs 24MHz clock to operate WM8994 codec.
641 */
642 __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
643}
644
645static void __init aquila_map_io(void)
646{
647 s5pv210_init_io(NULL, 0);
648 s3c24xx_init_clocks(24000000);
649 s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
650 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
651}
652
653static void __init aquila_machine_init(void)
654{
655 /* PMIC */
656 aquila_pmic_init();
657 i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
658 ARRAY_SIZE(i2c_gpio_pmic_devs));
659 /* SDHCI */
660 aquila_setup_sdhci();
661
662 s3c_fimc_setname(0, "s5p-fimc");
663 s3c_fimc_setname(1, "s5p-fimc");
664 s3c_fimc_setname(2, "s5p-fimc");
665
666 /* SOUND */
667 aquila_sound_init();
668 i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
669 ARRAY_SIZE(i2c_gpio5_devs));
670
671 /* FB */
672 s3c_fb_set_platdata(&aquila_lcd_pdata);
673
674 platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
675}
676
677MACHINE_START(AQUILA, "Aquila")
678 /* Maintainers:
679 Marek Szyprowski <m.szyprowski@samsung.com>
680 Kyungmin Park <kyungmin.park@samsung.com> */
681 .atag_offset = 0x100,
682 .init_irq = s5pv210_init_irq,
683 .map_io = aquila_map_io,
684 .init_machine = aquila_machine_init,
685 .init_time = samsung_timer_init,
686 .restart = s5pv210_restart,
687MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
deleted file mode 100644
index c1ce921c4088..000000000000
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ /dev/null
@@ -1,916 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-goni.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <linux/fb.h>
17#include <linux/i2c.h>
18#include <linux/i2c-gpio.h>
19#include <linux/i2c/atmel_mxt_ts.h>
20#include <linux/mfd/max8998.h>
21#include <linux/mfd/wm8994/pdata.h>
22#include <linux/regulator/fixed.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/spi_gpio.h>
25#include <linux/lcd.h>
26#include <linux/gpio_keys.h>
27#include <linux/input.h>
28#include <linux/gpio.h>
29#include <linux/mmc/host.h>
30#include <linux/interrupt.h>
31#include <linux/platform_data/s3c-hsotg.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/setup.h>
36#include <asm/mach-types.h>
37
38#include <video/samsung_fimd.h>
39#include <mach/map.h>
40#include <mach/regs-clock.h>
41
42#include <plat/gpio-cfg.h>
43#include <plat/devs.h>
44#include <plat/cpu.h>
45#include <plat/fb.h>
46#include <linux/platform_data/i2c-s3c2410.h>
47#include <plat/keypad.h>
48#include <plat/sdhci.h>
49#include <plat/clock.h>
50#include <plat/samsung-time.h>
51#include <plat/mfc.h>
52
53#include "common.h"
54
55/* Following are default values for UCON, ULCON and UFCON UART registers */
56#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
57 S3C2410_UCON_RXILEVEL | \
58 S3C2410_UCON_TXIRQMODE | \
59 S3C2410_UCON_RXIRQMODE | \
60 S3C2410_UCON_RXFIFO_TOI | \
61 S3C2443_UCON_RXERR_IRQEN)
62
63#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
64
65#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
66
67static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
68 [0] = {
69 .hwport = 0,
70 .flags = 0,
71 .ucon = GONI_UCON_DEFAULT,
72 .ulcon = GONI_ULCON_DEFAULT,
73 .ufcon = GONI_UFCON_DEFAULT |
74 S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
75 },
76 [1] = {
77 .hwport = 1,
78 .flags = 0,
79 .ucon = GONI_UCON_DEFAULT,
80 .ulcon = GONI_ULCON_DEFAULT,
81 .ufcon = GONI_UFCON_DEFAULT |
82 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
83 },
84 [2] = {
85 .hwport = 2,
86 .flags = 0,
87 .ucon = GONI_UCON_DEFAULT,
88 .ulcon = GONI_ULCON_DEFAULT,
89 .ufcon = GONI_UFCON_DEFAULT |
90 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
91 },
92 [3] = {
93 .hwport = 3,
94 .flags = 0,
95 .ucon = GONI_UCON_DEFAULT,
96 .ulcon = GONI_ULCON_DEFAULT,
97 .ufcon = GONI_UFCON_DEFAULT |
98 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
99 },
100};
101
102/* Frame Buffer */
103static struct s3c_fb_pd_win goni_fb_win0 = {
104 .max_bpp = 32,
105 .default_bpp = 16,
106 .xres = 480,
107 .yres = 800,
108 .virtual_x = 480,
109 .virtual_y = 2 * 800,
110};
111
112static struct fb_videomode goni_lcd_timing = {
113 .left_margin = 16,
114 .right_margin = 16,
115 .upper_margin = 2,
116 .lower_margin = 28,
117 .hsync_len = 2,
118 .vsync_len = 1,
119 .xres = 480,
120 .yres = 800,
121 .refresh = 55,
122};
123
124static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
125 .win[0] = &goni_fb_win0,
126 .vtiming = &goni_lcd_timing,
127 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
128 VIDCON0_CLKSEL_LCD,
129 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
130 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
131 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
132};
133
134static int lcd_power_on(struct lcd_device *ld, int enable)
135{
136 return 1;
137}
138
139static int reset_lcd(struct lcd_device *ld)
140{
141 static unsigned int first = 1;
142 int reset_gpio = -1;
143
144 reset_gpio = S5PV210_MP05(5);
145
146 if (first) {
147 gpio_request(reset_gpio, "MLCD_RST");
148 first = 0;
149 }
150
151 gpio_direction_output(reset_gpio, 1);
152 return 1;
153}
154
155static struct lcd_platform_data goni_lcd_platform_data = {
156 .reset = reset_lcd,
157 .power_on = lcd_power_on,
158 .lcd_enabled = 0,
159 .reset_delay = 120, /* 120ms */
160 .power_on_delay = 25, /* 25ms */
161 .power_off_delay = 200, /* 200ms */
162};
163
164#define LCD_BUS_NUM 3
165static struct spi_board_info spi_board_info[] __initdata = {
166 {
167 .modalias = "s6e63m0",
168 .platform_data = &goni_lcd_platform_data,
169 .max_speed_hz = 1200000,
170 .bus_num = LCD_BUS_NUM,
171 .chip_select = 0,
172 .mode = SPI_MODE_3,
173 .controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
174 },
175};
176
177static struct spi_gpio_platform_data lcd_spi_gpio_data = {
178 .sck = S5PV210_MP04(1), /* DISPLAY_CLK */
179 .mosi = S5PV210_MP04(3), /* DISPLAY_SI */
180 .miso = SPI_GPIO_NO_MISO,
181 .num_chipselect = 1,
182};
183
184static struct platform_device goni_spi_gpio = {
185 .name = "spi_gpio",
186 .id = LCD_BUS_NUM,
187 .dev = {
188 .parent = &s3c_device_fb.dev,
189 .platform_data = &lcd_spi_gpio_data,
190 },
191};
192
193/* KEYPAD */
194static uint32_t keymap[] __initdata = {
195 /* KEY(row, col, keycode) */
196 KEY(0, 1, KEY_MENU), /* Send */
197 KEY(0, 2, KEY_BACK), /* End */
198 KEY(1, 1, KEY_CONFIG), /* Half shot */
199 KEY(1, 2, KEY_VOLUMEUP),
200 KEY(2, 1, KEY_CAMERA), /* Full shot */
201 KEY(2, 2, KEY_VOLUMEDOWN),
202};
203
204static struct matrix_keymap_data keymap_data __initdata = {
205 .keymap = keymap,
206 .keymap_size = ARRAY_SIZE(keymap),
207};
208
209static struct samsung_keypad_platdata keypad_data __initdata = {
210 .keymap_data = &keymap_data,
211 .rows = 3,
212 .cols = 3,
213};
214
215/* Radio */
216static struct i2c_board_info i2c1_devs[] __initdata = {
217 {
218 I2C_BOARD_INFO("si470x", 0x10),
219 },
220};
221
222static void __init goni_radio_init(void)
223{
224 int gpio;
225
226 gpio = S5PV210_GPJ2(4); /* XMSMDATA_4 */
227 gpio_request(gpio, "FM_INT");
228 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
229 i2c1_devs[0].irq = gpio_to_irq(gpio);
230
231 gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */
232 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
233}
234
235/* TSP */
236static struct mxt_platform_data qt602240_platform_data = {
237 .irqflags = IRQF_TRIGGER_FALLING,
238};
239
240static struct s3c2410_platform_i2c i2c2_data __initdata = {
241 .flags = 0,
242 .bus_num = 2,
243 .slave_addr = 0x10,
244 .frequency = 400 * 1000,
245 .sda_delay = 100,
246};
247
248static struct i2c_board_info i2c2_devs[] __initdata = {
249 {
250 I2C_BOARD_INFO("qt602240_ts", 0x4a),
251 .platform_data = &qt602240_platform_data,
252 },
253};
254
255static void __init goni_tsp_init(void)
256{
257 int gpio;
258
259 gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */
260 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
261 gpio_export(gpio, 0);
262
263 gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */
264 gpio_request(gpio, "TSP_INT");
265
266 s5p_register_gpio_interrupt(gpio);
267 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
268 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
269 i2c2_devs[0].irq = gpio_to_irq(gpio);
270}
271
272/* USB OTG */
273static struct s3c_hsotg_plat goni_hsotg_pdata;
274
275/* MAX8998 regulators */
276#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
277
278static struct regulator_consumer_supply goni_ldo3_consumers[] = {
279 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
280};
281
282static struct regulator_consumer_supply goni_ldo5_consumers[] = {
283 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
284};
285
286static struct regulator_consumer_supply goni_ldo8_consumers[] = {
287 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
288 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
289};
290
291static struct regulator_consumer_supply goni_ldo11_consumers[] = {
292 REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
293};
294
295static struct regulator_consumer_supply goni_ldo13_consumers[] = {
296 REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
297};
298
299static struct regulator_consumer_supply goni_ldo14_consumers[] = {
300 REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
301};
302
303static struct regulator_init_data goni_ldo2_data = {
304 .constraints = {
305 .name = "VALIVE_1.1V",
306 .min_uV = 1100000,
307 .max_uV = 1100000,
308 .apply_uV = 1,
309 .always_on = 1,
310 .state_mem = {
311 .enabled = 1,
312 },
313 },
314};
315
316static struct regulator_init_data goni_ldo3_data = {
317 .constraints = {
318 .name = "VUSB+MIPI_1.1V",
319 .min_uV = 1100000,
320 .max_uV = 1100000,
321 .apply_uV = 1,
322 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
323 },
324 .num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
325 .consumer_supplies = goni_ldo3_consumers,
326};
327
328static struct regulator_init_data goni_ldo4_data = {
329 .constraints = {
330 .name = "VDAC_3.3V",
331 .min_uV = 3300000,
332 .max_uV = 3300000,
333 .apply_uV = 1,
334 },
335};
336
337static struct regulator_init_data goni_ldo5_data = {
338 .constraints = {
339 .name = "VTF_2.8V",
340 .min_uV = 2800000,
341 .max_uV = 2800000,
342 .apply_uV = 1,
343 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
344 },
345 .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
346 .consumer_supplies = goni_ldo5_consumers,
347};
348
349static struct regulator_init_data goni_ldo6_data = {
350 .constraints = {
351 .name = "VCC_3.3V",
352 .min_uV = 3300000,
353 .max_uV = 3300000,
354 .apply_uV = 1,
355 },
356};
357
358static struct regulator_init_data goni_ldo7_data = {
359 .constraints = {
360 .name = "VLCD_1.8V",
361 .min_uV = 1800000,
362 .max_uV = 1800000,
363 .apply_uV = 1,
364 .always_on = 1,
365 },
366};
367
368static struct regulator_init_data goni_ldo8_data = {
369 .constraints = {
370 .name = "VUSB+VADC_3.3V",
371 .min_uV = 3300000,
372 .max_uV = 3300000,
373 .apply_uV = 1,
374 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
375 },
376 .num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
377 .consumer_supplies = goni_ldo8_consumers,
378};
379
380static struct regulator_init_data goni_ldo9_data = {
381 .constraints = {
382 .name = "VCC+VCAM_2.8V",
383 .min_uV = 2800000,
384 .max_uV = 2800000,
385 .apply_uV = 1,
386 },
387};
388
389static struct regulator_init_data goni_ldo10_data = {
390 .constraints = {
391 .name = "VPLL_1.1V",
392 .min_uV = 1100000,
393 .max_uV = 1100000,
394 .apply_uV = 1,
395 .boot_on = 1,
396 },
397};
398
399static struct regulator_init_data goni_ldo11_data = {
400 .constraints = {
401 .name = "CAM_IO_2.8V",
402 .min_uV = 2800000,
403 .max_uV = 2800000,
404 .apply_uV = 1,
405 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
406 },
407 .num_consumer_supplies = ARRAY_SIZE(goni_ldo11_consumers),
408 .consumer_supplies = goni_ldo11_consumers,
409};
410
411static struct regulator_init_data goni_ldo12_data = {
412 .constraints = {
413 .name = "CAM_ISP_1.2V",
414 .min_uV = 1200000,
415 .max_uV = 1200000,
416 .apply_uV = 1,
417 },
418};
419
420static struct regulator_init_data goni_ldo13_data = {
421 .constraints = {
422 .name = "CAM_A_2.8V",
423 .min_uV = 2800000,
424 .max_uV = 2800000,
425 .apply_uV = 1,
426 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
427 },
428 .num_consumer_supplies = ARRAY_SIZE(goni_ldo13_consumers),
429 .consumer_supplies = goni_ldo13_consumers,
430};
431
432static struct regulator_init_data goni_ldo14_data = {
433 .constraints = {
434 .name = "CAM_CIF_1.8V",
435 .min_uV = 1800000,
436 .max_uV = 1800000,
437 .apply_uV = 1,
438 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
439 },
440 .num_consumer_supplies = ARRAY_SIZE(goni_ldo14_consumers),
441 .consumer_supplies = goni_ldo14_consumers,
442};
443
444static struct regulator_init_data goni_ldo15_data = {
445 .constraints = {
446 .name = "CAM_AF_3.3V",
447 .min_uV = 3300000,
448 .max_uV = 3300000,
449 .apply_uV = 1,
450 },
451};
452
453static struct regulator_init_data goni_ldo16_data = {
454 .constraints = {
455 .name = "VMIPI_1.8V",
456 .min_uV = 1800000,
457 .max_uV = 1800000,
458 .apply_uV = 1,
459 },
460};
461
462static struct regulator_init_data goni_ldo17_data = {
463 .constraints = {
464 .name = "VCC_3.0V_LCD",
465 .min_uV = 3000000,
466 .max_uV = 3000000,
467 .apply_uV = 1,
468 .always_on = 1,
469 },
470};
471
472/* BUCK */
473static struct regulator_consumer_supply buck1_consumer =
474 REGULATOR_SUPPLY("vddarm", NULL);
475
476static struct regulator_consumer_supply buck2_consumer =
477 REGULATOR_SUPPLY("vddint", NULL);
478
479static struct regulator_consumer_supply buck3_consumer =
480 REGULATOR_SUPPLY("vdet", "s5p-sdo");
481
482
483static struct regulator_init_data goni_buck1_data = {
484 .constraints = {
485 .name = "VARM_1.2V",
486 .min_uV = 1200000,
487 .max_uV = 1200000,
488 .apply_uV = 1,
489 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
490 REGULATOR_CHANGE_STATUS,
491 },
492 .num_consumer_supplies = 1,
493 .consumer_supplies = &buck1_consumer,
494};
495
496static struct regulator_init_data goni_buck2_data = {
497 .constraints = {
498 .name = "VINT_1.2V",
499 .min_uV = 1200000,
500 .max_uV = 1200000,
501 .apply_uV = 1,
502 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
503 REGULATOR_CHANGE_STATUS,
504 },
505 .num_consumer_supplies = 1,
506 .consumer_supplies = &buck2_consumer,
507};
508
509static struct regulator_init_data goni_buck3_data = {
510 .constraints = {
511 .name = "VCC_1.8V",
512 .min_uV = 1800000,
513 .max_uV = 1800000,
514 .apply_uV = 1,
515 .state_mem = {
516 .enabled = 1,
517 },
518 },
519 .num_consumer_supplies = 1,
520 .consumer_supplies = &buck3_consumer,
521};
522
523static struct regulator_init_data goni_buck4_data = {
524 .constraints = {
525 .name = "CAM_CORE_1.2V",
526 .min_uV = 1200000,
527 .max_uV = 1200000,
528 .apply_uV = 1,
529 .always_on = 1,
530 },
531};
532
533static struct max8998_regulator_data goni_regulators[] = {
534 { MAX8998_LDO2, &goni_ldo2_data },
535 { MAX8998_LDO3, &goni_ldo3_data },
536 { MAX8998_LDO4, &goni_ldo4_data },
537 { MAX8998_LDO5, &goni_ldo5_data },
538 { MAX8998_LDO6, &goni_ldo6_data },
539 { MAX8998_LDO7, &goni_ldo7_data },
540 { MAX8998_LDO8, &goni_ldo8_data },
541 { MAX8998_LDO9, &goni_ldo9_data },
542 { MAX8998_LDO10, &goni_ldo10_data },
543 { MAX8998_LDO11, &goni_ldo11_data },
544 { MAX8998_LDO12, &goni_ldo12_data },
545 { MAX8998_LDO13, &goni_ldo13_data },
546 { MAX8998_LDO14, &goni_ldo14_data },
547 { MAX8998_LDO15, &goni_ldo15_data },
548 { MAX8998_LDO16, &goni_ldo16_data },
549 { MAX8998_LDO17, &goni_ldo17_data },
550 { MAX8998_BUCK1, &goni_buck1_data },
551 { MAX8998_BUCK2, &goni_buck2_data },
552 { MAX8998_BUCK3, &goni_buck3_data },
553 { MAX8998_BUCK4, &goni_buck4_data },
554};
555
556static struct max8998_platform_data goni_max8998_pdata = {
557 .num_regulators = ARRAY_SIZE(goni_regulators),
558 .regulators = goni_regulators,
559 .buck1_set1 = S5PV210_GPH0(3),
560 .buck1_set2 = S5PV210_GPH0(4),
561 .buck2_set3 = S5PV210_GPH0(5),
562 .buck1_voltage = { 1200000, 1200000, 1200000, 1200000 },
563 .buck2_voltage = { 1200000, 1200000 },
564};
565#endif
566
567static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
568 REGULATOR_SUPPLY("DBVDD", "5-001a"),
569 REGULATOR_SUPPLY("AVDD2", "5-001a"),
570 REGULATOR_SUPPLY("CPVDD", "5-001a"),
571};
572
573static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
574 REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
575 REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
576};
577
578static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
579 .constraints = {
580 .always_on = 1,
581 },
582 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
583 .consumer_supplies = wm8994_fixed_voltage0_supplies,
584};
585
586static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
587 .constraints = {
588 .always_on = 1,
589 },
590 .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
591 .consumer_supplies = wm8994_fixed_voltage1_supplies,
592};
593
594static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
595 .supply_name = "VCC_1.8V_PDA",
596 .microvolts = 1800000,
597 .gpio = -EINVAL,
598 .init_data = &wm8994_fixed_voltage0_init_data,
599};
600
601static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
602 .supply_name = "V_BAT",
603 .microvolts = 3700000,
604 .gpio = -EINVAL,
605 .init_data = &wm8994_fixed_voltage1_init_data,
606};
607
608static struct platform_device wm8994_fixed_voltage0 = {
609 .name = "reg-fixed-voltage",
610 .id = 0,
611 .dev = {
612 .platform_data = &wm8994_fixed_voltage0_config,
613 },
614};
615
616static struct platform_device wm8994_fixed_voltage1 = {
617 .name = "reg-fixed-voltage",
618 .id = 1,
619 .dev = {
620 .platform_data = &wm8994_fixed_voltage1_config,
621 },
622};
623
624static struct regulator_consumer_supply wm8994_avdd1_supply =
625 REGULATOR_SUPPLY("AVDD1", "5-001a");
626
627static struct regulator_consumer_supply wm8994_dcvdd_supply =
628 REGULATOR_SUPPLY("DCVDD", "5-001a");
629
630static struct regulator_init_data wm8994_ldo1_data = {
631 .constraints = {
632 .name = "AVDD1_3.0V",
633 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
634 },
635 .num_consumer_supplies = 1,
636 .consumer_supplies = &wm8994_avdd1_supply,
637};
638
639static struct regulator_init_data wm8994_ldo2_data = {
640 .constraints = {
641 .name = "DCVDD_1.0V",
642 },
643 .num_consumer_supplies = 1,
644 .consumer_supplies = &wm8994_dcvdd_supply,
645};
646
647static struct wm8994_pdata wm8994_platform_data = {
648 /* configure gpio1 function: 0x0001(Logic level input/output) */
649 .gpio_defaults[0] = 0x0001,
650 /* configure gpio3/4/5/7 function for AIF2 voice */
651 .gpio_defaults[2] = 0x8100,
652 .gpio_defaults[3] = 0x8100,
653 .gpio_defaults[4] = 0x8100,
654 .gpio_defaults[6] = 0x0100,
655 /* configure gpio8/9/10/11 function for AIF3 BT */
656 .gpio_defaults[7] = 0x8100,
657 .gpio_defaults[8] = 0x0100,
658 .gpio_defaults[9] = 0x0100,
659 .gpio_defaults[10] = 0x0100,
660 .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data }, /* XM0FRNB_2 */
661 .ldo[1] = { 0, &wm8994_ldo2_data },
662};
663
664/* GPIO I2C PMIC */
665#define AP_I2C_GPIO_PMIC_BUS_4 4
666static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
667 .sda_pin = S5PV210_GPJ4(0), /* XMSMCSN */
668 .scl_pin = S5PV210_GPJ4(3), /* XMSMIRQN */
669};
670
671static struct platform_device goni_i2c_gpio_pmic = {
672 .name = "i2c-gpio",
673 .id = AP_I2C_GPIO_PMIC_BUS_4,
674 .dev = {
675 .platform_data = &goni_i2c_gpio_pmic_data,
676 },
677};
678
679static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
680#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
681 {
682 /* 0xCC when SRAD = 0 */
683 I2C_BOARD_INFO("max8998", 0xCC >> 1),
684 .platform_data = &goni_max8998_pdata,
685 },
686#endif
687};
688
689/* GPIO I2C AP 1.8V */
690#define AP_I2C_GPIO_BUS_5 5
691static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
692 .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
693 .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
694};
695
696static struct platform_device goni_i2c_gpio5 = {
697 .name = "i2c-gpio",
698 .id = AP_I2C_GPIO_BUS_5,
699 .dev = {
700 .platform_data = &goni_i2c_gpio5_data,
701 },
702};
703
704static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
705 {
706 /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
707 I2C_BOARD_INFO("wm8994", 0x1a),
708 .platform_data = &wm8994_platform_data,
709 },
710};
711
712/* PMIC Power button */
713static struct gpio_keys_button goni_gpio_keys_table[] = {
714 {
715 .code = KEY_POWER,
716 .gpio = S5PV210_GPH2(6),
717 .desc = "gpio-keys: KEY_POWER",
718 .type = EV_KEY,
719 .active_low = 1,
720 .wakeup = 1,
721 .debounce_interval = 1,
722 },
723};
724
725static struct gpio_keys_platform_data goni_gpio_keys_data = {
726 .buttons = goni_gpio_keys_table,
727 .nbuttons = ARRAY_SIZE(goni_gpio_keys_table),
728};
729
730static struct platform_device goni_device_gpiokeys = {
731 .name = "gpio-keys",
732 .dev = {
733 .platform_data = &goni_gpio_keys_data,
734 },
735};
736
737static void __init goni_pmic_init(void)
738{
739 /* AP_PMIC_IRQ: EINT7 */
740 s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_SFN(0xf));
741 s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
742
743 /* nPower: EINT22 */
744 s3c_gpio_cfgpin(S5PV210_GPH2(6), S3C_GPIO_SFN(0xf));
745 s3c_gpio_setpull(S5PV210_GPH2(6), S3C_GPIO_PULL_UP);
746}
747
748/* MoviNAND */
749static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
750 .max_width = 4,
751 .cd_type = S3C_SDHCI_CD_PERMANENT,
752};
753
754/* Wireless LAN */
755static struct s3c_sdhci_platdata goni_hsmmc1_data __initdata = {
756 .max_width = 4,
757 .cd_type = S3C_SDHCI_CD_EXTERNAL,
758 /* ext_cd_{init,cleanup} callbacks will be added later */
759};
760
761/* External Flash */
762#define GONI_EXT_FLASH_EN S5PV210_MP05(4)
763#define GONI_EXT_FLASH_CD S5PV210_GPH3(4)
764static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = {
765 .max_width = 4,
766 .cd_type = S3C_SDHCI_CD_GPIO,
767 .ext_cd_gpio = GONI_EXT_FLASH_CD,
768 .ext_cd_gpio_invert = 1,
769};
770
771static struct regulator_consumer_supply mmc2_supplies[] = {
772 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
773};
774
775static struct regulator_init_data mmc2_fixed_voltage_init_data = {
776 .constraints = {
777 .name = "V_TF_2.8V",
778 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
779 },
780 .num_consumer_supplies = ARRAY_SIZE(mmc2_supplies),
781 .consumer_supplies = mmc2_supplies,
782};
783
784static struct fixed_voltage_config mmc2_fixed_voltage_config = {
785 .supply_name = "EXT_FLASH_EN",
786 .microvolts = 2800000,
787 .gpio = GONI_EXT_FLASH_EN,
788 .enable_high = true,
789 .init_data = &mmc2_fixed_voltage_init_data,
790};
791
792static struct platform_device mmc2_fixed_voltage = {
793 .name = "reg-fixed-voltage",
794 .id = 2,
795 .dev = {
796 .platform_data = &mmc2_fixed_voltage_config,
797 },
798};
799
800static void goni_setup_sdhci(void)
801{
802 s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
803 s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
804 s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
805};
806
807/* Audio device */
808static struct platform_device goni_device_audio = {
809 .name = "smdk-audio",
810 .id = -1,
811};
812
813static struct platform_device *goni_devices[] __initdata = {
814 &s3c_device_fb,
815 &s5p_device_onenand,
816 &goni_spi_gpio,
817 &goni_i2c_gpio_pmic,
818 &goni_i2c_gpio5,
819 &goni_device_audio,
820 &mmc2_fixed_voltage,
821 &goni_device_gpiokeys,
822 &s5p_device_mfc,
823 &s5p_device_mfc_l,
824 &s5p_device_mfc_r,
825 &s5p_device_mixer,
826 &s5p_device_sdo,
827 &s3c_device_i2c0,
828 &s3c_device_hsmmc0,
829 &s3c_device_hsmmc1,
830 &s3c_device_hsmmc2,
831 &s5pv210_device_iis0,
832 &s3c_device_usb_hsotg,
833 &samsung_device_keypad,
834 &s3c_device_i2c1,
835 &s3c_device_i2c2,
836 &wm8994_fixed_voltage0,
837 &wm8994_fixed_voltage1,
838};
839
840static void __init goni_sound_init(void)
841{
842 /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
843 * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
844 * because it needs 24MHz clock to operate WM8994 codec.
845 */
846 __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
847}
848
849static void __init goni_map_io(void)
850{
851 s5pv210_init_io(NULL, 0);
852 s3c24xx_init_clocks(clk_xusbxti.rate);
853 s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
854 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
855}
856
857static void __init goni_reserve(void)
858{
859 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
860}
861
862static void __init goni_machine_init(void)
863{
864 /* Radio: call before I2C 1 registeration */
865 goni_radio_init();
866
867 /* I2C0 */
868 s3c_i2c0_set_platdata(NULL);
869
870 /* I2C1 */
871 s3c_i2c1_set_platdata(NULL);
872 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
873
874 /* TSP: call before I2C 2 registeration */
875 goni_tsp_init();
876
877 /* I2C2 */
878 s3c_i2c2_set_platdata(&i2c2_data);
879 i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
880
881 /* PMIC */
882 goni_pmic_init();
883 i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
884 ARRAY_SIZE(i2c_gpio_pmic_devs));
885 /* SDHCI */
886 goni_setup_sdhci();
887
888 /* SOUND */
889 goni_sound_init();
890 i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
891 ARRAY_SIZE(i2c_gpio5_devs));
892
893 /* FB */
894 s3c_fb_set_platdata(&goni_lcd_pdata);
895
896 s3c_hsotg_set_platdata(&goni_hsotg_pdata);
897
898 /* SPI */
899 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
900
901 /* KEYPAD */
902 samsung_keypad_set_platdata(&keypad_data);
903
904 platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
905}
906
907MACHINE_START(GONI, "GONI")
908 /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
909 .atag_offset = 0x100,
910 .init_irq = s5pv210_init_irq,
911 .map_io = goni_map_io,
912 .init_machine = goni_machine_init,
913 .init_time = samsung_timer_init,
914 .reserve = &goni_reserve,
915 .restart = s5pv210_restart,
916MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
deleted file mode 100644
index 448e1d2eeed6..000000000000
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-smdkc110.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/serial_s3c.h>
16#include <linux/i2c.h>
17#include <linux/device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/setup.h>
22#include <asm/mach-types.h>
23
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/devs.h>
28#include <plat/cpu.h>
29#include <linux/platform_data/ata-samsung_cf.h>
30#include <linux/platform_data/i2c-s3c2410.h>
31#include <plat/pm.h>
32#include <plat/samsung-time.h>
33#include <plat/mfc.h>
34
35#include "common.h"
36
37/* Following are default values for UCON, ULCON and UFCON UART registers */
38#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
39 S3C2410_UCON_RXILEVEL | \
40 S3C2410_UCON_TXIRQMODE | \
41 S3C2410_UCON_RXIRQMODE | \
42 S3C2410_UCON_RXFIFO_TOI | \
43 S3C2443_UCON_RXERR_IRQEN)
44
45#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
46
47#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
48 S5PV210_UFCON_TXTRIG4 | \
49 S5PV210_UFCON_RXTRIG4)
50
51static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
52 [0] = {
53 .hwport = 0,
54 .flags = 0,
55 .ucon = SMDKC110_UCON_DEFAULT,
56 .ulcon = SMDKC110_ULCON_DEFAULT,
57 .ufcon = SMDKC110_UFCON_DEFAULT,
58 },
59 [1] = {
60 .hwport = 1,
61 .flags = 0,
62 .ucon = SMDKC110_UCON_DEFAULT,
63 .ulcon = SMDKC110_ULCON_DEFAULT,
64 .ufcon = SMDKC110_UFCON_DEFAULT,
65 },
66 [2] = {
67 .hwport = 2,
68 .flags = 0,
69 .ucon = SMDKC110_UCON_DEFAULT,
70 .ulcon = SMDKC110_ULCON_DEFAULT,
71 .ufcon = SMDKC110_UFCON_DEFAULT,
72 },
73 [3] = {
74 .hwport = 3,
75 .flags = 0,
76 .ucon = SMDKC110_UCON_DEFAULT,
77 .ulcon = SMDKC110_ULCON_DEFAULT,
78 .ufcon = SMDKC110_UFCON_DEFAULT,
79 },
80};
81
82static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
83 .setup_gpio = s5pv210_ide_setup_gpio,
84};
85
86static struct platform_device *smdkc110_devices[] __initdata = {
87 &s5pv210_device_iis0,
88 &s5pv210_device_ac97,
89 &s5pv210_device_spdif,
90 &s3c_device_cfcon,
91 &s3c_device_i2c0,
92 &s3c_device_i2c1,
93 &s3c_device_i2c2,
94 &s3c_device_rtc,
95 &s3c_device_wdt,
96 &s5p_device_fimc0,
97 &s5p_device_fimc1,
98 &s5p_device_fimc2,
99 &s5p_device_fimc_md,
100 &s5p_device_mfc,
101 &s5p_device_mfc_l,
102 &s5p_device_mfc_r,
103};
104
105static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
106 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
107 { I2C_BOARD_INFO("wm8580", 0x1b), },
108};
109
110static struct i2c_board_info smdkc110_i2c_devs1[] __initdata = {
111 /* To Be Updated */
112};
113
114static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = {
115 /* To Be Updated */
116};
117
118static void __init smdkc110_map_io(void)
119{
120 s5pv210_init_io(NULL, 0);
121 s3c24xx_init_clocks(24000000);
122 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
123 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
124}
125
126static void __init smdkc110_reserve(void)
127{
128 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
129}
130
131static void __init smdkc110_machine_init(void)
132{
133 s3c_pm_init();
134
135 s3c_i2c0_set_platdata(NULL);
136 s3c_i2c1_set_platdata(NULL);
137 s3c_i2c2_set_platdata(NULL);
138 i2c_register_board_info(0, smdkc110_i2c_devs0,
139 ARRAY_SIZE(smdkc110_i2c_devs0));
140 i2c_register_board_info(1, smdkc110_i2c_devs1,
141 ARRAY_SIZE(smdkc110_i2c_devs1));
142 i2c_register_board_info(2, smdkc110_i2c_devs2,
143 ARRAY_SIZE(smdkc110_i2c_devs2));
144
145 s3c_ide_set_platdata(&smdkc110_ide_pdata);
146
147 platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
148}
149
150MACHINE_START(SMDKC110, "SMDKC110")
151 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
152 .atag_offset = 0x100,
153 .init_irq = s5pv210_init_irq,
154 .map_io = smdkc110_map_io,
155 .init_machine = smdkc110_machine_init,
156 .init_time = samsung_timer_init,
157 .restart = s5pv210_restart,
158 .reserve = &smdkc110_reserve,
159MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
deleted file mode 100644
index 2a6655fb63e7..000000000000
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ /dev/null
@@ -1,337 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-smdkv210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/serial_core.h>
16#include <linux/serial_s3c.h>
17#include <linux/device.h>
18#include <linux/dm9000.h>
19#include <linux/fb.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/pwm_backlight.h>
23#include <linux/platform_data/s3c-hsotg.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29
30#include <video/platform_lcd.h>
31#include <video/samsung_fimd.h>
32
33#include <mach/map.h>
34#include <mach/regs-clock.h>
35
36#include <plat/regs-srom.h>
37#include <plat/gpio-cfg.h>
38#include <plat/devs.h>
39#include <plat/cpu.h>
40#include <plat/adc.h>
41#include <linux/platform_data/touchscreen-s3c2410.h>
42#include <linux/platform_data/ata-samsung_cf.h>
43#include <linux/platform_data/i2c-s3c2410.h>
44#include <plat/keypad.h>
45#include <plat/pm.h>
46#include <plat/fb.h>
47#include <plat/samsung-time.h>
48#include <plat/backlight.h>
49#include <plat/mfc.h>
50#include <plat/clock.h>
51
52#include "common.h"
53
54/* Following are default values for UCON, ULCON and UFCON UART registers */
55#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
56 S3C2410_UCON_RXILEVEL | \
57 S3C2410_UCON_TXIRQMODE | \
58 S3C2410_UCON_RXIRQMODE | \
59 S3C2410_UCON_RXFIFO_TOI | \
60 S3C2443_UCON_RXERR_IRQEN)
61
62#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
63
64#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
65 S5PV210_UFCON_TXTRIG4 | \
66 S5PV210_UFCON_RXTRIG4)
67
68static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
69 [0] = {
70 .hwport = 0,
71 .flags = 0,
72 .ucon = SMDKV210_UCON_DEFAULT,
73 .ulcon = SMDKV210_ULCON_DEFAULT,
74 .ufcon = SMDKV210_UFCON_DEFAULT,
75 },
76 [1] = {
77 .hwport = 1,
78 .flags = 0,
79 .ucon = SMDKV210_UCON_DEFAULT,
80 .ulcon = SMDKV210_ULCON_DEFAULT,
81 .ufcon = SMDKV210_UFCON_DEFAULT,
82 },
83 [2] = {
84 .hwport = 2,
85 .flags = 0,
86 .ucon = SMDKV210_UCON_DEFAULT,
87 .ulcon = SMDKV210_ULCON_DEFAULT,
88 .ufcon = SMDKV210_UFCON_DEFAULT,
89 },
90 [3] = {
91 .hwport = 3,
92 .flags = 0,
93 .ucon = SMDKV210_UCON_DEFAULT,
94 .ulcon = SMDKV210_ULCON_DEFAULT,
95 .ufcon = SMDKV210_UFCON_DEFAULT,
96 },
97};
98
99static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = {
100 .setup_gpio = s5pv210_ide_setup_gpio,
101};
102
103static uint32_t smdkv210_keymap[] __initdata = {
104 /* KEY(row, col, keycode) */
105 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
106 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
107 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
108 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
109};
110
111static struct matrix_keymap_data smdkv210_keymap_data __initdata = {
112 .keymap = smdkv210_keymap,
113 .keymap_size = ARRAY_SIZE(smdkv210_keymap),
114};
115
116static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
117 .keymap_data = &smdkv210_keymap_data,
118 .rows = 8,
119 .cols = 8,
120};
121
122static struct resource smdkv210_dm9000_resources[] = {
123 [0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1),
124 [1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1),
125 [2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \
126 | IORESOURCE_IRQ_HIGHLEVEL),
127};
128
129static struct dm9000_plat_data smdkv210_dm9000_platdata = {
130 .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
131 .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
132};
133
134static struct platform_device smdkv210_dm9000 = {
135 .name = "dm9000",
136 .id = -1,
137 .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),
138 .resource = smdkv210_dm9000_resources,
139 .dev = {
140 .platform_data = &smdkv210_dm9000_platdata,
141 },
142};
143
144static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
145 unsigned int power)
146{
147 if (power) {
148#if !defined(CONFIG_BACKLIGHT_PWM)
149 gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
150 gpio_free(S5PV210_GPD0(3));
151#endif
152
153 /* fire nRESET on power up */
154 gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
155
156 gpio_set_value(S5PV210_GPH0(6), 0);
157 mdelay(10);
158
159 gpio_set_value(S5PV210_GPH0(6), 1);
160 mdelay(10);
161
162 gpio_free(S5PV210_GPH0(6));
163 } else {
164#if !defined(CONFIG_BACKLIGHT_PWM)
165 gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
166 gpio_free(S5PV210_GPD0(3));
167#endif
168 }
169}
170
171static struct plat_lcd_data smdkv210_lcd_lte480wv_data = {
172 .set_power = smdkv210_lte480wv_set_power,
173};
174
175static struct platform_device smdkv210_lcd_lte480wv = {
176 .name = "platform-lcd",
177 .dev.parent = &s3c_device_fb.dev,
178 .dev.platform_data = &smdkv210_lcd_lte480wv_data,
179};
180
181static struct s3c_fb_pd_win smdkv210_fb_win0 = {
182 .max_bpp = 32,
183 .default_bpp = 24,
184 .xres = 800,
185 .yres = 480,
186};
187
188static struct fb_videomode smdkv210_lcd_timing = {
189 .left_margin = 13,
190 .right_margin = 8,
191 .upper_margin = 7,
192 .lower_margin = 5,
193 .hsync_len = 3,
194 .vsync_len = 1,
195 .xres = 800,
196 .yres = 480,
197};
198
199static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
200 .win[0] = &smdkv210_fb_win0,
201 .vtiming = &smdkv210_lcd_timing,
202 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
203 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
204 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
205};
206
207/* USB OTG */
208static struct s3c_hsotg_plat smdkv210_hsotg_pdata;
209
210static struct platform_device *smdkv210_devices[] __initdata = {
211 &s3c_device_adc,
212 &s3c_device_cfcon,
213 &s3c_device_fb,
214 &s3c_device_hsmmc0,
215 &s3c_device_hsmmc1,
216 &s3c_device_hsmmc2,
217 &s3c_device_hsmmc3,
218 &s3c_device_i2c0,
219 &s3c_device_i2c1,
220 &s3c_device_i2c2,
221 &samsung_device_pwm,
222 &s3c_device_rtc,
223 &s3c_device_ts,
224 &s3c_device_usb_hsotg,
225 &s3c_device_wdt,
226 &s5p_device_fimc0,
227 &s5p_device_fimc1,
228 &s5p_device_fimc2,
229 &s5p_device_fimc_md,
230 &s5p_device_jpeg,
231 &s5p_device_mfc,
232 &s5p_device_mfc_l,
233 &s5p_device_mfc_r,
234 &s5pv210_device_ac97,
235 &s5pv210_device_iis0,
236 &s5pv210_device_spdif,
237 &samsung_asoc_idma,
238 &samsung_device_keypad,
239 &smdkv210_dm9000,
240 &smdkv210_lcd_lte480wv,
241};
242
243static void __init smdkv210_dm9000_init(void)
244{
245 unsigned int tmp;
246
247 gpio_request(S5PV210_MP01(5), "nCS5");
248 s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2));
249 gpio_free(S5PV210_MP01(5));
250
251 tmp = (5 << S5P_SROM_BCX__TACC__SHIFT);
252 __raw_writel(tmp, S5P_SROM_BC5);
253
254 tmp = __raw_readl(S5P_SROM_BW);
255 tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT);
256 tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT);
257 __raw_writel(tmp, S5P_SROM_BW);
258}
259
260static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = {
261 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */
262 { I2C_BOARD_INFO("wm8580", 0x1b), },
263};
264
265static struct i2c_board_info smdkv210_i2c_devs1[] __initdata = {
266 /* To Be Updated */
267};
268
269static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
270 /* To Be Updated */
271};
272
273/* LCD Backlight data */
274static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
275 .no = S5PV210_GPD0(3),
276 .func = S3C_GPIO_SFN(2),
277};
278
279static struct platform_pwm_backlight_data smdkv210_bl_data = {
280 .pwm_id = 3,
281 .pwm_period_ns = 1000,
282 .enable_gpio = -1,
283};
284
285static void __init smdkv210_map_io(void)
286{
287 s5pv210_init_io(NULL, 0);
288 s3c24xx_init_clocks(clk_xusbxti.rate);
289 s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
290 samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
291}
292
293static void __init smdkv210_reserve(void)
294{
295 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
296}
297
298static void __init smdkv210_machine_init(void)
299{
300 s3c_pm_init();
301
302 smdkv210_dm9000_init();
303
304 samsung_keypad_set_platdata(&smdkv210_keypad_data);
305 s3c24xx_ts_set_platdata(NULL);
306
307 s3c_i2c0_set_platdata(NULL);
308 s3c_i2c1_set_platdata(NULL);
309 s3c_i2c2_set_platdata(NULL);
310 i2c_register_board_info(0, smdkv210_i2c_devs0,
311 ARRAY_SIZE(smdkv210_i2c_devs0));
312 i2c_register_board_info(1, smdkv210_i2c_devs1,
313 ARRAY_SIZE(smdkv210_i2c_devs1));
314 i2c_register_board_info(2, smdkv210_i2c_devs2,
315 ARRAY_SIZE(smdkv210_i2c_devs2));
316
317 s3c_ide_set_platdata(&smdkv210_ide_pdata);
318
319 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
320
321 s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
322
323 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
324
325 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
326}
327
328MACHINE_START(SMDKV210, "SMDKV210")
329 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
330 .atag_offset = 0x100,
331 .init_irq = s5pv210_init_irq,
332 .map_io = smdkv210_map_io,
333 .init_machine = smdkv210_machine_init,
334 .init_time = samsung_timer_init,
335 .restart = s5pv210_restart,
336 .reserve = &smdkv210_reserve,
337MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
deleted file mode 100644
index 157805529f26..000000000000
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
2 *
3 * Copyright (c) 2010 aESOP Community
4 * http://www.aesop.or.kr/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/serial_core.h>
16#include <linux/serial_s3c.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/setup.h>
21#include <asm/mach-types.h>
22
23#include <mach/map.h>
24#include <mach/regs-clock.h>
25
26#include <plat/devs.h>
27#include <plat/cpu.h>
28#include <linux/platform_data/i2c-s3c2410.h>
29#include <plat/samsung-time.h>
30
31#include "common.h"
32
33/* Following are default values for UCON, ULCON and UFCON UART registers */
34#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41#define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
42
43#define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = TORBRECK_UCON_DEFAULT,
52 .ulcon = TORBRECK_ULCON_DEFAULT,
53 .ufcon = TORBRECK_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = TORBRECK_UCON_DEFAULT,
59 .ulcon = TORBRECK_ULCON_DEFAULT,
60 .ufcon = TORBRECK_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = TORBRECK_UCON_DEFAULT,
66 .ulcon = TORBRECK_ULCON_DEFAULT,
67 .ufcon = TORBRECK_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = TORBRECK_UCON_DEFAULT,
73 .ulcon = TORBRECK_ULCON_DEFAULT,
74 .ufcon = TORBRECK_UFCON_DEFAULT,
75 },
76};
77
78static struct platform_device *torbreck_devices[] __initdata = {
79 &s5pv210_device_iis0,
80 &s3c_device_cfcon,
81 &s3c_device_hsmmc0,
82 &s3c_device_hsmmc1,
83 &s3c_device_hsmmc2,
84 &s3c_device_hsmmc3,
85 &s3c_device_i2c0,
86 &s3c_device_i2c1,
87 &s3c_device_i2c2,
88 &s3c_device_rtc,
89 &s3c_device_wdt,
90};
91
92static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
93 /* To Be Updated */
94};
95
96static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
97 /* To Be Updated */
98};
99
100static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
101 /* To Be Updated */
102};
103
104static void __init torbreck_map_io(void)
105{
106 s5pv210_init_io(NULL, 0);
107 s3c24xx_init_clocks(24000000);
108 s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
109 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
110}
111
112static void __init torbreck_machine_init(void)
113{
114 s3c_i2c0_set_platdata(NULL);
115 s3c_i2c1_set_platdata(NULL);
116 s3c_i2c2_set_platdata(NULL);
117 i2c_register_board_info(0, torbreck_i2c_devs0,
118 ARRAY_SIZE(torbreck_i2c_devs0));
119 i2c_register_board_info(1, torbreck_i2c_devs1,
120 ARRAY_SIZE(torbreck_i2c_devs1));
121 i2c_register_board_info(2, torbreck_i2c_devs2,
122 ARRAY_SIZE(torbreck_i2c_devs2));
123
124 platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
125}
126
127MACHINE_START(TORBRECK, "TORBRECK")
128 /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
129 .atag_offset = 0x100,
130 .init_irq = s5pv210_init_irq,
131 .map_io = torbreck_map_io,
132 .init_machine = torbreck_machine_init,
133 .init_time = samsung_timer_init,
134 .restart = s5pv210_restart,
135MACHINE_END
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 3cf3f9c8ddd1..123163dd2ab0 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv210/pm.c 1/* linux/arch/arm/mach-s5pv210/pm.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV210 - Power Management support 6 * S5PV210 - Power Management support
@@ -19,65 +19,28 @@
19#include <linux/syscore_ops.h> 19#include <linux/syscore_ops.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <plat/cpu.h> 22#include <asm/cacheflush.h>
23#include <plat/pm.h> 23#include <asm/suspend.h>
24
25#include <plat/pm-common.h>
24 26
25#include <mach/regs-irq.h>
26#include <mach/regs-clock.h> 27#include <mach/regs-clock.h>
27 28
28static struct sleep_save s5pv210_core_save[] = { 29#include "common.h"
29 /* Clock source */
30 SAVE_ITEM(S5P_CLK_SRC0),
31 SAVE_ITEM(S5P_CLK_SRC1),
32 SAVE_ITEM(S5P_CLK_SRC2),
33 SAVE_ITEM(S5P_CLK_SRC3),
34 SAVE_ITEM(S5P_CLK_SRC4),
35 SAVE_ITEM(S5P_CLK_SRC5),
36 SAVE_ITEM(S5P_CLK_SRC6),
37
38 /* Clock source Mask */
39 SAVE_ITEM(S5P_CLK_SRC_MASK0),
40 SAVE_ITEM(S5P_CLK_SRC_MASK1),
41
42 /* Clock Divider */
43 SAVE_ITEM(S5P_CLK_DIV0),
44 SAVE_ITEM(S5P_CLK_DIV1),
45 SAVE_ITEM(S5P_CLK_DIV2),
46 SAVE_ITEM(S5P_CLK_DIV3),
47 SAVE_ITEM(S5P_CLK_DIV4),
48 SAVE_ITEM(S5P_CLK_DIV5),
49 SAVE_ITEM(S5P_CLK_DIV6),
50 SAVE_ITEM(S5P_CLK_DIV7),
51
52 /* Clock Main Gate */
53 SAVE_ITEM(S5P_CLKGATE_MAIN0),
54 SAVE_ITEM(S5P_CLKGATE_MAIN1),
55 SAVE_ITEM(S5P_CLKGATE_MAIN2),
56
57 /* Clock source Peri Gate */
58 SAVE_ITEM(S5P_CLKGATE_PERI0),
59 SAVE_ITEM(S5P_CLKGATE_PERI1),
60
61 /* Clock source SCLK Gate */
62 SAVE_ITEM(S5P_CLKGATE_SCLK0),
63 SAVE_ITEM(S5P_CLKGATE_SCLK1),
64
65 /* Clock IP Clock gate */
66 SAVE_ITEM(S5P_CLKGATE_IP0),
67 SAVE_ITEM(S5P_CLKGATE_IP1),
68 SAVE_ITEM(S5P_CLKGATE_IP2),
69 SAVE_ITEM(S5P_CLKGATE_IP3),
70 SAVE_ITEM(S5P_CLKGATE_IP4),
71
72 /* Clock Blcok and Bus gate */
73 SAVE_ITEM(S5P_CLKGATE_BLOCK),
74 SAVE_ITEM(S5P_CLKGATE_BUS0),
75 30
31static struct sleep_save s5pv210_core_save[] = {
76 /* Clock ETC */ 32 /* Clock ETC */
77 SAVE_ITEM(S5P_CLK_OUT),
78 SAVE_ITEM(S5P_MDNIE_SEL), 33 SAVE_ITEM(S5P_MDNIE_SEL),
79}; 34};
80 35
36/*
37 * VIC wake-up support (TODO)
38 */
39static u32 s5pv210_irqwake_intmask = 0xffffffff;
40
41/*
42 * Suspend helpers.
43 */
81static int s5pv210_cpu_suspend(unsigned long arg) 44static int s5pv210_cpu_suspend(unsigned long arg)
82{ 45{
83 unsigned long tmp; 46 unsigned long tmp;
@@ -102,8 +65,12 @@ static void s5pv210_pm_prepare(void)
102{ 65{
103 unsigned int tmp; 66 unsigned int tmp;
104 67
68 /* Set wake-up mask registers */
69 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
70 __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
71
105 /* ensure at least INFORM0 has the resume address */ 72 /* ensure at least INFORM0 has the resume address */
106 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); 73 __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
107 74
108 tmp = __raw_readl(S5P_SLEEP_CFG); 75 tmp = __raw_readl(S5P_SLEEP_CFG);
109 tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN); 76 tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
@@ -123,26 +90,70 @@ static void s5pv210_pm_prepare(void)
123 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); 90 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
124} 91}
125 92
126static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) 93/*
94 * Suspend operations.
95 */
96static int s5pv210_suspend_enter(suspend_state_t state)
127{ 97{
128 pm_cpu_prep = s5pv210_pm_prepare; 98 int ret;
129 pm_cpu_sleep = s5pv210_cpu_suspend; 99
100 s3c_pm_debug_init();
101
102 S3C_PMDBG("%s: suspending the system...\n", __func__);
103
104 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
105 s5pv210_irqwake_intmask, exynos_get_eint_wake_mask());
106
107 if (s5pv210_irqwake_intmask == -1U
108 && exynos_get_eint_wake_mask() == -1U) {
109 pr_err("%s: No wake-up sources!\n", __func__);
110 pr_err("%s: Aborting sleep\n", __func__);
111 return -EINVAL;
112 }
113
114 s3c_pm_save_uarts();
115 s5pv210_pm_prepare();
116 flush_cache_all();
117 s3c_pm_check_store();
118
119 ret = cpu_suspend(0, s5pv210_cpu_suspend);
120 if (ret)
121 return ret;
122
123 s3c_pm_restore_uarts();
124
125 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
126 __raw_readl(S5P_WAKEUP_STAT));
127
128 s3c_pm_check_restore();
129
130 S3C_PMDBG("%s: resuming the system...\n", __func__);
130 131
131 return 0; 132 return 0;
132} 133}
133 134
134static struct subsys_interface s5pv210_pm_interface = { 135static int s5pv210_suspend_prepare(void)
135 .name = "s5pv210_pm", 136{
136 .subsys = &s5pv210_subsys, 137 s3c_pm_check_prepare();
137 .add_dev = s5pv210_pm_add,
138};
139 138
140static __init int s5pv210_pm_drvinit(void) 139 return 0;
140}
141
142static void s5pv210_suspend_finish(void)
141{ 143{
142 return subsys_interface_register(&s5pv210_pm_interface); 144 s3c_pm_check_cleanup();
143} 145}
144arch_initcall(s5pv210_pm_drvinit);
145 146
147static const struct platform_suspend_ops s5pv210_suspend_ops = {
148 .enter = s5pv210_suspend_enter,
149 .prepare = s5pv210_suspend_prepare,
150 .finish = s5pv210_suspend_finish,
151 .valid = suspend_valid_only_mem,
152};
153
154/*
155 * Syscore operations used to delay restore of certain registers.
156 */
146static void s5pv210_pm_resume(void) 157static void s5pv210_pm_resume(void)
147{ 158{
148 u32 tmp; 159 u32 tmp;
@@ -159,9 +170,11 @@ static struct syscore_ops s5pv210_pm_syscore_ops = {
159 .resume = s5pv210_pm_resume, 170 .resume = s5pv210_pm_resume,
160}; 171};
161 172
162static __init int s5pv210_pm_syscore_init(void) 173/*
174 * Initialization entry point.
175 */
176void __init s5pv210_pm_init(void)
163{ 177{
164 register_syscore_ops(&s5pv210_pm_syscore_ops); 178 register_syscore_ops(&s5pv210_pm_syscore_ops);
165 return 0; 179 suspend_set_ops(&s5pv210_suspend_ops);
166} 180}
167arch_initcall(s5pv210_pm_syscore_init);
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
new file mode 100644
index 000000000000..53feff33d129
--- /dev/null
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -0,0 +1,77 @@
1/*
2 * Samsung's S5PC110/S5PV210 flattened device tree enabled machine.
3 *
4 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
5 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
6 * Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/of_fdt.h>
14#include <linux/of_platform.h>
15
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18#include <asm/system_misc.h>
19
20#include <plat/map-base.h>
21#include <mach/regs-clock.h>
22
23#include "common.h"
24
25static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
26 int depth, void *data)
27{
28 struct map_desc iodesc;
29 const __be32 *reg;
30 int len;
31
32 if (!of_flat_dt_is_compatible(node, "samsung,s5pv210-clock"))
33 return 0;
34
35 reg = of_get_flat_dt_prop(node, "reg", &len);
36 if (reg == NULL || len != (sizeof(unsigned long) * 2))
37 return 0;
38
39 iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
40 iodesc.length = be32_to_cpu(reg[1]) - 1;
41 iodesc.virtual = (unsigned long)S3C_VA_SYS;
42 iodesc.type = MT_DEVICE;
43 iotable_init(&iodesc, 1);
44
45 return 1;
46}
47
48static void __init s5pv210_dt_map_io(void)
49{
50 debug_ll_io_init();
51
52 of_scan_flat_dt(s5pv210_fdt_map_sys, NULL);
53}
54
55static void s5pv210_dt_restart(enum reboot_mode mode, const char *cmd)
56{
57 __raw_writel(0x1, S5P_SWRESET);
58}
59
60static void __init s5pv210_dt_init_late(void)
61{
62 platform_device_register_simple("s5pv210-cpufreq", -1, NULL, 0);
63 s5pv210_pm_init();
64}
65
66static char const *s5pv210_dt_compat[] __initconst = {
67 "samsung,s5pc110",
68 "samsung,s5pv210",
69 NULL
70};
71
72DT_MACHINE_START(S5PV210_DT, "Samsung S5PC110/S5PV210-based board")
73 .dt_compat = s5pv210_dt_compat,
74 .map_io = s5pv210_dt_map_io,
75 .restart = s5pv210_dt_restart,
76 .init_late = s5pv210_dt_init_late,
77MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
deleted file mode 100644
index 55103c8220b3..000000000000
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Base s5pv210 setup information for 24bpp LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/fb.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <plat/fb.h>
20#include <mach/regs-clock.h>
21#include <plat/gpio-cfg.h>
22
23static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
24{
25 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
26
27 for (; nr > 0; nr--, base++)
28 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
29}
30
31
32void s5pv210_fb_gpio_setup_24bpp(void)
33{
34 s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
35 s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
36 s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
37 s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
38
39 /* Set DISPLAY_CONTROL register for Display path selection.
40 *
41 * ouput | RGB | I80 | ITU
42 * -----------------------------------
43 * 00 | MIE | FIMD | FIMD
44 * 01 | MDNIE | MDNIE | FIMD
45 * 10 | FIMD | FIMD | FIMD
46 * 11 | FIMD | FIMD | FIMD
47 */
48 writel(0x2, S5P_MDNIE_SEL);
49}
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c
deleted file mode 100644
index 54cc5b11be0b..000000000000
--- a/arch/arm/mach-s5pv210/setup-fimc.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5PV210 camera interface GPIO configuration.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13#include <plat/camport.h>
14
15int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
16{
17 u32 gpio8, gpio5;
18 int ret;
19
20 switch (id) {
21 case S5P_CAMPORT_A:
22 gpio8 = S5PV210_GPE0(0);
23 gpio5 = S5PV210_GPE1(0);
24 break;
25
26 case S5P_CAMPORT_B:
27 gpio8 = S5PV210_GPJ0(0);
28 gpio5 = S5PV210_GPJ1(0);
29 break;
30
31 default:
32 WARN(1, "Wrong camport id: %d\n", id);
33 return -EINVAL;
34 }
35
36 ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
37 S3C_GPIO_PULL_UP);
38 if (ret)
39 return ret;
40
41 return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
42 S3C_GPIO_PULL_UP);
43}
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
deleted file mode 100644
index 4a15849766c0..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
deleted file mode 100644
index 4777f6b97a92..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-i2c1.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C1 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c1.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
deleted file mode 100644
index bbce6c74b915..000000000000
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-i2c2.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C2 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c2_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
deleted file mode 100644
index ea123d546bd2..000000000000
--- a/arch/arm/mach-s5pv210/setup-ide.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV210 setup information for IDE
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15
16#include <plat/gpio-cfg.h>
17
18static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
19{
20 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
21
22 for (; nr > 0; nr--, base++)
23 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
24}
25
26void s5pv210_ide_setup_gpio(void)
27{
28 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
29 s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
30
31 /* CF_Data[0 - 7] */
32 s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
33
34 /* CF_Data[8 - 15] */
35 s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
36
37 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
38 s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
39}
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
deleted file mode 100644
index c56420a52f48..000000000000
--- a/arch/arm/mach-s5pv210/setup-keypad.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pv210/setup-keypad.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co.Ltd
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/gpio.h>
15#include <plat/gpio-cfg.h>
16
17void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
18{
19 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
20 s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3));
21
22 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
23 s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3));
24}
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
deleted file mode 100644
index 0512ada00522..000000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,103 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/sdhci.h>
24
25void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
26{
27 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
28
29 /* Set all the necessary GPG0/GPG1 pins to special-function 2 */
30 s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2));
31
32 switch (width) {
33 case 8:
34 /* GPG1[3:6] special-function 3 */
35 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
36 case 4:
37 /* GPG0[3:6] special-function 2 */
38 s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
39 default:
40 break;
41 }
42
43 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
44 s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
45 s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
46 }
47}
48
49void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
50{
51 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
52
53 /* Set all the necessary GPG1[0:1] pins to special-function 2 */
54 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2));
55
56 /* Data pin GPG1[3:6] to special-function 2 */
57 s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2));
58
59 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
60 s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
61 s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
62 }
63}
64
65void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
66{
67 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
68
69 /* Set all the necessary GPG2[0:1] pins to special-function 2 */
70 s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2));
71
72 switch (width) {
73 case 8:
74 /* Data pin GPG3[3:6] to special-function 3 */
75 s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3));
76 case 4:
77 /* Data pin GPG2[3:6] to special-function 2 */
78 s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2));
79 default:
80 break;
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
85 s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
86 }
87}
88
89void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
90{
91 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
92
93 /* Set all the necessary GPG3[0:1] pins to special-function 2 */
94 s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2));
95
96 /* Data pin GPG3[3:6] to special-function 2 */
97 s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2));
98
99 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
100 s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
101 s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
102 }
103}
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
deleted file mode 100644
index 81aecc162f82..000000000000
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
18 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
19 s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
20 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
21 return 0;
22}
23#endif
24
25#ifdef CONFIG_S3C64XX_DEV_SPI1
26int s3c64xx_spi1_cfg_gpio(void)
27{
28 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
30 s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
31 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
32 return 0;
33}
34#endif
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
deleted file mode 100644
index b2ee5333f89c..000000000000
--- a/arch/arm/mach-s5pv210/setup-usb-phy.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundationr
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15
16#include <mach/map.h>
17
18#include <plat/cpu.h>
19#include <plat/regs-usb-hsotg-phy.h>
20#include <plat/usb-phy.h>
21
22#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
23#define S5PV210_USB_PHY0_EN (1 << 0)
24#define S5PV210_USB_PHY1_EN (1 << 1)
25
26static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
27{
28 struct clk *xusbxti;
29 u32 phyclk;
30
31 writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
32 S5PV210_USB_PHY_CON);
33
34 /* set clock frequency for PLL */
35 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
36
37 xusbxti = clk_get(&pdev->dev, "xusbxti");
38 if (xusbxti && !IS_ERR(xusbxti)) {
39 switch (clk_get_rate(xusbxti)) {
40 case 12 * MHZ:
41 phyclk |= S3C_PHYCLK_CLKSEL_12M;
42 break;
43 case 24 * MHZ:
44 phyclk |= S3C_PHYCLK_CLKSEL_24M;
45 break;
46 default:
47 case 48 * MHZ:
48 /* default reference clock */
49 break;
50 }
51 clk_put(xusbxti);
52 }
53
54 /* TODO: select external clock/oscillator */
55 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
56
57 /* set to normal OTG PHY */
58 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
59 mdelay(1);
60
61 /* reset OTG PHY and Link */
62 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
63 S3C_RSTCON);
64 udelay(20); /* at-least 10uS */
65 writel(0, S3C_RSTCON);
66
67 return 0;
68}
69
70static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
71{
72 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
73 S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
74
75 writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
76 S5PV210_USB_PHY_CON);
77
78 return 0;
79}
80
81int s5p_usb_phy_init(struct platform_device *pdev, int type)
82{
83 if (type == USB_PHY_TYPE_DEVICE)
84 return s5pv210_usb_otgphy_init(pdev);
85
86 return -EINVAL;
87}
88
89int s5p_usb_phy_exit(struct platform_device *pdev, int type)
90{
91 if (type == USB_PHY_TYPE_DEVICE)
92 return s5pv210_usb_otgphy_exit(pdev);
93
94 return -EINVAL;
95}
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/mach-s5pv210/sleep.S
index 25c68ceb9e2b..7c43ddd33ba8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com 3 * http://www.samsung.com
4 * 4 *
5 * Common S5P Sleep Code 5 * S5PV210 Sleep Code
6 * Based on S3C64XX sleep code by: 6 * Based on S3C64XX sleep code by:
7 * Ben Dooks, (c) 2008 Simtec Electronics 7 * Ben Dooks, (c) 2008 Simtec Electronics
8 * 8 *
@@ -10,16 +10,7 @@
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 */
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23 14
24#include <linux/linkage.h> 15#include <linux/linkage.h>
25 16
@@ -40,6 +31,6 @@
40 * resume code entry for bootloader to call 31 * resume code entry for bootloader to call
41 */ 32 */
42 33
43ENTRY(s3c_cpu_resume) 34ENTRY(s5pv210_cpu_resume)
44 b cpu_resume 35 b cpu_resume
45ENDPROC(s3c_cpu_resume) 36ENDPROC(s5pv210_cpu_resume)
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 1c629c2c270f..1091b0a3729a 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,30 +6,16 @@
6 6
7config PLAT_SAMSUNG 7config PLAT_SAMSUNG
8 bool 8 bool
9 depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS 9 depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210
10 default y 10 default y
11 select GENERIC_IRQ_CHIP 11 select GENERIC_IRQ_CHIP
12 select NO_IOPORT_MAP 12 select NO_IOPORT_MAP
13 help 13 help
14 Base platform code for all Samsung SoC based systems 14 Base platform code for all Samsung SoC based systems
15 15
16config PLAT_S5P
17 bool
18 depends on ARCH_S5PV210
19 default y
20 select ARCH_REQUIRE_GPIOLIB
21 select ARM_VIC
22 select NO_IOPORT_MAP
23 select PLAT_SAMSUNG
24 select S3C_GPIO_TRACK
25 select S5P_GPIO_DRVSTR
26 select SAMSUNG_CLKSRC if !COMMON_CLK
27 help
28 Base platform code for Samsung's S5P series SoC.
29
30config SAMSUNG_PM 16config SAMSUNG_PM
31 bool 17 bool
32 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM) 18 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX)
33 default y 19 default y
34 help 20 help
35 Base platform power management code for samsung code 21 Base platform power management code for samsung code
@@ -65,48 +51,6 @@ config SAMSUNG_ATAGS
65 51
66if SAMSUNG_ATAGS 52if SAMSUNG_ATAGS
67 53
68# clock options
69
70config SAMSUNG_CLOCK
71 bool
72 default y if !COMMON_CLK
73
74config SAMSUNG_CLKSRC
75 bool
76 help
77 Select the clock code for the clksrc implementation
78 used by newer systems such as the S3C64XX.
79
80config S5P_CLOCK
81 def_bool ARCH_S5PV210
82 help
83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
84
85# options for IRQ support
86
87config S5P_IRQ
88 def_bool ARCH_S5PV210
89 help
90 Support common interrupt part for ARCH_S5P SoCs
91
92config S5P_EXT_INT
93 bool
94 help
95 Use the external interrupts (other than GPIO interrupts.)
96
97config S5P_GPIO_INT
98 bool
99 help
100 Common code for the GPIO interrupts (other than external interrupts.)
101
102# options for gpio configuration support
103
104config S5P_GPIO_DRVSTR
105 bool
106 help
107 Internal configuration to get and set correct GPIO driver strength
108 helper
109
110config SAMSUNG_GPIO_EXTRA 54config SAMSUNG_GPIO_EXTRA
111 int "Number of additional GPIO pins" 55 int "Number of additional GPIO pins"
112 default 128 if SAMSUNG_GPIO_EXTRA128 56 default 128 if SAMSUNG_GPIO_EXTRA128
@@ -138,12 +82,6 @@ config S3C_GPIO_TRACK
138 Internal configuration option to enable the s3c specific gpio 82 Internal configuration option to enable the s3c specific gpio
139 chip tracking if the platform requires it. 83 chip tracking if the platform requires it.
140 84
141# uart options
142
143config S5P_DEV_UART
144 def_bool y
145 depends on ARCH_S5PV210
146
147# ADC driver 85# ADC driver
148 86
149config S3C_ADC 87config S3C_ADC
@@ -301,66 +239,6 @@ config SAMSUNG_DEV_BACKLIGHT
301 help 239 help
302 Compile in platform device definition LCD backlight with PWM Timer 240 Compile in platform device definition LCD backlight with PWM Timer
303 241
304config S5P_DEV_CSIS0
305 bool
306 help
307 Compile in platform device definitions for MIPI-CSIS channel 0
308
309config S5P_DEV_CSIS1
310 bool
311 help
312 Compile in platform device definitions for MIPI-CSIS channel 1
313
314config S5P_DEV_FIMC0
315 bool
316 help
317 Compile in platform device definitions for FIMC controller 0
318
319config S5P_DEV_FIMC1
320 bool
321 help
322 Compile in platform device definitions for FIMC controller 1
323
324config S5P_DEV_FIMC2
325 bool
326 help
327 Compile in platform device definitions for FIMC controller 2
328
329config S5P_DEV_FIMC3
330 bool
331 help
332 Compile in platform device definitions for FIMC controller 3
333
334config S5P_DEV_FIMD0
335 bool
336 help
337 Compile in platform device definitions for FIMD controller 0
338
339config S5P_DEV_G2D
340 bool
341 help
342 Compile in platform device definitions for G2D device
343
344config S5P_DEV_I2C_HDMIPHY
345 bool
346 help
347 Compile in platform device definitions for I2C HDMIPHY controller
348
349config S5P_DEV_JPEG
350 bool
351 help
352 Compile in platform device definitions for JPEG codec
353
354config S5P_DEV_ONENAND
355 bool
356 help
357 Compile in platform device definition for OneNAND controller
358
359config S5P_DEV_TV
360 bool
361 help
362 Compile in platform device definition for TV interface
363
364config S3C24XX_PWM 242config S3C24XX_PWM
365 bool "PWM device support" 243 bool "PWM device support"
366 select PWM 244 select PWM
@@ -381,12 +259,6 @@ config S3C_DMA
381 help 259 help
382 Internal configuration for S3C DMA core 260 Internal configuration for S3C DMA core
383 261
384config S5P_IRQ_PM
385 bool
386 default y if S5P_PM
387 help
388 Legacy IRQ power management for S5P platforms
389
390config SAMSUNG_PM_GPIO 262config SAMSUNG_PM_GPIO
391 bool 263 bool
392 default y if GPIO_SAMSUNG && PM 264 default y if GPIO_SAMSUNG && PM
@@ -469,17 +341,6 @@ config SAMSUNG_WDT_RESET
469 Compile support for system restart by triggering watchdog reset. 341 Compile support for system restart by triggering watchdog reset.
470 Used on SoCs that do not provide dedicated reset control. 342 Used on SoCs that do not provide dedicated reset control.
471 343
472config S5P_PM
473 bool
474 help
475 Common code for power management support on S5P and newer SoCs
476
477config S5P_SLEEP
478 bool
479 help
480 Internal config node to apply common S5P sleep management code.
481 Can be selected by S5P and newer SoCs with similar sleep procedure.
482
483config DEBUG_S3C_UART 344config DEBUG_S3C_UART
484 depends on PLAT_SAMSUNG 345 depends on PLAT_SAMSUNG
485 int 346 int
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 5e5beaa9ae15..5fe175017f07 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -5,7 +5,6 @@
5# Licensed under GPLv2 5# Licensed under GPLv2
6 6
7ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include 7ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
8ccflags-$(CONFIG_ARCH_EXYNOS) += -I$(srctree)/arch/arm/mach-exynos/include
9 8
10obj-y := 9obj-y :=
11obj-m := 10obj-m :=
@@ -16,15 +15,6 @@ obj- :=
16 15
17obj-y += init.o cpu.o 16obj-y += init.o cpu.o
18 17
19obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
20
21obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
22obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
23
24obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
25obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
26obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
27
28# ADC 18# ADC
29 19
30obj-$(CONFIG_S3C_ADC) += adc.o 20obj-$(CONFIG_S3C_ADC) += adc.o
@@ -36,7 +26,6 @@ obj-$(CONFIG_SAMSUNG_ATAGS) += platformdata.o
36obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o 26obj-$(CONFIG_SAMSUNG_ATAGS) += devs.o
37obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o 27obj-$(CONFIG_SAMSUNG_ATAGS) += dev-uart.o
38obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o 28obj-$(CONFIG_S5P_DEV_MFC) += s5p-dev-mfc.o
39obj-$(CONFIG_S5P_DEV_UART) += s5p-dev-uart.o
40 29
41obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o 30obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
42 31
@@ -58,7 +47,3 @@ obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o
58 47
59obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o 48obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
60obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o 49obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
61
62obj-$(CONFIG_S5P_PM) += s5p-pm.o
63obj-$(CONFIG_S5P_IRQ_PM) += s5p-irq-pm.o
64obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
deleted file mode 100644
index 786a4107a157..000000000000
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/* linux/arch/arm/plat-samsung/clock-clksrc.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/io.h>
21
22#include <plat/clock.h>
23#include <plat/clock-clksrc.h>
24#include <plat/cpu-freq.h>
25
26static inline struct clksrc_clk *to_clksrc(struct clk *clk)
27{
28 return container_of(clk, struct clksrc_clk, clk);
29}
30
31static inline u32 bit_mask(u32 shift, u32 nr_bits)
32{
33 u32 mask = 0xffffffff >> (32 - nr_bits);
34
35 return mask << shift;
36}
37
38static unsigned long s3c_getrate_clksrc(struct clk *clk)
39{
40 struct clksrc_clk *sclk = to_clksrc(clk);
41 unsigned long rate = clk_get_rate(clk->parent);
42 u32 clkdiv = __raw_readl(sclk->reg_div.reg);
43 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
44
45 clkdiv &= mask;
46 clkdiv >>= sclk->reg_div.shift;
47 clkdiv++;
48
49 rate /= clkdiv;
50 return rate;
51}
52
53static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
54{
55 struct clksrc_clk *sclk = to_clksrc(clk);
56 void __iomem *reg = sclk->reg_div.reg;
57 unsigned int div;
58 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
59 u32 val;
60
61 rate = clk_round_rate(clk, rate);
62 div = clk_get_rate(clk->parent) / rate;
63 if (div > (1 << sclk->reg_div.size))
64 return -EINVAL;
65
66 val = __raw_readl(reg);
67 val &= ~mask;
68 val |= (div - 1) << sclk->reg_div.shift;
69 __raw_writel(val, reg);
70
71 return 0;
72}
73
74static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
75{
76 struct clksrc_clk *sclk = to_clksrc(clk);
77 struct clksrc_sources *srcs = sclk->sources;
78 u32 clksrc = __raw_readl(sclk->reg_src.reg);
79 u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
80 int src_nr = -1;
81 int ptr;
82
83 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
84 if (srcs->sources[ptr] == parent) {
85 src_nr = ptr;
86 break;
87 }
88
89 if (src_nr >= 0) {
90 clk->parent = parent;
91
92 clksrc &= ~mask;
93 clksrc |= src_nr << sclk->reg_src.shift;
94
95 __raw_writel(clksrc, sclk->reg_src.reg);
96 return 0;
97 }
98
99 return -EINVAL;
100}
101
102static unsigned long s3c_roundrate_clksrc(struct clk *clk,
103 unsigned long rate)
104{
105 struct clksrc_clk *sclk = to_clksrc(clk);
106 unsigned long parent_rate = clk_get_rate(clk->parent);
107 int max_div = 1 << sclk->reg_div.size;
108 int div;
109
110 if (rate >= parent_rate)
111 rate = parent_rate;
112 else {
113 div = parent_rate / rate;
114 if (parent_rate % rate)
115 div++;
116
117 if (div == 0)
118 div = 1;
119 if (div > max_div)
120 div = max_div;
121
122 rate = parent_rate / div;
123 }
124
125 return rate;
126}
127
128/* Clock initialisation code */
129
130void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
131{
132 struct clksrc_sources *srcs = clk->sources;
133 u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
134 u32 clksrc;
135
136 if (!clk->reg_src.reg) {
137 if (!clk->clk.parent)
138 printk(KERN_ERR "%s: no parent clock specified\n",
139 clk->clk.name);
140 return;
141 }
142
143 clksrc = __raw_readl(clk->reg_src.reg);
144 clksrc &= mask;
145 clksrc >>= clk->reg_src.shift;
146
147 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
148 printk(KERN_ERR "%s: bad source %d\n",
149 clk->clk.name, clksrc);
150 return;
151 }
152
153 clk->clk.parent = srcs->sources[clksrc];
154
155 if (announce)
156 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
157 clk->clk.name, clk->clk.parent->name, clksrc,
158 clk_get_rate(&clk->clk));
159}
160
161static struct clk_ops clksrc_ops = {
162 .set_parent = s3c_setparent_clksrc,
163 .get_rate = s3c_getrate_clksrc,
164 .set_rate = s3c_setrate_clksrc,
165 .round_rate = s3c_roundrate_clksrc,
166};
167
168static struct clk_ops clksrc_ops_nodiv = {
169 .set_parent = s3c_setparent_clksrc,
170};
171
172static struct clk_ops clksrc_ops_nosrc = {
173 .get_rate = s3c_getrate_clksrc,
174 .set_rate = s3c_setrate_clksrc,
175 .round_rate = s3c_roundrate_clksrc,
176};
177
178void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
179{
180 int ret;
181
182 for (; size > 0; size--, clksrc++) {
183 if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
184 printk(KERN_ERR "%s: clock %s has no registers set\n",
185 __func__, clksrc->clk.name);
186
187 /* fill in the default functions */
188
189 if (!clksrc->clk.ops) {
190 if (!clksrc->reg_div.reg)
191 clksrc->clk.ops = &clksrc_ops_nodiv;
192 else if (!clksrc->reg_src.reg)
193 clksrc->clk.ops = &clksrc_ops_nosrc;
194 else
195 clksrc->clk.ops = &clksrc_ops;
196 }
197
198 /* setup the clocksource, but do not announce it
199 * as it may be re-set by the setup routines
200 * called after the rest of the clocks have been
201 * registered
202 */
203 s3c_set_clksrc(clksrc, false);
204
205 ret = s3c24xx_register_clock(&clksrc->clk);
206
207 if (ret < 0) {
208 printk(KERN_ERR "%s: failed to register %s (%d)\n",
209 __func__, clksrc->clk.name, ret);
210 }
211 }
212}
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
deleted file mode 100644
index d103ac1a52af..000000000000
--- a/arch/arm/plat-samsung/clock.c
+++ /dev/null
@@ -1,539 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/clock.c
2 *
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Core clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/device.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h>
40#include <linux/spinlock.h>
41#include <linux/io.h>
42#if defined(CONFIG_DEBUG_FS)
43#include <linux/debugfs.h>
44#endif
45
46#include <asm/irq.h>
47
48#include <plat/cpu-freq.h>
49
50#include <plat/clock.h>
51#include <plat/cpu.h>
52
53#include <linux/serial_core.h>
54#include <linux/serial_s3c.h> /* for s3c24xx_uart_devs */
55
56/* clock information */
57
58static LIST_HEAD(clocks);
59
60/* We originally used an mutex here, but some contexts (see resume)
61 * are calling functions such as clk_set_parent() with IRQs disabled
62 * causing an BUG to be triggered.
63 */
64DEFINE_SPINLOCK(clocks_lock);
65
66/* Global watchdog clock used by arch_wtd_reset() callback */
67struct clk *s3c2410_wdtclk;
68static int __init s3c_wdt_reset_init(void)
69{
70 s3c2410_wdtclk = clk_get(NULL, "watchdog");
71 if (IS_ERR(s3c2410_wdtclk))
72 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
73 return 0;
74}
75arch_initcall(s3c_wdt_reset_init);
76
77/* enable and disable calls for use with the clk struct */
78
79static int clk_null_enable(struct clk *clk, int enable)
80{
81 return 0;
82}
83
84int clk_enable(struct clk *clk)
85{
86 unsigned long flags;
87
88 if (IS_ERR(clk) || clk == NULL)
89 return -EINVAL;
90
91 clk_enable(clk->parent);
92
93 spin_lock_irqsave(&clocks_lock, flags);
94
95 if ((clk->usage++) == 0)
96 (clk->enable)(clk, 1);
97
98 spin_unlock_irqrestore(&clocks_lock, flags);
99 return 0;
100}
101
102void clk_disable(struct clk *clk)
103{
104 unsigned long flags;
105
106 if (IS_ERR(clk) || clk == NULL)
107 return;
108
109 spin_lock_irqsave(&clocks_lock, flags);
110
111 if ((--clk->usage) == 0)
112 (clk->enable)(clk, 0);
113
114 spin_unlock_irqrestore(&clocks_lock, flags);
115 clk_disable(clk->parent);
116}
117
118
119unsigned long clk_get_rate(struct clk *clk)
120{
121 if (IS_ERR_OR_NULL(clk))
122 return 0;
123
124 if (clk->rate != 0)
125 return clk->rate;
126
127 if (clk->ops != NULL && clk->ops->get_rate != NULL)
128 return (clk->ops->get_rate)(clk);
129
130 if (clk->parent != NULL)
131 return clk_get_rate(clk->parent);
132
133 return clk->rate;
134}
135
136long clk_round_rate(struct clk *clk, unsigned long rate)
137{
138 if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
139 return (clk->ops->round_rate)(clk, rate);
140
141 return rate;
142}
143
144int clk_set_rate(struct clk *clk, unsigned long rate)
145{
146 unsigned long flags;
147 int ret;
148
149 if (IS_ERR_OR_NULL(clk))
150 return -EINVAL;
151
152 /* We do not default just do a clk->rate = rate as
153 * the clock may have been made this way by choice.
154 */
155
156 WARN_ON(clk->ops == NULL);
157 WARN_ON(clk->ops && clk->ops->set_rate == NULL);
158
159 if (clk->ops == NULL || clk->ops->set_rate == NULL)
160 return -EINVAL;
161
162 spin_lock_irqsave(&clocks_lock, flags);
163 ret = (clk->ops->set_rate)(clk, rate);
164 spin_unlock_irqrestore(&clocks_lock, flags);
165
166 return ret;
167}
168
169struct clk *clk_get_parent(struct clk *clk)
170{
171 return clk->parent;
172}
173
174int clk_set_parent(struct clk *clk, struct clk *parent)
175{
176 unsigned long flags;
177 int ret = 0;
178
179 if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
180 return -EINVAL;
181
182 spin_lock_irqsave(&clocks_lock, flags);
183
184 if (clk->ops && clk->ops->set_parent)
185 ret = (clk->ops->set_parent)(clk, parent);
186
187 spin_unlock_irqrestore(&clocks_lock, flags);
188
189 return ret;
190}
191
192EXPORT_SYMBOL(clk_enable);
193EXPORT_SYMBOL(clk_disable);
194EXPORT_SYMBOL(clk_get_rate);
195EXPORT_SYMBOL(clk_round_rate);
196EXPORT_SYMBOL(clk_set_rate);
197EXPORT_SYMBOL(clk_get_parent);
198EXPORT_SYMBOL(clk_set_parent);
199
200/* base clocks */
201
202int clk_default_setrate(struct clk *clk, unsigned long rate)
203{
204 clk->rate = rate;
205 return 0;
206}
207
208struct clk_ops clk_ops_def_setrate = {
209 .set_rate = clk_default_setrate,
210};
211
212struct clk clk_xtal = {
213 .name = "xtal",
214 .rate = 0,
215 .parent = NULL,
216 .ctrlbit = 0,
217};
218
219struct clk clk_ext = {
220 .name = "ext",
221};
222
223struct clk clk_epll = {
224 .name = "epll",
225};
226
227struct clk clk_mpll = {
228 .name = "mpll",
229 .ops = &clk_ops_def_setrate,
230};
231
232struct clk clk_upll = {
233 .name = "upll",
234 .parent = NULL,
235 .ctrlbit = 0,
236};
237
238struct clk clk_f = {
239 .name = "fclk",
240 .rate = 0,
241 .parent = &clk_mpll,
242 .ctrlbit = 0,
243};
244
245struct clk clk_h = {
246 .name = "hclk",
247 .rate = 0,
248 .parent = NULL,
249 .ctrlbit = 0,
250 .ops = &clk_ops_def_setrate,
251};
252
253struct clk clk_p = {
254 .name = "pclk",
255 .rate = 0,
256 .parent = NULL,
257 .ctrlbit = 0,
258 .ops = &clk_ops_def_setrate,
259};
260
261struct clk clk_usb_bus = {
262 .name = "usb-bus",
263 .rate = 0,
264 .parent = &clk_upll,
265};
266
267
268struct clk s3c24xx_uclk = {
269 .name = "uclk",
270};
271
272/* initialise the clock system */
273
274/**
275 * s3c24xx_register_clock() - register a clock
276 * @clk: The clock to register
277 *
278 * Add the specified clock to the list of clocks known by the system.
279 */
280int s3c24xx_register_clock(struct clk *clk)
281{
282 if (clk->enable == NULL)
283 clk->enable = clk_null_enable;
284
285 /* fill up the clk_lookup structure and register it*/
286 clk->lookup.dev_id = clk->devname;
287 clk->lookup.con_id = clk->name;
288 clk->lookup.clk = clk;
289 clkdev_add(&clk->lookup);
290
291 return 0;
292}
293
294/**
295 * s3c24xx_register_clocks() - register an array of clock pointers
296 * @clks: Pointer to an array of struct clk pointers
297 * @nr_clks: The number of clocks in the @clks array.
298 *
299 * Call s3c24xx_register_clock() for all the clock pointers contained
300 * in the @clks list. Returns the number of failures.
301 */
302int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
303{
304 int fails = 0;
305
306 for (; nr_clks > 0; nr_clks--, clks++) {
307 if (s3c24xx_register_clock(*clks) < 0) {
308 struct clk *clk = *clks;
309 printk(KERN_ERR "%s: failed to register %p: %s\n",
310 __func__, clk, clk->name);
311 fails++;
312 }
313 }
314
315 return fails;
316}
317
318/**
319 * s3c_register_clocks() - register an array of clocks
320 * @clkp: Pointer to the first clock in the array.
321 * @nr_clks: Number of clocks to register.
322 *
323 * Call s3c24xx_register_clock() on the @clkp array given, printing an
324 * error if it fails to register the clock (unlikely).
325 */
326void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
327{
328 int ret;
329
330 for (; nr_clks > 0; nr_clks--, clkp++) {
331 ret = s3c24xx_register_clock(clkp);
332
333 if (ret < 0) {
334 printk(KERN_ERR "Failed to register clock %s (%d)\n",
335 clkp->name, ret);
336 }
337 }
338}
339
340/**
341 * s3c_disable_clocks() - disable an array of clocks
342 * @clkp: Pointer to the first clock in the array.
343 * @nr_clks: Number of clocks to register.
344 *
345 * for internal use only at initialisation time. disable the clocks in the
346 * @clkp array.
347 */
348
349void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
350{
351 for (; nr_clks > 0; nr_clks--, clkp++)
352 (clkp->enable)(clkp, 0);
353}
354
355/* initialise all the clocks */
356
357int __init s3c24xx_register_baseclocks(unsigned long xtal)
358{
359 printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
360
361 clk_xtal.rate = xtal;
362
363 /* register our clocks */
364
365 if (s3c24xx_register_clock(&clk_xtal) < 0)
366 printk(KERN_ERR "failed to register master xtal\n");
367
368 if (s3c24xx_register_clock(&clk_mpll) < 0)
369 printk(KERN_ERR "failed to register mpll clock\n");
370
371 if (s3c24xx_register_clock(&clk_upll) < 0)
372 printk(KERN_ERR "failed to register upll clock\n");
373
374 if (s3c24xx_register_clock(&clk_f) < 0)
375 printk(KERN_ERR "failed to register cpu fclk\n");
376
377 if (s3c24xx_register_clock(&clk_h) < 0)
378 printk(KERN_ERR "failed to register cpu hclk\n");
379
380 if (s3c24xx_register_clock(&clk_p) < 0)
381 printk(KERN_ERR "failed to register cpu pclk\n");
382
383 return 0;
384}
385
386#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
387/* debugfs support to trace clock tree hierarchy and attributes */
388
389static struct dentry *clk_debugfs_root;
390
391static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
392{
393 struct clk *child;
394 const char *state;
395 char buf[255] = { 0 };
396 int n = 0;
397
398 if (c->name)
399 n = snprintf(buf, sizeof(buf) - 1, "%s", c->name);
400
401 if (c->devname)
402 n += snprintf(buf + n, sizeof(buf) - 1 - n, ":%s", c->devname);
403
404 state = (c->usage > 0) ? "on" : "off";
405
406 seq_printf(s, "%*s%-*s %-6s %-3d %-10lu\n",
407 level * 3 + 1, "",
408 50 - level * 3, buf,
409 state, c->usage, clk_get_rate(c));
410
411 list_for_each_entry(child, &clocks, list) {
412 if (child->parent != c)
413 continue;
414
415 clock_tree_show_one(s, child, level + 1);
416 }
417}
418
419static int clock_tree_show(struct seq_file *s, void *data)
420{
421 struct clk *c;
422 unsigned long flags;
423
424 seq_printf(s, " clock state ref rate\n");
425 seq_printf(s, "----------------------------------------------------\n");
426
427 spin_lock_irqsave(&clocks_lock, flags);
428
429 list_for_each_entry(c, &clocks, list)
430 if (c->parent == NULL)
431 clock_tree_show_one(s, c, 0);
432
433 spin_unlock_irqrestore(&clocks_lock, flags);
434 return 0;
435}
436
437static int clock_tree_open(struct inode *inode, struct file *file)
438{
439 return single_open(file, clock_tree_show, inode->i_private);
440}
441
442static const struct file_operations clock_tree_fops = {
443 .open = clock_tree_open,
444 .read = seq_read,
445 .llseek = seq_lseek,
446 .release = single_release,
447};
448
449static int clock_rate_show(void *data, u64 *val)
450{
451 struct clk *c = data;
452 *val = clk_get_rate(c);
453 return 0;
454}
455DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_rate_show, NULL, "%llu\n");
456
457static int clk_debugfs_register_one(struct clk *c)
458{
459 int err;
460 struct dentry *d;
461 struct clk *pa = c->parent;
462 char s[255];
463 char *p = s;
464
465 p += sprintf(p, "%s", c->devname);
466
467 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
468 if (!d)
469 return -ENOMEM;
470
471 c->dent = d;
472
473 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
474 if (!d) {
475 err = -ENOMEM;
476 goto err_out;
477 }
478
479 d = debugfs_create_file("rate", S_IRUGO, c->dent, c, &clock_rate_fops);
480 if (!d) {
481 err = -ENOMEM;
482 goto err_out;
483 }
484 return 0;
485
486err_out:
487 debugfs_remove_recursive(c->dent);
488 return err;
489}
490
491static int clk_debugfs_register(struct clk *c)
492{
493 int err;
494 struct clk *pa = c->parent;
495
496 if (pa && !pa->dent) {
497 err = clk_debugfs_register(pa);
498 if (err)
499 return err;
500 }
501
502 if (!c->dent) {
503 err = clk_debugfs_register_one(c);
504 if (err)
505 return err;
506 }
507 return 0;
508}
509
510static int __init clk_debugfs_init(void)
511{
512 struct clk *c;
513 struct dentry *d;
514 int err = -ENOMEM;
515
516 d = debugfs_create_dir("clock", NULL);
517 if (!d)
518 return -ENOMEM;
519 clk_debugfs_root = d;
520
521 d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
522 &clock_tree_fops);
523 if (!d)
524 goto err_out;
525
526 list_for_each_entry(c, &clocks, list) {
527 err = clk_debugfs_register(c);
528 if (err)
529 goto err_out;
530 }
531 return 0;
532
533err_out:
534 debugfs_remove_recursive(clk_debugfs_root);
535 return err;
536}
537late_initcall(clk_debugfs_init);
538
539#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 364963a0a344..360618ee39e5 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -15,8 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18 18#include <plat/map-base.h>
19#include <mach/map.h>
20#include <plat/cpu.h> 19#include <plat/cpu.h>
21 20
22unsigned long samsung_cpu_id; 21unsigned long samsung_cpu_id;
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index ead4f1c94058..83c7d154bde0 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -53,7 +53,6 @@
53#include <linux/platform_data/ata-samsung_cf.h> 53#include <linux/platform_data/ata-samsung_cf.h>
54#include <plat/fb.h> 54#include <plat/fb.h>
55#include <plat/fb-s3c2410.h> 55#include <plat/fb-s3c2410.h>
56#include <plat/hdmi.h>
57#include <linux/platform_data/hwmon-s3c.h> 56#include <linux/platform_data/hwmon-s3c.h>
58#include <linux/platform_data/i2c-s3c2410.h> 57#include <linux/platform_data/i2c-s3c2410.h>
59#include <plat/keypad.h> 58#include <plat/keypad.h>
@@ -145,23 +144,6 @@ struct platform_device s3c_device_camif = {
145}; 144};
146#endif /* CONFIG_CPU_S3C2440 */ 145#endif /* CONFIG_CPU_S3C2440 */
147 146
148/* ASOC DMA */
149
150#ifdef CONFIG_PLAT_S5P
151static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
152
153struct platform_device samsung_asoc_idma = {
154 .name = "samsung-idma",
155 .id = -1,
156 .num_resources = 1,
157 .resource = &samsung_asoc_idma_resource,
158 .dev = {
159 .dma_mask = &samsung_device_dma_mask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 }
162};
163#endif
164
165/* FB */ 147/* FB */
166 148
167#ifdef CONFIG_S3C_DEV_FB 149#ifdef CONFIG_S3C_DEV_FB
@@ -190,151 +172,6 @@ void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
190} 172}
191#endif /* CONFIG_S3C_DEV_FB */ 173#endif /* CONFIG_S3C_DEV_FB */
192 174
193/* FIMC */
194
195#ifdef CONFIG_S5P_DEV_FIMC0
196static struct resource s5p_fimc0_resource[] = {
197 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
198 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
199};
200
201struct platform_device s5p_device_fimc0 = {
202 .name = "s5p-fimc",
203 .id = 0,
204 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
205 .resource = s5p_fimc0_resource,
206 .dev = {
207 .dma_mask = &samsung_device_dma_mask,
208 .coherent_dma_mask = DMA_BIT_MASK(32),
209 },
210};
211
212struct platform_device s5p_device_fimc_md = {
213 .name = "s5p-fimc-md",
214 .id = -1,
215};
216#endif /* CONFIG_S5P_DEV_FIMC0 */
217
218#ifdef CONFIG_S5P_DEV_FIMC1
219static struct resource s5p_fimc1_resource[] = {
220 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
221 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
222};
223
224struct platform_device s5p_device_fimc1 = {
225 .name = "s5p-fimc",
226 .id = 1,
227 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
228 .resource = s5p_fimc1_resource,
229 .dev = {
230 .dma_mask = &samsung_device_dma_mask,
231 .coherent_dma_mask = DMA_BIT_MASK(32),
232 },
233};
234#endif /* CONFIG_S5P_DEV_FIMC1 */
235
236#ifdef CONFIG_S5P_DEV_FIMC2
237static struct resource s5p_fimc2_resource[] = {
238 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
239 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
240};
241
242struct platform_device s5p_device_fimc2 = {
243 .name = "s5p-fimc",
244 .id = 2,
245 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
246 .resource = s5p_fimc2_resource,
247 .dev = {
248 .dma_mask = &samsung_device_dma_mask,
249 .coherent_dma_mask = DMA_BIT_MASK(32),
250 },
251};
252#endif /* CONFIG_S5P_DEV_FIMC2 */
253
254#ifdef CONFIG_S5P_DEV_FIMC3
255static struct resource s5p_fimc3_resource[] = {
256 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
257 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
258};
259
260struct platform_device s5p_device_fimc3 = {
261 .name = "s5p-fimc",
262 .id = 3,
263 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
264 .resource = s5p_fimc3_resource,
265 .dev = {
266 .dma_mask = &samsung_device_dma_mask,
267 .coherent_dma_mask = DMA_BIT_MASK(32),
268 },
269};
270#endif /* CONFIG_S5P_DEV_FIMC3 */
271
272/* G2D */
273
274#ifdef CONFIG_S5P_DEV_G2D
275static struct resource s5p_g2d_resource[] = {
276 [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
277 [1] = DEFINE_RES_IRQ(IRQ_2D),
278};
279
280struct platform_device s5p_device_g2d = {
281 .name = "s5p-g2d",
282 .id = 0,
283 .num_resources = ARRAY_SIZE(s5p_g2d_resource),
284 .resource = s5p_g2d_resource,
285 .dev = {
286 .dma_mask = &samsung_device_dma_mask,
287 .coherent_dma_mask = DMA_BIT_MASK(32),
288 },
289};
290#endif /* CONFIG_S5P_DEV_G2D */
291
292#ifdef CONFIG_S5P_DEV_JPEG
293static struct resource s5p_jpeg_resource[] = {
294 [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
295 [1] = DEFINE_RES_IRQ(IRQ_JPEG),
296};
297
298struct platform_device s5p_device_jpeg = {
299 .name = "s5p-jpeg",
300 .id = 0,
301 .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
302 .resource = s5p_jpeg_resource,
303 .dev = {
304 .dma_mask = &samsung_device_dma_mask,
305 .coherent_dma_mask = DMA_BIT_MASK(32),
306 },
307};
308#endif /* CONFIG_S5P_DEV_JPEG */
309
310/* FIMD0 */
311
312#ifdef CONFIG_S5P_DEV_FIMD0
313static struct resource s5p_fimd0_resource[] = {
314 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
315 [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
316 [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
317 [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
318};
319
320struct platform_device s5p_device_fimd0 = {
321 .name = "s5p-fb",
322 .id = 0,
323 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
324 .resource = s5p_fimd0_resource,
325 .dev = {
326 .dma_mask = &samsung_device_dma_mask,
327 .coherent_dma_mask = DMA_BIT_MASK(32),
328 },
329};
330
331void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
332{
333 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
334 &s5p_device_fimd0);
335}
336#endif /* CONFIG_S5P_DEV_FIMD0 */
337
338/* HWMON */ 175/* HWMON */
339 176
340#ifdef CONFIG_S3C_DEV_HWMON 177#ifdef CONFIG_S3C_DEV_HWMON
@@ -722,60 +559,6 @@ void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
722} 559}
723#endif /* CONFIG_S3C_DEV_I2C7 */ 560#endif /* CONFIG_S3C_DEV_I2C7 */
724 561
725/* I2C HDMIPHY */
726
727#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
728static struct resource s5p_i2c_resource[] = {
729 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
730 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
731};
732
733struct platform_device s5p_device_i2c_hdmiphy = {
734 .name = "s3c2440-hdmiphy-i2c",
735 .id = -1,
736 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
737 .resource = s5p_i2c_resource,
738};
739
740void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
741{
742 struct s3c2410_platform_i2c *npd;
743
744 if (!pd) {
745 pd = &default_i2c_data;
746
747 if (soc_is_s5pv210())
748 pd->bus_num = 3;
749 else
750 pd->bus_num = 0;
751 }
752
753 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
754 &s5p_device_i2c_hdmiphy);
755}
756
757static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
758
759void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
760 struct i2c_board_info *mhl_info, int mhl_bus)
761{
762 struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
763
764 if (soc_is_s5pv210())
765 pd->hdmiphy_bus = 3;
766 else
767 pd->hdmiphy_bus = 0;
768
769 pd->hdmiphy_info = hdmiphy_info;
770 pd->mhl_info = mhl_info;
771 pd->mhl_bus = mhl_bus;
772
773 s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
774 &s5p_device_hdmi);
775}
776
777#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
778
779/* I2S */ 562/* I2S */
780 563
781#ifdef CONFIG_PLAT_S3C24XX 564#ifdef CONFIG_PLAT_S3C24XX
@@ -879,36 +662,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
879} 662}
880#endif /* CONFIG_PLAT_S3C24XX */ 663#endif /* CONFIG_PLAT_S3C24XX */
881 664
882/* MIPI CSIS */
883
884#ifdef CONFIG_S5P_DEV_CSIS0
885static struct resource s5p_mipi_csis0_resource[] = {
886 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
887 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
888};
889
890struct platform_device s5p_device_mipi_csis0 = {
891 .name = "s5p-mipi-csis",
892 .id = 0,
893 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
894 .resource = s5p_mipi_csis0_resource,
895};
896#endif /* CONFIG_S5P_DEV_CSIS0 */
897
898#ifdef CONFIG_S5P_DEV_CSIS1
899static struct resource s5p_mipi_csis1_resource[] = {
900 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
901 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
902};
903
904struct platform_device s5p_device_mipi_csis1 = {
905 .name = "s5p-mipi-csis",
906 .id = 1,
907 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
908 .resource = s5p_mipi_csis1_resource,
909};
910#endif
911
912/* NAND */ 665/* NAND */
913 666
914#ifdef CONFIG_S3C_DEV_NAND 667#ifdef CONFIG_S3C_DEV_NAND
@@ -1052,43 +805,6 @@ void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1052} 805}
1053#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */ 806#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1054 807
1055#ifdef CONFIG_S5P_DEV_ONENAND
1056static struct resource s5p_onenand_resources[] = {
1057 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1058 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1059 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1060};
1061
1062struct platform_device s5p_device_onenand = {
1063 .name = "s5pc110-onenand",
1064 .id = -1,
1065 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1066 .resource = s5p_onenand_resources,
1067};
1068#endif /* CONFIG_S5P_DEV_ONENAND */
1069
1070/* PMU */
1071
1072#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
1073static struct resource s5p_pmu_resource[] = {
1074 DEFINE_RES_IRQ(IRQ_PMU)
1075};
1076
1077static struct platform_device s5p_device_pmu = {
1078 .name = "arm-pmu",
1079 .id = -1,
1080 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1081 .resource = s5p_pmu_resource,
1082};
1083
1084static int __init s5p_pmu_init(void)
1085{
1086 platform_device_register(&s5p_device_pmu);
1087 return 0;
1088}
1089arch_initcall(s5p_pmu_init);
1090#endif /* CONFIG_PLAT_S5P */
1091
1092/* PWM Timer */ 808/* PWM Timer */
1093 809
1094#ifdef CONFIG_SAMSUNG_DEV_PWM 810#ifdef CONFIG_SAMSUNG_DEV_PWM
@@ -1251,52 +967,6 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1251} 967}
1252#endif /* CONFIG_SAMSUNG_DEV_TS */ 968#endif /* CONFIG_SAMSUNG_DEV_TS */
1253 969
1254/* TV */
1255
1256#ifdef CONFIG_S5P_DEV_TV
1257
1258static struct resource s5p_hdmi_resources[] = {
1259 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1260 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1261};
1262
1263struct platform_device s5p_device_hdmi = {
1264 .name = "s5p-hdmi",
1265 .id = -1,
1266 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1267 .resource = s5p_hdmi_resources,
1268};
1269
1270static struct resource s5p_sdo_resources[] = {
1271 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1272 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1273};
1274
1275struct platform_device s5p_device_sdo = {
1276 .name = "s5p-sdo",
1277 .id = -1,
1278 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1279 .resource = s5p_sdo_resources,
1280};
1281
1282static struct resource s5p_mixer_resources[] = {
1283 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1284 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1285 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1286};
1287
1288struct platform_device s5p_device_mixer = {
1289 .name = "s5p-mixer",
1290 .id = -1,
1291 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1292 .resource = s5p_mixer_resources,
1293 .dev = {
1294 .dma_mask = &samsung_device_dma_mask,
1295 .coherent_dma_mask = DMA_BIT_MASK(32),
1296 }
1297};
1298#endif /* CONFIG_S5P_DEV_TV */
1299
1300/* USB */ 970/* USB */
1301 971
1302#ifdef CONFIG_S3C_DEV_USB_HOST 972#ifdef CONFIG_S3C_DEV_USB_HOST
diff --git a/arch/arm/plat-samsung/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h
deleted file mode 100644
index a5708bf84b3a..000000000000
--- a/arch/arm/plat-samsung/include/plat/camport.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series camera interface helper functions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __PLAT_SAMSUNG_CAMPORT_H_
12#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
13
14enum s5p_camport_id {
15 S5P_CAMPORT_A,
16 S5P_CAMPORT_B,
17};
18
19/*
20 * The helper functions to configure GPIO for the camera parallel bus.
21 * The camera port can be multiplexed with any FIMC entity, even multiple
22 * FIMC entities are allowed to be attached to a single port simultaneously.
23 * These functions are to be used in the board setup code.
24 */
25int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
26int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
27
28#endif /* __PLAT_SAMSUNG_CAMPORT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
deleted file mode 100644
index 50a8ca7c3760..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
2 *
3 * Parts taken from arch/arm/plat-s3c64xx/clock.c
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
10 * Copyright 2009 Harald Welte
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/**
18 * struct clksrc_sources - list of sources for a given clock
19 * @sources: array of pointers to clocks
20 * @nr_sources: The size of @sources
21 */
22struct clksrc_sources {
23 unsigned int nr_sources;
24 struct clk **sources;
25};
26
27/**
28 * struct clksrc_reg - register definition for clock control bits
29 * @reg: pointer to the register in virtual memory.
30 * @shift: the shift in bits to where the bitfield is.
31 * @size: the size in bits of the bitfield.
32 *
33 * This specifies the size and position of the bits we are interested
34 * in within the register specified by @reg.
35 */
36struct clksrc_reg {
37 void __iomem *reg;
38 unsigned short shift;
39 unsigned short size;
40};
41
42/**
43 * struct clksrc_clk - class of clock for newer style samsung devices.
44 * @clk: the standard clock representation
45 * @sources: the sources for this clock
46 * @reg_src: the register definition for selecting the clock's source
47 * @reg_div: the register definition for the clock's output divisor
48 *
49 * This clock implements the features required by the newer SoCs where
50 * the standard clock block provides an input mux and a post-mux divisor
51 * to provide the periperhal's clock.
52 *
53 * The array of @sources provides the mapping of mux position to the
54 * clock, and @reg_src shows the code where to modify to change the mux
55 * position. The @reg_div defines how to change the divider settings on
56 * the output.
57 */
58struct clksrc_clk {
59 struct clk clk;
60 struct clksrc_sources *sources;
61
62 struct clksrc_reg reg_src;
63 struct clksrc_reg reg_div;
64};
65
66/**
67 * s3c_set_clksrc() - setup the clock from the register settings
68 * @clk: The clock to setup.
69 * @announce: true to announce the setting to printk().
70 *
71 * Setup the clock from the current register settings, for when the
72 * kernel boots or if it is resuming from a possibly unknown state.
73 */
74extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
75
76/**
77 * s3c_register_clksrc() register clocks from an array of clksrc clocks
78 * @srcs: The array of clocks to register
79 * @size: The size of the @srcs array.
80 *
81 * Initialise and register the array of clocks described by @srcs.
82 */
83extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
deleted file mode 100644
index 63239f409807..000000000000
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ /dev/null
@@ -1,152 +0,0 @@
1/* linux/arch/arm/plat-s3c/include/plat/clock.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
15#include <linux/spinlock.h>
16#include <linux/clkdev.h>
17
18struct clk;
19
20/**
21 * struct clk_ops - standard clock operations
22 * @set_rate: set the clock rate, see clk_set_rate().
23 * @get_rate: get the clock rate, see clk_get_rate().
24 * @round_rate: round a given clock rate, see clk_round_rate().
25 * @set_parent: set the clock's parent, see clk_set_parent().
26 *
27 * Group the common clock implementations together so that we
28 * don't have to keep setting the same fields again. We leave
29 * enable in struct clk.
30 *
31 * Adding an extra layer of indirection into the process should
32 * not be a problem as it is unlikely these operations are going
33 * to need to be called quickly.
34 */
35struct clk_ops {
36 int (*set_rate)(struct clk *c, unsigned long rate);
37 unsigned long (*get_rate)(struct clk *c);
38 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
39 int (*set_parent)(struct clk *c, struct clk *parent);
40};
41
42struct clk {
43 struct list_head list;
44 struct module *owner;
45 struct clk *parent;
46 const char *name;
47 const char *devname;
48 int id;
49 int usage;
50 unsigned long rate;
51 unsigned long ctrlbit;
52
53 struct clk_ops *ops;
54 int (*enable)(struct clk *, int enable);
55 struct clk_lookup lookup;
56#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
57 struct dentry *dent; /* For visible tree hierarchy */
58#endif
59};
60
61/* other clocks which may be registered by board support */
62
63extern struct clk s3c24xx_dclk0;
64extern struct clk s3c24xx_dclk1;
65extern struct clk s3c24xx_clkout0;
66extern struct clk s3c24xx_clkout1;
67extern struct clk s3c24xx_uclk;
68
69extern struct clk clk_usb_bus;
70
71/* core clock support */
72
73extern struct clk clk_f;
74extern struct clk clk_h;
75extern struct clk clk_p;
76extern struct clk clk_mpll;
77extern struct clk clk_upll;
78extern struct clk clk_epll;
79extern struct clk clk_xtal;
80extern struct clk clk_ext;
81
82/* S3C2443/S3C2416 specific clocks */
83extern struct clksrc_clk clk_epllref;
84extern struct clksrc_clk clk_esysclk;
85
86/* S3C24XX UART clocks */
87extern struct clk s3c24xx_clk_uart0;
88extern struct clk s3c24xx_clk_uart1;
89extern struct clk s3c24xx_clk_uart2;
90
91/* S3C64XX specific clocks */
92extern struct clk clk_h2;
93extern struct clk clk_27m;
94extern struct clk clk_48m;
95extern struct clk clk_xusbxti;
96
97extern int clk_default_setrate(struct clk *clk, unsigned long rate);
98extern struct clk_ops clk_ops_def_setrate;
99
100/* exports for arch/arm/mach-s3c2410
101 *
102 * Please DO NOT use these outside of arch/arm/mach-s3c2410
103*/
104
105extern spinlock_t clocks_lock;
106
107extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
108
109extern int s3c24xx_register_clock(struct clk *clk);
110extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
111
112extern void s3c_register_clocks(struct clk *clk, int nr_clks);
113extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
114
115extern int s3c24xx_register_baseclocks(unsigned long xtal);
116
117extern void s5p_register_clocks(unsigned long xtal_freq);
118
119extern void s3c24xx_setup_clocks(unsigned long fclk,
120 unsigned long hclk,
121 unsigned long pclk);
122
123extern void s3c2410_setup_clocks(void);
124extern void s3c2412_setup_clocks(void);
125extern void s3c244x_setup_clocks(void);
126
127/* S3C2410 specific clock functions */
128
129extern int s3c2410_baseclk_add(void);
130
131/* S3C2443/S3C2416 specific clock functions */
132
133typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
134
135extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
136extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
137 unsigned int *divs, int nr_divs,
138 int divmask);
139
140extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
141extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
142extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
143
144/* S3C64XX specific functions and clocks */
145
146extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
147
148/* Global watchdog clock used by arch_wtd_reset() callback */
149
150extern struct clk *s3c2410_wdtclk;
151
152#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 72d4178ad23b..317c52303288 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -140,7 +140,6 @@ struct s3c_cpufreq_config {
140 * any frequency changes. This is really only need by devices like the 140 * any frequency changes. This is really only need by devices like the
141 * S3C2410 where there is no or limited divider between the PLL and the 141 * S3C2410 where there is no or limited divider between the PLL and the
142 * ARMCLK. 142 * ARMCLK.
143 * @resume_clocks: Update the clocks on resume.
144 * @get_iotiming: Get the current IO timing data, mainly for use at start. 143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
145 * @set_iotiming: Update the IO timings from the cached copies calculated 144 * @set_iotiming: Update the IO timings from the cached copies calculated
146 * from the @calc_iotiming entry when changing the frequency. 145 * from the @calc_iotiming entry when changing the frequency.
@@ -169,8 +168,6 @@ struct s3c_cpufreq_info {
169 168
170 /* driver routines */ 169 /* driver routines */
171 170
172 void (*resume_clocks)(void);
173
174 int (*get_iotiming)(struct s3c_cpufreq_config *cfg, 171 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
175 struct s3c_iotimings *timings); 172 struct s3c_iotimings *timings);
176 173
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index d1d4659025bb..61d14f3a0426 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -47,7 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
47IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) 47IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
48IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) 48IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
49IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) 49IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
50IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
51 50
52#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 51#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
53 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ 52 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -76,12 +75,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
76# define soc_is_s3c64xx() 0 75# define soc_is_s3c64xx() 0
77#endif 76#endif
78 77
79#if defined(CONFIG_CPU_S5PV210)
80# define soc_is_s5pv210() is_samsung_s5pv210()
81#else
82# define soc_is_s5pv210() 0
83#endif
84
85#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 78#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
86 79
87#ifndef KHZ 80#ifndef KHZ
@@ -117,12 +110,9 @@ extern void s3c_init_cpu(unsigned long idcode,
117 110
118/* core initialisation functions */ 111/* core initialisation functions */
119 112
120extern void s5p_init_irq(u32 *vic, u32 num_vic);
121
122extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); 113extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
123 114
124extern void s3c64xx_init_cpu(void); 115extern void s3c64xx_init_cpu(void);
125extern void s5p_init_cpu(void __iomem *cpuid_addr);
126 116
127extern unsigned int samsung_rev(void); 117extern unsigned int samsung_rev(void);
128 118
@@ -149,8 +139,5 @@ extern struct bus_type s3c2440_subsys;
149extern struct bus_type s3c2442_subsys; 139extern struct bus_type s3c2442_subsys;
150extern struct bus_type s3c2443_subsys; 140extern struct bus_type s3c2443_subsys;
151extern struct bus_type s3c6410_subsys; 141extern struct bus_type s3c6410_subsys;
152extern struct bus_type s5pv210_subsys;
153
154extern void (*s5pc1xx_idle)(void);
155 142
156#endif 143#endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5f5a28d08c2e..e23fed311e5f 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -25,9 +25,6 @@ struct s3c24xx_uart_resources {
25 25
26extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; 26extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; 27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
28extern struct s3c24xx_uart_resources s5p_uart_resources[];
29extern struct s3c24xx_uart_resources exynos4_uart_resources[];
30extern struct s3c24xx_uart_resources exynos5_uart_resources[];
31 28
32extern struct platform_device *s3c24xx_uart_devs[]; 29extern struct platform_device *s3c24xx_uart_devs[];
33extern struct platform_device *s3c24xx_uart_src[]; 30extern struct platform_device *s3c24xx_uart_src[];
@@ -75,45 +72,6 @@ extern struct platform_device s3c_device_usb_hsotg;
75extern struct platform_device s3c_device_usb_hsudc; 72extern struct platform_device s3c_device_usb_hsudc;
76extern struct platform_device s3c_device_wdt; 73extern struct platform_device s3c_device_wdt;
77 74
78extern struct platform_device s5p_device_fimc0;
79extern struct platform_device s5p_device_fimc1;
80extern struct platform_device s5p_device_fimc2;
81extern struct platform_device s5p_device_fimc3;
82extern struct platform_device s5p_device_fimc_md;
83extern struct platform_device s5p_device_jpeg;
84extern struct platform_device s5p_device_g2d;
85extern struct platform_device s5p_device_fimd0;
86extern struct platform_device s5p_device_hdmi;
87extern struct platform_device s5p_device_i2c_hdmiphy;
88extern struct platform_device s5p_device_mfc;
89extern struct platform_device s5p_device_mfc_l;
90extern struct platform_device s5p_device_mfc_r;
91extern struct platform_device s5p_device_mipi_csis0;
92extern struct platform_device s5p_device_mipi_csis1;
93extern struct platform_device s5p_device_mixer;
94extern struct platform_device s5p_device_onenand;
95extern struct platform_device s5p_device_sdo;
96
97extern struct platform_device s5pv210_device_ac97;
98extern struct platform_device s5pv210_device_iis0;
99extern struct platform_device s5pv210_device_iis1;
100extern struct platform_device s5pv210_device_iis2;
101extern struct platform_device s5pv210_device_pcm0;
102extern struct platform_device s5pv210_device_pcm1;
103extern struct platform_device s5pv210_device_pcm2;
104extern struct platform_device s5pv210_device_spdif;
105
106extern struct platform_device exynos4_device_ac97;
107extern struct platform_device exynos4_device_ahci;
108extern struct platform_device exynos4_device_i2s0;
109extern struct platform_device exynos4_device_i2s1;
110extern struct platform_device exynos4_device_i2s2;
111extern struct platform_device exynos4_device_ohci;
112extern struct platform_device exynos4_device_pcm0;
113extern struct platform_device exynos4_device_pcm1;
114extern struct platform_device exynos4_device_pcm2;
115extern struct platform_device exynos4_device_spdif;
116
117extern struct platform_device samsung_asoc_idma; 75extern struct platform_device samsung_asoc_idma;
118extern struct platform_device samsung_device_keypad; 76extern struct platform_device samsung_device_keypad;
119extern struct platform_device samsung_device_pwm; 77extern struct platform_device samsung_device_pwm;
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index 6abcbf139cee..bca383efcf6d 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,19 +26,4 @@ static inline void s3c_fb_setname(char *name)
26#endif 26#endif
27} 27}
28 28
29/* Re-define device name depending on support. */
30static inline void s5p_fb_setname(int id, char *name)
31{
32 switch (id) {
33#ifdef CONFIG_S5P_DEV_FIMD0
34 case 0:
35 s5p_device_fimd0.name = name;
36 break;
37#endif
38 default:
39 printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
40 break;
41 }
42}
43
44#endif /* __ASM_PLAT_FB_CORE_H */ 29#endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 5a0e26afb961..b89f8f208515 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -26,32 +26,10 @@
26extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); 26extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
27 27
28/** 28/**
29 * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
30 * @pd: The platform data to set. The data is copied from the passed structure
31 * so the machine data can mark the data __initdata so that any unused
32 * machines will end up dumping their data at runtime.
33 */
34extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
35
36/**
37 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD 29 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
38 * 30 *
39 * Initialise the GPIO for an 24bpp LCD display on the RGB interface. 31 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
40 */ 32 */
41extern void s3c64xx_fb_gpio_setup_24bpp(void); 33extern void s3c64xx_fb_gpio_setup_24bpp(void);
42 34
43/**
44 * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
45 *
46 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
47 */
48extern void s5pv210_fb_gpio_setup_24bpp(void);
49
50/**
51 * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
52 *
53 * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
54 */
55extern void exynos4_fimd0_gpio_setup_24bpp(void);
56
57#endif /* __PLAT_S3C_FB_H */ 35#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/fimc-core.h b/arch/arm/plat-samsung/include/plat/fimc-core.h
deleted file mode 100644
index 1d6cb2b8b094..000000000000
--- a/arch/arm/plat-samsung/include/plat/fimc-core.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * arch/arm/plat-samsung/include/plat/fimc-core.h
3 *
4 * Copyright 2010 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * Samsung camera interface driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_PLAT_FIMC_CORE_H
15#define __ASM_PLAT_FIMC_CORE_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s3c_fimc_setname(int id, char *name)
24{
25 switch (id) {
26#ifdef CONFIG_S5P_DEV_FIMC0
27 case 0:
28 s5p_device_fimc0.name = name;
29 break;
30#endif
31#ifdef CONFIG_S5P_DEV_FIMC1
32 case 1:
33 s5p_device_fimc1.name = name;
34 break;
35#endif
36#ifdef CONFIG_S5P_DEV_FIMC2
37 case 2:
38 s5p_device_fimc2.name = name;
39 break;
40#endif
41#ifdef CONFIG_S5P_DEV_FIMC3
42 case 3:
43 s5p_device_fimc3.name = name;
44 break;
45#endif
46 default:
47 break;
48 }
49}
50
51#endif /* __ASM_PLAT_FIMC_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 08740eed050c..b5294eff18b5 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -27,7 +27,6 @@
27#include <linux/types.h> 27#include <linux/types.h>
28 28
29typedef unsigned int __bitwise__ samsung_gpio_pull_t; 29typedef unsigned int __bitwise__ samsung_gpio_pull_t;
30typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
31 30
32/* forward declaration if gpio-core.h hasn't been included */ 31/* forward declaration if gpio-core.h hasn't been included */
33struct samsung_gpio_chip; 32struct samsung_gpio_chip;
@@ -180,67 +179,4 @@ static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
180 return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE); 179 return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
181} 180}
182 181
183/* Define values for the drvstr available for each gpio pin.
184 *
185 * These values control the value of the output signal driver strength,
186 * configurable on most pins on the S5P series.
187 */
188#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
189#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
190#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
191#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
192
193/**
194 * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
195 * @pin: The pin number to get the settings for
196 *
197 * Read the driver streght value for the specified pin.
198*/
199extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
200
201/**
202 * s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin
203 * @pin: The pin number to configure the driver streght value
204 * @drvstr: The new value of the driver strength
205 *
206 * This function sets the driver strength value for the specified pin.
207 * It will return 0 if successful, or a negative error code if the pin
208 * cannot support the requested setting.
209*/
210extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
211
212/**
213 * s5p_register_gpio_interrupt() - register interrupt support for a gpio group
214 * @pin: The pin number from the group to be registered
215 *
216 * This function registers gpio interrupt support for the group that the
217 * specified pin belongs to.
218 *
219 * The total number of gpio pins is quite large ob s5p series. Registering
220 * irq support for all of them would be a resource waste. Because of that the
221 * interrupt support for standard gpio pins is registered dynamically.
222 *
223 * It will return the irq number of the interrupt that has been registered
224 * or -ENOMEM if no more gpio interrupts can be registered. It is allowed
225 * to call this function more than once for the same gpio group (the group
226 * will be registered only once).
227 */
228extern int s5p_register_gpio_interrupt(int pin);
229
230/** s5p_register_gpioint_bank() - add gpio bank for further gpio interrupt
231 * registration (see s5p_register_gpio_interrupt function)
232 * @chain_irq: chained irq number for the gpio int handler for this bank
233 * @start: start gpio group number of this bank
234 * @nr_groups: number of gpio groups handled by this bank
235 *
236 * This functions registers initial information about gpio banks that
237 * can be later used by the s5p_register_gpio_interrupt() function to
238 * enable support for gpio interrupt for particular gpio group.
239 */
240#ifdef CONFIG_S5P_GPIO_INT
241extern int s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups);
242#else
243#define s5p_register_gpioint_bank(chain_irq, start, nr_groups) do { } while (0)
244#endif
245
246#endif /* __PLAT_GPIO_CFG_H */ 182#endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/hdmi.h b/arch/arm/plat-samsung/include/plat/hdmi.h
deleted file mode 100644
index 331d046ac2c5..000000000000
--- a/arch/arm/plat-samsung/include/plat/hdmi.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_HDMI_H
11#define __PLAT_SAMSUNG_HDMI_H __FILE__
12
13extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
14 struct i2c_board_info *mhl_info, int mhl_bus);
15
16#endif /* __PLAT_SAMSUNG_HDMI_H */
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
deleted file mode 100644
index 039001c0ef05..000000000000
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/irqs.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P Common IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_IRQS_H
14#define __PLAT_SAMSUNG_IRQS_H __FILE__
15
16/* we keep the first set of CPU IRQs out of the range of
17 * the ISA space, so that the PC104 has them to itself
18 * and we don't end up having to do horrible things to the
19 * standard ISA drivers....
20 *
21 * note, since we're using the VICs, our start must be a
22 * mulitple of 32 to allow the common code to work
23 */
24
25#define S5P_IRQ_OFFSET (32)
26
27#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
28
29#define S5P_VIC0_BASE S5P_IRQ(0)
30#define S5P_VIC1_BASE S5P_IRQ(32)
31#define S5P_VIC2_BASE S5P_IRQ(64)
32#define S5P_VIC3_BASE S5P_IRQ(96)
33
34#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
35
36#define IRQ_VIC0_BASE S5P_VIC0_BASE
37#define IRQ_VIC1_BASE S5P_VIC1_BASE
38#define IRQ_VIC2_BASE S5P_VIC2_BASE
39
40/* VIC based IRQs */
41
42#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
43#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
46
47#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
48 : ((x) - 16 + S5P_EINT_BASE2))
49
50#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
51 ((irq) - S5P_EINT_BASE1) : \
52 ((irq) + 16 - S5P_EINT_BASE2))
53
54#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
55
56/* Typically only a few gpio chips require gpio interrupt support.
57 To avoid memory waste irq descriptors are allocated only for
58 S5P_GPIOINT_GROUP_COUNT chips, each with total number of
59 S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
60 to any gpio chip with the s5p_register_gpio_interrupt() function */
61#define S5P_GPIOINT_GROUP_COUNT 4
62#define S5P_GPIOINT_GROUP_SIZE 8
63#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
64
65/* IRQ types common for all s5p platforms */
66#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
67#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
68#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
69#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
70#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
71
72#endif /* __PLAT_SAMSUNG_IRQS_H */
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
deleted file mode 100644
index 033654e91e22..000000000000
--- a/arch/arm/plat-samsung/include/plat/mfc.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_MFC_H
11#define __PLAT_SAMSUNG_MFC_H __FILE__
12
13struct s5p_mfc_dt_meminfo {
14 unsigned long loff;
15 unsigned long lsize;
16 unsigned long roff;
17 unsigned long rsize;
18 char *compatible;
19};
20
21/**
22 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
23 * @rbase: base address for MFC 'right' memory interface
24 * @rsize: size of the memory reserved for MFC 'right' interface
25 * @lbase: base address for MFC 'left' memory interface
26 * @lsize: size of the memory reserved for MFC 'left' interface
27 *
28 * This function reserves system memory for both MFC device memory
29 * interfaces and registers it to respective struct device entries as
30 * coherent memory.
31 */
32void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
33 phys_addr_t lbase, unsigned int lsize);
34
35#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
deleted file mode 100644
index 357af7c1c664..000000000000
--- a/arch/arm/plat-samsung/include/plat/pll.h
+++ /dev/null
@@ -1,323 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/pll.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Samsung PLL codes
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#include <asm/div64.h>
19
20#define S3C24XX_PLL_MDIV_MASK (0xFF)
21#define S3C24XX_PLL_PDIV_MASK (0x1F)
22#define S3C24XX_PLL_SDIV_MASK (0x3)
23#define S3C24XX_PLL_MDIV_SHIFT (12)
24#define S3C24XX_PLL_PDIV_SHIFT (4)
25#define S3C24XX_PLL_SDIV_SHIFT (0)
26
27static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
28 unsigned int baseclk)
29{
30 unsigned int mdiv, pdiv, sdiv;
31 uint64_t fvco;
32
33 mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
34 pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
35 sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
36
37 fvco = (uint64_t)baseclk * (mdiv + 8);
38 do_div(fvco, (pdiv + 2) << sdiv);
39
40 return (unsigned int)fvco;
41}
42
43#define S3C2416_PLL_MDIV_MASK (0x3FF)
44#define S3C2416_PLL_PDIV_MASK (0x3F)
45#define S3C2416_PLL_SDIV_MASK (0x7)
46#define S3C2416_PLL_MDIV_SHIFT (14)
47#define S3C2416_PLL_PDIV_SHIFT (5)
48#define S3C2416_PLL_SDIV_SHIFT (0)
49
50static inline unsigned int s3c2416_get_pll(unsigned int pllval,
51 unsigned int baseclk)
52{
53 unsigned int mdiv, pdiv, sdiv;
54 uint64_t fvco;
55
56 mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
57 pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
58 sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
59
60 fvco = (uint64_t)baseclk * mdiv;
61 do_div(fvco, (pdiv << sdiv));
62
63 return (unsigned int)fvco;
64}
65
66#define S3C6400_PLL_MDIV_MASK (0x3FF)
67#define S3C6400_PLL_PDIV_MASK (0x3F)
68#define S3C6400_PLL_SDIV_MASK (0x7)
69#define S3C6400_PLL_MDIV_SHIFT (16)
70#define S3C6400_PLL_PDIV_SHIFT (8)
71#define S3C6400_PLL_SDIV_SHIFT (0)
72
73static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
74 u32 pllcon)
75{
76 u32 mdiv, pdiv, sdiv;
77 u64 fvco = baseclk;
78
79 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
80 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
81 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
82
83 fvco *= mdiv;
84 do_div(fvco, (pdiv << sdiv));
85
86 return (unsigned long)fvco;
87}
88
89#define PLL6553X_MDIV_MASK (0x7F)
90#define PLL6553X_PDIV_MASK (0x1F)
91#define PLL6553X_SDIV_MASK (0x3)
92#define PLL6553X_KDIV_MASK (0xFFFF)
93#define PLL6553X_MDIV_SHIFT (16)
94#define PLL6553X_PDIV_SHIFT (8)
95#define PLL6553X_SDIV_SHIFT (0)
96
97static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
98 u32 pll_con0, u32 pll_con1)
99{
100 unsigned long result;
101 u32 mdiv, pdiv, sdiv, kdiv;
102 u64 tmp;
103
104 mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
105 pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
106 sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
107 kdiv = pll_con1 & PLL6553X_KDIV_MASK;
108
109 /*
110 * We need to multiple baseclk by mdiv (the integer part) and kdiv
111 * which is in 2^16ths, so shift mdiv up (does not overflow) and
112 * add kdiv before multiplying. The use of tmp is to avoid any
113 * overflows before shifting bac down into result when multipling
114 * by the mdiv and kdiv pair.
115 */
116
117 tmp = baseclk;
118 tmp *= (mdiv << 16) + kdiv;
119 do_div(tmp, (pdiv << sdiv));
120 result = tmp >> 16;
121
122 return result;
123}
124
125#define PLL35XX_MDIV_MASK (0x3FF)
126#define PLL35XX_PDIV_MASK (0x3F)
127#define PLL35XX_SDIV_MASK (0x7)
128#define PLL35XX_MDIV_SHIFT (16)
129#define PLL35XX_PDIV_SHIFT (8)
130#define PLL35XX_SDIV_SHIFT (0)
131
132static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
133{
134 u32 mdiv, pdiv, sdiv;
135 u64 fvco = baseclk;
136
137 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
138 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
139 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
140
141 fvco *= mdiv;
142 do_div(fvco, (pdiv << sdiv));
143
144 return (unsigned long)fvco;
145}
146
147#define PLL36XX_KDIV_MASK (0xFFFF)
148#define PLL36XX_MDIV_MASK (0x1FF)
149#define PLL36XX_PDIV_MASK (0x3F)
150#define PLL36XX_SDIV_MASK (0x7)
151#define PLL36XX_MDIV_SHIFT (16)
152#define PLL36XX_PDIV_SHIFT (8)
153#define PLL36XX_SDIV_SHIFT (0)
154
155static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
156 u32 pll_con0, u32 pll_con1)
157{
158 unsigned long result;
159 u32 mdiv, pdiv, sdiv, kdiv;
160 u64 tmp;
161
162 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
163 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
164 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
165 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
166
167 tmp = baseclk;
168
169 tmp *= (mdiv << 16) + kdiv;
170 do_div(tmp, (pdiv << sdiv));
171 result = tmp >> 16;
172
173 return result;
174}
175
176#define PLL45XX_MDIV_MASK (0x3FF)
177#define PLL45XX_PDIV_MASK (0x3F)
178#define PLL45XX_SDIV_MASK (0x7)
179#define PLL45XX_MDIV_SHIFT (16)
180#define PLL45XX_PDIV_SHIFT (8)
181#define PLL45XX_SDIV_SHIFT (0)
182
183enum pll45xx_type_t {
184 pll_4500,
185 pll_4502,
186 pll_4508
187};
188
189static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
190 enum pll45xx_type_t pll_type)
191{
192 u32 mdiv, pdiv, sdiv;
193 u64 fvco = baseclk;
194
195 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
196 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
197 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
198
199 if (pll_type == pll_4508)
200 sdiv = sdiv - 1;
201
202 fvco *= mdiv;
203 do_div(fvco, (pdiv << sdiv));
204
205 return (unsigned long)fvco;
206}
207
208/* CON0 bit-fields */
209#define PLL46XX_MDIV_MASK (0x1FF)
210#define PLL46XX_PDIV_MASK (0x3F)
211#define PLL46XX_SDIV_MASK (0x7)
212#define PLL46XX_LOCKED_SHIFT (29)
213#define PLL46XX_MDIV_SHIFT (16)
214#define PLL46XX_PDIV_SHIFT (8)
215#define PLL46XX_SDIV_SHIFT (0)
216
217/* CON1 bit-fields */
218#define PLL46XX_MRR_MASK (0x1F)
219#define PLL46XX_MFR_MASK (0x3F)
220#define PLL46XX_KDIV_MASK (0xFFFF)
221#define PLL4650C_KDIV_MASK (0xFFF)
222#define PLL46XX_MRR_SHIFT (24)
223#define PLL46XX_MFR_SHIFT (16)
224#define PLL46XX_KDIV_SHIFT (0)
225
226enum pll46xx_type_t {
227 pll_4600,
228 pll_4650,
229 pll_4650c,
230};
231
232static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
233 u32 pll_con0, u32 pll_con1,
234 enum pll46xx_type_t pll_type)
235{
236 unsigned long result;
237 u32 mdiv, pdiv, sdiv, kdiv;
238 u64 tmp;
239
240 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
241 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
242 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
243 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
244
245 if (pll_type == pll_4650c)
246 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
247 else
248 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
249
250 tmp = baseclk;
251
252 if (pll_type == pll_4600) {
253 tmp *= (mdiv << 16) + kdiv;
254 do_div(tmp, (pdiv << sdiv));
255 result = tmp >> 16;
256 } else {
257 tmp *= (mdiv << 10) + kdiv;
258 do_div(tmp, (pdiv << sdiv));
259 result = tmp >> 10;
260 }
261
262 return result;
263}
264
265#define PLL90XX_MDIV_MASK (0xFF)
266#define PLL90XX_PDIV_MASK (0x3F)
267#define PLL90XX_SDIV_MASK (0x7)
268#define PLL90XX_KDIV_MASK (0xffff)
269#define PLL90XX_LOCKED_SHIFT (29)
270#define PLL90XX_MDIV_SHIFT (16)
271#define PLL90XX_PDIV_SHIFT (8)
272#define PLL90XX_SDIV_SHIFT (0)
273#define PLL90XX_KDIV_SHIFT (0)
274
275static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
276 u32 pll_con, u32 pll_conk)
277{
278 unsigned long result;
279 u32 mdiv, pdiv, sdiv, kdiv;
280 u64 tmp;
281
282 mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
283 pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
284 sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
285 kdiv = pll_conk & PLL90XX_KDIV_MASK;
286
287 /*
288 * We need to multiple baseclk by mdiv (the integer part) and kdiv
289 * which is in 2^16ths, so shift mdiv up (does not overflow) and
290 * add kdiv before multiplying. The use of tmp is to avoid any
291 * overflows before shifting bac down into result when multipling
292 * by the mdiv and kdiv pair.
293 */
294
295 tmp = baseclk;
296 tmp *= (mdiv << 16) + kdiv;
297 do_div(tmp, (pdiv << sdiv));
298 result = tmp >> 16;
299
300 return result;
301}
302
303#define PLL65XX_MDIV_MASK (0x3FF)
304#define PLL65XX_PDIV_MASK (0x3F)
305#define PLL65XX_SDIV_MASK (0x7)
306#define PLL65XX_MDIV_SHIFT (16)
307#define PLL65XX_PDIV_SHIFT (8)
308#define PLL65XX_SDIV_SHIFT (0)
309
310static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
311{
312 u32 mdiv, pdiv, sdiv;
313 u64 fvco = baseclk;
314
315 mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
316 pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
317 sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
318
319 fvco *= mdiv;
320 do_div(fvco, (pdiv << sdiv));
321
322 return (unsigned long)fvco;
323}
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
deleted file mode 100644
index acacc4b88a39..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ /dev/null
@@ -1,65 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_CLOCK_H
14#define __ASM_PLAT_S5P_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19
20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_bpll clk_ext_xtal_mux
22#define clk_fin_cpll clk_ext_xtal_mux
23#define clk_fin_mpll clk_ext_xtal_mux
24#define clk_fin_epll clk_ext_xtal_mux
25#define clk_fin_dpll clk_ext_xtal_mux
26#define clk_fin_vpll clk_ext_xtal_mux
27#define clk_fin_hpll clk_ext_xtal_mux
28
29extern struct clk clk_ext_xtal_mux;
30extern struct clk clk_xusbxti;
31extern struct clk clk_48m;
32extern struct clk s5p_clk_27m;
33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_bpll_div2;
36extern struct clk clk_fout_cpll;
37extern struct clk clk_fout_mpll;
38extern struct clk clk_fout_mpll_div2;
39extern struct clk clk_fout_epll;
40extern struct clk clk_fout_dpll;
41extern struct clk clk_fout_vpll;
42extern struct clk clk_arm;
43extern struct clk clk_vpll;
44
45extern struct clksrc_sources clk_src_apll;
46extern struct clksrc_sources clk_src_bpll;
47extern struct clksrc_sources clk_src_bpll_fout;
48extern struct clksrc_sources clk_src_cpll;
49extern struct clksrc_sources clk_src_mpll;
50extern struct clksrc_sources clk_src_mpll_fout;
51extern struct clksrc_sources clk_src_epll;
52extern struct clksrc_sources clk_src_dpll;
53
54extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
55
56/* Common EPLL operations for S5P platform */
57extern int s5p_epll_enable(struct clk *clk, int enable);
58extern unsigned long s5p_epll_get_rate(struct clk *clk);
59
60/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
62extern unsigned long s5p_spdif_get_rate(struct clk *clk);
63
64extern struct clk_ops s5p_sclk_spdif_ops;
65#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index f84b6cbc8745..2787553c3ae2 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -57,14 +57,6 @@ extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
59extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 59extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
60extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
61extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
62extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
63extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
64extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
65extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
66extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
67extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
68 60
69/* S3C2416 SDHCI setup */ 61/* S3C2416 SDHCI setup */
70 62
@@ -144,45 +136,6 @@ static inline void s3c6400_default_sdhci2(void) { }
144 136
145#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 137#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
146 138
147/* S5PV210 SDHCI setup */
148
149#ifdef CONFIG_S5PV210_SETUP_SDHCI
150static inline void s5pv210_default_sdhci0(void)
151{
152#ifdef CONFIG_S3C_DEV_HSMMC
153 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
154#endif
155}
156
157static inline void s5pv210_default_sdhci1(void)
158{
159#ifdef CONFIG_S3C_DEV_HSMMC1
160 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
161#endif
162}
163
164static inline void s5pv210_default_sdhci2(void)
165{
166#ifdef CONFIG_S3C_DEV_HSMMC2
167 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
168#endif
169}
170
171static inline void s5pv210_default_sdhci3(void)
172{
173#ifdef CONFIG_S3C_DEV_HSMMC3
174 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
175#endif
176}
177
178#else
179static inline void s5pv210_default_sdhci0(void) { }
180static inline void s5pv210_default_sdhci1(void) { }
181static inline void s5pv210_default_sdhci2(void) { }
182static inline void s5pv210_default_sdhci3(void) { }
183
184#endif /* CONFIG_S5PV210_SETUP_SDHCI */
185
186static inline void s3c_sdhci_setname(int id, char *name) 139static inline void s3c_sdhci_setname(int id, char *name)
187{ 140{
188 switch (id) { 141 switch (id) {
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
deleted file mode 100644
index 3bc34f3ce28f..000000000000
--- a/arch/arm/plat-samsung/include/plat/tv-core.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * arch/arm/plat-samsung/include/plat/tv.h
3 *
4 * Copyright 2011 Samsung Electronics Co., Ltd.
5 * Tomasz Stanislawski <t.stanislaws@samsung.com>
6 *
7 * Samsung TV driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __SAMSUNG_PLAT_TV_H
15#define __SAMSUNG_PLAT_TV_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s5p_hdmi_setname(char *name)
24{
25#ifdef CONFIG_S5P_DEV_TV
26 s5p_device_hdmi.name = name;
27#endif
28}
29
30static inline void s5p_mixer_setname(char *name)
31{
32#ifdef CONFIG_S5P_DEV_TV
33 s5p_device_mixer.name = name;
34#endif
35}
36
37static inline void s5p_sdo_setname(char *name)
38{
39#ifdef CONFIG_S5P_DEV_TV
40 s5p_device_sdo.name = name;
41#endif
42}
43
44#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index a1f925f3121f..11fbbc26e49f 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -30,7 +30,6 @@
30 30
31#include <plat/cpu.h> 31#include <plat/cpu.h>
32#include <plat/devs.h> 32#include <plat/devs.h>
33#include <plat/clock.h>
34 33
35static struct cpu_table *cpu; 34static struct cpu_table *cpu;
36 35
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index da268813901b..f6084f641e6f 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -196,7 +196,7 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
196 .resume = samsung_gpio_pm_2bit_resume, 196 .resume = samsung_gpio_pm_2bit_resume,
197}; 197};
198 198
199#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) 199#if defined(CONFIG_ARCH_S3C64XX)
200static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) 200static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
201{ 201{
202 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); 202 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -306,7 +306,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
306 .save = samsung_gpio_pm_4bit_save, 306 .save = samsung_gpio_pm_4bit_save,
307 .resume = samsung_gpio_pm_4bit_resume, 307 .resume = samsung_gpio_pm_4bit_resume,
308}; 308};
309#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ 309#endif /* CONFIG_ARCH_S3C64XX */
310 310
311/** 311/**
312 * samsung_pm_save_gpio() - save gpio chip data for suspend 312 * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
deleted file mode 100644
index 48a159911037..000000000000
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Copyright 2009 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * S5P - Common clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/device.h>
20#include <linux/io.h>
21#include <asm/div64.h>
22
23#include <mach/regs-clock.h>
24
25#include <plat/clock.h>
26#include <plat/clock-clksrc.h>
27#include <plat/s5p-clock.h>
28
29/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
30 * clk_ext_xtal_mux.
31*/
32struct clk clk_ext_xtal_mux = {
33 .name = "ext_xtal",
34 .id = -1,
35};
36
37struct clk clk_xusbxti = {
38 .name = "xusbxti",
39 .id = -1,
40 .rate = 24000000,
41};
42
43struct clk s5p_clk_27m = {
44 .name = "clk_27m",
45 .id = -1,
46 .rate = 27000000,
47};
48
49/* 48MHz USB Phy clock output */
50struct clk clk_48m = {
51 .name = "clk_48m",
52 .id = -1,
53 .rate = 48000000,
54};
55
56/* APLL clock output
57 * No need .ctrlbit, this is always on
58*/
59struct clk clk_fout_apll = {
60 .name = "fout_apll",
61 .id = -1,
62};
63
64/* BPLL clock output */
65
66struct clk clk_fout_bpll = {
67 .name = "fout_bpll",
68 .id = -1,
69};
70
71struct clk clk_fout_bpll_div2 = {
72 .name = "fout_bpll_div2",
73 .id = -1,
74};
75
76/* CPLL clock output */
77
78struct clk clk_fout_cpll = {
79 .name = "fout_cpll",
80 .id = -1,
81};
82
83/* MPLL clock output
84 * No need .ctrlbit, this is always on
85*/
86struct clk clk_fout_mpll = {
87 .name = "fout_mpll",
88 .id = -1,
89};
90
91struct clk clk_fout_mpll_div2 = {
92 .name = "fout_mpll_div2",
93 .id = -1,
94};
95
96/* EPLL clock output */
97struct clk clk_fout_epll = {
98 .name = "fout_epll",
99 .id = -1,
100 .ctrlbit = (1 << 31),
101};
102
103/* DPLL clock output */
104struct clk clk_fout_dpll = {
105 .name = "fout_dpll",
106 .id = -1,
107 .ctrlbit = (1 << 31),
108};
109
110/* VPLL clock output */
111struct clk clk_fout_vpll = {
112 .name = "fout_vpll",
113 .id = -1,
114 .ctrlbit = (1 << 31),
115};
116
117/* Possible clock sources for APLL Mux */
118static struct clk *clk_src_apll_list[] = {
119 [0] = &clk_fin_apll,
120 [1] = &clk_fout_apll,
121};
122
123struct clksrc_sources clk_src_apll = {
124 .sources = clk_src_apll_list,
125 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
126};
127
128/* Possible clock sources for BPLL Mux */
129static struct clk *clk_src_bpll_list[] = {
130 [0] = &clk_fin_bpll,
131 [1] = &clk_fout_bpll,
132};
133
134struct clksrc_sources clk_src_bpll = {
135 .sources = clk_src_bpll_list,
136 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
137};
138
139static struct clk *clk_src_bpll_fout_list[] = {
140 [0] = &clk_fout_bpll_div2,
141 [1] = &clk_fout_bpll,
142};
143
144struct clksrc_sources clk_src_bpll_fout = {
145 .sources = clk_src_bpll_fout_list,
146 .nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
147};
148
149/* Possible clock sources for CPLL Mux */
150static struct clk *clk_src_cpll_list[] = {
151 [0] = &clk_fin_cpll,
152 [1] = &clk_fout_cpll,
153};
154
155struct clksrc_sources clk_src_cpll = {
156 .sources = clk_src_cpll_list,
157 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
158};
159
160/* Possible clock sources for MPLL Mux */
161static struct clk *clk_src_mpll_list[] = {
162 [0] = &clk_fin_mpll,
163 [1] = &clk_fout_mpll,
164};
165
166struct clksrc_sources clk_src_mpll = {
167 .sources = clk_src_mpll_list,
168 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
169};
170
171static struct clk *clk_src_mpll_fout_list[] = {
172 [0] = &clk_fout_mpll_div2,
173 [1] = &clk_fout_mpll,
174};
175
176struct clksrc_sources clk_src_mpll_fout = {
177 .sources = clk_src_mpll_fout_list,
178 .nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
179};
180
181/* Possible clock sources for EPLL Mux */
182static struct clk *clk_src_epll_list[] = {
183 [0] = &clk_fin_epll,
184 [1] = &clk_fout_epll,
185};
186
187struct clksrc_sources clk_src_epll = {
188 .sources = clk_src_epll_list,
189 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
190};
191
192/* Possible clock sources for DPLL Mux */
193static struct clk *clk_src_dpll_list[] = {
194 [0] = &clk_fin_dpll,
195 [1] = &clk_fout_dpll,
196};
197
198struct clksrc_sources clk_src_dpll = {
199 .sources = clk_src_dpll_list,
200 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
201};
202
203struct clk clk_vpll = {
204 .name = "vpll",
205 .id = -1,
206};
207
208int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
209{
210 unsigned int ctrlbit = clk->ctrlbit;
211 u32 con;
212
213 con = __raw_readl(reg);
214 con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
215 __raw_writel(con, reg);
216 return 0;
217}
218
219int s5p_epll_enable(struct clk *clk, int enable)
220{
221 unsigned int ctrlbit = clk->ctrlbit;
222 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
223
224 if (enable)
225 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
226 else
227 __raw_writel(epll_con, S5P_EPLL_CON);
228
229 return 0;
230}
231
232unsigned long s5p_epll_get_rate(struct clk *clk)
233{
234 return clk->rate;
235}
236
237int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
238{
239 struct clk *pclk;
240 int ret;
241
242 pclk = clk_get_parent(clk);
243 if (IS_ERR(pclk))
244 return -EINVAL;
245
246 ret = pclk->ops->set_rate(pclk, rate);
247 clk_put(pclk);
248
249 return ret;
250}
251
252unsigned long s5p_spdif_get_rate(struct clk *clk)
253{
254 struct clk *pclk;
255 int rate;
256
257 pclk = clk_get_parent(clk);
258 if (IS_ERR(pclk))
259 return -EINVAL;
260
261 rate = pclk->ops->get_rate(pclk);
262 clk_put(pclk);
263
264 return rate;
265}
266
267struct clk_ops s5p_sclk_spdif_ops = {
268 .set_rate = s5p_spdif_set_rate,
269 .get_rate = s5p_spdif_get_rate,
270};
271
272static struct clk *s5p_clks[] __initdata = {
273 &clk_ext_xtal_mux,
274 &clk_48m,
275 &s5p_clk_27m,
276 &clk_fout_apll,
277 &clk_fout_mpll,
278 &clk_fout_epll,
279 &clk_fout_dpll,
280 &clk_fout_vpll,
281 &clk_vpll,
282 &clk_xusbxti,
283};
284
285void __init s5p_register_clocks(unsigned long xtal_freq)
286{
287 int ret;
288
289 clk_ext_xtal_mux.rate = xtal_freq;
290
291 ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
292 if (ret > 0)
293 printk(KERN_ERR "Failed to register s5p clocks\n");
294}
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index 469b86260fe3..0b04b6b0fa30 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,56 +17,16 @@
17#include <linux/of_fdt.h> 17#include <linux/of_fdt.h>
18#include <linux/of.h> 18#include <linux/of.h>
19 19
20#include <plat/mfc.h>
21
22#ifdef CONFIG_SAMSUNG_ATAGS
23#include <mach/map.h>
24#include <mach/irqs.h>
25#include <plat/devs.h>
26
27static struct resource s5p_mfc_resource[] = {
28 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
29 [1] = DEFINE_RES_IRQ(IRQ_MFC),
30};
31
32struct platform_device s5p_device_mfc = {
33 .name = "s5p-mfc",
34 .id = -1,
35 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
36 .resource = s5p_mfc_resource,
37};
38
39/*
40 * MFC hardware has 2 memory interfaces which are modelled as two separate
41 * platform devices to let dma-mapping distinguish between them.
42 *
43 * MFC parent device (s5p_device_mfc) must be registered before memory
44 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
45 */
46
47struct platform_device s5p_device_mfc_l = {
48 .name = "s5p-mfc-l",
49 .id = -1,
50 .dev = {
51 .parent = &s5p_device_mfc.dev,
52 .dma_mask = &s5p_device_mfc_l.dev.coherent_dma_mask,
53 .coherent_dma_mask = DMA_BIT_MASK(32),
54 },
55};
56
57struct platform_device s5p_device_mfc_r = {
58 .name = "s5p-mfc-r",
59 .id = -1,
60 .dev = {
61 .parent = &s5p_device_mfc.dev,
62 .dma_mask = &s5p_device_mfc_r.dev.coherent_dma_mask,
63 .coherent_dma_mask = DMA_BIT_MASK(32),
64 },
65};
66#else
67static struct platform_device s5p_device_mfc_l; 20static struct platform_device s5p_device_mfc_l;
68static struct platform_device s5p_device_mfc_r; 21static struct platform_device s5p_device_mfc_r;
69#endif 22
23struct s5p_mfc_dt_meminfo {
24 unsigned long loff;
25 unsigned long lsize;
26 unsigned long roff;
27 unsigned long rsize;
28 char *compatible;
29};
70 30
71struct s5p_mfc_reserved_mem { 31struct s5p_mfc_reserved_mem {
72 phys_addr_t base; 32 phys_addr_t base;
@@ -77,7 +37,7 @@ struct s5p_mfc_reserved_mem {
77static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; 37static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
78 38
79 39
80void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, 40static void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
81 phys_addr_t lbase, unsigned int lsize) 41 phys_addr_t lbase, unsigned int lsize)
82{ 42{
83 int i; 43 int i;
@@ -100,28 +60,6 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
100 } 60 }
101} 61}
102 62
103#ifdef CONFIG_SAMSUNG_ATAGS
104static int __init s5p_mfc_memory_init(void)
105{
106 int i;
107
108 for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
109 struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
110 if (!area->base)
111 continue;
112
113 if (dma_declare_coherent_memory(area->dev, area->base,
114 area->base, area->size,
115 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
116 printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
117 area->size, (unsigned long) area->base);
118 }
119 return 0;
120}
121device_initcall(s5p_mfc_memory_init);
122#endif
123
124#ifdef CONFIG_OF
125int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, 63int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
126 int depth, void *data) 64 int depth, void *data)
127{ 65{
@@ -154,4 +92,3 @@ int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
154 92
155 return 1; 93 return 1;
156} 94}
157#endif
diff --git a/arch/arm/plat-samsung/s5p-dev-uart.c b/arch/arm/plat-samsung/s5p-dev-uart.c
deleted file mode 100644
index 8c4487af98c8..000000000000
--- a/arch/arm/plat-samsung/s5p-dev-uart.c
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright (c) 2009,2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Base S5P UART resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/irq.h>
21#include <mach/map.h>
22
23#include <plat/devs.h>
24
25 /* Serial port registrations */
26
27static struct resource s5p_uart0_resource[] = {
28 [0] = DEFINE_RES_MEM(S5P_PA_UART0, S5P_SZ_UART),
29 [1] = DEFINE_RES_IRQ(IRQ_UART0),
30};
31
32static struct resource s5p_uart1_resource[] = {
33 [0] = DEFINE_RES_MEM(S5P_PA_UART1, S5P_SZ_UART),
34 [1] = DEFINE_RES_IRQ(IRQ_UART1),
35};
36
37static struct resource s5p_uart2_resource[] = {
38 [0] = DEFINE_RES_MEM(S5P_PA_UART2, S5P_SZ_UART),
39 [1] = DEFINE_RES_IRQ(IRQ_UART2),
40};
41
42static struct resource s5p_uart3_resource[] = {
43#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
44 [0] = DEFINE_RES_MEM(S5P_PA_UART3, S5P_SZ_UART),
45 [1] = DEFINE_RES_IRQ(IRQ_UART3),
46#endif
47};
48
49static struct resource s5p_uart4_resource[] = {
50#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
51 [0] = DEFINE_RES_MEM(S5P_PA_UART4, S5P_SZ_UART),
52 [1] = DEFINE_RES_IRQ(IRQ_UART4),
53#endif
54};
55
56static struct resource s5p_uart5_resource[] = {
57#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
58 [0] = DEFINE_RES_MEM(S5P_PA_UART5, S5P_SZ_UART),
59 [1] = DEFINE_RES_IRQ(IRQ_UART5),
60#endif
61};
62
63struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
64 [0] = {
65 .resources = s5p_uart0_resource,
66 .nr_resources = ARRAY_SIZE(s5p_uart0_resource),
67 },
68 [1] = {
69 .resources = s5p_uart1_resource,
70 .nr_resources = ARRAY_SIZE(s5p_uart1_resource),
71 },
72 [2] = {
73 .resources = s5p_uart2_resource,
74 .nr_resources = ARRAY_SIZE(s5p_uart2_resource),
75 },
76 [3] = {
77 .resources = s5p_uart3_resource,
78 .nr_resources = ARRAY_SIZE(s5p_uart3_resource),
79 },
80 [4] = {
81 .resources = s5p_uart4_resource,
82 .nr_resources = ARRAY_SIZE(s5p_uart4_resource),
83 },
84 [5] = {
85 .resources = s5p_uart5_resource,
86 .nr_resources = ARRAY_SIZE(s5p_uart5_resource),
87 },
88};
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c
deleted file mode 100644
index ebee4dc11a94..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-eint.c
+++ /dev/null
@@ -1,221 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P - IRQ EINT support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/device.h>
17#include <linux/gpio.h>
18#include <linux/irqchip/arm-vic.h>
19#include <linux/of.h>
20
21#include <plat/regs-irqtype.h>
22
23#include <mach/map.h>
24#include <plat/cpu.h>
25#include <plat/pm.h>
26
27#include <plat/gpio-cfg.h>
28#include <mach/regs-gpio.h>
29
30static inline void s5p_irq_eint_mask(struct irq_data *data)
31{
32 u32 mask;
33
34 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
35 mask |= eint_irq_to_bit(data->irq);
36 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
37}
38
39static void s5p_irq_eint_unmask(struct irq_data *data)
40{
41 u32 mask;
42
43 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
44 mask &= ~(eint_irq_to_bit(data->irq));
45 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
46}
47
48static inline void s5p_irq_eint_ack(struct irq_data *data)
49{
50 __raw_writel(eint_irq_to_bit(data->irq),
51 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
52}
53
54static void s5p_irq_eint_maskack(struct irq_data *data)
55{
56 /* compiler should in-line these */
57 s5p_irq_eint_mask(data);
58 s5p_irq_eint_ack(data);
59}
60
61static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
62{
63 int offs = EINT_OFFSET(data->irq);
64 int shift;
65 u32 ctrl, mask;
66 u32 newvalue = 0;
67
68 switch (type) {
69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
71 break;
72
73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
75 break;
76
77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
79 break;
80
81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
83 break;
84
85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
87 break;
88
89 default:
90 printk(KERN_ERR "No such irq type %d", type);
91 return -EINVAL;
92 }
93
94 shift = (offs & 0x7) * 4;
95 mask = 0x7 << shift;
96
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
98 ctrl &= ~mask;
99 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
101
102 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
104
105 else if ((8 <= offs) && (offs < 16))
106 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
107
108 else if ((16 <= offs) && (offs < 24))
109 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
110
111 else if ((24 <= offs) && (offs < 32))
112 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
113
114 else
115 printk(KERN_ERR "No such irq number %d", offs);
116
117 return 0;
118}
119
120static struct irq_chip s5p_irq_eint = {
121 .name = "s5p-eint",
122 .irq_mask = s5p_irq_eint_mask,
123 .irq_unmask = s5p_irq_eint_unmask,
124 .irq_mask_ack = s5p_irq_eint_maskack,
125 .irq_ack = s5p_irq_eint_ack,
126 .irq_set_type = s5p_irq_eint_set_type,
127#ifdef CONFIG_PM
128 .irq_set_wake = s3c_irqext_wake,
129#endif
130};
131
132/* s5p_irq_demux_eint
133 *
134 * This function demuxes the IRQ from the group0 external interrupts,
135 * from EINTs 16 to 31. It is designed to be inlined into the specific
136 * handler s5p_irq_demux_eintX_Y.
137 *
138 * Each EINT pend/mask registers handle eight of them.
139 */
140static inline void s5p_irq_demux_eint(unsigned int start)
141{
142 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
143 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
144 unsigned int irq;
145
146 status &= ~mask;
147 status &= 0xff;
148
149 while (status) {
150 irq = fls(status) - 1;
151 generic_handle_irq(irq + start);
152 status &= ~(1 << irq);
153 }
154}
155
156static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
157{
158 s5p_irq_demux_eint(IRQ_EINT(16));
159 s5p_irq_demux_eint(IRQ_EINT(24));
160}
161
162static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
163{
164 void __iomem *base = irq_data_get_irq_chip_data(data);
165
166 s5p_irq_eint_mask(data);
167 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
168}
169
170static void s5p_irq_vic_eint_unmask(struct irq_data *data)
171{
172 void __iomem *base = irq_data_get_irq_chip_data(data);
173
174 s5p_irq_eint_unmask(data);
175 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
176}
177
178static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
179{
180 __raw_writel(eint_irq_to_bit(data->irq),
181 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
182}
183
184static void s5p_irq_vic_eint_maskack(struct irq_data *data)
185{
186 s5p_irq_vic_eint_mask(data);
187 s5p_irq_vic_eint_ack(data);
188}
189
190static struct irq_chip s5p_irq_vic_eint = {
191 .name = "s5p_vic_eint",
192 .irq_mask = s5p_irq_vic_eint_mask,
193 .irq_unmask = s5p_irq_vic_eint_unmask,
194 .irq_mask_ack = s5p_irq_vic_eint_maskack,
195 .irq_ack = s5p_irq_vic_eint_ack,
196 .irq_set_type = s5p_irq_eint_set_type,
197#ifdef CONFIG_PM
198 .irq_set_wake = s3c_irqext_wake,
199#endif
200};
201
202static int __init s5p_init_irq_eint(void)
203{
204 int irq;
205
206 if (of_have_populated_dt())
207 return -ENODEV;
208
209 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
210 irq_set_chip(irq, &s5p_irq_vic_eint);
211
212 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
213 irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
214 set_irq_flags(irq, IRQF_VALID);
215 }
216
217 irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
218 return 0;
219}
220
221arch_initcall(s5p_init_irq_eint);
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
deleted file mode 100644
index fafdb059043a..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ /dev/null
@@ -1,218 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * Author: Kyungmin Park <kyungmin.park@samsung.com>
4 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
5 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20#include <linux/slab.h>
21
22#include <mach/map.h>
23#include <plat/gpio-core.h>
24#include <plat/gpio-cfg.h>
25
26#define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
27
28#define CON_OFFSET 0x700
29#define MASK_OFFSET 0x900
30#define PEND_OFFSET 0xA00
31#define REG_OFFSET(x) ((x) << 2)
32
33struct s5p_gpioint_bank {
34 struct list_head list;
35 int start;
36 int nr_groups;
37 int irq;
38 struct samsung_gpio_chip **chips;
39 void (*handler)(unsigned int, struct irq_desc *);
40};
41
42static LIST_HEAD(banks);
43
44static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
45{
46 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
47 struct irq_chip_type *ct = gc->chip_types;
48 unsigned int shift = (d->irq - gc->irq_base) << 2;
49
50 switch (type) {
51 case IRQ_TYPE_EDGE_RISING:
52 type = S5P_IRQ_TYPE_EDGE_RISING;
53 break;
54 case IRQ_TYPE_EDGE_FALLING:
55 type = S5P_IRQ_TYPE_EDGE_FALLING;
56 break;
57 case IRQ_TYPE_EDGE_BOTH:
58 type = S5P_IRQ_TYPE_EDGE_BOTH;
59 break;
60 case IRQ_TYPE_LEVEL_HIGH:
61 type = S5P_IRQ_TYPE_LEVEL_HIGH;
62 break;
63 case IRQ_TYPE_LEVEL_LOW:
64 type = S5P_IRQ_TYPE_LEVEL_LOW;
65 break;
66 case IRQ_TYPE_NONE:
67 default:
68 printk(KERN_WARNING "No irq type\n");
69 return -EINVAL;
70 }
71
72 gc->type_cache &= ~(0x7 << shift);
73 gc->type_cache |= type << shift;
74 writel(gc->type_cache, gc->reg_base + ct->regs.type);
75 return 0;
76}
77
78static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
79{
80 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
81 int group, pend_offset, mask_offset;
82 unsigned int pend, mask;
83
84 struct irq_chip *chip = irq_get_chip(irq);
85 chained_irq_enter(chip, desc);
86
87 for (group = 0; group < bank->nr_groups; group++) {
88 struct samsung_gpio_chip *chip = bank->chips[group];
89 if (!chip)
90 continue;
91
92 pend_offset = REG_OFFSET(group);
93 pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
94 if (!pend)
95 continue;
96
97 mask_offset = REG_OFFSET(group);
98 mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
99 pend &= ~mask;
100
101 while (pend) {
102 int offset = fls(pend) - 1;
103 int real_irq = chip->irq_base + offset;
104 generic_handle_irq(real_irq);
105 pend &= ~BIT(offset);
106 }
107 }
108 chained_irq_exit(chip, desc);
109}
110
111static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
112{
113 static int used_gpioint_groups = 0;
114 int group = chip->group;
115 struct s5p_gpioint_bank *b, *bank = NULL;
116 struct irq_chip_generic *gc;
117 struct irq_chip_type *ct;
118
119 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
120 return -ENOMEM;
121
122 list_for_each_entry(b, &banks, list) {
123 if (group >= b->start && group < b->start + b->nr_groups) {
124 bank = b;
125 break;
126 }
127 }
128 if (!bank)
129 return -EINVAL;
130
131 if (!bank->handler) {
132 bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
133 bank->nr_groups, GFP_KERNEL);
134 if (!bank->chips)
135 return -ENOMEM;
136
137 irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
138 irq_set_handler_data(bank->irq, bank);
139 bank->handler = s5p_gpioint_handler;
140 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
141 bank->irq);
142 }
143
144 /*
145 * chained GPIO irq has been successfully registered, allocate new gpio
146 * int group and assign irq nubmers
147 */
148 chip->irq_base = S5P_GPIOINT_BASE +
149 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
150 used_gpioint_groups++;
151
152 bank->chips[group - bank->start] = chip;
153
154 gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
155 GPIO_BASE(chip),
156 handle_level_irq);
157 if (!gc)
158 return -ENOMEM;
159 ct = gc->chip_types;
160 ct->chip.irq_ack = irq_gc_ack_set_bit;
161 ct->chip.irq_mask = irq_gc_mask_set_bit;
162 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
163 ct->chip.irq_set_type = s5p_gpioint_set_type,
164 ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
165 ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
166 ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
167 irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
168 IRQ_GC_INIT_MASK_CACHE,
169 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
170 return 0;
171}
172
173int __init s5p_register_gpio_interrupt(int pin)
174{
175 struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
176 int offset, group;
177 int ret;
178
179 if (!my_chip)
180 return -EINVAL;
181
182 offset = pin - my_chip->chip.base;
183 group = my_chip->group;
184
185 /* check if the group has been already registered */
186 if (my_chip->irq_base)
187 goto success;
188
189 /* register gpio group */
190 ret = s5p_gpioint_add(my_chip);
191 if (ret == 0) {
192 my_chip->chip.to_irq = samsung_gpiolib_to_irq;
193 printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
194 group);
195 goto success;
196 }
197 return ret;
198success:
199 my_chip->bitmap_gpio_int |= BIT(offset);
200
201 return my_chip->irq_base + offset;
202}
203
204int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
205{
206 struct s5p_gpioint_bank *bank;
207
208 bank = kzalloc(sizeof(*bank), GFP_KERNEL);
209 if (!bank)
210 return -ENOMEM;
211
212 bank->start = start;
213 bank->nr_groups = nr_groups;
214 bank->irq = chain_irq;
215
216 list_add_tail(&bank->list, &banks);
217 return 0;
218}
diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c
deleted file mode 100644
index 52b16943617e..000000000000
--- a/arch/arm/plat-samsung/s5p-irq-pm.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Based on arch/arm/plat-s3c24xx/irq-pm.c,
6 * Copyright (c) 2003,2004 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18
19#include <plat/cpu.h>
20#include <plat/irqs.h>
21#include <plat/pm.h>
22#include <mach/map.h>
23
24#include <mach/regs-gpio.h>
25#include <mach/regs-irq.h>
26
27/* state for IRQs over sleep */
28
29/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
30 * as wakeup sources
31 *
32 * set bit to 1 in allow bitfield to enable the wakeup settings on it
33*/
34
35unsigned long s3c_irqwake_intallow = 0x00000006L;
36unsigned long s3c_irqwake_eintallow = 0xffffffffL;
37
38int s3c_irq_wake(struct irq_data *data, unsigned int state)
39{
40 unsigned long irqbit;
41 unsigned int irq_rtc_tic, irq_rtc_alarm;
42
43 irq_rtc_tic = IRQ_RTC_TIC;
44 irq_rtc_alarm = IRQ_RTC_ALARM;
45
46 if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
47 irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
48
49 if (!state)
50 s3c_irqwake_intmask |= irqbit;
51 else
52 s3c_irqwake_intmask &= ~irqbit;
53 } else {
54 return -ENOENT;
55 }
56
57 return 0;
58}
59
60static struct sleep_save eint_save[] = {
61 SAVE_ITEM(S5P_EINT_CON(0)),
62 SAVE_ITEM(S5P_EINT_CON(1)),
63 SAVE_ITEM(S5P_EINT_CON(2)),
64 SAVE_ITEM(S5P_EINT_CON(3)),
65
66 SAVE_ITEM(S5P_EINT_FLTCON(0)),
67 SAVE_ITEM(S5P_EINT_FLTCON(1)),
68 SAVE_ITEM(S5P_EINT_FLTCON(2)),
69 SAVE_ITEM(S5P_EINT_FLTCON(3)),
70 SAVE_ITEM(S5P_EINT_FLTCON(4)),
71 SAVE_ITEM(S5P_EINT_FLTCON(5)),
72 SAVE_ITEM(S5P_EINT_FLTCON(6)),
73 SAVE_ITEM(S5P_EINT_FLTCON(7)),
74
75 SAVE_ITEM(S5P_EINT_MASK(0)),
76 SAVE_ITEM(S5P_EINT_MASK(1)),
77 SAVE_ITEM(S5P_EINT_MASK(2)),
78 SAVE_ITEM(S5P_EINT_MASK(3)),
79};
80
81int s3c24xx_irq_suspend(void)
82{
83 s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
84
85 return 0;
86}
87
88void s3c24xx_irq_resume(void)
89{
90 s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
91}
92
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
deleted file mode 100644
index ddfaca9c79d8..000000000000
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * S5P - Interrupt handling
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/irqchip/arm-vic.h>
17
18#include <mach/irqs.h>
19#include <mach/map.h>
20#include <plat/cpu.h>
21
22void __init s5p_init_irq(u32 *vic, u32 num_vic)
23{
24#ifdef CONFIG_ARM_VIC
25 int irq;
26
27 /* initialize the VICs */
28 for (irq = 0; irq < num_vic; irq++)
29 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
30#endif
31}
diff --git a/arch/arm/plat-samsung/s5p-pm.c b/arch/arm/plat-samsung/s5p-pm.c
deleted file mode 100644
index 0747468f0936..000000000000
--- a/arch/arm/plat-samsung/s5p-pm.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P Power Manager (Suspend-To-RAM) support
6 *
7 * Based on arch/arm/plat-s3c24xx/pm.c
8 * Copyright (c) 2004,2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/suspend.h>
17#include <plat/pm.h>
18
19#define PFX "s5p pm: "
20
21/* s3c_pm_configure_extint
22 *
23 * configure all external interrupt pins
24*/
25
26void s3c_pm_configure_extint(void)
27{
28 /* nothing here yet */
29}
30
31void s3c_pm_restore_core(void)
32{
33 /* nothing here yet */
34}
35
36void s3c_pm_save_core(void)
37{
38 /* nothing here yet */
39}
40