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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 17:37:00 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 17:37:00 -0400
commit70ada77920723fbc2b35e9b301022fb1e166b41b (patch)
treef30f24135eff89020d8ae21d6c7a83cf5c812585 /arch/arm
parentb22793f7fdc38d73c4bb4299a313deef56dcfe66 (diff)
parent2764c500be0c1f057349ee6c81557239de060f87 (diff)
Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: (53 commits) spi/omap2_mcspi: Verify TX reg is empty after TX only xfer with DMA spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode spi/bfin_spi: namespace local structs spi/bfin_spi: init early spi/bfin_spi: check per-transfer bits_per_word spi/bfin_spi: warn when CS is driven by hardware (CPHA=0) spi/bfin_spi: cs should be always low when a new transfer begins spi/bfin_spi: fix typo in comment spi/bfin_spi: reject unsupported SPI modes spi/bfin_spi: use dma_disable_irq_nosync() in irq handler spi/bfin_spi: combine duplicate SPI_CTL read/write logic spi/bfin_spi: reset ctl_reg bits when setup is run again on a device spi/bfin_spi: push all size checks into the transfer function spi/bfin_spi: use nosync when disabling the IRQ from the IRQ handler spi/bfin_spi: sync hardware state before reprogramming everything spi/bfin_spi: save/restore state when suspending/resuming spi/bfin_spi: redo GPIO CS handling Blackfin: SPI: expand SPI bitmasks spi/bfin_spi: use the SPI namespaced bit names spi/bfin_spi: drop extra memory we don't need ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c7
-rw-r--r--arch/arm/mach-u300/dummyspichip.c5
-rw-r--r--arch/arm/mach-u300/spi.c10
-rw-r--r--arch/arm/mach-ux500/board-mop500.c8
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h3
5 files changed, 8 insertions, 25 deletions
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bc9a42da2145..0c936cf5675a 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -172,18 +172,12 @@ static void phy3250_spi_cs_set(u32 control)
172} 172}
173 173
174static struct pl022_config_chip spi0_chip_info = { 174static struct pl022_config_chip spi0_chip_info = {
175 .lbm = LOOPBACK_DISABLED,
176 .com_mode = INTERRUPT_TRANSFER, 175 .com_mode = INTERRUPT_TRANSFER,
177 .iface = SSP_INTERFACE_MOTOROLA_SPI, 176 .iface = SSP_INTERFACE_MOTOROLA_SPI,
178 .hierarchy = SSP_MASTER, 177 .hierarchy = SSP_MASTER,
179 .slave_tx_disable = 0, 178 .slave_tx_disable = 0,
180 .endian_tx = SSP_TX_LSB,
181 .endian_rx = SSP_RX_LSB,
182 .data_size = SSP_DATA_BITS_8,
183 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, 179 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
184 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, 180 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
185 .clk_phase = SSP_CLK_FIRST_EDGE,
186 .clk_pol = SSP_CLK_POL_IDLE_LOW,
187 .ctrl_len = SSP_BITS_8, 181 .ctrl_len = SSP_BITS_8,
188 .wait_state = SSP_MWIRE_WAIT_ZERO, 182 .wait_state = SSP_MWIRE_WAIT_ZERO,
189 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 183 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -239,6 +233,7 @@ static int __init phy3250_spi_board_register(void)
239 .max_speed_hz = 5000000, 233 .max_speed_hz = 5000000,
240 .bus_num = 0, 234 .bus_num = 0,
241 .chip_select = 0, 235 .chip_select = 0,
236 .mode = SPI_MODE_0,
242 .platform_data = &eeprom, 237 .platform_data = &eeprom,
243 .controller_data = &spi0_chip_info, 238 .controller_data = &spi0_chip_info,
244 }, 239 },
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 5f55012b7c9e..03f793612594 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -46,7 +46,6 @@ static ssize_t dummy_looptest(struct device *dev,
46 * struct, this is just used here to alter the behaviour of the chip 46 * struct, this is just used here to alter the behaviour of the chip
47 * in order to perform tests. 47 * in order to perform tests.
48 */ 48 */
49 struct pl022_config_chip *chip_info = spi->controller_data;
50 int status; 49 int status;
51 u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD, 50 u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD,
52 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05, 51 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05,
@@ -72,7 +71,7 @@ static ssize_t dummy_looptest(struct device *dev,
72 * Force chip to 8 bit mode 71 * Force chip to 8 bit mode
73 * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! 72 * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
74 */ 73 */
75 chip_info->data_size = SSP_DATA_BITS_8; 74 spi->bits_per_word = 8;
76 /* You should NOT DO THIS EITHER */ 75 /* You should NOT DO THIS EITHER */
77 spi->master->setup(spi); 76 spi->master->setup(spi);
78 77
@@ -159,7 +158,7 @@ static ssize_t dummy_looptest(struct device *dev,
159 * Force chip to 16 bit mode 158 * Force chip to 16 bit mode
160 * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! 159 * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
161 */ 160 */
162 chip_info->data_size = SSP_DATA_BITS_16; 161 spi->bits_per_word = 16;
163 /* You should NOT DO THIS EITHER */ 162 /* You should NOT DO THIS EITHER */
164 spi->master->setup(spi); 163 spi->master->setup(spi);
165 164
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index f0e887bea30e..edb2c0d255c2 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -30,8 +30,6 @@ static void select_dummy_chip(u32 chipselect)
30} 30}
31 31
32struct pl022_config_chip dummy_chip_info = { 32struct pl022_config_chip dummy_chip_info = {
33 /* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */
34 .lbm = LOOPBACK_ENABLED,
35 /* 33 /*
36 * available POLLING_TRANSFER and INTERRUPT_TRANSFER, 34 * available POLLING_TRANSFER and INTERRUPT_TRANSFER,
37 * DMA_TRANSFER does not work 35 * DMA_TRANSFER does not work
@@ -42,14 +40,8 @@ struct pl022_config_chip dummy_chip_info = {
42 .hierarchy = SSP_MASTER, 40 .hierarchy = SSP_MASTER,
43 /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ 41 /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
44 .slave_tx_disable = 0, 42 .slave_tx_disable = 0,
45 /* LSB first */
46 .endian_tx = SSP_TX_LSB,
47 .endian_rx = SSP_RX_LSB,
48 .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */
49 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 43 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
50 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 44 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
51 .clk_phase = SSP_CLK_SECOND_EDGE,
52 .clk_pol = SSP_CLK_POL_IDLE_LOW,
53 .ctrl_len = SSP_BITS_12, 45 .ctrl_len = SSP_BITS_12,
54 .wait_state = SSP_MWIRE_WAIT_ZERO, 46 .wait_state = SSP_MWIRE_WAIT_ZERO,
55 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 47 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
@@ -75,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = {
75 .bus_num = 0, /* Only one bus on this chip */ 67 .bus_num = 0, /* Only one bus on this chip */
76 .chip_select = 0, 68 .chip_select = 0,
77 /* Means SPI_CS_HIGH, change if e.g low CS */ 69 /* Means SPI_CS_HIGH, change if e.g low CS */
78 .mode = 0, 70 .mode = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP,
79 }, 71 },
80#endif 72#endif
81}; 73};
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0e8fd135a57d..219ae0ca4eef 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -55,19 +55,13 @@ static void ab4500_spi_cs_control(u32 command)
55} 55}
56 56
57struct pl022_config_chip ab4500_chip_info = { 57struct pl022_config_chip ab4500_chip_info = {
58 .lbm = LOOPBACK_DISABLED,
59 .com_mode = INTERRUPT_TRANSFER, 58 .com_mode = INTERRUPT_TRANSFER,
60 .iface = SSP_INTERFACE_MOTOROLA_SPI, 59 .iface = SSP_INTERFACE_MOTOROLA_SPI,
61 /* we can act as master only */ 60 /* we can act as master only */
62 .hierarchy = SSP_MASTER, 61 .hierarchy = SSP_MASTER,
63 .slave_tx_disable = 0, 62 .slave_tx_disable = 0,
64 .endian_rx = SSP_RX_MSB,
65 .endian_tx = SSP_TX_MSB,
66 .data_size = SSP_DATA_BITS_24,
67 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 63 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
68 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 64 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
69 .clk_phase = SSP_CLK_SECOND_EDGE,
70 .clk_pol = SSP_CLK_POL_IDLE_HIGH,
71 .cs_control = ab4500_spi_cs_control, 65 .cs_control = ab4500_spi_cs_control,
72}; 66};
73 67
@@ -83,7 +77,7 @@ static struct spi_board_info u8500_spi_devices[] = {
83 .max_speed_hz = 12000000, 77 .max_speed_hz = 12000000,
84 .bus_num = 0, 78 .bus_num = 0,
85 .chip_select = 0, 79 .chip_select = 0,
86 .mode = SPI_MODE_0, 80 .mode = SPI_MODE_3,
87 .irq = IRQ_DB8500_AB8500, 81 .irq = IRQ_DB8500_AB8500,
88 }, 82 },
89}; 83};
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index e5aba8f95b79..b226f7405e6b 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -32,6 +32,8 @@ struct s3c64xx_spi_csinfo {
32 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock. 34 * @src_clk_name: Platform name of the corresponding clock.
35 * @clk_from_cmu: If the SPI clock/prescalar control block is present
36 * by the platform's clock-management-unit and not in SPI controller.
35 * @num_cs: Number of CS this controller emulates. 37 * @num_cs: Number of CS this controller emulates.
36 * @cfg_gpio: Configure pins for this SPI controller. 38 * @cfg_gpio: Configure pins for this SPI controller.
37 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 39 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
@@ -41,6 +43,7 @@ struct s3c64xx_spi_csinfo {
41struct s3c64xx_spi_info { 43struct s3c64xx_spi_info {
42 int src_clk_nr; 44 int src_clk_nr;
43 char *src_clk_name; 45 char *src_clk_name;
46 bool clk_from_cmu;
44 47
45 int num_cs; 48 int num_cs;
46 49