diff options
24 files changed, 3842 insertions, 1232 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt index 80510c018eea..777abd7399d5 100644 --- a/Documentation/powerpc/dts-bindings/fsl/spi.txt +++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt | |||
| @@ -1,7 +1,9 @@ | |||
| 1 | * SPI (Serial Peripheral Interface) | 1 | * SPI (Serial Peripheral Interface) |
| 2 | 2 | ||
| 3 | Required properties: | 3 | Required properties: |
| 4 | - cell-index : SPI controller index. | 4 | - cell-index : QE SPI subblock index. |
| 5 | 0: QE subblock SPI1 | ||
| 6 | 1: QE subblock SPI2 | ||
| 5 | - compatible : should be "fsl,spi". | 7 | - compatible : should be "fsl,spi". |
| 6 | - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". | 8 | - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". |
| 7 | - reg : Offset and length of the register set for the device | 9 | - reg : Offset and length of the register set for the device |
| @@ -29,3 +31,23 @@ Example: | |||
| 29 | gpios = <&gpio 18 1 // device reg=<0> | 31 | gpios = <&gpio 18 1 // device reg=<0> |
| 30 | &gpio 19 1>; // device reg=<1> | 32 | &gpio 19 1>; // device reg=<1> |
| 31 | }; | 33 | }; |
| 34 | |||
| 35 | |||
| 36 | * eSPI (Enhanced Serial Peripheral Interface) | ||
| 37 | |||
| 38 | Required properties: | ||
| 39 | - compatible : should be "fsl,mpc8536-espi". | ||
| 40 | - reg : Offset and length of the register set for the device. | ||
| 41 | - interrupts : should contain eSPI interrupt, the device has one interrupt. | ||
| 42 | - fsl,espi-num-chipselects : the number of the chipselect signals. | ||
| 43 | |||
| 44 | Example: | ||
| 45 | spi@110000 { | ||
| 46 | #address-cells = <1>; | ||
| 47 | #size-cells = <0>; | ||
| 48 | compatible = "fsl,mpc8536-espi"; | ||
| 49 | reg = <0x110000 0x1000>; | ||
| 50 | interrupts = <53 0x2>; | ||
| 51 | interrupt-parent = <&mpic>; | ||
| 52 | fsl,espi-num-chipselects = <4>; | ||
| 53 | }; | ||
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index bc9a42da2145..0c936cf5675a 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c | |||
| @@ -172,18 +172,12 @@ static void phy3250_spi_cs_set(u32 control) | |||
| 172 | } | 172 | } |
| 173 | 173 | ||
| 174 | static struct pl022_config_chip spi0_chip_info = { | 174 | static struct pl022_config_chip spi0_chip_info = { |
| 175 | .lbm = LOOPBACK_DISABLED, | ||
| 176 | .com_mode = INTERRUPT_TRANSFER, | 175 | .com_mode = INTERRUPT_TRANSFER, |
| 177 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | 176 | .iface = SSP_INTERFACE_MOTOROLA_SPI, |
| 178 | .hierarchy = SSP_MASTER, | 177 | .hierarchy = SSP_MASTER, |
| 179 | .slave_tx_disable = 0, | 178 | .slave_tx_disable = 0, |
| 180 | .endian_tx = SSP_TX_LSB, | ||
| 181 | .endian_rx = SSP_RX_LSB, | ||
| 182 | .data_size = SSP_DATA_BITS_8, | ||
| 183 | .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, | 179 | .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, |
| 184 | .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, | 180 | .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, |
| 185 | .clk_phase = SSP_CLK_FIRST_EDGE, | ||
| 186 | .clk_pol = SSP_CLK_POL_IDLE_LOW, | ||
| 187 | .ctrl_len = SSP_BITS_8, | 181 | .ctrl_len = SSP_BITS_8, |
| 188 | .wait_state = SSP_MWIRE_WAIT_ZERO, | 182 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
| 189 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | 183 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
| @@ -239,6 +233,7 @@ static int __init phy3250_spi_board_register(void) | |||
| 239 | .max_speed_hz = 5000000, | 233 | .max_speed_hz = 5000000, |
| 240 | .bus_num = 0, | 234 | .bus_num = 0, |
| 241 | .chip_select = 0, | 235 | .chip_select = 0, |
| 236 | .mode = SPI_MODE_0, | ||
| 242 | .platform_data = &eeprom, | 237 | .platform_data = &eeprom, |
| 243 | .controller_data = &spi0_chip_info, | 238 | .controller_data = &spi0_chip_info, |
| 244 | }, | 239 | }, |
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c index 5f55012b7c9e..03f793612594 100644 --- a/arch/arm/mach-u300/dummyspichip.c +++ b/arch/arm/mach-u300/dummyspichip.c | |||
| @@ -46,7 +46,6 @@ static ssize_t dummy_looptest(struct device *dev, | |||
| 46 | * struct, this is just used here to alter the behaviour of the chip | 46 | * struct, this is just used here to alter the behaviour of the chip |
| 47 | * in order to perform tests. | 47 | * in order to perform tests. |
| 48 | */ | 48 | */ |
| 49 | struct pl022_config_chip *chip_info = spi->controller_data; | ||
| 50 | int status; | 49 | int status; |
| 51 | u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD, | 50 | u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD, |
| 52 | 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05, | 51 | 0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05, |
| @@ -72,7 +71,7 @@ static ssize_t dummy_looptest(struct device *dev, | |||
| 72 | * Force chip to 8 bit mode | 71 | * Force chip to 8 bit mode |
| 73 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! | 72 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! |
| 74 | */ | 73 | */ |
| 75 | chip_info->data_size = SSP_DATA_BITS_8; | 74 | spi->bits_per_word = 8; |
| 76 | /* You should NOT DO THIS EITHER */ | 75 | /* You should NOT DO THIS EITHER */ |
| 77 | spi->master->setup(spi); | 76 | spi->master->setup(spi); |
| 78 | 77 | ||
| @@ -159,7 +158,7 @@ static ssize_t dummy_looptest(struct device *dev, | |||
| 159 | * Force chip to 16 bit mode | 158 | * Force chip to 16 bit mode |
| 160 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! | 159 | * WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC! |
| 161 | */ | 160 | */ |
| 162 | chip_info->data_size = SSP_DATA_BITS_16; | 161 | spi->bits_per_word = 16; |
| 163 | /* You should NOT DO THIS EITHER */ | 162 | /* You should NOT DO THIS EITHER */ |
| 164 | spi->master->setup(spi); | 163 | spi->master->setup(spi); |
| 165 | 164 | ||
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index f0e887bea30e..edb2c0d255c2 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c | |||
| @@ -30,8 +30,6 @@ static void select_dummy_chip(u32 chipselect) | |||
| 30 | } | 30 | } |
| 31 | 31 | ||
| 32 | struct pl022_config_chip dummy_chip_info = { | 32 | struct pl022_config_chip dummy_chip_info = { |
| 33 | /* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */ | ||
| 34 | .lbm = LOOPBACK_ENABLED, | ||
| 35 | /* | 33 | /* |
| 36 | * available POLLING_TRANSFER and INTERRUPT_TRANSFER, | 34 | * available POLLING_TRANSFER and INTERRUPT_TRANSFER, |
| 37 | * DMA_TRANSFER does not work | 35 | * DMA_TRANSFER does not work |
| @@ -42,14 +40,8 @@ struct pl022_config_chip dummy_chip_info = { | |||
| 42 | .hierarchy = SSP_MASTER, | 40 | .hierarchy = SSP_MASTER, |
| 43 | /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ | 41 | /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ |
| 44 | .slave_tx_disable = 0, | 42 | .slave_tx_disable = 0, |
| 45 | /* LSB first */ | ||
| 46 | .endian_tx = SSP_TX_LSB, | ||
| 47 | .endian_rx = SSP_RX_LSB, | ||
| 48 | .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */ | ||
| 49 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | 43 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, |
| 50 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | 44 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, |
| 51 | .clk_phase = SSP_CLK_SECOND_EDGE, | ||
| 52 | .clk_pol = SSP_CLK_POL_IDLE_LOW, | ||
| 53 | .ctrl_len = SSP_BITS_12, | 45 | .ctrl_len = SSP_BITS_12, |
| 54 | .wait_state = SSP_MWIRE_WAIT_ZERO, | 46 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
| 55 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | 47 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
| @@ -75,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = { | |||
| 75 | .bus_num = 0, /* Only one bus on this chip */ | 67 | .bus_num = 0, /* Only one bus on this chip */ |
| 76 | .chip_select = 0, | 68 | .chip_select = 0, |
| 77 | /* Means SPI_CS_HIGH, change if e.g low CS */ | 69 | /* Means SPI_CS_HIGH, change if e.g low CS */ |
| 78 | .mode = 0, | 70 | .mode = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP, |
| 79 | }, | ||
