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authorOlof Johansson <olof@lixom.net>2013-10-28 17:39:03 -0400
committerOlof Johansson <olof@lixom.net>2013-10-28 17:39:03 -0400
commit43d93947a54cf9323198a3a37eaf3ec14adb23e1 (patch)
tree0c290a7fcbc644b94527f399e4f9509a8d379a5d /arch/arm
parent02673f94d04e629e4cdc41e2bf2dc980743cf3df (diff)
parent54b89756a14aa1043507ce0811b4b6c02c5dddcc (diff)
Merge tag 'omap-for-v3.13/cm-scm-cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Paul Walmsley <paul@pwsan.com> via Tony Lindgren: Move some of the OMAP2+ CM and System Control Module direct register accesses into CM- and System Control Module-specific "drivers" underneath arch/arm/mach-omap2/. This is a prerequisite for moving this code out of arch/arm/mach-omap2/ into drivers/. Basic test logs are available here: http://www.pwsan.com/omap/testlogs/cm_scm_cleanup_a_v3.13/20131019101809/ * tag 'omap-for-v3.13/cm-scm-cleanup-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP3: control: add API for setting IVA bootmode ARM: OMAP3: CM/control: move CM scratchpad save to CM driver ARM: OMAP3: McBSP: do not access CM register directly ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock ARM: OMAP2: CM/PM: remove direct register accesses outside CM code + Linux 3.12-rc4 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts49
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi11
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi6
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi12
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi3
-rw-r--r--arch/arm/boot/dts/prima2.dtsi27
-rw-r--r--arch/arm/common/edma.c38
-rw-r--r--arch/arm/configs/multi_v7_defconfig1
-rw-r--r--arch/arm/crypto/aes-armv4.S6
-rw-r--r--arch/arm/include/asm/uaccess.h7
-rw-r--r--arch/arm/kernel/entry-common.S4
-rw-r--r--arch/arm/kernel/entry-header.S8
-rw-r--r--arch/arm/kvm/reset.c6
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c2
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c2
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S8
-rw-r--r--arch/arm/mach-at91/at91x40_time.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h4
-rw-r--r--arch/arm/mach-integrator/pci_v3.h7
-rw-r--r--arch/arm/mach-mvebu/coherency.c8
-rw-r--r--arch/arm/mach-mvebu/pmsu.c1
-rw-r--r--arch/arm/mach-mvebu/system-controller.c1
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c4
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c11
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c24
-rw-r--r--arch/arm/mach-omap2/clock.c38
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c67
-rw-r--r--arch/arm/mach-omap2/cm2xxx.h8
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c22
-rw-r--r--arch/arm/mach-omap2/cm3xxx.h1
-rw-r--r--arch/arm/mach-omap2/control.c54
-rw-r--r--arch/arm/mach-omap2/control.h1
-rw-r--r--arch/arm/mach-omap2/mcbsp.c16
-rw-r--r--arch/arm/mach-omap2/pm24xx.c24
-rw-r--r--arch/arm/mach-omap2/pm34xx.c3
-rw-r--r--arch/arm/mach-vexpress/tc2_pm.c11
40 files changed, 355 insertions, 151 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da5e1b0d322c..25ad39a52ecd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2185,8 +2185,7 @@ config NEON
2185 2185
2186config KERNEL_MODE_NEON 2186config KERNEL_MODE_NEON
2187 bool "Support for NEON in kernel mode" 2187 bool "Support for NEON in kernel mode"
2188 default n 2188 depends on NEON && AEABI
2189 depends on NEON
2190 help 2189 help
2191 Say Y to include support for NEON in kernel mode. 2190 Say Y to include support for NEON in kernel mode.
2192 2191
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3b07800536f7..c485157b0b5b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -41,6 +41,8 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
41dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 41dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
43 43
44dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
45
44dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 46dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
45dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \ 47dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
46 bcm28155-ap.dtb 48 bcm28155-ap.dtb
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 05e4485a8225..8ac2ac1f69cc 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -27,6 +27,25 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
31 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
32
33 pcie-controller {
34 status = "okay";
35
36 /* Connected to Marvell SATA controller */
37 pcie@1,0 {
38 /* Port 0, Lane 0 */
39 status = "okay";
40 };
41
42 /* Connected to FL1009 USB 3.0 controller */
43 pcie@2,0 {
44 /* Port 1, Lane 0 */
45 status = "okay";
46 };
47 };
48
30 internal-regs { 49 internal-regs {
31 serial@12000 { 50 serial@12000 {
32 clock-frequency = <200000000>; 51 clock-frequency = <200000000>;
@@ -57,6 +76,11 @@
57 marvell,pins = "mpp56"; 76 marvell,pins = "mpp56";
58 marvell,function = "gpio"; 77 marvell,function = "gpio";
59 }; 78 };
79
80 poweroff: poweroff {
81 marvell,pins = "mpp8";
82 marvell,function = "gpio";
83 };
60 }; 84 };
61 85
62 mdio { 86 mdio {
@@ -89,22 +113,6 @@
89 pwm_polarity = <0>; 113 pwm_polarity = <0>;
90 }; 114 };
91 }; 115 };
92
93 pcie-controller {
94 status = "okay";
95
96 /* Connected to Marvell SATA controller */
97 pcie@1,0 {
98 /* Port 0, Lane 0 */
99 status = "okay";
100 };
101
102 /* Connected to FL1009 USB 3.0 controller */
103 pcie@2,0 {
104 /* Port 1, Lane 0 */
105 status = "okay";
106 };
107 };
108 }; 116 };
109 }; 117 };
110 118
@@ -160,7 +168,7 @@
160 button@1 { 168 button@1 {
161 label = "Power Button"; 169 label = "Power Button";
162 linux,code = <116>; /* KEY_POWER */ 170 linux,code = <116>; /* KEY_POWER */
163 gpios = <&gpio1 30 1>; 171 gpios = <&gpio1 30 0>;
164 }; 172 };
165 173
166 button@2 { 174 button@2 {
@@ -176,4 +184,11 @@
176 }; 184 };
177 }; 185 };
178 186
187 gpio_poweroff {
188 compatible = "gpio-poweroff";
189 pinctrl-0 = <&poweroff>;
190 pinctrl-names = "default";
191 gpios = <&gpio0 8 1>;
192 };
193
179}; 194};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index def125c0eeaa..3058522f5aad 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -70,6 +70,8 @@
70 70
71 timer@20300 { 71 timer@20300 {
72 compatible = "marvell,armada-xp-timer"; 72 compatible = "marvell,armada-xp-timer";
73 clocks = <&coreclk 2>, <&refclk>;
74 clock-names = "nbclk", "fixed";
73 }; 75 };
74 76
75 coreclk: mvebu-sar@18230 { 77 coreclk: mvebu-sar@18230 {
@@ -169,4 +171,13 @@
169 }; 171 };
170 }; 172 };
171 }; 173 };
174
175 clocks {
176 /* 25 MHz reference crystal */
177 refclk: oscillator {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <25000000>;
181 };
182 };
172}; 183};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 417899002c41..40267a116c3c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -190,12 +190,12 @@
190 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ 190 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
191 }; 191 };
192 192
193 pinctrl_uart2_rts: uart2_rts-0 { 193 pinctrl_usart2_rts: usart2_rts-0 {
194 atmel,pins = 194 atmel,pins =
195 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 195 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
196 }; 196 };
197 197
198 pinctrl_uart2_cts: uart2_cts-0 { 198 pinctrl_usart2_cts: usart2_cts-0 {
199 atmel,pins = 199 atmel,pins =
200 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 200 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
201 }; 201 };
@@ -505,6 +505,7 @@
505 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 505 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
506 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; 506 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
507 dma-names = "rxtx"; 507 dma-names = "rxtx";
508 pinctrl-names = "default";
508 #address-cells = <1>; 509 #address-cells = <1>;
509 #size-cells = <0>; 510 #size-cells = <0>;
510 status = "disabled"; 511 status = "disabled";
@@ -516,6 +517,7 @@
516 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 517 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
517 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; 518 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
518 dma-names = "rxtx"; 519 dma-names = "rxtx";
520 pinctrl-names = "default";
519 #address-cells = <1>; 521 #address-cells = <1>;
520 #size-cells = <0>; 522 #size-cells = <0>;
521 status = "disabled"; 523 status = "disabled";
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 8678e0c11119..6db4f81d4795 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -181,6 +181,8 @@
181 interrupts = <17>; 181 interrupts = <17>;
182 fifosize = <128>; 182 fifosize = <128>;
183 clocks = <&clks 13>; 183 clocks = <&clks 13>;
184 sirf,uart-dma-rx-channel = <21>;
185 sirf,uart-dma-tx-channel = <2>;
184 }; 186 };
185 187
186 uart1: uart@b0060000 { 188 uart1: uart@b0060000 {
@@ -199,6 +201,8 @@
199 interrupts = <19>; 201 interrupts = <19>;
200 fifosize = <128>; 202 fifosize = <128>;
201 clocks = <&clks 15>; 203 clocks = <&clks 15>;
204 sirf,uart-dma-rx-channel = <6>;
205 sirf,uart-dma-tx-channel = <7>;
202 }; 206 };
203 207
204 usp0: usp@b0080000 { 208 usp0: usp@b0080000 {
@@ -206,7 +210,10 @@
206 compatible = "sirf,prima2-usp"; 210 compatible = "sirf,prima2-usp";
207 reg = <0xb0080000 0x10000>; 211 reg = <0xb0080000 0x10000>;
208 interrupts = <20>; 212 interrupts = <20>;
213 fifosize = <128>;
209 clocks = <&clks 28>; 214 clocks = <&clks 28>;
215 sirf,usp-dma-rx-channel = <17>;
216 sirf,usp-dma-tx-channel = <18>;
210 }; 217 };
211 218
212 usp1: usp@b0090000 { 219 usp1: usp@b0090000 {
@@ -214,7 +221,10 @@
214 compatible = "sirf,prima2-usp"; 221 compatible = "sirf,prima2-usp";
215 reg = <0xb0090000 0x10000>; 222 reg = <0xb0090000 0x10000>;
216 interrupts = <21>; 223 interrupts = <21>;
224 fifosize = <128>;
217 clocks = <&clks 29>; 225 clocks = <&clks 29>;
226 sirf,usp-dma-rx-channel = <14>;
227 sirf,usp-dma-tx-channel = <15>;
218 }; 228 };
219 229
220 dmac0: dma-controller@b00b0000 { 230 dmac0: dma-controller@b00b0000 {
@@ -237,6 +247,8 @@
237 compatible = "sirf,prima2-vip"; 247 compatible = "sirf,prima2-vip";
238 reg = <0xb00C0000 0x10000>; 248 reg = <0xb00C0000 0x10000>;
239 clocks = <&clks 31>; 249 clocks = <&clks 31>;
250 interrupts = <14>;
251 sirf,vip-dma-rx-channel = <16>;
240 }; 252 };
241 253
242 spi0: spi@b00d0000 { 254 spi0: spi@b00d0000 {
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cf7aeaf89e9c..1335b2e1bed4 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -13,6 +13,7 @@
13 cpu@0 { 13 cpu@0 {
14 device_type = "cpu"; 14 device_type = "cpu";
15 compatible = "marvell,feroceon"; 15 compatible = "marvell,feroceon";
16 reg = <0>;
16 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; 17 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
17 clock-names = "cpu_clk", "ddrclk", "powersave"; 18 clock-names = "cpu_clk", "ddrclk", "powersave";
18 }; 19 };
@@ -167,7 +168,7 @@
167 xor@60900 { 168 xor@60900 {
168 compatible = "marvell,orion-xor"; 169 compatible = "marvell,orion-xor";
169 reg = <0x60900 0x100 170 reg = <0x60900 0x100
170 0xd0B00 0x100>; 171 0x60B00 0x100>;
171 status = "okay"; 172 status = "okay";
172 clocks = <&gate_clk 16>; 173 clocks = <&gate_clk 16>;
173 174
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index bbeb623fc2c6..27ed9f5144bc 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -171,7 +171,8 @@
171 compatible = "simple-bus"; 171 compatible = "simple-bus";
172 #address-cells = <1>; 172 #address-cells = <1>;
173 #size-cells = <1>; 173 #size-cells = <1>;
174 ranges = <0xb0000000 0xb0000000 0x180000>; 174 ranges = <0xb0000000 0xb0000000 0x180000>,
175 <0x56000000 0x56000000 0x1b00000>;
175 176
176 timer@b0020000 { 177 timer@b0020000 {
177 compatible = "sirf,prima2-tick"; 178 compatible = "sirf,prima2-tick";
@@ -196,25 +197,32 @@
196 uart0: uart@b0050000 { 197 uart0: uart@b0050000 {
197 cell-index = <0>; 198 cell-index = <0>;
198 compatible = "sirf,prima2-uart"; 199 compatible = "sirf,prima2-uart";
199 reg = <0xb0050000 0x10000>; 200 reg = <0xb0050000 0x1000>;
200 interrupts = <17>; 201 interrupts = <17>;
202 fifosize = <128>;
201 clocks = <&clks 13>; 203 clocks = <&clks 13>;
204 sirf,uart-dma-rx-channel = <21>;
205 sirf,uart-dma-tx-channel = <2>;
202 }; 206 };
203 207
204 uart1: uart@b0060000 { 208 uart1: uart@b0060000 {
205 cell-index = <1>; 209 cell-index = <1>;
206 compatible = "sirf,prima2-uart"; 210 compatible = "sirf,prima2-uart";
207 reg = <0xb0060000 0x10000>; 211 reg = <0xb0060000 0x1000>;
208 interrupts = <18>; 212 interrupts = <18>;
213 fifosize = <32>;
209 clocks = <&clks 14>; 214 clocks = <&clks 14>;
210 }; 215 };
211 216
212 uart2: uart@b0070000 { 217 uart2: uart@b0070000 {
213 cell-index = <2>; 218 cell-index = <2>;
214 compatible = "sirf,prima2-uart"; 219 compatible = "sirf,prima2-uart";
215 reg = <0xb0070000 0x10000>; 220 reg = <0xb0070000 0x1000>;
216 interrupts = <19>; 221 interrupts = <19>;
222 fifosize = <128>;
217 clocks = <&clks 15>; 223 clocks = <&clks 15>;
224 sirf,uart-dma-rx-channel = <6>;
225 sirf,uart-dma-tx-channel = <7>;
218 }; 226 };
219 227
220 usp0: usp@b0080000 { 228 usp0: usp@b0080000 {
@@ -222,7 +230,10 @@
222 compatible = "sirf,prima2-usp"; 230 compatible = "sirf,prima2-usp";
223 reg = <0xb0080000 0x10000>; 231 reg = <0xb0080000 0x10000>;
224 interrupts = <20>; 232 interrupts = <20>;
233 fifosize = <128>;
225 clocks = <&clks 28>; 234 clocks = <&clks 28>;
235 sirf,usp-dma-rx-channel = <17>;
236 sirf,usp-dma-tx-channel = <18>;
226 }; 237 };
227 238
228 usp1: usp@b0090000 { 239 usp1: usp@b0090000 {
@@ -230,7 +241,10 @@
230 compatible = "sirf,prima2-usp"; 241 compatible = "sirf,prima2-usp";
231 reg = <0xb0090000 0x10000>; 242 reg = <0xb0090000 0x10000>;
232 interrupts = <21>; 243 interrupts = <21>;
244 fifosize = <128>;
233 clocks = <&clks 29>; 245 clocks = <&clks 29>;
246 sirf,usp-dma-rx-channel = <14>;
247 sirf,usp-dma-tx-channel = <15>;
234 }; 248 };
235 249
236 usp2: usp@b00a0000 { 250 usp2: usp@b00a0000 {
@@ -238,7 +252,10 @@
238 compatible = "sirf,prima2-usp"; 252 compatible = "sirf,prima2-usp";
239 reg = <0xb00a0000 0x10000>; 253 reg = <0xb00a0000 0x10000>;
240 interrupts = <22>; 254 interrupts = <22>;
255 fifosize = <128>;
241 clocks = <&clks 30>; 256 clocks = <&clks 30>;
257 sirf,usp-dma-rx-channel = <10>;
258 sirf,usp-dma-tx-channel = <11>;
242 }; 259 };
243 260
244 dmac0: dma-controller@b00b0000 { 261 dmac0: dma-controller@b00b0000 {
@@ -261,6 +278,8 @@
261 compatible = "sirf,prima2-vip"; 278 compatible = "sirf,prima2-vip";
262 reg = <0xb00C0000 0x10000>; 279 reg = <0xb00C0000 0x10000>;
263 clocks = <&clks 31>; 280 clocks = <&clks 31>;
281 interrupts = <14>;
282 sirf,vip-dma-rx-channel = <16>;
264 }; 283 };
265 284
266 spi0: spi@b00d0000 { 285 spi0: spi@b00d0000 {
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 117f955a2a06..8e1a0245907f 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -269,6 +269,11 @@ static const struct edmacc_param dummy_paramset = {
269 .ccnt = 1, 269 .ccnt = 1,
270}; 270};
271 271
272static const struct of_device_id edma_of_ids[] = {
273 { .compatible = "ti,edma3", },
274 {}
275};
276
272/*****************************************************************************/ 277/*****************************************************************************/
273 278
274static void map_dmach_queue(unsigned ctlr, unsigned ch_no, 279static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
@@ -560,14 +565,38 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
560static int prepare_unused_channel_list(struct device *dev, void *data) 565static int prepare_unused_channel_list(struct device *dev, void *data)
561{ 566{
562 struct platform_device *pdev = to_platform_device(dev); 567 struct platform_device *pdev = to_platform_device(dev);
563 int i, ctlr; 568 int i, count, ctlr;
569 struct of_phandle_args dma_spec;
564 570
571 if (dev->of_node) {
572 count = of_property_count_strings(dev->of_node, "dma-names");
573 if (count < 0)
574 return 0;
575 for (i = 0; i < count; i++) {
576 if (of_parse_phandle_with_args(dev->of_node, "dmas",
577 "#dma-cells", i,
578 &dma_spec))
579 continue;
580
581 if (!of_match_node(edma_of_ids, dma_spec.np)) {
582 of_node_put(dma_spec.np);
583 continue;
584 }
585
586 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
587 edma_cc[0]->edma_unused);
588 of_node_put(dma_spec.np);
589 }
590 return 0;
591 }
592
593 /* For non-OF case */
565 for (i = 0; i < pdev->num_resources; i++) { 594 for (i = 0; i < pdev->num_resources; i++) {
566 if ((pdev->resource[i].flags & IORESOURCE_DMA) && 595 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
567 (int)pdev->resource[i].start >= 0) { 596 (int)pdev->resource[i].start >= 0) {
568 ctlr = EDMA_CTLR(pdev->resource[i].start); 597 ctlr = EDMA_CTLR(pdev->resource[i].start);
569 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), 598 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
570 edma_cc[ctlr]->edma_unused); 599 edma_cc[ctlr]->edma_unused);
571 } 600 }
572 } 601 }
573 602
@@ -1762,11 +1791,6 @@ static int edma_probe(struct platform_device *pdev)
1762 return 0; 1791 return 0;
1763} 1792}
1764 1793
1765static const struct of_device_id edma_of_ids[] = {
1766 { .compatible = "ti,edma3", },
1767 {}
1768};
1769
1770static struct platform_driver edma_driver = { 1794static struct platform_driver edma_driver = {
1771 .driver = { 1795 .driver = {
1772 .name = "edma", 1796 .name = "edma",
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index f3935b46df29..119fc378fc52 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -135,6 +135,7 @@ CONFIG_MMC=y
135CONFIG_MMC_ARMMMCI=y 135CONFIG_MMC_ARMMMCI=y
136CONFIG_MMC_SDHCI=y 136CONFIG_MMC_SDHCI=y
137CONFIG_MMC_SDHCI_PLTFM=y 137CONFIG_MMC_SDHCI_PLTFM=y
138CONFIG_MMC_SDHCI_ESDHC_IMX=y
138CONFIG_MMC_SDHCI_TEGRA=y 139CONFIG_MMC_SDHCI_TEGRA=y
139CONFIG_MMC_SDHCI_SPEAR=y 140CONFIG_MMC_SDHCI_SPEAR=y
140CONFIG_MMC_OMAP=y 141CONFIG_MMC_OMAP=y
diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S
index 19d6cd6f29f9..3a14ea8fe97e 100644
--- a/arch/arm/crypto/aes-armv4.S
+++ b/arch/arm/crypto/aes-armv4.S
@@ -148,7 +148,7 @@ AES_Te:
148@ const AES_KEY *key) { 148@ const AES_KEY *key) {
149.align 5 149.align 5
150ENTRY(AES_encrypt) 150ENTRY(AES_encrypt)
151 sub r3,pc,#8 @ AES_encrypt 151 adr r3,AES_encrypt
152 stmdb sp!,{r1,r4-r12,lr} 152 stmdb sp!,{r1,r4-r12,lr}
153 mov r12,r0 @ inp 153 mov r12,r0 @ inp
154 mov r11,r2 154 mov r11,r2
@@ -381,7 +381,7 @@ _armv4_AES_encrypt:
381.align 5 381.align 5
382ENTRY(private_AES_set_encrypt_key) 382ENTRY(private_AES_set_encrypt_key)
383_armv4_AES_set_encrypt_key: 383_armv4_AES_set_encrypt_key:
384 sub r3,pc,#8 @ AES_set_encrypt_key 384 adr r3,_armv4_AES_set_encrypt_key
385 teq r0,#0 385 teq r0,#0
386 moveq r0,#-1 386 moveq r0,#-1
387 beq .Labrt 387 beq .Labrt
@@ -843,7 +843,7 @@ AES_Td:
843@ const AES_KEY *key) { 843@ const AES_KEY *key) {
844.align 5 844.align 5
845ENTRY(AES_decrypt) 845ENTRY(AES_decrypt)
846 sub r3,pc,#8 @ AES_decrypt 846 adr r3,AES_decrypt
847 stmdb sp!,{r1,r4-r12,lr} 847 stmdb sp!,{r1,r4-r12,lr}
848 mov r12,r0 @ inp 848 mov r12,r0 @ inp
849 mov r11,r2 849 mov r11,r2
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 7e1f76027f66..72abdc541f38 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -19,6 +19,13 @@
19#include <asm/unified.h> 19#include <asm/unified.h>
20#include <asm/compiler.h> 20#include <asm/compiler.h>
21 21
22#if __LINUX_ARM_ARCH__ < 6
23#include <asm-generic/uaccess-unaligned.h>
24#else
25#define __get_user_unaligned __get_user
26#define __put_user_unaligned __put_user
27#endif
28
22#define VERIFY_READ 0 29#define VERIFY_READ 0
23#define VERIFY_WRITE 1 30#define VERIFY_WRITE 1
24 31
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 74ad15d1a065..bc6bd9683ba4 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -442,10 +442,10 @@ local_restart:
442 ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine 442 ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
443 443
444 add r1, sp, #S_OFF 444 add r1, sp, #S_OFF
445 cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE) 4452: cmp scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)
446 eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back 446 eor r0, scno, #__NR_SYSCALL_BASE @ put OS number back
447 bcs arm_syscall 447 bcs arm_syscall
4482: mov why, #0 @ no longer a real syscall 448 mov why, #0 @ no longer a real syscall
449 b sys_ni_syscall @ not private func 449 b sys_ni_syscall @ not private func
450 450
451#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI) 451#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index de23a9beed13..39f89fbd5111 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -329,10 +329,10 @@
329#ifdef CONFIG_CONTEXT_TRACKING 329#ifdef CONFIG_CONTEXT_TRACKING
330 .if \save 330 .if \save
331 stmdb sp!, {r0-r3, ip, lr} 331 stmdb sp!, {r0-r3, ip, lr}
332 bl user_exit 332 bl context_tracking_user_exit
333 ldmia sp!, {r0-r3, ip, lr} 333 ldmia sp!, {r0-r3, ip, lr}
334 .else 334 .else
335 bl user_exit 335 bl context_tracking_user_exit
336 .endif 336 .endif
337#endif 337#endif
338 .endm 338 .endm
@@ -341,10 +341,10 @@
341#ifdef CONFIG_CONTEXT_TRACKING 341#ifdef CONFIG_CONTEXT_TRACKING
342 .if \save 342 .if \save
343 stmdb sp!, {r0-r3, ip, lr} 343 stmdb sp!, {r0-r3, ip, lr}
344 bl user_enter 344 bl context_tracking_user_enter
345 ldmia sp!, {r0-r3, ip, lr} 345 ldmia sp!, {r0-r3, ip, lr}
346 .else 346 .else
347 bl user_enter 347 bl context_tracking_user_enter
348 .endif 348 .endif
349#endif 349#endif
350 .endm 350 .endm
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index 71e08baee209..c02ba4af599f 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -58,14 +58,14 @@ static const struct kvm_irq_level a15_vtimer_irq = {
58 */ 58 */
59int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 59int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
60{ 60{
61 struct kvm_regs *cpu_reset; 61 struct kvm_regs *reset_regs;
62 const struct kvm_irq_level *cpu_vtimer_irq; 62 const struct kvm_irq_level *cpu_vtimer_irq;
63 63
64 switch (vcpu->arch.target) { 64 switch (vcpu->arch.target) {
65 case KVM_ARM_TARGET_CORTEX_A15: 65 case KVM_ARM_TARGET_CORTEX_A15:
66 if (vcpu->vcpu_id > a15_max_cpu_idx) 66 if (vcpu->vcpu_id > a15_max_cpu_idx)
67 return -EINVAL; 67 return -EINVAL;
68 cpu_reset = &a15_regs_reset; 68 reset_regs = &a15_regs_reset;
69 vcpu->arch.midr = read_cpuid_id(); 69 vcpu->arch.midr = read_cpuid_id();
70 cpu_vtimer_irq = &a15_vtimer_irq; 70 cpu_vtimer_irq = &a15_vtimer_irq;
71 break; 71 break;
@@ -74,7 +74,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
74 } 74 }
75 75
76 /* Reset core registers */ 76 /* Reset core registers */
77 memcpy(&vcpu->arch.regs, cpu_reset, sizeof(vcpu->arch.regs)); 77 memcpy(&vcpu->arch.regs, reset_regs, sizeof(vcpu->arch.regs));
78 78
79 /* Reset CP15 registers */ 79 /* Reset CP15 registers */
80 kvm_reset_coprocs(vcpu); 80 kvm_reset_coprocs(vcpu);
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 180b3024bec3..f607deb40f4d 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -93,7 +93,7 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
93 93
94static struct irqaction at91rm9200_timer_irq = { 94static struct irqaction at91rm9200_timer_irq = {
95 .name = "at91_tick", 95 .name = "at91_tick",
96 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 96 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
97 .handler = at91rm9200_timer_interrupt, 97 .handler = at91rm9200_timer_interrupt,
98 .irq = NR_IRQS_LEGACY + AT91_ID_SYS, 98 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
99}; 99};
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 3a4bc2e1a65e..bb392320a0dd 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -171,7 +171,7 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
171 171
172static struct irqaction at91sam926x_pit_irq = { 172static struct irqaction at91sam926x_pit_irq = {
173 .name = "at91_tick", 173 .name = "at91_tick",
174 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 174 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
175 .handler = at91sam926x_pit_interrupt, 175 .handler = at91sam926x_pit_interrupt,
176 .irq = NR_IRQS_LEGACY + AT91_ID_SYS, 176 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
177}; 177};
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 721a1a34dd1d..c40c1e2ef80f 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -16,11 +16,17 @@
16#include "at91_rstc.h" 16#include "at91_rstc.h"
17 .arm 17 .arm
18 18
19/*
20 * at91_ramc_base is an array void*
21 * init at NULL if only one DDR controler is present in or DT
22 */
19 .globl at91sam9g45_restart 23 .globl at91sam9g45_restart
20 24
21at91sam9g45_restart: 25at91sam9g45_restart:
22 ldr r5, =at91_ramc_base @ preload constants 26 ldr r5, =at91_ramc_base @ preload constants
23 ldr r0, [r5] 27 ldr r0, [r5]
28 ldr r5, [r5, #4] @ ddr1
29 cmp r5, #0
24 ldr r4, =at91_rstc_base 30 ldr r4, =at91_rstc_base
25 ldr r1, [r4] 31 ldr r1, [r4]
26 32
@@ -30,6 +36,8 @@ at91sam9g45_restart:
30 36
31 .balign 32 @ align to cache line 37 .balign 32 @ align to cache line
32 38
39 strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access
40 strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1
33 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access 41 str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
34 str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 42 str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
35 str r4, [r1, #AT91_RSTC_CR] @ reset processor 43 str r4, [r1, #AT91_RSTC_CR] @ reset processor
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 2919eba41ff4..c0e637adf65d 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -57,7 +57,7 @@ static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
57 57
58static struct irqaction at91x40_timer_irq = { 58static struct irqaction at91x40_timer_irq = {
59 .name = "at91_tick", 59 .name = "at91_tick",
60 .flags = IRQF_DISABLED | IRQF_TIMER, 60 .flags = IRQF_TIMER,
61 .handler = at91x40_timer_interrupt 61 .handler = at91x40_timer_interrupt
62}; 62};
63 63
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 92b7f770615a..4078ba93776b 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -176,7 +176,7 @@ static struct at24_platform_data eeprom_info = {
176 .context = (void *)0x7f00, 176 .context = (void *)0x7f00,
177}; 177};
178 178
179static struct snd_platform_data dm365_evm_snd_data = { 179static struct snd_platform_data dm365_evm_snd_data __maybe_unused = {
180 .asp_chan_q = EVENTQ_3, 180 .asp_chan_q = EVENTQ_3,
181}; 181};
182 182
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 52b8571b2e70..ce402cd21fa0 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,8 +15,6 @@
15 15
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17 17
18#include <linux/platform_device.h>
19
20#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 18#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
21#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 19#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
22#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 20#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
@@ -39,6 +37,8 @@
39#define UART_DM646X_SCR_TX_WATERMARK 0x08 37#define UART_DM646X_SCR_TX_WATERMARK 0x08
40 38
41#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
40#include <linux/platform_device.h>
41
42extern int davinci_serial_init(struct platform_device *); 42extern int davinci_serial_init(struct platform_device *);
43#endif 43#endif
44 44
diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h
index 755fd29fed4a..06a9e2e7d007 100644
--- a/arch/arm/mach-integrator/pci_v3.h
+++ b/arch/arm/mach-integrator/pci_v3.h
@@ -1,2 +1,9 @@
1/* Simple oneliner include to the PCIv3 early init */ 1/* Simple oneliner include to the PCIv3 early init */
2#ifdef CONFIG_PCI
2extern int pci_v3_early_init(void); 3extern int pci_v3_early_init(void);
4#else
5static inline int pci_v3_early_init(void)
6{
7 return 0;
8}
9#endif
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 4c24303ec481..58adf2fd9cfc 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -140,6 +140,7 @@ int __init coherency_init(void)
140 coherency_base = of_iomap(np, 0); 140 coherency_base = of_iomap(np, 0);
141 coherency_cpu_base = of_iomap(np, 1); 141 coherency_cpu_base = of_iomap(np, 1);
142 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); 142 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
143 of_node_put(np);
143 } 144 }
144 145
145 return 0; 146 return 0;
@@ -147,9 +148,14 @@ int __init coherency_init(void)
147 148
148static int __init coherency_late_init(void) 149static int __init coherency_late_init(void)
149{ 150{
150 if (of_find_matching_node(NULL, of_coherency_table)) 151 struct device_node *np;
152
153 np = of_find_matching_node(NULL, of_coherency_table);
154 if (np) {
151 bus_register_notifier(&platform_bus_type, 155 bus_register_notifier(&platform_bus_type,
152 &mvebu_hwcc_platform_nb); 156 &mvebu_hwcc_platform_nb);
157 of_node_put(np);
158 }
153 return 0; 159 return 0;
154} 160}
155 161
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 3cc4bef6401c..27fc4f049474 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -67,6 +67,7 @@ int __init armada_370_xp_pmsu_init(void)
67 pr_info("Initializing Power Management Service Unit\n"); 67 pr_info("Initializing Power Management Service Unit\n");
68 pmsu_mp_base = of_iomap(np, 0); 68 pmsu_mp_base = of_iomap(np, 0);
69 pmsu_reset_base = of_iomap(np, 1); 69 pmsu_reset_base = of_iomap(np, 1);
70 of_node_put(np);
70 } 71 }
71 72
72 return 0; 73 return 0;
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index f875124ff4f9..5175083cdb34 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -98,6 +98,7 @@ static int __init mvebu_system_controller_init(void)
98 BUG_ON(!match); 98 BUG_ON(!match);
99 system_controller_base = of_iomap(np, 0); 99 system_controller_base = of_iomap(np, 0);
100 mvebu_sc = (struct mvebu_system_controller *)match->data; 100 mvebu_sc = (struct mvebu_system_controller *)match->data;
101 of_node_put(np);
101 } 102 }
102 103
103 return 0; 104 return 0;
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 25b1feed480d..c78e893eba7d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -52,7 +52,7 @@ static bool omap2xxx_clk_apll_locked(struct clk_hw *hw)
52 52
53 apll_mask = EN_APLL_LOCKED << clk->enable_bit; 53 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
54 54
55 r = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); 55 r = omap2xxx_cm_get_pll_status();
56 56
57 return ((r & apll_mask) == apll_mask) ? true : false; 57 return ((r & apll_mask) == apll_mask) ? true : false;
58} 58}
@@ -126,7 +126,7 @@ u32 omap2xxx_get_apll_clkin(void)
126{ 126{
127 u32 aplls, srate = 0; 127 u32 aplls, srate = 0;
128 128
129 aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); 129 aplls = omap2xxx_cm_get_pll_config();
130 aplls &= OMAP24XX_APLLS_CLKIN_MASK; 130 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
131 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; 131 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
132 132
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index d8620105c42a..3ff32543493c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void)
60 60
61 core_clk = omap2_get_dpll_rate(dpll_core_ck); 61 core_clk = omap2_get_dpll_rate(dpll_core_ck);
62 62
63 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 63 v = omap2xxx_cm_get_core_clk_src();
64 v &= OMAP24XX_CORE_CLK_SRC_MASK;
65 64
66 if (v == CORE_CLK_SRC_32K) 65 if (v == CORE_CLK_SRC_32K)
67 core_clk = 32768; 66 core_clk = 32768;
@@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
79{ 78{
80 u32 high, low, core_clk_src; 79 u32 high, low, core_clk_src;
81 80
82 core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 81 core_clk_src = omap2xxx_cm_get_core_clk_src();
83 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
84 82
85 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ 83 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
86 high = curr_prcm_set->dpll_speed * 2; 84 high = curr_prcm_set->dpll_speed * 2;
@@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
120 const struct dpll_data *dd; 118 const struct dpll_data *dd;
121 119
122 cur_rate = omap2xxx_clk_get_core_rate(); 120 cur_rate = omap2xxx_clk_get_core_rate();
123 mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 121 mult = omap2xxx_cm_get_core_clk_src();
124 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
125 122
126 if ((rate == (cur_rate / 2)) && (mult == 2)) { 123 if ((rate == (cur_rate / 2)) && (mult == 2)) {
127 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); 124 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
145 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 142 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
146 dd->div1_mask); 143 dd->div1_mask);
147 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 144 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
148 tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 145 tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
149 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; 146 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
150 if (rate > low) { 147 if (rate > low) {
151 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; 148 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index ae2b35e76dc8..b935ed2922d8 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -98,7 +98,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
98int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, 98int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
99 unsigned long parent_rate) 99 unsigned long parent_rate)
100{ 100{
101 u32 cur_rate, done_rate, bypass = 0, tmp; 101 u32 cur_rate, done_rate, bypass = 0;
102 const struct prcm_config *prcm; 102 const struct prcm_config *prcm;
103 unsigned long found_speed = 0; 103 unsigned long found_speed = 0;
104 unsigned long flags; 104 unsigned long flags;
@@ -141,23 +141,11 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
141 else 141 else
142 done_rate = CORE_CLK_SRC_DPLL; 142 done_rate = CORE_CLK_SRC_DPLL;
143 143
144 /* MPU divider */ 144 omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu,
145 omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); 145 prcm->cm_clksel_dsp,
146 146 prcm->cm_clksel_gfx,
147 /* dsp + iva1 div(2420), iva2.1(2430) */ 147 prcm->cm_clksel1_core,
148 omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, 148 prcm->cm_clksel_mdm);
149 OMAP24XX_DSP_MOD, CM_CLKSEL);
150
151 omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
152
153 /* Major subsystem dividers */
154 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
155 omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
156 CM_CLKSEL1);
157
158 if (cpu_is_omap2430())
159 omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
160 OMAP2430_MDM_MOD, CM_CLKSEL);
161 149
162 /* x2 to enter omap2xxx_sdrc_init_params() */ 150 /* x2 to enter omap2xxx_sdrc_init_params() */
163 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 151 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0c38ca96c840..c7c5d31e9082 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -543,6 +543,44 @@ int omap2_clk_disable_autoidle_all(void)
543} 543}
544 544
545/** 545/**
546 * omap2_clk_deny_idle - disable autoidle on an OMAP clock
547 * @clk: struct clk * to disable autoidle for
548 *
549 * Disable autoidle on an OMAP clock.
550 */
551int omap2_clk_deny_idle(struct clk *clk)
552{
553 struct clk_hw_omap *c;
554
555 if (__clk_get_flags(clk) & CLK_IS_BASIC)
556 return -EINVAL;
557
558 c = to_clk_hw_omap(__clk_get_hw(clk));
559 if (c->ops && c->ops->deny_idle)
560 c->ops->deny_idle(c);
561 return 0;
562}
563
564/**
565 * omap2_clk_allow_idle - enable autoidle on an OMAP clock
566 * @clk: struct clk * to enable autoidle for
567 *
568 * Enable autoidle on an OMAP clock.
569 */
570int omap2_clk_allow_idle(struct clk *clk)
571{
572 struct clk_hw_omap *c;
573
574 if (__clk_get_flags(clk) & CLK_IS_BASIC)
575 return -EINVAL;
576
577 c = to_clk_hw_omap(__clk_get_hw(clk));
578 if (c->ops && c->ops->allow_idle)
579 c->ops->allow_idle(c);
580 return 0;
581}
582
583/**
546 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 584 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
547 * @clk_names: ptr to an array of strings of clock names to enable 585 * @clk_names: ptr to an array of strings of clock names to enable
548 * @num_clocks: number of clock names in @clk_names 586 * @num_clocks: number of clock names in @clk_names
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 7aa32cd292f9..82916cc82c92 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -411,6 +411,8 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
411void omap2_init_clk_hw_omap_clocks(struct clk *clk); 411void omap2_init_clk_hw_omap_clocks(struct clk *clk);
412int omap2_clk_enable_autoidle_all(void); 412int omap2_clk_enable_autoidle_all(void);
413int omap2_clk_disable_autoidle_all(void); 413int omap2_clk_disable_autoidle_all(void);
414int omap2_clk_allow_idle(struct clk *clk);
415int omap2_clk_deny_idle(struct clk *clk);
414void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 416void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
415int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 417int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
416void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 418void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 6774a53a3874..ce25abbcffae 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -327,6 +327,73 @@ struct clkdm_ops omap2_clkdm_operations = {
327 .clkdm_clk_disable = omap2xxx_clkdm_clk_disable, 327 .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
328}; 328};
329 329
330int omap2xxx_cm_fclks_active(void)
331{
332 u32 f1, f2;
333
334 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
335 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
336
337 return (f1 | f2) ? 1 : 0;
338}
339
340int omap2xxx_cm_mpu_retention_allowed(void)
341{
342 u32 l;
343
344 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
345 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
346 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
347 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
348 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
349 return 0;
350 /* Check for UART3. */
351 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
352 if (l & OMAP24XX_EN_UART3_MASK)
353 return 0;
354
355 return 1;
356}
357
358u32 omap2xxx_cm_get_core_clk_src(void)
359{
360 u32 v;
361
362 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
363 v &= OMAP24XX_CORE_CLK_SRC_MASK;
364
365 return v;
366}
367
368u32 omap2xxx_cm_get_core_pll_config(void)
369{
370 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
371}
372
373u32 omap2xxx_cm_get_pll_config(void)
374{
375 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
376}
377
378u32 omap2xxx_cm_get_pll_status(void)
379{
380 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
381}
382
383void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
384{
385 u32 tmp;
386
387 omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
388 omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
389 omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
390 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
391 OMAP24XX_CLKSEL_DSS2_MASK;
392 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
393 if (cpu_is_omap2430())
394 omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
395}
396
330/* 397/*
331 * 398 *
332 */ 399 */
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 4cbb39b051d2..891d81c3c8f4 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -62,6 +62,14 @@ extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
62 u8 idlest_shift); 62 u8 idlest_shift);
63extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, 63extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
64 s16 *prcm_inst, u8 *idlest_reg_id); 64 s16 *prcm_inst, u8 *idlest_reg_id);
65extern int omap2xxx_cm_fclks_active(void);
66extern int omap2xxx_cm_mpu_retention_allowed(void);
67extern u32 omap2xxx_cm_get_core_clk_src(void);
68extern u32 omap2xxx_cm_get_core_pll_config(void);
69extern u32 omap2xxx_cm_get_pll_config(void);
70extern u32 omap2xxx_cm_get_pll_status(void);
71extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
72 u32 mdm);
65 73
66extern int __init omap2xxx_cm_init(void); 74extern int __init omap2xxx_cm_init(void);
67 75
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index 9061c307d915..f6f028867bfe 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -636,6 +636,28 @@ void omap3_cm_restore_context(void)
636 OMAP3_CM_CLKOUT_CTRL_OFFSET); 636 OMAP3_CM_CLKOUT_CTRL_OFFSET);
637} 637}
638 638
639void omap3_cm_save_scratchpad_contents(u32 *ptr)
640{
641 *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
642 *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
643 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
644
645 /*
646 * As per erratum i671, ROM code does not respect the PER DPLL
647 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
648 * Then, in anycase, clear these bits to avoid extra latencies.
649 */
650 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
651 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
652 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
653 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
654 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
655 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
656 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
657 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
658 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
659}
660
639/* 661/*
640 * 662 *
641 */ 663 */
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index e8e146f4a43f..8224c91b4d7a 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -83,6 +83,7 @@ extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
83 83
84extern void omap3_cm_save_context(void); 84extern void omap3_cm_save_context(void);
85extern void omap3_cm_restore_context(void); 85extern void omap3_cm_restore_context(void);
86extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
86 87
87extern int __init omap3xxx_cm_init(void); 88extern int __init omap3xxx_cm_init(void);
88 89
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 31e0dfe4a4ea..44bb4d544dcf 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -46,17 +46,7 @@ struct omap3_scratchpad {
46struct omap3_scratchpad_prcm_block { 46struct omap3_scratchpad_prcm_block {
47 u32 prm_clksrc_ctrl; 47 u32 prm_clksrc_ctrl;
48 u32 prm_clksel; 48 u32 prm_clksel;
49 u32 cm_clksel_core; 49 u32 cm_contents[11];
50 u32 cm_clksel_wkup;
51 u32 cm_clken_pll;
52 u32 cm_autoidle_pll;
53 u32 cm_clksel1_pll;
54 u32 cm_clksel2_pll;
55 u32 cm_clksel3_pll;
56 u32 cm_clken_pll_mpu;
57 u32 cm_autoidle_pll_mpu;
58 u32 cm_clksel1_pll_mpu;
59 u32 cm_clksel2_pll_mpu;
60 u32 prcm_block_size; 50 u32 prcm_block_size;
61}; 51};
62 52
@@ -347,34 +337,9 @@ void omap3_save_scratchpad_contents(void)
347 prcm_block_contents.prm_clksel = 337 prcm_block_contents.prm_clksel =
348 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, 338 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
349 OMAP3_PRM_CLKSEL_OFFSET); 339 OMAP3_PRM_CLKSEL_OFFSET);
350 prcm_block_contents.cm_clksel_core = 340
351 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 341 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
352 prcm_block_contents.cm_clksel_wkup = 342
353 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
354 prcm_block_contents.cm_clken_pll =
355 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
356 /*
357 * As per erratum i671, ROM code does not respect the PER DPLL
358 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
359 * Then, in anycase, clear these bits to avoid extra latencies.
360 */
361 prcm_block_contents.cm_autoidle_pll =
362 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
363 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
364 prcm_block_contents.cm_clksel1_pll =
365 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
366 prcm_block_contents.cm_clksel2_pll =
367 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
368 prcm_block_contents.cm_clksel3_pll =
369 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
370 prcm_block_contents.cm_clken_pll_mpu =
371 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
372 prcm_block_contents.cm_autoidle_pll_mpu =
373 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
374 prcm_block_contents.cm_clksel1_pll_mpu =
375 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
376 prcm_block_contents.cm_clksel2_pll_mpu =
377 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
378 prcm_block_contents.prcm_block_size = 0x0; 343 prcm_block_contents.prcm_block_size = 0x0;
379 344
380 /* Populate the SDRC block contents */ 345 /* Populate the SDRC block contents */
@@ -604,4 +569,15 @@ int omap3_ctrl_save_padconf(void)
604 return 0; 569 return 0;
605} 570}
606 571
572/**
573 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
574 *
575 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
576 * force disable IVA2 so that it does not prevent any low-power states.
577 */
578void omap3_ctrl_set_iva_bootmode_idle(void)
579{
580 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
581 OMAP343X_CONTROL_IVA2_BOOTMOD);
582}
607#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 583#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index f7d7c2ef1b40..da054801b114 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -427,6 +427,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
427extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); 427extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
428extern void omap3630_ctrl_disable_rta(void); 428extern void omap3630_ctrl_disable_rta(void);
429extern int omap3_ctrl_save_padconf(void); 429extern int omap3_ctrl_save_padconf(void);
430extern void omap3_ctrl_set_iva_bootmode_idle(void);
430extern void omap2_set_globals_control(void __iomem *ctrl, 431extern void omap2_set_globals_control(void __iomem *ctrl,
431 void __iomem *ctrl_pad); 432 void __iomem *ctrl_pad);
432#else 433#else
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 5d8768075dd9..b4ac3af1160c 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,6 +25,7 @@
25 25
26#include "soc.h" 26#include "soc.h"
27#include "omap_device.h" 27#include "omap_device.h"
28#include "clock.h"
28 29
29/* 30/*
30 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. 31 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
@@ -33,22 +34,18 @@
33#include "cm3xxx.h" 34#include "cm3xxx.h"
34#include "cm-regbits-34xx.h" 35#include "cm-regbits-34xx.h"
35 36
37static struct clk *mcbsp_iclks[5];
38
36static int omap3_enable_st_clock(unsigned int id, bool enable) 39static int omap3_enable_st_clock(unsigned int id, bool enable)
37{ 40{
38 unsigned int w;
39
40 /* 41 /*
41 * Sidetone uses McBSP ICLK - which must not idle when sidetones 42 * Sidetone uses McBSP ICLK - which must not idle when sidetones
42 * are enabled or sidetones start sounding ugly. 43 * are enabled or sidetones start sounding ugly.
43 */ 44 */
44 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
45 if (enable) 45 if (enable)
46 w &= ~(1 << (id - 2)); 46 return omap2_clk_deny_idle(mcbsp_iclks[id]);
47 else 47 else
48 w |= 1 << (id - 2); 48 return omap2_clk_allow_idle(mcbsp_iclks[id]);
49 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
50
51 return 0;
52} 49}
53 50
54static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused) 51static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
@@ -58,6 +55,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
58 struct omap_hwmod *oh_device[2]; 55 struct omap_hwmod *oh_device[2];
59 struct omap_mcbsp_platform_data *pdata = NULL; 56 struct omap_mcbsp_platform_data *pdata = NULL;
60 struct platform_device *pdev; 57 struct platform_device *pdev;
58 char clk_name[11];
61 59
62 sscanf(oh->name, "mcbsp%d", &id); 60 sscanf(oh->name, "mcbsp%d", &id);
63 61
@@ -99,6 +97,8 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
99 oh_device[1] = omap_hwmod_lookup(( 97 oh_device[1] = omap_hwmod_lookup((
100 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); 98 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
101 pdata->enable_st_clock = omap3_enable_st_clock; 99 pdata->enable_st_clock = omap3_enable_st_clock;
100 sprintf(clk_name, "mcbsp%d_ick", id);
101 mcbsp_iclks[id] = clk_get(NULL, clk_name);
102 count++; 102 count++;
103 } 103 }
104 pdev = omap_device_build_ss(name, id, oh_device, count, pdata, 104 pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index ce956b0a7ba4..8c0759496c8d 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -62,16 +62,6 @@ static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
62 62
63static struct clk *osc_ck, *emul_ck; 63static struct clk *osc_ck, *emul_ck;
64 64
65static int omap2_fclks_active(void)
66{
67 u32 f1, f2;
68
69 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
70 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
71
72 return (f1 | f2) ? 1 : 0;
73}
74
75static int omap2_enter_full_retention(void) 65static int omap2_enter_full_retention(void)
76{ 66{
77 u32 l; 67 u32 l;
@@ -142,17 +132,7 @@ static int sti_console_enabled;
142 132
143static int omap2_allow_mpu_retention(void) 133static int omap2_allow_mpu_retention(void)
144{ 134{
145 u32 l; 135 if (!omap2xxx_cm_mpu_retention_allowed())
146
147 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
148 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
149 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
150 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
151 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
152 return 0;
153 /* Check for UART3. */
154 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
155 if (l & OMAP24XX_EN_UART3_MASK)
156 return 0; 136 return 0;
157 if (sti_console_enabled) 137 if (sti_console_enabled)
158 return 0; 138 return 0;
@@ -188,7 +168,7 @@ static void omap2_enter_mpu_retention(void)
188 168
189static int omap2_can_sleep(void) 169static int omap2_can_sleep(void)
190{ 170{
191 if (omap2_fclks_active()) 171 if (omap2xxx_cm_fclks_active())
192 return 0; 172 return 0;
193 if (__clk_is_enabled(osc_ck)) 173 if (__clk_is_enabled(osc_ck))
194 return 0; 174 return 0;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5a2d8034c8de..93b80e5da8d4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -430,8 +430,7 @@ static void __init omap3_iva_idle(void)
430 OMAP3430_IVA2_MOD, CM_FCLKEN); 430 OMAP3430_IVA2_MOD, CM_FCLKEN);
431 431
432 /* Set IVA2 boot mode to 'idle' */ 432 /* Set IVA2 boot mode to 'idle' */
433 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 433 omap3_ctrl_set_iva_bootmode_idle();
434 OMAP343X_CONTROL_IVA2_BOOTMOD);
435 434
436 /* Un-reset IVA2 */ 435 /* Un-reset IVA2 */
437 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 436 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 7aeb5d60e484..e6eb48192912 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -131,6 +131,16 @@ static void tc2_pm_down(u64 residency)
131 } else 131 } else
132 BUG(); 132 BUG();
133 133
134 /*
135 * If the CPU is committed to power down, make sure
136 * the power controller will be in charge of waking it
137 * up upon IRQ, ie IRQ lines are cut from GIC CPU IF
138 * to the CPU by disabling the GIC CPU IF to prevent wfi
139 * from completing execution behind power controller back
140 */
141 if (!skip_wfi)
142 gic_cpu_if_down();
143
134 if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { 144 if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
135 arch_spin_unlock(&tc2_pm_lock); 145 arch_spin_unlock(&tc2_pm_lock);
136 146
@@ -231,7 +241,6 @@ static void tc2_pm_suspend(u64 residency)
231 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 241 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
232 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 242 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
233 ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point)); 243 ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
234 gic_cpu_if_down();
235 tc2_pm_down(residency); 244 tc2_pm_down(residency);
236} 245}
237 246
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 06:27:20 -0400