diff options
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_dpllcore.c')
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index d8620105c42a..3ff32543493c 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c | |||
@@ -60,8 +60,7 @@ unsigned long omap2xxx_clk_get_core_rate(void) | |||
60 | 60 | ||
61 | core_clk = omap2_get_dpll_rate(dpll_core_ck); | 61 | core_clk = omap2_get_dpll_rate(dpll_core_ck); |
62 | 62 | ||
63 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 63 | v = omap2xxx_cm_get_core_clk_src(); |
64 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
65 | 64 | ||
66 | if (v == CORE_CLK_SRC_32K) | 65 | if (v == CORE_CLK_SRC_32K) |
67 | core_clk = 32768; | 66 | core_clk = 32768; |
@@ -79,8 +78,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) | |||
79 | { | 78 | { |
80 | u32 high, low, core_clk_src; | 79 | u32 high, low, core_clk_src; |
81 | 80 | ||
82 | core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 81 | core_clk_src = omap2xxx_cm_get_core_clk_src(); |
83 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
84 | 82 | ||
85 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | 83 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ |
86 | high = curr_prcm_set->dpll_speed * 2; | 84 | high = curr_prcm_set->dpll_speed * 2; |
@@ -120,8 +118,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, | |||
120 | const struct dpll_data *dd; | 118 | const struct dpll_data *dd; |
121 | 119 | ||
122 | cur_rate = omap2xxx_clk_get_core_rate(); | 120 | cur_rate = omap2xxx_clk_get_core_rate(); |
123 | mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 121 | mult = omap2xxx_cm_get_core_clk_src(); |
124 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
125 | 122 | ||
126 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | 123 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
127 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | 124 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
@@ -145,7 +142,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, | |||
145 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | 142 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
146 | dd->div1_mask); | 143 | dd->div1_mask); |
147 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | 144 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
148 | tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 145 | tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config(); |
149 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | 146 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
150 | if (rate > low) { | 147 | if (rate > low) { |
151 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | 148 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |