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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 17:33:21 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 17:33:21 -0400
commit0bf6a210a43f7118d858806200127e421649fc4e (patch)
tree9a17d88ebd1b9bc693fba7f39c12123dec96e930 /arch/arm
parentee1a8d402e7e204d57fb108aa40003b6d1633036 (diff)
parent5c913a9a9772f4b434aaea7328836419287b5d1c (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann: "These changes are all driver specific and cross over between arm-soc contents and some other subsystem, in these cases cpufreq, crypto, dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have these changes merged through arm-soc. As we proceed to untangle the dependencies between platform code and driver code, the amount of changes in this category is fortunately shrinking, for 3.11 we have 16 branches here and 101 non-merge changesets, the majority of which are for the stedma40 dma engine driver used in the ux500 platform. Cleaning up that code touches multiple subsystems, but gets rid of the dependency in the end. The mailbox code moved out from mach-omap2 to drivers/mailbox is an intermediate step and is still omap specific at the moment. Patches exist to generalize the subsystem and add other drivers with the same API, but those did not make it for 3.11." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) crypto: ux500: use dmaengine_submit API crypto: ux500: use dmaengine_prep_slave_sg API crypto: ux500: use dmaengine_device_control API crypto: ux500/crypt: add missing __iomem qualifiers crypto: ux500/hash: add missing static qualifiers crypto: ux500/hash: use readl on iomem addresses dmaengine: ste_dma40: Declare memcpy config as static ARM: ux500: Remove mop500_snowball_ethernet_clock_enable() ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO ARM: ux500: Provide a AB8500 GPIO Device Tree node gpio: rcar: fix gpio_rcar_of_table gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections gpio-rcar: Reference core gpio documentation in the DT bindings clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 ARM: dts: Update Samsung I2S documentation ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: add Exynos audio subsystem clock controller node clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: use #include for all device trees for Samsung pinctrl: s3c24xx: use correct header for chained_irq functions ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig47
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412-smdk4412.dts2
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts2
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts2
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi20
-rw-r--r--arch/arm/boot/dts/exynos5440-sd5v1.dts2
-rw-r--r--arch/arm/boot/dts/exynos5440-ssdk5440.dts2
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts1
-rw-r--r--arch/arm/boot/dts/s3c2416-smdk2416.dts2
-rw-r--r--arch/arm/boot/dts/s3c2416.dtsi4
-rw-r--r--arch/arm/boot/dts/s3c24xx.dtsi2
-rw-r--r--arch/arm/boot/dts/snowball.dts13
-rw-r--r--arch/arm/configs/omap1_defconfig3
-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/mailbox.c199
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/board-flash.c3
-rw-r--r--arch/arm/mach-omap2/devices.c13
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c44
-rw-r--r--arch/arm/mach-omap2/gpmc.c82
-rw-r--r--arch/arm/mach-omap2/mailbox.c430
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c14
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c13
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig66
-rw-r--r--arch/arm/mach-s3c24xx/Makefile6
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-debugfs.c198
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-s3c2410.c160
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-s3c2412.c258
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-s3c2440.c312
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq.c711
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/s3c2412.h (renamed from arch/arm/mach-s3c24xx/s3c2412.h)0
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2412.c2
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c68
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c56
-rw-r--r--arch/arm/mach-ux500/board-mop500.c94
-rw-r--r--arch/arm/mach-ux500/board-mop500.h2
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c66
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c123
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db8500.h193
-rw-r--r--arch/arm/mach-ux500/usb.c47
-rw-r--r--arch/arm/plat-omap/Kconfig16
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/include/plat/mailbox.h105
-rw-r--r--arch/arm/plat-omap/mailbox.c435
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq.h6
61 files changed, 365 insertions, 3529 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a13c2cd7a86..49fdc432512f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2087,53 +2087,6 @@ menu "CPU Power Management"
2087 2087
2088if ARCH_HAS_CPUFREQ 2088if ARCH_HAS_CPUFREQ
2089source "drivers/cpufreq/Kconfig" 2089source "drivers/cpufreq/Kconfig"
2090
2091config CPU_FREQ_S3C
2092 bool
2093 help
2094 Internal configuration node for common cpufreq on Samsung SoC
2095
2096config CPU_FREQ_S3C24XX
2097 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2098 depends on ARCH_S3C24XX && CPU_FREQ
2099 select CPU_FREQ_S3C
2100 help
2101 This enables the CPUfreq driver for the Samsung S3C24XX family
2102 of CPUs.
2103
2104 For details, take a look at <file:Documentation/cpu-freq>.
2105
2106 If in doubt, say N.
2107
2108config CPU_FREQ_S3C24XX_PLL
2109 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2110 depends on CPU_FREQ_S3C24XX
2111 help
2112 Compile in support for changing the PLL frequency from the
2113 S3C24XX series CPUfreq driver. The PLL takes time to settle
2114 after a frequency change, so by default it is not enabled.
2115
2116 This also means that the PLL tables for the selected CPU(s) will
2117 be built which may increase the size of the kernel image.
2118
2119config CPU_FREQ_S3C24XX_DEBUG
2120 bool "Debug CPUfreq Samsung driver core"
2121 depends on CPU_FREQ_S3C24XX
2122 help
2123 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2124
2125config CPU_FREQ_S3C24XX_IODEBUG
2126 bool "Debug CPUfreq Samsung driver IO timing"
2127 depends on CPU_FREQ_S3C24XX
2128 help
2129 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2130
2131config CPU_FREQ_S3C24XX_DEBUGFS
2132 bool "Export debugfs for CPUFreq"
2133 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2134 help
2135 Export status information via debugfs.
2136
2137endif 2090endif
2138 2091
2139source "drivers/cpuidle/Kconfig" 2092source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index a082f0ba1ddb..a1529455f081 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -360,6 +360,11 @@
360 interrupt-controller; 360 interrupt-controller;
361 #interrupt-cells = <2>; 361 #interrupt-cells = <2>;
362 362
363 ab8500_gpio: ab8500-gpio {
364 gpio-controller;
365 #gpio-cells = <2>;
366 };
367
363 ab8500-rtc { 368 ab8500-rtc {
364 compatible = "stericsson,ab8500-rtc"; 369 compatible = "stericsson,ab8500-rtc";
365 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 370 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee2e4f6..3f94fe8e3706 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 */ 20 */
21 21
22/include/ "skeleton.dtsi" 22#include "skeleton.dtsi"
23 23
24/ { 24/ {
25 interrupt-parent = <&gic>; 25 interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 08609b8bdaf1..382d8c7e2906 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
15*/ 15*/
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "exynos4210.dtsi" 18#include "exynos4210.dtsi"
19 19
20/ { 20/ {
21 model = "Insignal Origen evaluation board based on Exynos4210"; 21 model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b72acf5..9c01b718d29d 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
15*/ 15*/
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "exynos4210.dtsi" 18#include "exynos4210.dtsi"
19 19
20/ { 20/ {
21 model = "Samsung smdkv310 evaluation board based on Exynos4210"; 21 model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484c7bb1..94eebffe3044 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4210.dtsi" 16#include "exynos4210.dtsi"
17 17
18/ { 18/ {
19 model = "Samsung Trats based on Exynos4210"; 19 model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb51dcb7..889cdada1ce9 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4210.dtsi" 16#include "exynos4210.dtsi"
17 17
18/ { 18/ {
19 model = "Samsung Universal C210 based on Exynos4210 rev0"; 19 model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index d4f8067e89ba..b7f358a93bcb 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20*/ 20*/
21 21
22/include/ "exynos4.dtsi" 22#include "exynos4.dtsi"
23/include/ "exynos4210-pinctrl.dtsi" 23#include "exynos4210-pinctrl.dtsi"
24 24
25/ { 25/ {
26 compatible = "samsung,exynos4210"; 26 compatible = "samsung,exynos4210";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f49cea6..6f34d7f6ba7e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "exynos4x12.dtsi" 20#include "exynos4x12.dtsi"
21 21
22/ { 22/ {
23 compatible = "samsung,exynos4212"; 23 compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 867d9452619b..46c678ee119c 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
12*/ 12*/
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "exynos4412.dtsi" 15#include "exynos4412.dtsi"
16 16
17/ { 17/ {
18 model = "Hardkernel ODROID-X board based on Exynos4412"; 18 model = "Hardkernel ODROID-X board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index ca73c42f77e1..7993641cb32a 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17 17
18/ { 18/ {
19 model = "Insignal Origen evaluation board based on Exynos4412"; 19 model = "Insignal Origen evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index a8ba195c41ac..ad316a1ee9e0 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15/dts-v1/; 15/dts-v1/;
16/include/ "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17 17
18/ { 18/ {
19 model = "Samsung SMDK evaluation board based on Exynos4412"; 19 model = "Samsung SMDK evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389e0a1b..e743e677a9e2 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "exynos4x12.dtsi" 20#include "exynos4x12.dtsi"
21 21
22/ { 22/ {
23 compatible = "samsung,exynos4412"; 23 compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 35cb2099d55e..01da194ba329 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "exynos4.dtsi" 20#include "exynos4.dtsi"
21/include/ "exynos4x12-pinctrl.dtsi" 21#include "exynos4x12-pinctrl.dtsi"
22 22
23/ { 23/ {
24 aliases { 24 aliases {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index c6db281a3430..abc7272c7afd 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5250.dtsi" 13#include "exynos5250.dtsi"
14 14
15/ { 15/ {
16 model = "Insignal Arndale evaluation board based on EXYNOS5250"; 16 model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1e21200b6d85..35a66dee4011 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5250.dtsi" 13#include "exynos5250.dtsi"
14 14
15/ { 15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; 16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 05244f150dd9..e79331dba12d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
9*/ 9*/
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "exynos5250.dtsi" 12#include "exynos5250.dtsi"
13/include/ "cros5250-common.dtsi" 13#include "cros5250-common.dtsi"
14 14
15/ { 15/ {
16 model = "Google Snow"; 16 model = "Google Snow";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 54a35e64c781..964158c1844f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,8 +17,10 @@
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18*/ 18*/
19 19
20/include/ "skeleton.dtsi" 20#include "skeleton.dtsi"
21/include/ "exynos5250-pinctrl.dtsi" 21#include "exynos5250-pinctrl.dtsi"
22
23#include <dt-bindings/clk/exynos-audss-clk.h>
22 24
23/ { 25/ {
24 compatible = "samsung,exynos5250"; 26 compatible = "samsung,exynos5250";
@@ -72,6 +74,12 @@
72 #clock-cells = <1>; 74 #clock-cells = <1>;
73 }; 75 };
74 76
77 clock_audss: audss-clock-controller@3810000 {
78 compatible = "samsung,exynos5250-audss-clock";
79 reg = <0x03810000 0x0C>;
80 #clock-cells = <1>;
81 };
82
75 gic:interrupt-controller@10481000 { 83 gic:interrupt-controller@10481000 {
76 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 84 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
77 #interrupt-cells = <3>; 85 #interrupt-cells = <3>;
@@ -451,6 +459,10 @@
451 &pdma0 9 459 &pdma0 9
452 &pdma0 8>; 460 &pdma0 8>;
453 dma-names = "tx", "rx", "tx-sec"; 461 dma-names = "tx", "rx", "tx-sec";
462 clocks = <&clock_audss EXYNOS_I2S_BUS>,
463 <&clock_audss EXYNOS_I2S_BUS>,
464 <&clock_audss EXYNOS_SCLK_I2S>;
465 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
454 samsung,supports-6ch; 466 samsung,supports-6ch;
455 samsung,supports-rstclr; 467 samsung,supports-rstclr;
456 samsung,supports-secdai; 468 samsung,supports-secdai;
@@ -465,6 +477,8 @@
465 dmas = <&pdma1 12 477 dmas = <&pdma1 12
466 &pdma1 11>; 478 &pdma1 11>;
467 dma-names = "tx", "rx"; 479 dma-names = "tx", "rx";
480 clocks = <&clock 307>, <&clock 157>;
481 clock-names = "iis", "i2s_opclk0";
468 pinctrl-names = "default"; 482 pinctrl-names = "default";
469 pinctrl-0 = <&i2s1_bus>; 483 pinctrl-0 = <&i2s1_bus>;
470 }; 484 };
@@ -475,6 +489,8 @@
475 dmas = <&pdma0 12 489 dmas = <&pdma0 12
476 &pdma0 11>; 490 &pdma0 11>;
477 dma-names = "tx", "rx"; 491 dma-names = "tx", "rx";
492 clocks = <&clock 308>, <&clock 158>;
493 clock-names = "iis", "i2s_opclk0";
478 pinctrl-names = "default"; 494 pinctrl-names = "default";
479 pinctrl-0 = <&i2s2_bus>; 495 pinctrl-0 = <&i2s2_bus>;
480 }; 496 };
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index f722a0263ac8..5b22508050da 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,7 +10,7 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5440.dtsi" 13#include "exynos5440.dtsi"
14 14
15/ { 15/ {
16 model = "SAMSUNG SD5v1 board based on EXYNOS5440"; 16 model = "SAMSUNG SD5v1 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index ba88cfd2486f..ede772741f81 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,7 +10,7 @@
10*/ 10*/
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "exynos5440.dtsi" 13#include "exynos5440.dtsi"
14 14
15/ { 15/ {
16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; 16 model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index bfcb907b7e33..ff7f5d855845 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,7 +9,7 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12/include/ "skeleton.dtsi" 12#include "skeleton.dtsi"
13 13
14/ { 14/ {
15 compatible = "samsung,exynos5440"; 15 compatible = "samsung,exynos5440";
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index c4a1c0a97728..e2249bcc3e63 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -106,7 +106,6 @@
106 nand-bus-width = <8>; 106 nand-bus-width = <8>;
107 107
108 ti,nand-ecc-opt = "sw"; 108 ti,nand-ecc-opt = "sw";
109 gpmc,device-nand;
110 gpmc,cs-on-ns = <0>; 109 gpmc,cs-on-ns = <0>;
111 gpmc,cs-rd-off-ns = <36>; 110 gpmc,cs-rd-off-ns = <36>;
112 gpmc,cs-wr-off-ns = <36>; 111 gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index ad1dd09c10eb..59594cf15998 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "s3c2416.dtsi" 12#include "s3c2416.dtsi"
13 13
14/ { 14/ {
15 model = "SMDK2416"; 15 model = "SMDK2416";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6809324934a3..e6555bdd81b8 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,8 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11/include/ "s3c24xx.dtsi" 11#include "s3c24xx.dtsi"
12/include/ "s3c2416-pinctrl.dtsi" 12#include "s3c2416-pinctrl.dtsi"
13 13
14/ { 14/ {
15 model = "Samsung S3C2416 SoC"; 15 model = "Samsung S3C2416 SoC";
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
index cab46ff5fb4d..2d1d7dc9418a 100644
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -8,7 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11/include/ "skeleton.dtsi" 11#include "skeleton.dtsi"
12 12
13/ { 13/ {
14 compatible = "samsung,s3c24xx"; 14 compatible = "samsung,s3c24xx";
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index fb9dce529da6..49824be66845 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -22,12 +22,13 @@
22 22
23 en_3v3_reg: en_3v3 { 23 en_3v3_reg: en_3v3 {
24 compatible = "regulator-fixed"; 24 compatible = "regulator-fixed";
25 regulator-name = "en-3v3-fixed-supply"; 25 regulator-name = "en-3v3-fixed-supply";
26 regulator-min-microvolt = <3300000>; 26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>; 27 regulator-max-microvolt = <3300000>;
28 gpios = <&gpio0 26 0x4>; // 26 28 /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */
29 startup-delay-us = <5000>; 29 gpio = <&ab8500_gpio 25 0x4>;
30 enable-active-high; 30 startup-delay-us = <5000>;
31 enable-active-high;
31 }; 32 };
32 33
33 gpio_keys { 34 gpio_keys {
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 9940f7b4e438..d74edbad18fc 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -26,7 +26,8 @@ CONFIG_ARCH_OMAP=y
26CONFIG_ARCH_OMAP1=y 26CONFIG_ARCH_OMAP1=y
27CONFIG_OMAP_RESET_CLOCKS=y 27CONFIG_OMAP_RESET_CLOCKS=y
28# CONFIG_OMAP_MUX is not set 28# CONFIG_OMAP_MUX is not set
29CONFIG_OMAP_MBOX_FWK=y 29CONFIG_MAILBOX=y
30CONFIG_OMAP1_MBOX=y
30CONFIG_OMAP_32K_TIMER=y 31CONFIG_OMAP_32K_TIMER=y
31CONFIG_OMAP_DM_TIMER=y 32CONFIG_OMAP_DM_TIMER=y
32CONFIG_ARCH_OMAP730=y 33CONFIG_ARCH_OMAP730=y
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 222d58c0ae76..3889b6cd211e 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -19,10 +19,6 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
19# Power Management 19# Power Management
20obj-$(CONFIG_PM) += pm.o sleep.o 20obj-$(CONFIG_PM) += pm.o sleep.o
21 21
22# DSP
23obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
24mailbox_mach-objs := mailbox.o
25
26i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o 22i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
27obj-y += $(i2c-omap-m) $(i2c-omap-y) 23obj-y += $(i2c-omap-m) $(i2c-omap-y)
28 24
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
deleted file mode 100644
index efc8f207f6fc..000000000000
--- a/arch/arm/mach-omap1/mailbox.c
+++ /dev/null
@@ -1,199 +0,0 @@
1/*
2 * Mailbox reservation modules for OMAP1
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <plat/mailbox.h>
17
18#define MAILBOX_ARM2DSP1 0x00
19#define MAILBOX_ARM2DSP1b 0x04
20#define MAILBOX_DSP2ARM1 0x08
21#define MAILBOX_DSP2ARM1b 0x0c
22#define MAILBOX_DSP2ARM2 0x10
23#define MAILBOX_DSP2ARM2b 0x14
24#define MAILBOX_ARM2DSP1_Flag 0x18
25#define MAILBOX_DSP2ARM1_Flag 0x1c
26#define MAILBOX_DSP2ARM2_Flag 0x20
27
28static void __iomem *mbox_base;
29
30struct omap_mbox1_fifo {
31 unsigned long cmd;
32 unsigned long data;
33 unsigned long flag;
34};
35
36struct omap_mbox1_priv {
37 struct omap_mbox1_fifo tx_fifo;
38 struct omap_mbox1_fifo rx_fifo;
39};
40
41static inline int mbox_read_reg(size_t ofs)
42{
43 return __raw_readw(mbox_base + ofs);
44}
45
46static inline void mbox_write_reg(u32 val, size_t ofs)
47{
48 __raw_writew(val, mbox_base + ofs);
49}
50
51/* msg */
52static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
53{
54 struct omap_mbox1_fifo *fifo =
55 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
56 mbox_msg_t msg;
57
58 msg = mbox_read_reg(fifo->data);
59 msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
60
61 return msg;
62}
63
64static void
65omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
66{
67 struct omap_mbox1_fifo *fifo =
68 &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo;
69
70 mbox_write_reg(msg & 0xffff, fifo->data);
71 mbox_write_reg(msg >> 16, fifo->cmd);
72}
73
74static int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
75{
76 return 0;
77}
78
79static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
80{
81 struct omap_mbox1_fifo *fifo =
82 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
83
84 return mbox_read_reg(fifo->flag);
85}
86
87/* irq */
88static void
89omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
90{
91 if (irq == IRQ_RX)
92 enable_irq(mbox->irq);
93}
94
95static void
96omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
97{
98 if (irq == IRQ_RX)
99 disable_irq(mbox->irq);
100}
101
102static int
103omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
104{
105 if (irq == IRQ_TX)
106 return 0;
107 return 1;
108}
109
110static struct omap_mbox_ops omap1_mbox_ops = {
111 .type = OMAP_MBOX_TYPE1,
112 .fifo_read = omap1_mbox_fifo_read,
113 .fifo_write = omap1_mbox_fifo_write,
114 .fifo_empty = omap1_mbox_fifo_empty,
115 .fifo_full = omap1_mbox_fifo_full,
116 .enable_irq = omap1_mbox_enable_irq,
117 .disable_irq = omap1_mbox_disable_irq,
118 .is_irq = omap1_mbox_is_irq,
119};
120
121/* FIXME: the following struct should be created automatically by the user id */
122
123/* DSP */
124static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
125 .tx_fifo = {
126 .cmd = MAILBOX_ARM2DSP1b,
127 .data = MAILBOX_ARM2DSP1,
128 .flag = MAILBOX_ARM2DSP1_Flag,
129 },
130 .rx_fifo = {
131 .cmd = MAILBOX_DSP2ARM1b,
132 .data = MAILBOX_DSP2ARM1,
133 .flag = MAILBOX_DSP2ARM1_Flag,
134 },
135};
136
137static struct omap_mbox mbox_dsp_info = {
138 .name = "dsp",
139 .ops = &omap1_mbox_ops,
140 .priv = &omap1_mbox_dsp_priv,
141};
142
143static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
144
145static int omap1_mbox_probe(struct platform_device *pdev)
146{
147 struct resource *mem;
148 int ret;
149 struct omap_mbox **list;
150
151 list = omap1_mboxes;
152 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
153
154 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
155 mbox_base = ioremap(mem->start, resource_size(mem));
156 if (!mbox_base)
157 return -ENOMEM;
158
159 ret = omap_mbox_register(&pdev->dev, list);
160 if (ret) {
161 iounmap(mbox_base);
162 return ret;
163 }
164
165 return 0;
166}
167
168static int omap1_mbox_remove(struct platform_device *pdev)
169{
170 omap_mbox_unregister();
171 iounmap(mbox_base);
172 return 0;
173}
174
175static struct platform_driver omap1_mbox_driver = {
176 .probe = omap1_mbox_probe,
177 .remove = omap1_mbox_remove,
178 .driver = {
179 .name = "omap-mailbox",
180 },
181};
182
183static int __init omap1_mbox_init(void)
184{
185 return platform_driver_register(&omap1_mbox_driver);
186}
187
188static void __exit omap1_mbox_exit(void)
189{
190 platform_driver_unregister(&omap1_mbox_driver);
191}
192
193module_init(omap1_mbox_init);
194module_exit(omap1_mbox_exit);
195
196MODULE_LICENSE("GPL v2");
197MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
198MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
199MODULE_ALIAS("platform:omap1-mailbox");
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8e8c605ebefe..ea5a27ff9941 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -212,9 +212,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
212obj-$(CONFIG_OMAP3_EMU) += emu.o 212obj-$(CONFIG_OMAP3_EMU) += emu.o
213obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o 213obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
214 214
215obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
216mailbox_mach-objs := mailbox.o
217
218iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 215iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
219obj-y += $(iommu-m) $(iommu-y) 216obj-y += $(iommu-m) $(iommu-y)
220 217
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index c33adea0247c..fc20a61f6b2a 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = {
112 .cs_rd_off = 36, 112 .cs_rd_off = 36,
113 .cs_wr_off = 36, 113 .cs_wr_off = 36,
114 114
115 .we_on = 6,
116 .oe_on = 6,
117
115 .adv_on = 6, 118 .adv_on = 6,
116 .adv_rd_off = 24, 119 .adv_rd_off = 24,
117 .adv_wr_off = 36, 120 .adv_wr_off = 36,
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 403c211e35d0..aef96e45cb20 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -21,6 +21,7 @@
21#include <linux/pinctrl/machine.h> 21#include <linux/pinctrl/machine.h>
22#include <linux/platform_data/omap4-keypad.h> 22#include <linux/platform_data/omap4-keypad.h>
23#include <linux/wl12xx.h> 23#include <linux/wl12xx.h>
24#include <linux/platform_data/mailbox-omap.h>
24 25
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
@@ -283,25 +284,31 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
283 return 0; 284 return 0;
284} 285}
285 286
286#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 287#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
287static inline void __init omap_init_mbox(void) 288static inline void __init omap_init_mbox(void)
288{ 289{
289 struct omap_hwmod *oh; 290 struct omap_hwmod *oh;
290 struct platform_device *pdev; 291 struct platform_device *pdev;
292 struct omap_mbox_pdata *pdata;
291 293
292 oh = omap_hwmod_lookup("mailbox"); 294 oh = omap_hwmod_lookup("mailbox");
293 if (!oh) { 295 if (!oh) {
294 pr_err("%s: unable to find hwmod\n", __func__); 296 pr_err("%s: unable to find hwmod\n", __func__);
295 return; 297 return;
296 } 298 }
299 if (!oh->dev_attr) {
300 pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
301 return;
302 }
297 303
298 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0); 304 pdata = (struct omap_mbox_pdata *)oh->dev_attr;
305 pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
299 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 306 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
300 __func__, PTR_ERR(pdev)); 307 __func__, PTR_ERR(pdev));
301} 308}
302#else 309#else
303static inline void omap_init_mbox(void) { } 310static inline void omap_init_mbox(void) { }
304#endif /* CONFIG_OMAP_MBOX_FWK */ 311#endif /* CONFIG_OMAP2PLUS_MBOX */
305 312
306static inline void omap_init_sti(void) {} 313static inline void omap_init_sti(void) {}
307 314
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c27195caf0..662c7fd633cc 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
43 .resource = gpmc_nand_resource, 43 .resource = gpmc_nand_resource,
44}; 44};
45 45
46static int omap2_nand_gpmc_retime(
47 struct omap_nand_platform_data *gpmc_nand_data,
48 struct gpmc_timings *gpmc_t)
49{
50 struct gpmc_timings t;
51 int err;
52
53 memset(&t, 0, sizeof(t));
54 t.sync_clk = gpmc_t->sync_clk;
55 t.cs_on = gpmc_t->cs_on;
56 t.adv_on = gpmc_t->adv_on;
57
58 /* Read */
59 t.adv_rd_off = gpmc_t->adv_rd_off;
60 t.oe_on = t.adv_on;
61 t.access = gpmc_t->access;
62 t.oe_off = gpmc_t->oe_off;
63 t.cs_rd_off = gpmc_t->cs_rd_off;
64 t.rd_cycle = gpmc_t->rd_cycle;
65
66 /* Write */
67 t.adv_wr_off = gpmc_t->adv_wr_off;
68 t.we_on = t.oe_on;
69 if (cpu_is_omap34xx()) {
70 t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
71 t.wr_access = gpmc_t->wr_access;
72 }
73 t.we_off = gpmc_t->we_off;
74 t.cs_wr_off = gpmc_t->cs_wr_off;
75 t.wr_cycle = gpmc_t->wr_cycle;
76
77 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
78 if (err)
79 return err;
80
81 return 0;
82}
83
84static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 46static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
85{ 47{
86 /* support only OMAP3 class */ 48 /* support only OMAP3 class */
@@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
131 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); 93 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
132 94
133 if (gpmc_t) { 95 if (gpmc_t) {
134 err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); 96 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
135 if (err < 0) { 97 if (err < 0) {
136 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 98 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
137 return err; 99 return err;
@@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
140 if (gpmc_nand_data->of_node) { 102 if (gpmc_nand_data->of_node) {
141 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); 103 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
142 } else { 104 } else {
143 s.device_nand = true;
144
145 /* Enable RD PIN Monitoring Reg */ 105 /* Enable RD PIN Monitoring Reg */
146 if (gpmc_nand_data->dev_ready) { 106 if (gpmc_nand_data->dev_ready) {
147 s.wait_on_read = true; 107 s.wait_on_read = true;
@@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
149 } 109 }
150 } 110 }
151 111
112 s.device_nand = true;
113
152 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 114 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
153 s.device_width = GPMC_DEVWIDTH_16BIT; 115 s.device_width = GPMC_DEVWIDTH_16BIT;
154 else 116 else
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6c4da1254f53..1c7969e965d7 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -30,6 +30,7 @@
30#include <linux/of_mtd.h> 30#include <linux/of_mtd.h>
31#include <linux/of_device.h> 31#include <linux/of_device.h>
32#include <linux/mtd/nand.h> 32#include <linux/mtd/nand.h>
33#include <linux/pm_runtime.h>
33 34
34#include <linux/platform_data/mtd-nand-omap2.h> 35#include <linux/platform_data/mtd-nand-omap2.h>
35 36
@@ -155,6 +156,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
155static DEFINE_SPINLOCK(gpmc_mem_lock); 156static DEFINE_SPINLOCK(gpmc_mem_lock);
156/* Define chip-selects as reserved by default until probe completes */ 157/* Define chip-selects as reserved by default until probe completes */
157static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); 158static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
159static unsigned int gpmc_cs_num = GPMC_CS_NUM;
158static unsigned int gpmc_nr_waitpins; 160static unsigned int gpmc_nr_waitpins;
159static struct device *gpmc_dev; 161static struct device *gpmc_dev;
160static int gpmc_irq; 162static int gpmc_irq;
@@ -521,8 +523,10 @@ static int gpmc_cs_remap(int cs, u32 base)
521 int ret; 523 int ret;
522 u32 old_base, size; 524 u32 old_base, size;
523 525
524 if (cs > GPMC_CS_NUM) 526 if (cs > gpmc_cs_num) {
527 pr_err("%s: requested chip-select is disabled\n", __func__);
525 return -ENODEV; 528 return -ENODEV;
529 }
526 gpmc_cs_get_memconf(cs, &old_base, &size); 530 gpmc_cs_get_memconf(cs, &old_base, &size);
527 if (base == old_base) 531 if (base == old_base)
528 return 0; 532 return 0;
@@ -545,9 +549,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
545 struct resource *res = &gpmc_cs_mem[cs]; 549 struct resource *res = &gpmc_cs_mem[cs];
546 int r = -1; 550 int r = -1;
547 551
548 if (cs > GPMC_CS_NUM) 552 if (cs > gpmc_cs_num) {
553 pr_err("%s: requested chip-select is disabled\n", __func__);
549 return -ENODEV; 554 return -ENODEV;
550 555 }
551 size = gpmc_mem_align(size); 556 size = gpmc_mem_align(size);
552 if (size > (1 << GPMC_SECTION_SHIFT)) 557 if (size > (1 << GPMC_SECTION_SHIFT))
553 return -ENOMEM; 558 return -ENOMEM;
@@ -582,7 +587,7 @@ EXPORT_SYMBOL(gpmc_cs_request);
582void gpmc_cs_free(int cs) 587void gpmc_cs_free(int cs)
583{ 588{
584 spin_lock(&gpmc_mem_lock); 589 spin_lock(&gpmc_mem_lock);
585 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { 590 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
586 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); 591 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
587 BUG(); 592 BUG();
588 spin_unlock(&gpmc_mem_lock); 593 spin_unlock(&gpmc_mem_lock);
@@ -777,7 +782,7 @@ static void gpmc_mem_exit(void)
777{ 782{
778 int cs; 783 int cs;
779 784
780 for (cs = 0; cs < GPMC_CS_NUM; cs++) { 785 for (cs = 0; cs < gpmc_cs_num; cs++) {
781 if (!gpmc_cs_mem_enabled(cs)) 786 if (!gpmc_cs_mem_enabled(cs))
782 continue; 787 continue;
783 gpmc_cs_delete_mem(cs); 788 gpmc_cs_delete_mem(cs);
@@ -798,7 +803,7 @@ static void gpmc_mem_init(void)
798 gpmc_mem_root.end = GPMC_MEM_END; 803 gpmc_mem_root.end = GPMC_MEM_END;
799 804
800 /* Reserve all regions that has been set up by bootloader */ 805 /* Reserve all regions that has been set up by bootloader */
801 for (cs = 0; cs < GPMC_CS_NUM; cs++) { 806 for (cs = 0; cs < gpmc_cs_num; cs++) {
802 u32 base, size; 807 u32 base, size;
803 808
804 if (!gpmc_cs_mem_enabled(cs)) 809 if (!gpmc_cs_mem_enabled(cs))
@@ -1245,7 +1250,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1245 1250
1246 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 1251 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1247 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 1252 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1248 p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
1249 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 1253 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1250 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 1254 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1251 1255
@@ -1345,6 +1349,13 @@ static const char * const nand_ecc_opts[] = {
1345 [OMAP_ECC_BCH8_CODE_HW] = "bch8", 1349 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1346}; 1350};
1347 1351
1352static const char * const nand_xfer_types[] = {
1353 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1354 [NAND_OMAP_POLLED] = "polled",
1355 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1356 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1357};
1358
1348static int gpmc_probe_nand_child(struct platform_device *pdev, 1359static int gpmc_probe_nand_child(struct platform_device *pdev,
1349 struct device_node *child) 1360 struct device_node *child)
1350{ 1361{
@@ -1374,6 +1385,13 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
1374 break; 1385 break;
1375 } 1386 }
1376 1387
1388 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1389 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1390 if (!strcasecmp(s, nand_xfer_types[val])) {
1391 gpmc_nand_data->xfer_type = val;
1392 break;
1393 }
1394
1377 val = of_get_nand_bus_width(child); 1395 val = of_get_nand_bus_width(child);
1378 if (val == 16) 1396 if (val == 16)
1379 gpmc_nand_data->devsize = NAND_BUSWIDTH_16; 1397 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
@@ -1513,6 +1531,20 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1513 if (!of_id) 1531 if (!of_id)
1514 return 0; 1532 return 0;
1515 1533
1534 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1535 &gpmc_cs_num);
1536 if (ret < 0) {
1537 pr_err("%s: number of chip-selects not defined\n", __func__);
1538 return ret;
1539 } else if (gpmc_cs_num < 1) {
1540 pr_err("%s: all chip-selects are disabled\n", __func__);
1541 return -EINVAL;
1542 } else if (gpmc_cs_num > GPMC_CS_NUM) {
1543 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1544 __func__, GPMC_CS_NUM);
1545 return -EINVAL;
1546 }
1547
1516 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 1548 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1517 &gpmc_nr_waitpins); 1549 &gpmc_nr_waitpins);
1518 if (ret < 0) { 1550 if (ret < 0) {
@@ -1577,7 +1609,8 @@ static int gpmc_probe(struct platform_device *pdev)
1577 return PTR_ERR(gpmc_l3_clk); 1609 return PTR_ERR(gpmc_l3_clk);
1578 } 1610 }
1579 1611
1580 clk_prepare_enable(gpmc_l3_clk); 1612 pm_runtime_enable(&pdev->dev);
1613 pm_runtime_get_sync(&pdev->dev);
1581 1614
1582 gpmc_dev = &pdev->dev; 1615 gpmc_dev = &pdev->dev;
1583 1616
@@ -1610,12 +1643,14 @@ static int gpmc_probe(struct platform_device *pdev)
1610 /* Now the GPMC is initialised, unreserve the chip-selects */ 1643 /* Now the GPMC is initialised, unreserve the chip-selects */
1611 gpmc_cs_map = 0; 1644 gpmc_cs_map = 0;
1612 1645
1613 if (!pdev->dev.of_node) 1646 if (!pdev->dev.of_node) {
1647 gpmc_cs_num = GPMC_CS_NUM;
1614 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 1648 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1649 }
1615 1650
1616 rc = gpmc_probe_dt(pdev); 1651 rc = gpmc_probe_dt(pdev);
1617 if (rc < 0) { 1652 if (rc < 0) {
1618 clk_disable_unprepare(gpmc_l3_clk); 1653 pm_runtime_put_sync(&pdev->dev);
1619 clk_put(gpmc_l3_clk); 1654 clk_put(gpmc_l3_clk);
1620 dev_err(gpmc_dev, "failed to probe DT parameters\n"); 1655 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1621 return rc; 1656 return rc;
@@ -1628,10 +1663,30 @@ static int gpmc_remove(struct platform_device *pdev)
1628{ 1663{
1629 gpmc_free_irq(); 1664 gpmc_free_irq();
1630 gpmc_mem_exit(); 1665 gpmc_mem_exit();
1666 pm_runtime_put_sync(&pdev->dev);
1667 pm_runtime_disable(&pdev->dev);
1631 gpmc_dev = NULL; 1668 gpmc_dev = NULL;
1632 return 0; 1669 return 0;
1633} 1670}
1634 1671
1672#ifdef CONFIG_PM_SLEEP
1673static int gpmc_suspend(struct device *dev)
1674{
1675 omap3_gpmc_save_context();
1676 pm_runtime_put_sync(dev);
1677 return 0;
1678}
1679
1680static int gpmc_resume(struct device *dev)
1681{
1682 pm_runtime_get_sync(dev);
1683 omap3_gpmc_restore_context();
1684 return 0;
1685}
1686#endif
1687
1688static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
1689
1635static struct platform_driver gpmc_driver = { 1690static struct platform_driver gpmc_driver = {
1636 .probe = gpmc_probe, 1691 .probe = gpmc_probe,
1637 .remove = gpmc_remove, 1692 .remove = gpmc_remove,
@@ -1639,6 +1694,7 @@ static struct platform_driver gpmc_driver = {
1639 .name = DEVICE_NAME, 1694 .name = DEVICE_NAME,
1640 .owner = THIS_MODULE, 1695 .owner = THIS_MODULE,
1641 .of_match_table = of_match_ptr(gpmc_dt_ids), 1696 .of_match_table = of_match_ptr(gpmc_dt_ids),
1697 .pm = &gpmc_pm_ops,
1642 }, 1698 },
1643}; 1699};
1644 1700
@@ -1701,7 +1757,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1701 return IRQ_HANDLED; 1757 return IRQ_HANDLED;
1702} 1758}
1703 1759
1704#ifdef CONFIG_ARCH_OMAP3
1705static struct omap3_gpmc_regs gpmc_context; 1760static struct omap3_gpmc_regs gpmc_context;
1706 1761
1707void omap3_gpmc_save_context(void) 1762void omap3_gpmc_save_context(void)
@@ -1715,7 +1770,7 @@ void omap3_gpmc_save_context(void)
1715 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 1770 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1716 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 1771 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1717 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 1772 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1718 for (i = 0; i < GPMC_CS_NUM; i++) { 1773 for (i = 0; i < gpmc_cs_num; i++) {
1719 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 1774 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1720 if (gpmc_context.cs_context[i].is_valid) { 1775 if (gpmc_context.cs_context[i].is_valid) {
1721 gpmc_context.cs_context[i].config1 = 1776 gpmc_context.cs_context[i].config1 =
@@ -1747,7 +1802,7 @@ void omap3_gpmc_restore_context(void)
1747 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); 1802 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1748 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); 1803 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1749 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); 1804 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1750 for (i = 0; i < GPMC_CS_NUM; i++) { 1805 for (i = 0; i < gpmc_cs_num; i++) {
1751 if (gpmc_context.cs_context[i].is_valid) { 1806 if (gpmc_context.cs_context[i].is_valid) {
1752 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 1807 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1753 gpmc_context.cs_context[i].config1); 1808 gpmc_context.cs_context[i].config1);
@@ -1766,4 +1821,3 @@ void omap3_gpmc_restore_context(void)
1766 } 1821 }
1767 } 1822 }
1768} 1823}
1769#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
deleted file mode 100644
index 0b080267b7f6..000000000000
--- a/arch/arm/mach-omap2/mailbox.c
+++ /dev/null
@@ -1,430 +0,0 @@
1/*
2 * Mailbox reservation modules for OMAP2/3
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/module.h>
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/pm_runtime.h>
19
20#include <plat/mailbox.h>
21
22#include "soc.h"
23
24#define MAILBOX_REVISION 0x000
25#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
26#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
27#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
28#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
29#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
30
31#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
32#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
33#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
34
35#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
36#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
37
38#define MBOX_REG_SIZE 0x120
39
40#define OMAP4_MBOX_REG_SIZE 0x130
41
42#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
43#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
44
45static void __iomem *mbox_base;
46
47struct omap_mbox2_fifo {
48 unsigned long msg;
49 unsigned long fifo_stat;
50 unsigned long msg_stat;
51};
52
53struct omap_mbox2_priv {
54 struct omap_mbox2_fifo tx_fifo;
55 struct omap_mbox2_fifo rx_fifo;
56 unsigned long irqenable;
57 unsigned long irqstatus;
58 u32 newmsg_bit;
59 u32 notfull_bit;
60 u32 ctx[OMAP4_MBOX_NR_REGS];
61 unsigned long irqdisable;
62};
63
64static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
65 omap_mbox_type_t irq);
66
67static inline unsigned int mbox_read_reg(size_t ofs)
68{
69 return __raw_readl(mbox_base + ofs);
70}
71
72static inline void mbox_write_reg(u32 val, size_t ofs)
73{
74 __raw_writel(val, mbox_base + ofs);
75}
76
77/* Mailbox H/W preparations */
78static int omap2_mbox_startup(struct omap_mbox *mbox)
79{
80 u32 l;
81
82 pm_runtime_enable(mbox->dev->parent);
83 pm_runtime_get_sync(mbox->dev->parent);
84
85 l = mbox_read_reg(MAILBOX_REVISION);
86 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
87
88 return 0;
89}
90
91static void omap2_mbox_shutdown(struct omap_mbox *mbox)
92{
93 pm_runtime_put_sync(mbox->dev->parent);
94 pm_runtime_disable(mbox->dev->parent);
95}
96
97/* Mailbox FIFO handle functions */
98static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
99{
100 struct omap_mbox2_fifo *fifo =
101 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
102 return (mbox_msg_t) mbox_read_reg(fifo->msg);
103}
104
105static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
106{
107 struct omap_mbox2_fifo *fifo =
108 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
109 mbox_write_reg(msg, fifo->msg);
110}
111
112static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
113{
114 struct omap_mbox2_fifo *fifo =
115 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
116 return (mbox_read_reg(fifo->msg_stat) == 0);
117}
118
119static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
120{
121 struct omap_mbox2_fifo *fifo =
122 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
123 return mbox_read_reg(fifo->fifo_stat);
124}
125
126/* Mailbox IRQ handle functions */
127static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
128 omap_mbox_type_t irq)
129{
130 struct omap_mbox2_priv *p = mbox->priv;
131 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
132
133 l = mbox_read_reg(p->irqenable);
134 l |= bit;
135 mbox_write_reg(l, p->irqenable);
136}
137
138static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
139 omap_mbox_type_t irq)
140{
141 struct omap_mbox2_priv *p = mbox->priv;
142 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
143
144 if (!cpu_is_omap44xx())
145 bit = mbox_read_reg(p->irqdisable) & ~bit;
146
147 mbox_write_reg(bit, p->irqdisable);
148}
149
150static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
151 omap_mbox_type_t irq)
152{
153 struct omap_mbox2_priv *p = mbox->priv;
154 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
155
156 mbox_write_reg(bit, p->irqstatus);
157
158 /* Flush posted write for irq status to avoid spurious interrupts */
159 mbox_read_reg(p->irqstatus);
160}
161
162static int omap2_mbox_is_irq(struct omap_mbox *mbox,
163 omap_mbox_type_t irq)
164{
165 struct omap_mbox2_priv *p = mbox->priv;
166 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
167 u32 enable = mbox_read_reg(p->irqenable);
168 u32 status = mbox_read_reg(p->irqstatus);
169
170 return (int)(enable & status & bit);
171}
172
173static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
174{
175 int i;
176 struct omap_mbox2_priv *p = mbox->priv;
177 int nr_regs;
178 if (cpu_is_omap44xx())
179 nr_regs = OMAP4_MBOX_NR_REGS;
180 else
181 nr_regs = MBOX_NR_REGS;
182 for (i = 0; i < nr_regs; i++) {
183 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
184
185 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
186 i, p->ctx[i]);
187 }
188}
189
190static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
191{
192 int i;
193 struct omap_mbox2_priv *p = mbox->priv;
194 int nr_regs;
195 if (cpu_is_omap44xx())
196 nr_regs = OMAP4_MBOX_NR_REGS;
197 else
198 nr_regs = MBOX_NR_REGS;
199 for (i = 0; i < nr_regs; i++) {
200 mbox_write_reg(p->ctx[i], i * sizeof(u32));
201
202 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
203 i, p->ctx[i]);
204 }
205}
206
207static struct omap_mbox_ops omap2_mbox_ops = {
208 .type = OMAP_MBOX_TYPE2,
209 .startup = omap2_mbox_startup,
210 .shutdown = omap2_mbox_shutdown,
211 .fifo_read = omap2_mbox_fifo_read,
212 .fifo_write = omap2_mbox_fifo_write,
213 .fifo_empty = omap2_mbox_fifo_empty,
214 .fifo_full = omap2_mbox_fifo_full,
215 .enable_irq = omap2_mbox_enable_irq,
216 .disable_irq = omap2_mbox_disable_irq,
217 .ack_irq = omap2_mbox_ack_irq,
218 .is_irq = omap2_mbox_is_irq,
219 .save_ctx = omap2_mbox_save_ctx,
220 .restore_ctx = omap2_mbox_restore_ctx,
221};
222
223/*
224 * MAILBOX 0: ARM -> DSP,
225 * MAILBOX 1: ARM <- DSP.
226 * MAILBOX 2: ARM -> IVA,
227 * MAILBOX 3: ARM <- IVA.
228 */
229
230/* FIXME: the following structs should be filled automatically by the user id */
231
232#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
233/* DSP */
234static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
235 .tx_fifo = {
236 .msg = MAILBOX_MESSAGE(0),
237 .fifo_stat = MAILBOX_FIFOSTATUS(0),
238 },
239 .rx_fifo = {
240 .msg = MAILBOX_MESSAGE(1),
241 .msg_stat = MAILBOX_MSGSTATUS(1),
242 },
243 .irqenable = MAILBOX_IRQENABLE(0),
244 .irqstatus = MAILBOX_IRQSTATUS(0),
245 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
246 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
247 .irqdisable = MAILBOX_IRQENABLE(0),
248};
249
250struct omap_mbox mbox_dsp_info = {
251 .name = "dsp",
252 .ops = &omap2_mbox_ops,
253 .priv = &omap2_mbox_dsp_priv,
254};
255#endif
256
257#if defined(CONFIG_ARCH_OMAP3)
258struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
259#endif
260
261#if defined(CONFIG_SOC_OMAP2420)
262/* IVA */
263static struct omap_mbox2_priv omap2_mbox_iva_priv = {
264 .tx_fifo = {
265 .msg = MAILBOX_MESSAGE(2),
266 .fifo_stat = MAILBOX_FIFOSTATUS(2),
267 },
268 .rx_fifo = {
269 .msg = MAILBOX_MESSAGE(3),
270 .msg_stat = MAILBOX_MSGSTATUS(3),
271 },
272 .irqenable = MAILBOX_IRQENABLE(3),
273 .irqstatus = MAILBOX_IRQSTATUS(3),
274 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
275 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
276 .irqdisable = MAILBOX_IRQENABLE(3),
277};
278
279static struct omap_mbox mbox_iva_info = {
280 .name = "iva",
281 .ops = &omap2_mbox_ops,
282 .priv = &omap2_mbox_iva_priv,
283};
284#endif
285
286#ifdef CONFIG_ARCH_OMAP2
287struct omap_mbox *omap2_mboxes[] = {
288 &mbox_dsp_info,
289#ifdef CONFIG_SOC_OMAP2420
290 &mbox_iva_info,
291#endif
292 NULL
293};
294#endif
295
296#if defined(CONFIG_ARCH_OMAP4)
297/* OMAP4 */
298static struct omap_mbox2_priv omap2_mbox_1_priv = {
299 .tx_fifo = {
300 .msg = MAILBOX_MESSAGE(0),
301 .fifo_stat = MAILBOX_FIFOSTATUS(0),
302 },
303 .rx_fifo = {
304 .msg = MAILBOX_MESSAGE(1),
305 .msg_stat = MAILBOX_MSGSTATUS(1),
306 },
307 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
308 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
309 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
310 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
311 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
312};
313
314struct omap_mbox mbox_1_info = {
315 .name = "mailbox-1",
316 .ops = &omap2_mbox_ops,
317 .priv = &omap2_mbox_1_priv,
318};
319
320static struct omap_mbox2_priv omap2_mbox_2_priv = {
321 .tx_fifo = {
322 .msg = MAILBOX_MESSAGE(3),
323 .fifo_stat = MAILBOX_FIFOSTATUS(3),
324 },
325 .rx_fifo = {
326 .msg = MAILBOX_MESSAGE(2),
327 .msg_stat = MAILBOX_MSGSTATUS(2),
328 },
329 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
330 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
331 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
332 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
333 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
334};
335
336struct omap_mbox mbox_2_info = {
337 .name = "mailbox-2",
338 .ops = &omap2_mbox_ops,
339 .priv = &omap2_mbox_2_priv,
340};
341
342struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
343#endif
344
345static int omap2_mbox_probe(struct platform_device *pdev)
346{
347 struct resource *mem;
348 int ret;
349 struct omap_mbox **list;
350
351 if (false)
352 ;
353#if defined(CONFIG_ARCH_OMAP3)
354 else if (cpu_is_omap34xx()) {
355 list = omap3_mboxes;
356
357 list[0]->irq = platform_get_irq(pdev, 0);
358 }
359#endif
360#if defined(CONFIG_ARCH_OMAP2)
361 else if (cpu_is_omap2430()) {
362 list = omap2_mboxes;
363
364 list[0]->irq = platform_get_irq(pdev, 0);
365 } else if (cpu_is_omap2420()) {
366 list = omap2_mboxes;
367
368 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
369 list[1]->irq = platform_get_irq_byname(pdev, "iva");
370 }
371#endif
372#if defined(CONFIG_ARCH_OMAP4)
373 else if (cpu_is_omap44xx()) {
374 list = omap4_mboxes;
375
376 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
377 }
378#endif
379 else {
380 pr_err("%s: platform not supported\n", __func__);
381 return -ENODEV;
382 }
383
384 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385 mbox_base = ioremap(mem->start, resource_size(mem));
386 if (!mbox_base)
387 return -ENOMEM;
388
389 ret = omap_mbox_register(&pdev->dev, list);
390 if (ret) {
391 iounmap(mbox_base);
392 return ret;
393 }
394
395 return 0;
396}
397
398static int omap2_mbox_remove(struct platform_device *pdev)
399{
400 omap_mbox_unregister();
401 iounmap(mbox_base);
402 return 0;
403}
404
405static struct platform_driver omap2_mbox_driver = {
406 .probe = omap2_mbox_probe,
407 .remove = omap2_mbox_remove,
408 .driver = {
409 .name = "omap-mailbox",
410 },
411};
412
413static int __init omap2_mbox_init(void)
414{
415 return platform_driver_register(&omap2_mbox_driver);
416}
417
418static void __exit omap2_mbox_exit(void)
419{
420 platform_driver_unregister(&omap2_mbox_driver);
421}
422
423module_init(omap2_mbox_init);
424module_exit(omap2_mbox_exit);
425
426MODULE_LICENSE("GPL v2");
427MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
428MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
429MODULE_AUTHOR("Paul Mundt");
430MODULE_ALIAS("platform:omap2-mailbox");
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 5137cc84b504..d8b9d60f854f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,6 +16,7 @@
16#include <linux/i2c-omap.h> 16#include <linux/i2c-omap.h>
17#include <linux/platform_data/spi-omap2-mcspi.h> 17#include <linux/platform_data/spi-omap2-mcspi.h>
18#include <linux/omap-dma.h> 18#include <linux/omap-dma.h>
19#include <linux/platform_data/mailbox-omap.h>
19#include <plat/dmtimer.h> 20#include <plat/dmtimer.h>
20 21
21#include "omap_hwmod.h" 22#include "omap_hwmod.h"
@@ -166,6 +167,18 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
166}; 167};
167 168
168/* mailbox */ 169/* mailbox */
170static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
171 { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
172 { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
173};
174
175static struct omap_mbox_pdata omap2420_mailbox_attrs = {
176 .num_users = 4,
177 .num_fifos = 6,
178 .info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
179 .info = omap2420_mailbox_info,
180};
181
169static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 182static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
170 { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, 183 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
171 { .name = "iva", .irq = 34 + OMAP_INTC_START, }, 184 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
@@ -186,6 +199,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
186 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 199 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
187 }, 200 },
188 }, 201 },
202 .dev_attr = &omap2420_mailbox_attrs,
189}; 203};
190 204
191/* 205/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4ce999ee3ee9..5b9083461dc5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,6 +17,7 @@
17#include <linux/platform_data/asoc-ti-mcbsp.h> 17#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/spi-omap2-mcspi.h> 18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include <linux/omap-dma.h> 19#include <linux/omap-dma.h>
20#include <linux/platform_data/mailbox-omap.h>
20#include <plat/dmtimer.h> 21#include <plat/dmtimer.h>
21 22
22#include "omap_hwmod.h" 23#include "omap_hwmod.h"
@@ -170,6 +171,17 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
170}; 171};
171 172
172/* mailbox */ 173/* mailbox */
174static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
175 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
176};
177
178static struct omap_mbox_pdata omap2430_mailbox_attrs = {
179 .num_users = 4,
180 .num_fifos = 6,
181 .info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
182 .info = omap2430_mailbox_info,
183};
184
173static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 185static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
174 { .irq = 26 + OMAP_INTC_START, }, 186 { .irq = 26 + OMAP_INTC_START, },
175 { .irq = -1 }, 187 { .irq = -1 },
@@ -189,6 +201,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
189 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 201 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
190 }, 202 },
191 }, 203 },
204 .dev_attr = &omap2430_mailbox_attrs,
192}; 205};
193 206
194/* mcspi3 */ 207/* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index fa9915411440..f7a3df2fb579 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,6 +25,7 @@
25#include <linux/platform_data/asoc-ti-mcbsp.h> 25#include <linux/platform_data/asoc-ti-mcbsp.h>
26#include <linux/platform_data/spi-omap2-mcspi.h> 26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/iommu-omap.h> 27#include <linux/platform_data/iommu-omap.h>
28#include <linux/platform_data/mailbox-omap.h>
28#include <plat/dmtimer.h> 29#include <plat/dmtimer.h>
29 30
30#include "am35xx.h" 31#include "am35xx.h"
@@ -1504,6 +1505,17 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1504 .sysc = &omap3xxx_mailbox_sysc, 1505 .sysc = &omap3xxx_mailbox_sysc,
1505}; 1506};
1506 1507
1508static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
1509 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
1510};
1511
1512static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
1513 .num_users = 2,
1514 .num_fifos = 2,
1515 .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
1516 .info = omap3xxx_mailbox_info,
1517};
1518
1507static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1519static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1508 { .irq = 26 + OMAP_INTC_START, }, 1520 { .irq = 26 + OMAP_INTC_START, },
1509 { .irq = -1 }, 1521 { .irq = -1 },
@@ -1523,6 +1535,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1523 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1535 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1524 }, 1536 },
1525 }, 1537 },
1538 .dev_attr = &omap3xxx_mailbox_attrs,
1526}; 1539};
1527 1540
1528/* 1541/*
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0adb2b85f830..6d9252e081ce 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -28,7 +28,7 @@ config CPU_S3C2410
28 select CPU_ARM920T 28 select CPU_ARM920T
29 select CPU_LLSERIAL_S3C2410 29 select CPU_LLSERIAL_S3C2410
30 select S3C2410_CLOCK 30 select S3C2410_CLOCK
31 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX 31 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
32 select S3C2410_PM if PM 32 select S3C2410_PM if PM
33 select SAMSUNG_HRT 33 select SAMSUNG_HRT
34 select SAMSUNG_WDT_RESET 34 select SAMSUNG_WDT_RESET
@@ -206,27 +206,38 @@ config S3C24XX_GPIO_EXTRA128
206 Add an extra 128 gpio numbers to the available GPIO pool. This is 206 Add an extra 128 gpio numbers to the available GPIO pool. This is
207 available for boards that need extra gpios for external devices. 207 available for boards that need extra gpios for external devices.
208 208
209config S3C24XX_PLL
210 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
211 depends on ARM_S3C24XX
212 help
213 Compile in support for changing the PLL frequency from the
214 S3C24XX series CPUfreq driver. The PLL takes time to settle
215 after a frequency change, so by default it is not enabled.
216
217 This also means that the PLL tables for the selected CPU(s) will
218 be built which may increase the size of the kernel image.
219
209# cpu frequency items common between s3c2410 and s3c2440/s3c2442 220# cpu frequency items common between s3c2410 and s3c2440/s3c2442
210 221
211config S3C2410_IOTIMING 222config S3C2410_IOTIMING
212 bool 223 bool
213 depends on CPU_FREQ_S3C24XX 224 depends on ARM_S3C24XX_CPUFREQ
214 help 225 help
215 Internal node to select io timing code that is common to the s3c2410 226 Internal node to select io timing code that is common to the s3c2410
216 and s3c2440/s3c2442 cpu frequency support. 227 and s3c2440/s3c2442 cpu frequency support.
217 228
218config S3C2410_CPUFREQ_UTILS 229config S3C2410_CPUFREQ_UTILS
219 bool 230 bool
220 depends on CPU_FREQ_S3C24XX 231 depends on ARM_S3C24XX_CPUFREQ
221 help 232 help
222 Internal node to select timing code that is common to the s3c2410 233 Internal node to select timing code that is common to the s3c2410
223 and s3c2440/s3c244 cpu frequency support. 234 and s3c2440/s3c244 cpu frequency support.
224 235
225# cpu frequency support common to s3c2412, s3c2413 and s3c2442 236# cpu frequency support common to s3c2412, s3c2413 and s3c2442
226 237
227config S3C2412_IOTIMING 238config S3C2412_IOTIMING
228 bool 239 bool
229 depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) 240 depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443)
230 help 241 help
231 Intel node to select io timing code that is common to the s3c2412 242 Intel node to select io timing code that is common to the s3c2412
232 and the s3c2443. 243 and the s3c2443.
@@ -235,16 +246,9 @@ config S3C2412_IOTIMING
235 246
236if CPU_S3C2410 247if CPU_S3C2410
237 248
238config S3C2410_CPUFREQ
239 bool
240 depends on CPU_FREQ_S3C24XX
241 select S3C2410_CPUFREQ_UTILS
242 help
243 CPU Frequency scaling support for S3C2410
244
245config S3C2410_PLL 249config S3C2410_PLL
246 bool 250 bool
247 depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL 251 depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL
248 default y 252 default y
249 help 253 help
250 Select the PLL table for the S3C2410 254 Select the PLL table for the S3C2410
@@ -280,7 +284,7 @@ config ARCH_BAST
280 bool "Simtec Electronics BAST (EB2410ITX)" 284 bool "Simtec Electronics BAST (EB2410ITX)"
281 select ISA 285 select ISA
282 select MACH_BAST_IDE 286 select MACH_BAST_IDE
283 select S3C2410_IOTIMING if S3C2410_CPUFREQ 287 select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
284 select S3C24XX_DCLK 288 select S3C24XX_DCLK
285 select S3C24XX_SIMTEC_NOR 289 select S3C24XX_SIMTEC_NOR
286 select S3C24XX_SIMTEC_PM if PM 290 select S3C24XX_SIMTEC_PM if PM
@@ -387,14 +391,6 @@ config CPU_S3C2412_ONLY
387 !CPU_S3C2442 && !CPU_S3C2443 391 !CPU_S3C2442 && !CPU_S3C2443
388 default y 392 default y
389 393
390config S3C2412_CPUFREQ
391 bool
392 depends on CPU_FREQ_S3C24XX
393 default y
394 select S3C2412_IOTIMING
395 help
396 CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
397
398config S3C2412_DMA 394config S3C2412_DMA
399 bool 395 bool
400 help 396 help
@@ -508,14 +504,6 @@ endif # CPU_S3C2416
508 504
509if CPU_S3C2440 505if CPU_S3C2440
510 506
511config S3C2440_CPUFREQ
512 bool "S3C2440/S3C2442 CPU Frequency scaling support"
513 depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
514 default y
515 select S3C2410_CPUFREQ_UTILS
516 help
517 CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
518
519config S3C2440_DMA 507config S3C2440_DMA
520 bool 508 bool
521 help 509 help
@@ -535,15 +523,15 @@ config S3C2440_XTAL_16934400
535 523
536config S3C2440_PLL_12000000 524config S3C2440_PLL_12000000
537 bool 525 bool
538 depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000 526 depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000
539 default y if CPU_FREQ_S3C24XX_PLL 527 default y if S3C24XX_PLL
540 help 528 help
541 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals. 529 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
542 530
543config S3C2440_PLL_16934400 531config S3C2440_PLL_16934400
544 bool 532 bool
545 depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400 533 depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400
546 default y if CPU_FREQ_S3C24XX_PLL 534 default y if S3C24XX_PLL
547 help 535 help
548 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals. 536 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
549 537
@@ -597,7 +585,7 @@ config MACH_NEXCODER_2440
597 585
598config MACH_OSIRIS 586config MACH_OSIRIS
599 bool "Simtec IM2440D20 (OSIRIS) module" 587 bool "Simtec IM2440D20 (OSIRIS) module"
600 select S3C2410_IOTIMING if S3C2440_CPUFREQ 588 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
601 select S3C2440_XTAL_12000000 589 select S3C2440_XTAL_12000000
602 select S3C24XX_DCLK 590 select S3C24XX_DCLK
603 select S3C24XX_GPIO_EXTRA128 591 select S3C24XX_GPIO_EXTRA128
@@ -669,7 +657,7 @@ config MACH_RX1950
669 bool "HP iPAQ rx1950" 657 bool "HP iPAQ rx1950"
670 select I2C 658 select I2C
671 select PM_H1940 if PM 659 select PM_H1940 if PM
672 select S3C2410_IOTIMING if S3C2440_CPUFREQ 660 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
673 select S3C2440_XTAL_16934400 661 select S3C2440_XTAL_16934400
674 select S3C24XX_DCLK 662 select S3C24XX_DCLK
675 select S3C24XX_PWM 663 select S3C24XX_PWM
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 6de730bada4d..7f54e5b954ca 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -17,13 +17,11 @@ obj- :=
17obj-y += common.o 17obj-y += common.o
18 18
19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o
21obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o 20obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
22obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o 21obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
23obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o 22obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
24 23
25obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o 24obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o
26obj-$(CONFIG_S3C2412_CPUFREQ) += cpufreq-s3c2412.o
27obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o 25obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
28obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o 26obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
29obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o 27obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
@@ -34,7 +32,6 @@ obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
34obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o 32obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o
35obj-$(CONFIG_CPU_S3C2442) += s3c2442.o 33obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
36obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o 34obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o
37obj-$(CONFIG_S3C2440_CPUFREQ) += cpufreq-s3c2440.o
38obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o 35obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
39obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o 36obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
40obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o 37obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
@@ -59,9 +56,6 @@ obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
59obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o 56obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o
60obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o 57obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
61 58
62obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o
63obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
64
65# 59#
66# machine support 60# machine support
67# following is ordered alphabetically by option text. 61# following is ordered alphabetically by option text.
diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
deleted file mode 100644
index 9b7b4289d66c..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
+++ /dev/null
@@ -1,198 +0,0 @@
1/*
2 * Copyright (c) 2009 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling - debugfs status support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/export.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/debugfs.h>
19#include <linux/seq_file.h>
20#include <linux/err.h>
21
22#include <plat/cpu-freq-core.h>
23
24static struct dentry *dbgfs_root;
25static struct dentry *dbgfs_file_io;
26static struct dentry *dbgfs_file_info;
27static struct dentry *dbgfs_file_board;
28
29#define print_ns(x) ((x) / 10), ((x) % 10)
30
31static void show_max(struct seq_file *seq, struct s3c_freq *f)
32{
33 seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
34 f->fclk, f->hclk, f->pclk, f->armclk);
35}
36
37static int board_show(struct seq_file *seq, void *p)
38{
39 struct s3c_cpufreq_config *cfg;
40 struct s3c_cpufreq_board *brd;
41
42 cfg = s3c_cpufreq_getconfig();
43 if (!cfg) {
44 seq_printf(seq, "no configuration registered\n");
45 return 0;
46 }
47
48 brd = cfg->board;
49 if (!brd) {
50 seq_printf(seq, "no board definition set?\n");
51 return 0;
52 }
53
54 seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
55 seq_printf(seq, "auto_io=%u\n", brd->auto_io);
56 seq_printf(seq, "need_io=%u\n", brd->need_io);
57
58 show_max(seq, &brd->max);
59
60
61 return 0;
62}
63
64static int fops_board_open(struct inode *inode, struct file *file)
65{
66 return single_open(file, board_show, NULL);
67}
68
69static const struct file_operations fops_board = {
70 .open = fops_board_open,
71 .read = seq_read,
72 .llseek = seq_lseek,
73 .release = single_release,
74 .owner = THIS_MODULE,
75};
76
77static int info_show(struct seq_file *seq, void *p)
78{
79 struct s3c_cpufreq_config *cfg;
80
81 cfg = s3c_cpufreq_getconfig();
82 if (!cfg) {
83 seq_printf(seq, "no configuration registered\n");
84 return 0;
85 }
86
87 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk);
88 seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n",
89 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
90 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk);
91 seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
92 seq_printf(seq, "\n");
93
94 show_max(seq, &cfg->max);
95
96 seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
97 cfg->divs.h_divisor, cfg->divs.p_divisor,
98 cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
99 seq_printf(seq, "\n");
100
101 seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
102
103 return 0;
104}
105
106static int fops_info_open(struct inode *inode, struct file *file)
107{
108 return single_open(file, info_show, NULL);
109}
110
111static const struct file_operations fops_info = {
112 .open = fops_info_open,
113 .read = seq_read,
114 .llseek = seq_lseek,
115 .release = single_release,
116 .owner = THIS_MODULE,
117};
118
119static int io_show(struct seq_file *seq, void *p)
120{
121 void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
122 struct s3c_cpufreq_config *cfg;
123 struct s3c_iotimings *iot;
124 union s3c_iobank *iob;
125 int bank;
126
127 cfg = s3c_cpufreq_getconfig();
128 if (!cfg) {
129 seq_printf(seq, "no configuration registered\n");
130 return 0;
131 }
132
133 show_bank = cfg->info->debug_io_show;
134 if (!show_bank) {
135 seq_printf(seq, "no code to show bank timing\n");
136 return 0;
137 }
138
139 iot = s3c_cpufreq_getiotimings();
140 if (!iot) {
141 seq_printf(seq, "no io timings registered\n");
142 return 0;
143 }
144
145 seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
146
147 for (bank = 0; bank < MAX_BANKS; bank++) {
148 iob = &iot->bank[bank];
149
150 seq_printf(seq, "bank %d: ", bank);
151
152 if (!iob->io_2410) {
153 seq_printf(seq, "nothing set\n");
154 continue;
155 }
156
157 show_bank(seq, cfg, iob);
158 }
159
160 return 0;
161}
162
163static int fops_io_open(struct inode *inode, struct file *file)
164{
165 return single_open(file, io_show, NULL);
166}
167
168static const struct file_operations fops_io = {
169 .open = fops_io_open,
170 .read = seq_read,
171 .llseek = seq_lseek,
172 .release = single_release,
173 .owner = THIS_MODULE,
174};
175
176
177static int __init s3c_freq_debugfs_init(void)
178{
179 dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
180 if (IS_ERR(dbgfs_root)) {
181 printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
182 return PTR_ERR(dbgfs_root);
183 }
184
185 dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
186 NULL, &fops_io);
187
188 dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
189 NULL, &fops_info);
190
191 dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
192 NULL, &fops_board);
193
194 return 0;
195}
196
197late_initcall(s3c_freq_debugfs_init);
198
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
deleted file mode 100644
index cfa0dd8723ec..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * Copyright (c) 2006-2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 CPU Frequency scaling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/device.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include <mach/regs-clock.h>
27
28#include <plat/cpu.h>
29#include <plat/clock.h>
30#include <plat/cpu-freq-core.h>
31
32/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
33
34static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
35{
36 u32 clkdiv = 0;
37
38 if (cfg->divs.h_divisor == 2)
39 clkdiv |= S3C2410_CLKDIVN_HDIVN;
40
41 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
42 clkdiv |= S3C2410_CLKDIVN_PDIVN;
43
44 __raw_writel(clkdiv, S3C2410_CLKDIVN);
45}
46
47static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
48{
49 unsigned long hclk, fclk, pclk;
50 unsigned int hdiv, pdiv;
51 unsigned long hclk_max;
52
53 fclk = cfg->freq.fclk;
54 hclk_max = cfg->max.hclk;
55
56 cfg->freq.armclk = fclk;
57
58 s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
59 __func__, fclk, hclk_max);
60
61 hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
62 hclk = fclk / hdiv;
63
64 if (hclk > cfg->max.hclk) {
65 s3c_freq_dbg("%s: hclk too big\n", __func__);
66 return -EINVAL;
67 }
68
69 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
70 pclk = hclk / pdiv;
71
72 if (pclk > cfg->max.pclk) {
73 s3c_freq_dbg("%s: pclk too big\n", __func__);
74 return -EINVAL;
75 }
76
77 pdiv *= hdiv;
78
79 /* record the result */
80 cfg->divs.p_divisor = pdiv;
81 cfg->divs.h_divisor = hdiv;
82
83 return 0;
84}
85
86static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
87 .max = {
88 .fclk = 200000000,
89 .hclk = 100000000,
90 .pclk = 50000000,
91 },
92
93 /* transition latency is about 5ms worst-case, so
94 * set 10ms to be sure */
95 .latency = 10000000,
96
97 .locktime_m = 150,
98 .locktime_u = 150,
99 .locktime_bits = 12,
100
101 .need_pll = 1,
102
103 .name = "s3c2410",
104 .calc_iotiming = s3c2410_iotiming_calc,
105 .set_iotiming = s3c2410_iotiming_set,
106 .get_iotiming = s3c2410_iotiming_get,
107 .resume_clocks = s3c2410_setup_clocks,
108
109 .set_fvco = s3c2410_set_fvco,
110 .set_refresh = s3c2410_cpufreq_setrefresh,
111 .set_divs = s3c2410_cpufreq_setdivs,
112 .calc_divs = s3c2410_cpufreq_calcdivs,
113
114 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
115};
116
117static int s3c2410_cpufreq_add(struct device *dev,
118 struct subsys_interface *sif)
119{
120 return s3c_cpufreq_register(&s3c2410_cpufreq_info);
121}
122
123static struct subsys_interface s3c2410_cpufreq_interface = {
124 .name = "s3c2410_cpufreq",
125 .subsys = &s3c2410_subsys,
126 .add_dev = s3c2410_cpufreq_add,
127};
128
129static int __init s3c2410_cpufreq_init(void)
130{
131 return subsys_interface_register(&s3c2410_cpufreq_interface);
132}
133arch_initcall(s3c2410_cpufreq_init);
134
135static int s3c2410a_cpufreq_add(struct device *dev,
136 struct subsys_interface *sif)
137{
138 /* alter the maximum freq settings for S3C2410A. If a board knows
139 * it only has a maximum of 200, then it should register its own
140 * limits. */
141
142 s3c2410_cpufreq_info.max.fclk = 266000000;
143 s3c2410_cpufreq_info.max.hclk = 133000000;
144 s3c2410_cpufreq_info.max.pclk = 66500000;
145 s3c2410_cpufreq_info.name = "s3c2410a";
146
147 return s3c2410_cpufreq_add(dev, sif);
148}
149
150static struct subsys_interface s3c2410a_cpufreq_interface = {
151 .name = "s3c2410a_cpufreq",
152 .subsys = &s3c2410a_subsys,
153 .add_dev = s3c2410a_cpufreq_add,
154};
155
156static int __init s3c2410a_cpufreq_init(void)
157{
158 return subsys_interface_register(&s3c2410a_cpufreq_interface);
159}
160arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
deleted file mode 100644
index 8bf0f3a77476..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * Copyright 2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 CPU Frequency scalling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/device.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/io.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <mach/regs-clock.h>
28
29#include <plat/cpu.h>
30#include <plat/clock.h>
31#include <plat/cpu-freq-core.h>
32
33#include "s3c2412.h"
34
35/* our clock resources. */
36static struct clk *xtal;
37static struct clk *fclk;
38static struct clk *hclk;
39static struct clk *armclk;
40
41/* HDIV: 1, 2, 3, 4, 6, 8 */
42
43static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
44{
45 unsigned int hdiv, pdiv, armdiv, dvs;
46 unsigned long hclk, fclk, armclk, armdiv_clk;
47 unsigned long hclk_max;
48
49 fclk = cfg->freq.fclk;
50 armclk = cfg->freq.armclk;
51 hclk_max = cfg->max.hclk;
52
53 /* We can't run hclk above armclk as at the best we have to
54 * have armclk and hclk in dvs mode. */
55
56 if (hclk_max > armclk)
57 hclk_max = armclk;
58
59 s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
60 __func__, fclk, armclk, hclk_max);
61 s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
62 __func__, cfg->freq.fclk, cfg->freq.armclk,
63 cfg->freq.hclk, cfg->freq.pclk);
64
65 armdiv = fclk / armclk;
66
67 if (armdiv < 1)
68 armdiv = 1;
69 if (armdiv > 2)
70 armdiv = 2;
71
72 cfg->divs.arm_divisor = armdiv;
73 armdiv_clk = fclk / armdiv;
74
75 hdiv = armdiv_clk / hclk_max;
76 if (hdiv < 1)
77 hdiv = 1;
78
79 cfg->freq.hclk = hclk = armdiv_clk / hdiv;
80
81 /* set dvs depending on whether we reached armclk or not. */
82 cfg->divs.dvs = dvs = armclk < armdiv_clk;
83
84 /* update the actual armclk we achieved. */
85 cfg->freq.armclk = dvs ? hclk : armdiv_clk;
86
87 s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
88 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
89
90 if (hdiv > 4)
91 goto invalid;
92
93 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
94
95 if ((hclk / pdiv) > cfg->max.pclk)
96 pdiv++;
97
98 cfg->freq.pclk = hclk / pdiv;
99
100 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
101
102 if (pdiv > 2)
103 goto invalid;
104
105 pdiv *= hdiv;
106
107 /* store the result, and then return */
108
109 cfg->divs.h_divisor = hdiv * armdiv;
110 cfg->divs.p_divisor = pdiv * armdiv;
111
112 return 0;
113
114invalid:
115 return -EINVAL;
116}
117
118static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
119{
120 unsigned long clkdiv;
121 unsigned long olddiv;
122
123 olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
124
125 /* clear off current clock info */
126
127 clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
128 clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
129 clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
130
131 if (cfg->divs.arm_divisor == 2)
132 clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
133
134 clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
135
136 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
137 clkdiv |= S3C2412_CLKDIVN_PDIVN;
138
139 s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
140 __raw_writel(clkdiv, S3C2410_CLKDIVN);
141
142 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
143}
144
145static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
146{
147 struct s3c_cpufreq_board *board = cfg->board;
148 unsigned long refresh;
149
150 s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
151 board->refresh, cfg->freq.hclk);
152
153 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
154 * by 10 each to ensure that we do not overflow 32 bit numbers. This
155 * should work for HCLK up to 133MHz and refresh period up to 30usec.
156 */
157
158 refresh = (board->refresh / 10);
159 refresh *= (cfg->freq.hclk / 100);
160 refresh /= (1 * 1000 * 1000); /* 10^6 */
161
162 s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
163 __raw_writel(refresh, S3C2412_REFRESH);
164}
165
166/* set the default cpu frequency information, based on an 200MHz part
167 * as we have no other way of detecting the speed rating in software.
168 */
169
170static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
171 .max = {
172 .fclk = 200000000,
173 .hclk = 100000000,
174 .pclk = 50000000,
175 },
176
177 .latency = 5000000, /* 5ms */
178
179 .locktime_m = 150,
180 .locktime_u = 150,
181 .locktime_bits = 16,
182
183 .name = "s3c2412",
184 .set_refresh = s3c2412_cpufreq_setrefresh,
185 .set_divs = s3c2412_cpufreq_setdivs,
186 .calc_divs = s3c2412_cpufreq_calcdivs,
187
188 .calc_iotiming = s3c2412_iotiming_calc,
189 .set_iotiming = s3c2412_iotiming_set,
190 .get_iotiming = s3c2412_iotiming_get,
191
192 .resume_clocks = s3c2412_setup_clocks,
193
194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
195};
196
197static int s3c2412_cpufreq_add(struct device *dev,
198 struct subsys_interface *sif)
199{
200 unsigned long fclk_rate;
201
202 hclk = clk_get(NULL, "hclk");
203 if (IS_ERR(hclk)) {
204 printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
205 return -ENOENT;
206 }
207
208 fclk = clk_get(NULL, "fclk");
209 if (IS_ERR(fclk)) {
210 printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
211 goto err_fclk;
212 }
213
214 fclk_rate = clk_get_rate(fclk);
215 if (fclk_rate > 200000000) {
216 printk(KERN_INFO
217 "%s: fclk %ld MHz, assuming 266MHz capable part\n",
218 __func__, fclk_rate / 1000000);
219 s3c2412_cpufreq_info.max.fclk = 266000000;
220 s3c2412_cpufreq_info.max.hclk = 133000000;
221 s3c2412_cpufreq_info.max.pclk = 66000000;
222 }
223
224 armclk = clk_get(NULL, "armclk");
225 if (IS_ERR(armclk)) {
226 printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
227 goto err_armclk;
228 }
229
230 xtal = clk_get(NULL, "xtal");
231 if (IS_ERR(xtal)) {
232 printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
233 goto err_xtal;
234 }
235
236 return s3c_cpufreq_register(&s3c2412_cpufreq_info);
237
238err_xtal:
239 clk_put(armclk);
240err_armclk:
241 clk_put(fclk);
242err_fclk:
243 clk_put(hclk);
244
245 return -ENOENT;
246}
247
248static struct subsys_interface s3c2412_cpufreq_interface = {
249 .name = "s3c2412_cpufreq",
250 .subsys = &s3c2412_subsys,
251 .add_dev = s3c2412_cpufreq_add,
252};
253
254static int s3c2412_cpufreq_init(void)
255{
256 return subsys_interface_register(&s3c2412_cpufreq_interface);
257}
258arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
deleted file mode 100644
index 72b2cc8a5a85..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
+++ /dev/null
@@ -1,312 +0,0 @@
1/*
2 * Copyright (c) 2006-2009 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * S3C2440/S3C2442 CPU Frequency scaling
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/cpufreq.h>
19#include <linux/device.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <mach/regs-clock.h>
31
32#include <plat/cpu.h>
33#include <plat/cpu-freq-core.h>
34#include <plat/clock.h>
35
36static struct clk *xtal;
37static struct clk *fclk;
38static struct clk *hclk;
39static struct clk *armclk;
40
41/* HDIV: 1, 2, 3, 4, 6, 8 */
42
43static inline int within_khz(unsigned long a, unsigned long b)
44{
45 long diff = a - b;
46
47 return (diff >= -1000 && diff <= 1000);
48}
49
50/**
51 * s3c2440_cpufreq_calcdivs - calculate divider settings
52 * @cfg: The cpu frequency settings.
53 *
54 * Calcualte the divider values for the given frequency settings
55 * specified in @cfg. The values are stored in @cfg for later use
56 * by the relevant set routine if the request settings can be reached.
57 */
58int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
59{
60 unsigned int hdiv, pdiv;
61 unsigned long hclk, fclk, armclk;
62 unsigned long hclk_max;
63
64 fclk = cfg->freq.fclk;
65 armclk = cfg->freq.armclk;
66 hclk_max = cfg->max.hclk;
67
68 s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
69 __func__, fclk, armclk, hclk_max);
70
71 if (armclk > fclk) {
72 printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
73 armclk = fclk;
74 }
75
76 /* if we are in DVS, we need HCLK to be <= ARMCLK */
77 if (armclk < fclk && armclk < hclk_max)
78 hclk_max = armclk;
79
80 for (hdiv = 1; hdiv < 9; hdiv++) {
81 if (hdiv == 5 || hdiv == 7)
82 hdiv++;
83
84 hclk = (fclk / hdiv);
85 if (hclk <= hclk_max || within_khz(hclk, hclk_max))
86 break;
87 }
88
89 s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
90
91 if (hdiv > 8)
92 goto invalid;
93
94 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
95
96 if ((hclk / pdiv) > cfg->max.pclk)
97 pdiv++;
98
99 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
100
101 if (pdiv > 2)
102 goto invalid;
103
104 pdiv *= hdiv;
105
106 /* calculate a valid armclk */
107
108 if (armclk < hclk)
109 armclk = hclk;
110
111 /* if we're running armclk lower than fclk, this really means
112 * that the system should go into dvs mode, which means that
113 * armclk is connected to hclk. */
114 if (armclk < fclk) {
115 cfg->divs.dvs = 1;
116 armclk = hclk;
117 } else
118 cfg->divs.dvs = 0;
119
120 cfg->freq.armclk = armclk;
121
122 /* store the result, and then return */
123
124 cfg->divs.h_divisor = hdiv;
125 cfg->divs.p_divisor = pdiv;
126
127 return 0;
128
129 invalid:
130 return -EINVAL;
131}
132
133#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
134 S3C2440_CAMDIVN_HCLK4_HALF)
135
136/**
137 * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
138 * @cfg: The cpu frequency settings.
139 *
140 * Set the divisors from the settings in @cfg, which where generated
141 * during the calculation phase by s3c2440_cpufreq_calcdivs().
142 */
143static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
144{
145 unsigned long clkdiv, camdiv;
146
147 s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
148 cfg->divs.h_divisor, cfg->divs.p_divisor);
149
150 clkdiv = __raw_readl(S3C2410_CLKDIVN);
151 camdiv = __raw_readl(S3C2440_CAMDIVN);
152
153 clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
154 camdiv &= ~CAMDIVN_HCLK_HALF;
155
156 switch (cfg->divs.h_divisor) {
157 case 1:
158 clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
159 break;
160
161 case 2:
162 clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
163 break;
164
165 case 6:
166 camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
167 case 3:
168 clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
169 break;
170
171 case 8:
172 camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
173 case 4:
174 clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
175 break;
176
177 default:
178 BUG(); /* we don't expect to get here. */
179 }
180
181 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
182 clkdiv |= S3C2440_CLKDIVN_PDIVN;
183
184 /* todo - set pclk. */
185
186 /* Write the divisors first with hclk intentionally halved so that
187 * when we write clkdiv we will under-frequency instead of over. We
188 * then make a short delay and remove the hclk halving if necessary.
189 */
190
191 __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
192 __raw_writel(clkdiv, S3C2410_CLKDIVN);
193
194 ndelay(20);
195 __raw_writel(camdiv, S3C2440_CAMDIVN);
196
197 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
198}
199
200static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
201 int *divs,
202 struct cpufreq_frequency_table *table,
203 size_t table_size)
204{
205 unsigned long freq;
206 int index = 0;
207 int div;
208
209 for (div = *divs; div > 0; div = *divs++) {
210 freq = fclk / div;
211
212 if (freq > max_hclk && div != 1)
213 continue;
214
215 freq /= 1000; /* table is in kHz */
216 index = s3c_cpufreq_addfreq(table, index, table_size, freq);
217 if (index < 0)
218 break;
219 }
220
221 return index;
222}
223
224static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
225
226static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
227 struct cpufreq_frequency_table *table,
228 size_t table_size)
229{
230 int ret;
231
232 WARN_ON(cfg->info == NULL);
233 WARN_ON(cfg->board == NULL);
234
235 ret = run_freq_for(cfg->info->max.hclk,
236 cfg->info->max.fclk,
237 hclk_divs,
238 table, table_size);
239
240 s3c_freq_dbg("%s: returning %d\n", __func__, ret);
241
242 return ret;
243}
244
245struct s3c_cpufreq_info s3c2440_cpufreq_info = {
246 .max = {
247 .fclk = 400000000,
248 .hclk = 133333333,
249 .pclk = 66666666,
250 },
251
252 .locktime_m = 300,
253 .locktime_u = 300,
254 .locktime_bits = 16,
255
256 .name = "s3c244x",
257 .calc_iotiming = s3c2410_iotiming_calc,
258 .set_iotiming = s3c2410_iotiming_set,
259 .get_iotiming = s3c2410_iotiming_get,
260 .set_fvco = s3c2410_set_fvco,
261
262 .set_refresh = s3c2410_cpufreq_setrefresh,
263 .set_divs = s3c2440_cpufreq_setdivs,
264 .calc_divs = s3c2440_cpufreq_calcdivs,
265 .calc_freqtable = s3c2440_cpufreq_calctable,
266
267 .resume_clocks = s3c244x_setup_clocks,
268
269 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
270};
271
272static int s3c2440_cpufreq_add(struct device *dev,
273 struct subsys_interface *sif)
274{
275 xtal = s3c_cpufreq_clk_get(NULL, "xtal");
276 hclk = s3c_cpufreq_clk_get(NULL, "hclk");
277 fclk = s3c_cpufreq_clk_get(NULL, "fclk");
278 armclk = s3c_cpufreq_clk_get(NULL, "armclk");
279
280 if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
281 printk(KERN_ERR "%s: failed to get clocks\n", __func__);
282 return -ENOENT;
283 }
284
285 return s3c_cpufreq_register(&s3c2440_cpufreq_info);
286}
287
288static struct subsys_interface s3c2440_cpufreq_interface = {
289 .name = "s3c2440_cpufreq",
290 .subsys = &s3c2440_subsys,
291 .add_dev = s3c2440_cpufreq_add,
292};
293
294static int s3c2440_cpufreq_init(void)
295{
296 return subsys_interface_register(&s3c2440_cpufreq_interface);
297}
298
299/* arch_initcall adds the clocks we need, so use subsys_initcall. */
300subsys_initcall(s3c2440_cpufreq_init);
301
302static struct subsys_interface s3c2442_cpufreq_interface = {
303 .name = "s3c2442_cpufreq",
304 .subsys = &s3c2442_subsys,
305 .add_dev = s3c2440_cpufreq_add,
306};
307
308static int s3c2442_cpufreq_init(void)
309{
310 return subsys_interface_register(&s3c2442_cpufreq_interface);
311}
312subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
deleted file mode 100644
index 3c0e78ede0da..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq.c
+++ /dev/null
@@ -1,711 +0,0 @@
1/*
2 * Copyright (c) 2006-2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX CPU Frequency scaling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
18#include <linux/cpu.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/sysfs.h>
24#include <linux/slab.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28
29#include <plat/cpu.h>
30#include <plat/clock.h>
31#include <plat/cpu-freq-core.h>
32
33#include <mach/regs-clock.h>
34
35/* note, cpufreq support deals in kHz, no Hz */
36
37static struct cpufreq_driver s3c24xx_driver;
38static struct s3c_cpufreq_config cpu_cur;
39static struct s3c_iotimings s3c24xx_iotiming;
40static struct cpufreq_frequency_table *pll_reg;
41static unsigned int last_target = ~0;
42static unsigned int ftab_size;
43static struct cpufreq_frequency_table *ftab;
44
45static struct clk *_clk_mpll;
46static struct clk *_clk_xtal;
47static struct clk *clk_fclk;
48static struct clk *clk_hclk;
49static struct clk *clk_pclk;
50static struct clk *clk_arm;
51
52#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
53struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
54{
55 return &cpu_cur;
56}
57
58struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
59{
60 return &s3c24xx_iotiming;
61}
62#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
63
64static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
65{
66 unsigned long fclk, pclk, hclk, armclk;
67
68 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
69 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
70 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
71 cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
72
73 cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
74 cfg->pll.frequency = fclk;
75
76 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
77
78 cfg->divs.h_divisor = fclk / hclk;
79 cfg->divs.p_divisor = fclk / pclk;
80}
81
82static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
83{
84 unsigned long pll = cfg->pll.frequency;
85
86 cfg->freq.fclk = pll;
87 cfg->freq.hclk = pll / cfg->divs.h_divisor;
88 cfg->freq.pclk = pll / cfg->divs.p_divisor;
89
90 /* convert hclk into 10ths of nanoseconds for io calcs */
91 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
92}
93
94static inline int closer(unsigned int target, unsigned int n, unsigned int c)
95{
96 int diff_cur = abs(target - c);
97 int diff_new = abs(target - n);
98
99 return (diff_new < diff_cur);
100}
101
102static void s3c_cpufreq_show(const char *pfx,
103 struct s3c_cpufreq_config *cfg)
104{
105 s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
106 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
107 cfg->freq.hclk, cfg->divs.h_divisor,
108 cfg->freq.pclk, cfg->divs.p_divisor);
109}
110
111/* functions to wrapper the driver info calls to do the cpu specific work */
112
113static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
114{
115 if (cfg->info->set_iotiming)
116 (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
117}
118
119static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
120{
121 if (cfg->info->calc_iotiming)
122 return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
123
124 return 0;
125}
126
127static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
128{
129 (cfg->info->set_refresh)(cfg);
130}
131
132static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
133{
134 (cfg->info->set_divs)(cfg);
135}
136
137static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
138{
139 return (cfg->info->calc_divs)(cfg);
140}
141
142static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
143{
144 (cfg->info->set_fvco)(cfg);
145}
146
147static inline void s3c_cpufreq_resume_clocks(void)
148{
149 cpu_cur.info->resume_clocks();
150}
151
152static inline void s3c_cpufreq_updateclk(struct clk *clk,
153 unsigned int freq)
154{
155 clk_set_rate(clk, freq);
156}
157
158static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
159 unsigned int target_freq,
160 struct cpufreq_frequency_table *pll)
161{
162 struct s3c_cpufreq_freqs freqs;
163 struct s3c_cpufreq_config cpu_new;
164 unsigned long flags;
165
166 cpu_new = cpu_cur; /* copy new from current */
167
168 s3c_cpufreq_show("cur", &cpu_cur);
169
170 /* TODO - check for DMA currently outstanding */
171
172 cpu_new.pll = pll ? *pll : cpu_cur.pll;
173
174 if (pll)
175 freqs.pll_changing = 1;
176
177 /* update our frequencies */
178
179 cpu_new.freq.armclk = target_freq;
180 cpu_new.freq.fclk = cpu_new.pll.frequency;
181
182 if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
183 printk(KERN_ERR "no divisors for %d\n", target_freq);
184 goto err_notpossible;
185 }
186
187 s3c_freq_dbg("%s: got divs\n", __func__);
188
189 s3c_cpufreq_calc(&cpu_new);
190
191 s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
192
193 if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
194 if (s3c_cpufreq_calcio(&cpu_new) < 0) {
195 printk(KERN_ERR "%s: no IO timings\n", __func__);
196 goto err_notpossible;
197 }
198 }
199
200 s3c_cpufreq_show("new", &cpu_new);
201
202 /* setup our cpufreq parameters */
203
204 freqs.old = cpu_cur.freq;
205 freqs.new = cpu_new.freq;
206
207 freqs.freqs.old = cpu_cur.freq.armclk / 1000;
208 freqs.freqs.new = cpu_new.freq.armclk / 1000;
209
210 /* update f/h/p clock settings before we issue the change
211 * notification, so that drivers do not need to do anything
212 * special if they want to recalculate on CPUFREQ_PRECHANGE. */
213
214 s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
215 s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
216 s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
217 s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
218
219 /* start the frequency change */
220 cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE);
221
222 /* If hclk is staying the same, then we do not need to
223 * re-write the IO or the refresh timings whilst we are changing
224 * speed. */
225
226 local_irq_save(flags);
227
228 /* is our memory clock slowing down? */
229 if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
230 s3c_cpufreq_setrefresh(&cpu_new);
231 s3c_cpufreq_setio(&cpu_new);
232 }
233
234 if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
235 /* not changing PLL, just set the divisors */
236
237 s3c_cpufreq_setdivs(&cpu_new);
238 } else {
239 if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
240 /* slow the cpu down, then set divisors */
241
242 s3c_cpufreq_setfvco(&cpu_new);
243 s3c_cpufreq_setdivs(&cpu_new);
244 } else {
245 /* set the divisors, then speed up */
246
247 s3c_cpufreq_setdivs(&cpu_new);
248 s3c_cpufreq_setfvco(&cpu_new);
249 }
250 }
251
252 /* did our memory clock speed up */
253 if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
254 s3c_cpufreq_setrefresh(&cpu_new);
255 s3c_cpufreq_setio(&cpu_new);
256 }
257
258 /* update our current settings */
259 cpu_cur = cpu_new;
260
261 local_irq_restore(flags);
262
263 /* notify everyone we've done this */
264 cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE);
265
266 s3c_freq_dbg("%s: finished\n", __func__);
267 return 0;
268
269 err_notpossible:
270 printk(KERN_ERR "no compatible settings for %d\n", target_freq);
271 return -EINVAL;
272}
273
274/* s3c_cpufreq_target
275 *
276 * called by the cpufreq core to adjust the frequency that the CPU
277 * is currently running at.
278 */
279
280static int s3c_cpufreq_target(struct cpufreq_policy *policy,
281 unsigned int target_freq,
282 unsigned int relation)
283{
284 struct cpufreq_frequency_table *pll;
285 unsigned int index;
286
287 /* avoid repeated calls which cause a needless amout of duplicated
288 * logging output (and CPU time as the calculation process is
289 * done) */
290 if (target_freq == last_target)
291 return 0;
292
293 last_target = target_freq;
294
295 s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
296 __func__, policy, target_freq, relation);
297
298 if (ftab) {
299 if (cpufreq_frequency_table_target(policy, ftab,
300 target_freq, relation,
301 &index)) {
302 s3c_freq_dbg("%s: table failed\n", __func__);
303 return -EINVAL;
304 }
305
306 s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
307 target_freq, index, ftab[index].frequency);
308 target_freq = ftab[index].frequency;
309 }
310
311 target_freq *= 1000; /* convert target to Hz */
312
313 /* find the settings for our new frequency */
314
315 if (!pll_reg || cpu_cur.lock_pll) {
316 /* either we've not got any PLL values, or we've locked
317 * to the current one. */
318 pll = NULL;
319 } else {
320 struct cpufreq_policy tmp_policy;
321 int ret;
322
323 /* we keep the cpu pll table in Hz, to ensure we get an
324 * accurate value for the PLL output. */
325
326 tmp_policy.min = policy->min * 1000;
327 tmp_policy.max = policy->max * 1000;
328 tmp_policy.cpu = policy->cpu;
329
330 /* cpufreq_frequency_table_target uses a pointer to 'index'
331 * which is the number of the table entry, not the value of
332 * the table entry's index field. */
333
334 ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
335 target_freq, relation,
336 &index);
337
338 if (ret < 0) {
339 printk(KERN_ERR "%s: no PLL available\n", __func__);
340 goto err_notpossible;
341 }
342
343 pll = pll_reg + index;
344
345 s3c_freq_dbg("%s: target %u => %u\n",
346 __func__, target_freq, pll->frequency);
347
348 target_freq = pll->frequency;
349 }
350
351 return s3c_cpufreq_settarget(policy, target_freq, pll);
352
353 err_notpossible:
354 printk(KERN_ERR "no compatible settings for %d\n", target_freq);
355 return -EINVAL;
356}
357
358static unsigned int s3c_cpufreq_get(unsigned int cpu)
359{
360 return clk_get_rate(clk_arm) / 1000;
361}
362
363struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
364{
365 struct clk *clk;
366
367 clk = clk_get(dev, name);
368 if (IS_ERR(clk))
369 printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
370
371 return clk;
372}
373
374static int s3c_cpufreq_init(struct cpufreq_policy *policy)
375{
376 printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
377
378 if (policy->cpu != 0)
379 return -EINVAL;
380
381 policy->cur = s3c_cpufreq_get(0);
382 policy->min = policy->cpuinfo.min_freq = 0;
383 policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
384 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
385
386 /* feed the latency information from the cpu driver */
387 policy->cpuinfo.transition_latency = cpu_cur.info->latency;
388
389 if (ftab)
390 cpufreq_frequency_table_cpuinfo(policy, ftab);
391
392 return 0;
393}
394
395static __init int s3c_cpufreq_initclks(void)
396{
397 _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
398 _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
399 clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
400 clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
401 clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
402 clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
403
404 if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
405 IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
406 printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
407 return -ENOENT;
408 }
409
410 printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
411 clk_get_rate(clk_fclk) / 1000,
412 clk_get_rate(clk_hclk) / 1000,
413 clk_get_rate(clk_pclk) / 1000,
414 clk_get_rate(clk_arm) / 1000);
415
416 return 0;
417}
418
419static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
420{
421 if (policy->cpu != 0)
422 return -EINVAL;
423
424 return 0;
425}
426
427#ifdef CONFIG_PM
428static struct cpufreq_frequency_table suspend_pll;
429static unsigned int suspend_freq;
430
431static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
432{
433 suspend_pll.frequency = clk_get_rate(_clk_mpll);
434 suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
435 suspend_freq = s3c_cpufreq_get(0) * 1000;
436
437 return 0;
438}
439
440static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
441{
442 int ret;
443
444 s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
445
446 last_target = ~0; /* invalidate last_target setting */
447
448 /* first, find out what speed we resumed at. */
449 s3c_cpufreq_resume_clocks();
450
451 /* whilst we will be called later on, we try and re-set the
452 * cpu frequencies as soon as possible so that we do not end
453 * up resuming devices and then immediately having to re-set
454 * a number of settings once these devices have restarted.
455 *
456 * as a note, it is expected devices are not used until they
457 * have been un-suspended and at that time they should have
458 * used the updated clock settings.
459 */
460
461 ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
462 if (ret) {
463 printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
464 return ret;
465 }
466
467 return 0;
468}
469#else
470#define s3c_cpufreq_resume NULL
471#define s3c_cpufreq_suspend NULL
472#endif
473
474static struct cpufreq_driver s3c24xx_driver = {
475 .flags = CPUFREQ_STICKY,
476 .verify = s3c_cpufreq_verify,
477 .target = s3c_cpufreq_target,
478 .get = s3c_cpufreq_get,
479 .init = s3c_cpufreq_init,
480 .suspend = s3c_cpufreq_suspend,
481 .resume = s3c_cpufreq_resume,
482 .name = "s3c24xx",
483};
484
485
486int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
487{
488 if (!info || !info->name) {
489 printk(KERN_ERR "%s: failed to pass valid information\n",
490 __func__);
491 return -EINVAL;
492 }
493
494 printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
495 info->name);
496
497 /* check our driver info has valid data */
498
499 BUG_ON(info->set_refresh == NULL);
500 BUG_ON(info->set_divs == NULL);
501 BUG_ON(info->calc_divs == NULL);
502
503 /* info->set_fvco is optional, depending on whether there
504 * is a need to set the clock code. */
505
506 cpu_cur.info = info;
507
508 /* Note, driver registering should probably update locktime */
509
510 return 0;
511}
512
513int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
514{
515 struct s3c_cpufreq_board *ours;
516
517 if (!board) {
518 printk(KERN_INFO "%s: no board data\n", __func__);
519 return -EINVAL;
520 }
521
522 /* Copy the board information so that each board can make this
523 * initdata. */
524
525 ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
526 if (ours == NULL) {
527 printk(KERN_ERR "%s: no memory\n", __func__);
528 return -ENOMEM;
529 }
530
531 *ours = *board;
532 cpu_cur.board = ours;
533
534 return 0;
535}
536
537int __init s3c_cpufreq_auto_io(void)
538{
539 int ret;
540
541 if (!cpu_cur.info->get_iotiming) {
542 printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
543 return -ENOENT;
544 }
545
546 printk(KERN_INFO "%s: working out IO settings\n", __func__);
547
548 ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
549 if (ret)
550 printk(KERN_ERR "%s: failed to get timings\n", __func__);
551
552 return ret;
553}
554
555/* if one or is zero, then return the other, otherwise return the min */
556#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
557
558/**
559 * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
560 * @dst: The destination structure
561 * @a: One argument.
562 * @b: The other argument.
563 *
564 * Create a minimum of each frequency entry in the 'struct s3c_freq',
565 * unless the entry is zero when it is ignored and the non-zero argument
566 * used.
567 */
568static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
569 struct s3c_freq *a, struct s3c_freq *b)
570{
571 dst->fclk = do_min(a->fclk, b->fclk);
572 dst->hclk = do_min(a->hclk, b->hclk);
573 dst->pclk = do_min(a->pclk, b->pclk);
574 dst->armclk = do_min(a->armclk, b->armclk);
575}
576
577static inline u32 calc_locktime(u32 freq, u32 time_us)
578{
579 u32 result;
580
581 result = freq * time_us;
582 result = DIV_ROUND_UP(result, 1000 * 1000);
583
584 return result;
585}
586
587static void s3c_cpufreq_update_loctkime(void)
588{
589 unsigned int bits = cpu_cur.info->locktime_bits;
590 u32 rate = (u32)clk_get_rate(_clk_xtal);
591 u32 val;
592
593 if (bits == 0) {
594 WARN_ON(1);
595 return;
596 }
597
598 val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
599 val |= calc_locktime(rate, cpu_cur.info->locktime_m);
600
601 printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
602 __raw_writel(val, S3C2410_LOCKTIME);
603}
604
605static int s3c_cpufreq_build_freq(void)
606{
607 int size, ret;
608
609 if (!cpu_cur.info->calc_freqtable)
610 return -EINVAL;
611
612 kfree(ftab);
613 ftab = NULL;
614
615 size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
616 size++;
617
618 ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
619 if (!ftab) {
620 printk(KERN_ERR "%s: no memory for tables\n", __func__);
621 return -ENOMEM;
622 }
623
624 ftab_size = size;
625
626 ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
627 s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
628
629 return 0;
630}
631
632static int __init s3c_cpufreq_initcall(void)
633{
634 int ret = 0;
635
636 if (cpu_cur.info && cpu_cur.board) {
637 ret = s3c_cpufreq_initclks();
638 if (ret)
639 goto out;
640
641 /* get current settings */
642 s3c_cpufreq_getcur(&cpu_cur);
643 s3c_cpufreq_show("cur", &cpu_cur);
644
645 if (cpu_cur.board->auto_io) {
646 ret = s3c_cpufreq_auto_io();
647 if (ret) {
648 printk(KERN_ERR "%s: failed to get io timing\n",
649 __func__);
650 goto out;
651 }
652 }
653
654 if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
655 printk(KERN_ERR "%s: no IO support registered\n",
656 __func__);
657 ret = -EINVAL;
658 goto out;
659 }
660
661 if (!cpu_cur.info->need_pll)
662 cpu_cur.lock_pll = 1;
663
664 s3c_cpufreq_update_loctkime();
665
666 s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
667 &cpu_cur.info->max);
668
669 if (cpu_cur.info->calc_freqtable)
670 s3c_cpufreq_build_freq();
671
672 ret = cpufreq_register_driver(&s3c24xx_driver);
673 }
674
675 out:
676 return ret;
677}
678
679late_initcall(s3c_cpufreq_initcall);
680
681/**
682 * s3c_plltab_register - register CPU PLL table.
683 * @plls: The list of PLL entries.
684 * @plls_no: The size of the PLL entries @plls.
685 *
686 * Register the given set of PLLs with the system.
687 */
688int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
689 unsigned int plls_no)
690{
691 struct cpufreq_frequency_table *vals;
692 unsigned int size;
693
694 size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
695
696 vals = kmalloc(size, GFP_KERNEL);
697 if (vals) {
698 memcpy(vals, plls, size);
699 pll_reg = vals;
700
701 /* write a terminating entry, we don't store it in the
702 * table that is stored in the kernel */
703 vals += plls_no;
704 vals->frequency = CPUFREQ_TABLE_END;
705
706 printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
707 } else
708 printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
709
710 return vals ? 0 : -ENOMEM;
711}
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
index 548ced42cbb7..548ced42cbb7 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.h
+++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index 663436d9db01..bd064c05c473 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -31,7 +31,7 @@
31#include <plat/cpu-freq-core.h> 31#include <plat/cpu-freq-core.h>
32#include <plat/clock.h> 32#include <plat/clock.h>
33 33
34#include "s3c2412.h" 34#include <mach/s3c2412.h>
35 35
36#define print_ns(x) ((x) / 10), ((x) % 10) 36#define print_ns(x) ((x) / 10), ((x) % 10)
37 37
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index aba9e5692958..bfe443daf4b0 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -21,28 +21,14 @@
21 21
22static struct stedma40_chan_cfg msp0_dma_rx = { 22static struct stedma40_chan_cfg msp0_dma_rx = {
23 .high_priority = true, 23 .high_priority = true,
24 .dir = STEDMA40_PERIPH_TO_MEM, 24 .dir = DMA_DEV_TO_MEM,
25 25 .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
26 .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
27 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
28
29 .src_info.psize = STEDMA40_PSIZE_LOG_4,
30 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
31
32 /* data_width is set during configuration */
33}; 26};
34 27
35static struct stedma40_chan_cfg msp0_dma_tx = { 28static struct stedma40_chan_cfg msp0_dma_tx = {
36 .high_priority = true, 29 .high_priority = true,
37 .dir = STEDMA40_MEM_TO_PERIPH, 30 .dir = DMA_MEM_TO_DEV,
38 31 .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
39 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
41
42 .src_info.psize = STEDMA40_PSIZE_LOG_4,
43 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
44
45 /* data_width is set during configuration */
46}; 32};
47 33
48struct msp_i2s_platform_data msp0_platform_data = { 34struct msp_i2s_platform_data msp0_platform_data = {
@@ -53,28 +39,14 @@ struct msp_i2s_platform_data msp0_platform_data = {
53 39
54static struct stedma40_chan_cfg msp1_dma_rx = { 40static struct stedma40_chan_cfg msp1_dma_rx = {
55 .high_priority = true, 41 .high_priority = true,
56 .dir = STEDMA40_PERIPH_TO_MEM, 42 .dir = DMA_DEV_TO_MEM,
57 43 .dev_type = DB8500_DMA_DEV30_MSP3,
58 .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
59 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
60
61 .src_info.psize = STEDMA40_PSIZE_LOG_4,
62 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
63
64 /* data_width is set during configuration */
65}; 44};
66 45
67static struct stedma40_chan_cfg msp1_dma_tx = { 46static struct stedma40_chan_cfg msp1_dma_tx = {
68 .high_priority = true, 47 .high_priority = true,
69 .dir = STEDMA40_MEM_TO_PERIPH, 48 .dir = DMA_MEM_TO_DEV,
70 49 .dev_type = DB8500_DMA_DEV30_MSP1,
71 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
72 .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
73
74 .src_info.psize = STEDMA40_PSIZE_LOG_4,
75 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
76
77 /* data_width is set during configuration */
78}; 50};
79 51
80struct msp_i2s_platform_data msp1_platform_data = { 52struct msp_i2s_platform_data msp1_platform_data = {
@@ -85,32 +57,16 @@ struct msp_i2s_platform_data msp1_platform_data = {
85 57
86static struct stedma40_chan_cfg msp2_dma_rx = { 58static struct stedma40_chan_cfg msp2_dma_rx = {
87 .high_priority = true, 59 .high_priority = true,
88 .dir = STEDMA40_PERIPH_TO_MEM, 60 .dir = DMA_DEV_TO_MEM,
89 61 .dev_type = DB8500_DMA_DEV14_MSP2,
90 .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
91 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
92
93 /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
94 .src_info.psize = STEDMA40_PSIZE_LOG_1,
95 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
96
97 /* data_width is set during configuration */
98}; 62};
99 63
100static struct stedma40_chan_cfg msp2_dma_tx = { 64static struct stedma40_chan_cfg msp2_dma_tx = {
101 .high_priority = true, 65 .high_priority = true,
102 .dir = STEDMA40_MEM_TO_PERIPH, 66 .dir = DMA_MEM_TO_DEV,
103 67 .dev_type = DB8500_DMA_DEV14_MSP2,
104 .src_dev_type = STEDMA40_DEV_DST_MEMORY,
105 .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
106
107 .src_info.psize = STEDMA40_PSIZE_LOG_4,
108 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
109
110 .use_fixed_channel = true, 68 .use_fixed_channel = true,
111 .phy_channel = 1, 69 .phy_channel = 1,
112
113 /* data_width is set during configuration */
114}; 70};
115 71
116static struct platform_device *db8500_add_msp_i2s(struct device *parent, 72static struct platform_device *db8500_add_msp_i2s(struct device *parent,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 43be3e0d4e30..b3e61a38e5c8 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -34,20 +34,14 @@
34#ifdef CONFIG_STE_DMA40 34#ifdef CONFIG_STE_DMA40
35struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { 35struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
36 .mode = STEDMA40_MODE_LOGICAL, 36 .mode = STEDMA40_MODE_LOGICAL,
37 .dir = STEDMA40_PERIPH_TO_MEM, 37 .dir = DMA_DEV_TO_MEM,
38 .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX, 38 .dev_type = DB8500_DMA_DEV29_SD_MM0,
39 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .src_info.data_width = STEDMA40_WORD_WIDTH,
41 .dst_info.data_width = STEDMA40_WORD_WIDTH,
42}; 39};
43 40
44static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { 41static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
45 .mode = STEDMA40_MODE_LOGICAL, 42 .mode = STEDMA40_MODE_LOGICAL,
46 .dir = STEDMA40_MEM_TO_PERIPH, 43 .dir = DMA_MEM_TO_DEV,
47 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 44 .dev_type = DB8500_DMA_DEV29_SD_MM0,
48 .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
49 .src_info.data_width = STEDMA40_WORD_WIDTH,
50 .dst_info.data_width = STEDMA40_WORD_WIDTH,
51}; 45};
52#endif 46#endif
53 47
@@ -89,20 +83,14 @@ void mop500_sdi_tc35892_init(struct device *parent)
89#ifdef CONFIG_STE_DMA40 83#ifdef CONFIG_STE_DMA40
90static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { 84static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
91 .mode = STEDMA40_MODE_LOGICAL, 85 .mode = STEDMA40_MODE_LOGICAL,
92 .dir = STEDMA40_PERIPH_TO_MEM, 86 .dir = DMA_DEV_TO_MEM,
93 .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX, 87 .dev_type = DB8500_DMA_DEV32_SD_MM1,
94 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
95 .src_info.data_width = STEDMA40_WORD_WIDTH,
96 .dst_info.data_width = STEDMA40_WORD_WIDTH,
97}; 88};
98 89
99static struct stedma40_chan_cfg sdi1_dma_cfg_tx = { 90static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
100 .mode = STEDMA40_MODE_LOGICAL, 91 .mode = STEDMA40_MODE_LOGICAL,
101 .dir = STEDMA40_MEM_TO_PERIPH, 92 .dir = DMA_MEM_TO_DEV,
102 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 93 .dev_type = DB8500_DMA_DEV32_SD_MM1,
103 .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
104 .src_info.data_width = STEDMA40_WORD_WIDTH,
105 .dst_info.data_width = STEDMA40_WORD_WIDTH,
106}; 94};
107#endif 95#endif
108 96
@@ -127,20 +115,14 @@ struct mmci_platform_data mop500_sdi1_data = {
127#ifdef CONFIG_STE_DMA40 115#ifdef CONFIG_STE_DMA40
128struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = { 116struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
129 .mode = STEDMA40_MODE_LOGICAL, 117 .mode = STEDMA40_MODE_LOGICAL,
130 .dir = STEDMA40_PERIPH_TO_MEM, 118 .dir = DMA_DEV_TO_MEM,
131 .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX, 119 .dev_type = DB8500_DMA_DEV28_SD_MM2,
132 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
133 .src_info.data_width = STEDMA40_WORD_WIDTH,
134 .dst_info.data_width = STEDMA40_WORD_WIDTH,
135}; 120};
136 121
137static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = { 122static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
138 .mode = STEDMA40_MODE_LOGICAL, 123 .mode = STEDMA40_MODE_LOGICAL,
139 .dir = STEDMA40_MEM_TO_PERIPH, 124 .dir = DMA_MEM_TO_DEV,
140 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 125 .dev_type = DB8500_DMA_DEV28_SD_MM2,
141 .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
142 .src_info.data_width = STEDMA40_WORD_WIDTH,
143 .dst_info.data_width = STEDMA40_WORD_WIDTH,
144}; 126};
145#endif 127#endif
146 128
@@ -169,20 +151,14 @@ struct mmci_platform_data mop500_sdi2_data = {
169#ifdef CONFIG_STE_DMA40 151#ifdef CONFIG_STE_DMA40
170struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = { 152struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
171 .mode = STEDMA40_MODE_LOGICAL, 153 .mode = STEDMA40_MODE_LOGICAL,
172 .dir = STEDMA40_PERIPH_TO_MEM, 154 .dir = DMA_DEV_TO_MEM,
173 .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX, 155 .dev_type = DB8500_DMA_DEV42_SD_MM4,
174 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
175 .src_info.data_width = STEDMA40_WORD_WIDTH,
176 .dst_info.data_width = STEDMA40_WORD_WIDTH,
177}; 156};
178 157
179static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { 158static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
180 .mode = STEDMA40_MODE_LOGICAL, 159 .mode = STEDMA40_MODE_LOGICAL,
181 .dir = STEDMA40_MEM_TO_PERIPH, 160 .dir = DMA_MEM_TO_DEV,
182 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 161 .dev_type = DB8500_DMA_DEV42_SD_MM4,
183 .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
184 .src_info.data_width = STEDMA40_WORD_WIDTH,
185 .dst_info.data_width = STEDMA40_WORD_WIDTH,
186}; 162};
187#endif 163#endif
188 164
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 78389de94dde..df5d27a532e9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -413,47 +413,23 @@ static void mop500_prox_deactivate(struct device *dev)
413 regulator_put(prox_regulator); 413 regulator_put(prox_regulator);
414} 414}
415 415
416void mop500_snowball_ethernet_clock_enable(void)
417{
418 struct clk *clk;
419
420 clk = clk_get_sys("fsmc", NULL);
421 if (!IS_ERR(clk))
422 clk_prepare_enable(clk);
423}
424
425static struct cryp_platform_data u8500_cryp1_platform_data = { 416static struct cryp_platform_data u8500_cryp1_platform_data = {
426 .mem_to_engine = { 417 .mem_to_engine = {
427 .dir = STEDMA40_MEM_TO_PERIPH, 418 .dir = DMA_MEM_TO_DEV,
428 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 419 .dev_type = DB8500_DMA_DEV48_CAC1,
429 .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
430 .src_info.data_width = STEDMA40_WORD_WIDTH,
431 .dst_info.data_width = STEDMA40_WORD_WIDTH,
432 .mode = STEDMA40_MODE_LOGICAL, 420 .mode = STEDMA40_MODE_LOGICAL,
433 .src_info.psize = STEDMA40_PSIZE_LOG_4,
434 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
435 }, 421 },
436 .engine_to_mem = { 422 .engine_to_mem = {
437 .dir = STEDMA40_PERIPH_TO_MEM, 423 .dir = DMA_DEV_TO_MEM,
438 .src_dev_type = DB8500_DMA_DEV48_CAC1_RX, 424 .dev_type = DB8500_DMA_DEV48_CAC1,
439 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
440 .src_info.data_width = STEDMA40_WORD_WIDTH,
441 .dst_info.data_width = STEDMA40_WORD_WIDTH,
442 .mode = STEDMA40_MODE_LOGICAL, 425 .mode = STEDMA40_MODE_LOGICAL,
443 .src_info.psize = STEDMA40_PSIZE_LOG_4,
444 .dst_info.psize = STEDMA40_PSIZE_LOG_4,
445 } 426 }
446}; 427};
447 428
448static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { 429static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
449 .dir = STEDMA40_MEM_TO_PERIPH, 430 .dir = DMA_MEM_TO_DEV,
450 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 431 .dev_type = DB8500_DMA_DEV50_HAC1_TX,
451 .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
452 .src_info.data_width = STEDMA40_WORD_WIDTH,
453 .dst_info.data_width = STEDMA40_WORD_WIDTH,
454 .mode = STEDMA40_MODE_LOGICAL, 432 .mode = STEDMA40_MODE_LOGICAL,
455 .src_info.psize = STEDMA40_PSIZE_LOG_16,
456 .dst_info.psize = STEDMA40_PSIZE_LOG_16,
457}; 433};
458 434
459static struct hash_platform_data u8500_hash1_platform_data = { 435static struct hash_platform_data u8500_hash1_platform_data = {
@@ -470,20 +446,14 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
470#ifdef CONFIG_STE_DMA40 446#ifdef CONFIG_STE_DMA40
471static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { 447static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
472 .mode = STEDMA40_MODE_LOGICAL, 448 .mode = STEDMA40_MODE_LOGICAL,
473 .dir = STEDMA40_PERIPH_TO_MEM, 449 .dir = DMA_DEV_TO_MEM,
474 .src_dev_type = DB8500_DMA_DEV8_SSP0_RX, 450 .dev_type = DB8500_DMA_DEV8_SSP0,
475 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
476 .src_info.data_width = STEDMA40_BYTE_WIDTH,
477 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
478}; 451};
479 452
480static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { 453static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
481 .mode = STEDMA40_MODE_LOGICAL, 454 .mode = STEDMA40_MODE_LOGICAL,
482 .dir = STEDMA40_MEM_TO_PERIPH, 455 .dir = DMA_MEM_TO_DEV,
483 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 456 .dev_type = DB8500_DMA_DEV8_SSP0,
484 .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
485 .src_info.data_width = STEDMA40_BYTE_WIDTH,
486 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
487}; 457};
488#endif 458#endif
489 459
@@ -511,56 +481,38 @@ static void __init mop500_spi_init(struct device *parent)
511#ifdef CONFIG_STE_DMA40 481#ifdef CONFIG_STE_DMA40
512static struct stedma40_chan_cfg uart0_dma_cfg_rx = { 482static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
513 .mode = STEDMA40_MODE_LOGICAL, 483 .mode = STEDMA40_MODE_LOGICAL,
514 .dir = STEDMA40_PERIPH_TO_MEM, 484 .dir = DMA_DEV_TO_MEM,
515 .src_dev_type = DB8500_DMA_DEV13_UART0_RX, 485 .dev_type = DB8500_DMA_DEV13_UART0,
516 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
517 .src_info.data_width = STEDMA40_BYTE_WIDTH,
518 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
519}; 486};
520 487
521static struct stedma40_chan_cfg uart0_dma_cfg_tx = { 488static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
522 .mode = STEDMA40_MODE_LOGICAL, 489 .mode = STEDMA40_MODE_LOGICAL,
523 .dir = STEDMA40_MEM_TO_PERIPH, 490 .dir = DMA_MEM_TO_DEV,
524 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 491 .dev_type = DB8500_DMA_DEV13_UART0,
525 .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
526 .src_info.data_width = STEDMA40_BYTE_WIDTH,
527 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
528}; 492};
529 493
530static struct stedma40_chan_cfg uart1_dma_cfg_rx = { 494static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
531 .mode = STEDMA40_MODE_LOGICAL, 495 .mode = STEDMA40_MODE_LOGICAL,
532 .dir = STEDMA40_PERIPH_TO_MEM, 496 .dir = DMA_DEV_TO_MEM,
533 .src_dev_type = DB8500_DMA_DEV12_UART1_RX, 497 .dev_type = DB8500_DMA_DEV12_UART1,
534 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
535 .src_info.data_width = STEDMA40_BYTE_WIDTH,
536 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
537}; 498};
538 499
539static struct stedma40_chan_cfg uart1_dma_cfg_tx = { 500static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
540 .mode = STEDMA40_MODE_LOGICAL, 501 .mode = STEDMA40_MODE_LOGICAL,
541 .dir = STEDMA40_MEM_TO_PERIPH, 502 .dir = DMA_MEM_TO_DEV,
542 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 503 .dev_type = DB8500_DMA_DEV12_UART1,
543 .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
544 .src_info.data_width = STEDMA40_BYTE_WIDTH,
545 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
546}; 504};
547 505
548static struct stedma40_chan_cfg uart2_dma_cfg_rx = { 506static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
549 .mode = STEDMA40_MODE_LOGICAL, 507 .mode = STEDMA40_MODE_LOGICAL,
550 .dir = STEDMA40_PERIPH_TO_MEM, 508 .dir = DMA_DEV_TO_MEM,
551 .src_dev_type = DB8500_DMA_DEV11_UART2_RX, 509 .dev_type = DB8500_DMA_DEV11_UART2,
552 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
553 .src_info.data_width = STEDMA40_BYTE_WIDTH,
554 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
555}; 510};
556 511
557static struct stedma40_chan_cfg uart2_dma_cfg_tx = { 512static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
558 .mode = STEDMA40_MODE_LOGICAL, 513 .mode = STEDMA40_MODE_LOGICAL,
559 .dir = STEDMA40_MEM_TO_PERIPH, 514 .dir = DMA_MEM_TO_DEV,
560 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, 515 .dev_type = DB8500_DMA_DEV11_UART2,
561 .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
562 .src_info.data_width = STEDMA40_BYTE_WIDTH,
563 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
564}; 516};
565#endif 517#endif
566 518
@@ -674,7 +626,7 @@ static void __init snowball_init_machine(void)
674 mop500_audio_init(parent); 626 mop500_audio_init(parent);
675 mop500_uart_init(parent); 627 mop500_uart_init(parent);
676 628
677 mop500_snowball_ethernet_clock_enable(); 629 u8500_cryp1_hash1_init(parent);
678 630
679 /* This board has full regulator constraints */ 631 /* This board has full regulator constraints */
680 regulator_has_full_constraints(); 632 regulator_has_full_constraints();
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 49514b825034..d6fab166cbf1 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat;
93extern struct amba_pl011_data uart1_plat; 93extern struct amba_pl011_data uart1_plat;
94extern struct amba_pl011_data uart2_plat; 94extern struct amba_pl011_data uart2_plat;
95extern struct pl022_ssp_controller ssp0_plat; 95extern struct pl022_ssp_controller ssp0_plat;
96extern struct stedma40_platform_data dma40_plat_data;
96 97
97extern void mop500_sdi_init(struct device *parent); 98extern void mop500_sdi_init(struct device *parent);
98extern void snowball_sdi_init(struct device *parent); 99extern void snowball_sdi_init(struct device *parent);
@@ -104,7 +105,6 @@ void __init mop500_pinmaps_init(void);
104void __init snowball_pinmaps_init(void); 105void __init snowball_pinmaps_init(void);
105void __init hrefv60_pinmaps_init(void); 106void __init hrefv60_pinmaps_init(void);
106void mop500_audio_init(struct device *parent); 107void mop500_audio_init(struct device *parent);
107void mop500_snowball_ethernet_clock_enable(void);
108 108
109int __init mop500_uib_init(void); 109int __init mop500_uib_init(void);
110void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 110void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7669a49fb6fb..12eee8167525 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -162,26 +162,15 @@ static void __init db8500_add_gpios(struct device *parent)
162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); 162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
163} 163}
164 164
165static int usb_db8500_rx_dma_cfg[] = { 165static int usb_db8500_dma_cfg[] = {
166 DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 166 DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
167 DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 167 DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
168 DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 168 DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
169 DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 169 DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
170 DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 170 DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
171 DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 171 DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
172 DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 172 DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
173 DB8500_DMA_DEV39_USB_OTG_IEP_8 173 DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
174};
175
176static int usb_db8500_tx_dma_cfg[] = {
177 DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
178 DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
179 DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
180 DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
181 DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
182 DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
183 DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
184 DB8500_DMA_DEV39_USB_OTG_OEP_8
185}; 174};
186 175
187static const char *db8500_read_soc_id(void) 176static const char *db8500_read_soc_id(void)
@@ -215,7 +204,7 @@ struct device * __init u8500_init_devices(void)
215 204
216 db8500_add_rtc(parent); 205 db8500_add_rtc(parent);
217 db8500_add_gpios(parent); 206 db8500_add_gpios(parent);
218 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 207 db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
219 208
220 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) 209 for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
221 platform_devs[i]->dev.parent = parent; 210 platform_devs[i]->dev.parent = parent;
@@ -226,34 +215,13 @@ struct device * __init u8500_init_devices(void)
226} 215}
227 216
228#ifdef CONFIG_MACH_UX500_DT 217#ifdef CONFIG_MACH_UX500_DT
229
230/* TODO: Once all pieces are DT:ed, remove completely. */
231static struct device * __init u8500_of_init_devices(void)
232{
233 struct device *parent = db8500_soc_device_init();
234
235 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
236
237 u8500_dma40_device.dev.parent = parent;
238
239 /*
240 * Devices to be DT:ed:
241 * u8500_dma40_device = todo
242 * db8500_pmu_device = done
243 * db8500_prcmu_device = done
244 */
245 platform_device_register(&u8500_dma40_device);
246
247 return parent;
248}
249
250static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 218static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
251 /* Requires call-back bindings. */ 219 /* Requires call-back bindings. */
252 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), 220 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
253 /* Requires DMA bindings. */ 221 /* Requires DMA bindings. */
254 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 222 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
255 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 223 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
256 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 224 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
257 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 225 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
258 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), 226 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
259 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), 227 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
@@ -294,6 +262,8 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
294 "ux500-msp-i2s.2", &msp2_platform_data), 262 "ux500-msp-i2s.2", &msp2_platform_data),
295 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, 263 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
296 "ux500-msp-i2s.3", &msp3_platform_data), 264 "ux500-msp-i2s.3", &msp3_platform_data),
265 /* Requires clock name bindings and channel address lookup table. */
266 OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
297 {}, 267 {},
298}; 268};
299 269
@@ -317,22 +287,18 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
317 287
318static void __init u8500_init_machine(void) 288static void __init u8500_init_machine(void)
319{ 289{
320 struct device *parent = NULL; 290 struct device *parent = db8500_soc_device_init();
321 291
322 /* Pinmaps must be in place before devices register */ 292 /* Pinmaps must be in place before devices register */
323 if (of_machine_is_compatible("st-ericsson,mop500")) 293 if (of_machine_is_compatible("st-ericsson,mop500"))
324 mop500_pinmaps_init(); 294 mop500_pinmaps_init();
325 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { 295 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
326 snowball_pinmaps_init(); 296 snowball_pinmaps_init();
327 mop500_snowball_ethernet_clock_enable();
328 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) 297 } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
329 hrefv60_pinmaps_init(); 298 hrefv60_pinmaps_init();
330 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} 299 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
331 /* TODO: Add pinmaps for ccu9540 board. */ 300 /* TODO: Add pinmaps for ccu9540 board. */
332 301
333 /* TODO: Export SoC, USB, cpu-freq and DMA40 */
334 parent = u8500_of_init_devices();
335
336 /* automatically probe child nodes of dbx5x0 devices */ 302 /* automatically probe child nodes of dbx5x0 devices */
337 if (of_machine_is_compatible("st-ericsson,u8540")) 303 if (of_machine_is_compatible("st-ericsson,u8540"))
338 of_platform_populate(NULL, u8500_local_bus_nodes, 304 of_platform_populate(NULL, u8500_local_bus_nodes,
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index ddbdcda8306a..516a6f57d159 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
42 } 42 }
43}; 43};
44 44
45/* Default configuration for physcial memcpy */ 45struct stedma40_platform_data dma40_plat_data = {
46struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
47 .mode = STEDMA40_MODE_PHYSICAL,
48 .dir = STEDMA40_MEM_TO_MEM,
49
50 .src_info.data_width = STEDMA40_BYTE_WIDTH,
51 .src_info.psize = STEDMA40_PSIZE_PHY_1,
52 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
53
54 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
55 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
56 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
57};
58/* Default configuration for logical memcpy */
59struct stedma40_chan_cfg dma40_memcpy_conf_log = {
60 .dir = STEDMA40_MEM_TO_MEM,
61
62 .src_info.data_width = STEDMA40_BYTE_WIDTH,
63 .src_info.psize = STEDMA40_PSIZE_LOG_1,
64 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
65
66 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
67 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
68 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
69};
70
71/*
72 * Mapping between destination event lines and physical device address.
73 * The event line is tied to a device and therefore the address is constant.
74 * When the address comes from a primecell it will be configured in runtime
75 * and we set the address to -1 as a placeholder.
76 */
77static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
78 /* MUSB - these will be runtime-reconfigured */
79 [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
80 [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
81 [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
82 [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
83 [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
84 [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
85 [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
86 [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
87 /* PrimeCells - run-time configured */
88 [DB8500_DMA_DEV0_SPI0_TX] = -1,
89 [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
90 [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
91 [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
92 [DB8500_DMA_DEV8_SSP0_TX] = -1,
93 [DB8500_DMA_DEV9_SSP1_TX] = -1,
94 [DB8500_DMA_DEV11_UART2_TX] = -1,
95 [DB8500_DMA_DEV12_UART1_TX] = -1,
96 [DB8500_DMA_DEV13_UART0_TX] = -1,
97 [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
98 [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
99 [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
100 [DB8500_DMA_DEV33_SPI2_TX] = -1,
101 [DB8500_DMA_DEV35_SPI1_TX] = -1,
102 [DB8500_DMA_DEV40_SPI3_TX] = -1,
103 [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
104 [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
105 [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
106 [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
107 [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
108 [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
109 [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
110 [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
111};
112
113/* Mapping between source event lines and physical device address */
114static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
115 /* MUSB - these will be runtime-reconfigured */
116 [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
117 [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
118 [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
119 [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
120 [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
121 [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
122 [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
123 [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
124 /* PrimeCells */
125 [DB8500_DMA_DEV0_SPI0_RX] = -1,
126 [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
127 [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
128 [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
129 [DB8500_DMA_DEV8_SSP0_RX] = -1,
130 [DB8500_DMA_DEV9_SSP1_RX] = -1,
131 [DB8500_DMA_DEV11_UART2_RX] = -1,
132 [DB8500_DMA_DEV12_UART1_RX] = -1,
133 [DB8500_DMA_DEV13_UART0_RX] = -1,
134 [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
135 [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
136 [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
137 [DB8500_DMA_DEV33_SPI2_RX] = -1,
138 [DB8500_DMA_DEV35_SPI1_RX] = -1,
139 [DB8500_DMA_DEV40_SPI3_RX] = -1,
140 [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
141 [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
142 [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
143 [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
144 [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
145 [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
146 [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
147};
148
149/* Reserved event lines for memcpy only */
150static int dma40_memcpy_event[] = {
151 DB8500_DMA_MEMCPY_TX_0,
152 DB8500_DMA_MEMCPY_TX_1,
153 DB8500_DMA_MEMCPY_TX_2,
154 DB8500_DMA_MEMCPY_TX_3,
155 DB8500_DMA_MEMCPY_TX_4,
156 DB8500_DMA_MEMCPY_TX_5,
157};
158
159static struct stedma40_platform_data dma40_plat_data = {
160 .dev_len = DB8500_DMA_NR_DEV,
161 .dev_rx = dma40_rx_map,
162 .dev_tx = dma40_tx_map,
163 .memcpy = dma40_memcpy_event,
164 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
165 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
166 .memcpy_conf_log = &dma40_memcpy_conf_log,
167 .disabled_channels = {-1}, 46 .disabled_channels = {-1},
168}; 47};
169 48
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index a616419bea76..0296ae5b0fd9 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -12,133 +12,74 @@
12 12
13#define DB8500_DMA_NR_DEV 64 13#define DB8500_DMA_NR_DEV 64
14 14
15enum dma_src_dev_type { 15/*
16 DB8500_DMA_DEV0_SPI0_RX = 0, 16 * Unless otherwise specified, all channels numbers are used for
17 DB8500_DMA_DEV1_SD_MMC0_RX = 1, 17 * TX & RX, and can be used for either source or destination
18 DB8500_DMA_DEV2_SD_MMC1_RX = 2, 18 * channels.
19 DB8500_DMA_DEV3_SD_MMC2_RX = 3, 19 */
20 DB8500_DMA_DEV4_I2C1_RX = 4, 20enum dma_dev_type {
21 DB8500_DMA_DEV5_I2C3_RX = 5, 21 DB8500_DMA_DEV0_SPI0 = 0,
22 DB8500_DMA_DEV6_I2C2_RX = 6, 22 DB8500_DMA_DEV1_SD_MMC0 = 1,
23 DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */ 23 DB8500_DMA_DEV2_SD_MMC1 = 2,
24 DB8500_DMA_DEV8_SSP0_RX = 8, 24 DB8500_DMA_DEV3_SD_MMC2 = 3,
25 DB8500_DMA_DEV9_SSP1_RX = 9, 25 DB8500_DMA_DEV4_I2C1 = 4,
26 DB8500_DMA_DEV10_MCDE_RX = 10, 26 DB8500_DMA_DEV5_I2C3 = 5,
27 DB8500_DMA_DEV11_UART2_RX = 11, 27 DB8500_DMA_DEV6_I2C2 = 6,
28 DB8500_DMA_DEV12_UART1_RX = 12, 28 DB8500_DMA_DEV7_I2C4 = 7, /* Only on V1 and later */
29 DB8500_DMA_DEV13_UART0_RX = 13, 29 DB8500_DMA_DEV8_SSP0 = 8,
30 DB8500_DMA_DEV14_MSP2_RX = 14, 30 DB8500_DMA_DEV9_SSP1 = 9,
31 DB8500_DMA_DEV15_I2C0_RX = 15, 31 DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */
32 DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16, 32 DB8500_DMA_DEV11_UART2 = 11,
33 DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17, 33 DB8500_DMA_DEV12_UART1 = 12,
34 DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18, 34 DB8500_DMA_DEV13_UART0 = 13,
35 DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19, 35 DB8500_DMA_DEV14_MSP2 = 14,
36 DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20, 36 DB8500_DMA_DEV15_I2C0 = 15,
37 DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21, 37 DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
38 DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22, 38 DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
39 DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23, 39 DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
40 DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24, 40 DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
41 DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25, 41 DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
42 DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26, 42 DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
43 DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27, 43 DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
44 DB8500_DMA_DEV28_SD_MM2_RX = 28, 44 DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
45 DB8500_DMA_DEV29_SD_MM0_RX = 29, 45 DB8500_DMA_DEV24_SXA0 = 24,
46 DB8500_DMA_DEV30_MSP1_RX = 30, 46 DB8500_DMA_DEV25_SXA1 = 25,
47 DB8500_DMA_DEV26_SXA2 = 26,
48 DB8500_DMA_DEV27_SXA3 = 27,
49 DB8500_DMA_DEV28_SD_MM2 = 28,
50 DB8500_DMA_DEV29_SD_MM0 = 29,
51 DB8500_DMA_DEV30_MSP1 = 30,
47 /* On DB8500v2, MSP3 RX replaces MSP1 RX */ 52 /* On DB8500v2, MSP3 RX replaces MSP1 RX */
48 DB8500_DMA_DEV30_MSP3_RX = 30, 53 DB8500_DMA_DEV30_MSP3 = 30,
49 DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31, 54 DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
50 DB8500_DMA_DEV32_SD_MM1_RX = 32, 55 DB8500_DMA_DEV32_SD_MM1 = 32,
51 DB8500_DMA_DEV33_SPI2_RX = 33, 56 DB8500_DMA_DEV33_SPI2 = 33,
52 DB8500_DMA_DEV34_I2C3_RX2 = 34, 57 DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
53 DB8500_DMA_DEV35_SPI1_RX = 35, 58 DB8500_DMA_DEV35_SPI1 = 35,
54 DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36, 59 DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
55 DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37, 60 DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
56 DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38, 61 DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
57 DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39, 62 DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
58 DB8500_DMA_DEV40_SPI3_RX = 40, 63 DB8500_DMA_DEV40_SPI3 = 40,
59 DB8500_DMA_DEV41_SD_MM3_RX = 41, 64 DB8500_DMA_DEV41_SD_MM3 = 41,
60 DB8500_DMA_DEV42_SD_MM4_RX = 42, 65 DB8500_DMA_DEV42_SD_MM4 = 42,
61 DB8500_DMA_DEV43_SD_MM5_RX = 43, 66 DB8500_DMA_DEV43_SD_MM5 = 43,
62 DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44, 67 DB8500_DMA_DEV44_SXA4 = 44,
63 DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45, 68 DB8500_DMA_DEV45_SXA5 = 45,
64 DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46, 69 DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
65 DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47, 70 DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
66 DB8500_DMA_DEV48_CAC1_RX = 48, 71 DB8500_DMA_DEV48_CAC1 = 48,
67 /* 49, 50 and 51 are not used */ 72 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */
68 DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52, 73 DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */
69 DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53, 74 DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */
70 DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54, 75 DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
71 DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55, 76 DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
72 /* 56, 57, 58, 59 and 60 are not used */ 77 DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
73 DB8500_DMA_DEV61_CAC0_RX = 61, 78 DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
74 /* 62 and 63 are not used */ 79 /* 56 -> 60 are channels reserved for memcpy only */
75}; 80 DB8500_DMA_DEV61_CAC0 = 61,
76 81 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */
77enum dma_dest_dev_type { 82 DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */
78 DB8500_DMA_DEV0_SPI0_TX = 0,
79 DB8500_DMA_DEV1_SD_MMC0_TX = 1,
80 DB8500_DMA_DEV2_SD_MMC1_TX = 2,
81 DB8500_DMA_DEV3_SD_MMC2_TX = 3,
82 DB8500_DMA_DEV4_I2C1_TX = 4,
83 DB8500_DMA_DEV5_I2C3_TX = 5,
84 DB8500_DMA_DEV6_I2C2_TX = 6,
85 DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
86 DB8500_DMA_DEV8_SSP0_TX = 8,
87 DB8500_DMA_DEV9_SSP1_TX = 9,
88 /* 10 is not used*/
89 DB8500_DMA_DEV11_UART2_TX = 11,
90 DB8500_DMA_DEV12_UART1_TX = 12,
91 DB8500_DMA_DEV13_UART0_TX = 13,
92 DB8500_DMA_DEV14_MSP2_TX = 14,
93 DB8500_DMA_DEV15_I2C0_TX = 15,
94 DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
95 DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
96 DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
97 DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
98 DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
99 DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
100 DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
101 DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
102 DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
103 DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
104 DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
105 DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
106 DB8500_DMA_DEV28_SD_MM2_TX = 28,
107 DB8500_DMA_DEV29_SD_MM0_TX = 29,
108 DB8500_DMA_DEV30_MSP1_TX = 30,
109 DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
110 DB8500_DMA_DEV32_SD_MM1_TX = 32,
111 DB8500_DMA_DEV33_SPI2_TX = 33,
112 DB8500_DMA_DEV34_I2C3_TX2 = 34,
113 DB8500_DMA_DEV35_SPI1_TX = 35,
114 DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
115 DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
116 DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
117 DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
118 DB8500_DMA_DEV40_SPI3_TX = 40,
119 DB8500_DMA_DEV41_SD_MM3_TX = 41,
120 DB8500_DMA_DEV42_SD_MM4_TX = 42,
121 DB8500_DMA_DEV43_SD_MM5_TX = 43,
122 DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
123 DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
124 DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
125 DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
126 DB8500_DMA_DEV48_CAC1_TX = 48,
127 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
128 DB8500_DMA_DEV50_HAC1_TX = 50,
129 DB8500_DMA_MEMCPY_TX_0 = 51,
130 DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
131 DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
132 DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
133 DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
134 DB8500_DMA_MEMCPY_TX_1 = 56,
135 DB8500_DMA_MEMCPY_TX_2 = 57,
136 DB8500_DMA_MEMCPY_TX_3 = 58,
137 DB8500_DMA_MEMCPY_TX_4 = 59,
138 DB8500_DMA_MEMCPY_TX_5 = 60,
139 DB8500_DMA_DEV61_CAC0_TX = 61,
140 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
141 DB8500_DMA_DEV63_HAC0_TX = 63,
142}; 83};
143 84
144#endif 85#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2dfc72f7cd8a..b7bd8d3a5507 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -14,25 +14,15 @@
14 14
15#define MUSB_DMA40_RX_CH { \ 15#define MUSB_DMA40_RX_CH { \
16 .mode = STEDMA40_MODE_LOGICAL, \ 16 .mode = STEDMA40_MODE_LOGICAL, \
17 .dir = STEDMA40_PERIPH_TO_MEM, \ 17 .dir = DMA_DEV_TO_MEM, \
18 .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
19 .src_info.data_width = STEDMA40_WORD_WIDTH, \
20 .dst_info.data_width = STEDMA40_WORD_WIDTH, \
21 .src_info.psize = STEDMA40_PSIZE_LOG_16, \
22 .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
23 } 18 }
24 19
25#define MUSB_DMA40_TX_CH { \ 20#define MUSB_DMA40_TX_CH { \
26 .mode = STEDMA40_MODE_LOGICAL, \ 21 .mode = STEDMA40_MODE_LOGICAL, \
27 .dir = STEDMA40_MEM_TO_PERIPH, \ 22 .dir = DMA_MEM_TO_DEV, \
28 .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
29 .src_info.data_width = STEDMA40_WORD_WIDTH, \
30 .dst_info.data_width = STEDMA40_WORD_WIDTH, \
31 .src_info.psize = STEDMA40_PSIZE_LOG_16, \
32 .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
33 } 23 }
34 24
35static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS] 25static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
36 = { 26 = {
37 MUSB_DMA40_RX_CH, 27 MUSB_DMA40_RX_CH,
38 MUSB_DMA40_RX_CH, 28 MUSB_DMA40_RX_CH,
@@ -44,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
44 MUSB_DMA40_RX_CH 34 MUSB_DMA40_RX_CH
45}; 35};
46 36
47static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS] 37static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
48 = { 38 = {
49 MUSB_DMA40_TX_CH, 39 MUSB_DMA40_TX_CH,
50 MUSB_DMA40_TX_CH, 40 MUSB_DMA40_TX_CH,
@@ -56,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
56 MUSB_DMA40_TX_CH, 46 MUSB_DMA40_TX_CH,
57}; 47};
58 48
59static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = { 49static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
60 &musb_dma_rx_ch[0], 50 &musb_dma_rx_ch[0],
61 &musb_dma_rx_ch[1], 51 &musb_dma_rx_ch[1],
62 &musb_dma_rx_ch[2], 52 &musb_dma_rx_ch[2],
@@ -67,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
67 &musb_dma_rx_ch[7] 57 &musb_dma_rx_ch[7]
68}; 58};
69 59
70static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = { 60static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
71 &musb_dma_tx_ch[0], 61 &musb_dma_tx_ch[0],
72 &musb_dma_tx_ch[1], 62 &musb_dma_tx_ch[1],
73 &musb_dma_tx_ch[2], 63 &musb_dma_tx_ch[2],
@@ -81,23 +71,11 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
81static struct ux500_musb_board_data musb_board_data = { 71static struct ux500_musb_board_data musb_board_data = {
82 .dma_rx_param_array = ux500_dma_rx_param_array, 72 .dma_rx_param_array = ux500_dma_rx_param_array,
83 .dma_tx_param_array = ux500_dma_tx_param_array, 73 .dma_tx_param_array = ux500_dma_tx_param_array,
84 .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
85 .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
86 .dma_filter = stedma40_filter, 74 .dma_filter = stedma40_filter,
87}; 75};
88 76
89static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
90
91static struct musb_hdrc_config musb_hdrc_config = {
92 .multipoint = true,
93 .dyn_fifo = true,
94 .num_eps = 16,
95 .ram_bits = 16,
96};
97
98static struct musb_hdrc_platform_data musb_platform_data = { 77static struct musb_hdrc_platform_data musb_platform_data = {
99 .mode = MUSB_OTG, 78 .mode = MUSB_OTG,
100 .config = &musb_hdrc_config,
101 .board_data = &musb_board_data, 79 .board_data = &musb_board_data,
102}; 80};
103 81
@@ -118,27 +96,26 @@ struct platform_device ux500_musb_device = {
118 .id = 0, 96 .id = 0,
119 .dev = { 97 .dev = {
120 .platform_data = &musb_platform_data, 98 .platform_data = &musb_platform_data,
121 .dma_mask = &ux500_musb_dmamask,
122 .coherent_dma_mask = DMA_BIT_MASK(32), 99 .coherent_dma_mask = DMA_BIT_MASK(32),
123 }, 100 },
124 .num_resources = ARRAY_SIZE(usb_resources), 101 .num_resources = ARRAY_SIZE(usb_resources),
125 .resource = usb_resources, 102 .resource = usb_resources,
126}; 103};
127 104
128static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type) 105static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
129{ 106{
130 u32 idx; 107 u32 idx;
131 108
132 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++) 109 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
133 musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx]; 110 musb_dma_rx_ch[idx].dev_type = dev_type[idx];
134} 111}
135 112
136static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type) 113static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
137{ 114{
138 u32 idx; 115 u32 idx;
139 116
140 for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++) 117 for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
141 musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx]; 118 musb_dma_tx_ch[idx].dev_type = dev_type[idx];
142} 119}
143 120
144void ux500_add_usb(struct device *parent, resource_size_t base, int irq, 121void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ce66eb9be481..f82bae2171eb 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -86,22 +86,6 @@ config OMAP_MUX_WARNINGS
86 to change the pin multiplexing setup. When there are no warnings 86 to change the pin multiplexing setup. When there are no warnings
87 printed, it's safe to deselect OMAP_MUX for your product. 87 printed, it's safe to deselect OMAP_MUX for your product.
88 88
89config OMAP_MBOX_FWK
90 tristate "Mailbox framework support"
91 depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
92 help
93 Say Y here if you want to use OMAP Mailbox framework support for
94 DSP, IVA1.0 and IVA2 in OMAP1/2/3.
95
96config OMAP_MBOX_KFIFO_SIZE
97 int "Mailbox kfifo default buffer size (bytes)"
98 depends on OMAP_MBOX_FWK
99 default 256
100 help
101 Specify the default size of mailbox's kfifo buffers (bytes).
102 This can also be changed at runtime (via the mbox_kfifo_size
103 module parameter).
104
105config OMAP_IOMMU_IVA2 89config OMAP_IOMMU_IVA2
106 bool 90 bool
107 91
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 31199417b56a..0b01b68fd033 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -17,6 +17,3 @@ obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
17i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o 17i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
18obj-y += $(i2c-omap-m) $(i2c-omap-y) 18obj-y += $(i2c-omap-m) $(i2c-omap-y)
19 19
20# OMAP mailbox framework
21obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
22
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
deleted file mode 100644
index cc3921e9059c..000000000000
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/* mailbox.h */
2
3#ifndef MAILBOX_H
4#define MAILBOX_H
5
6#include <linux/spinlock.h>
7#include <linux/workqueue.h>
8#include <linux/interrupt.h>
9#include <linux/device.h>
10#include <linux/kfifo.h>
11
12typedef u32 mbox_msg_t;
13struct omap_mbox;
14
15typedef int __bitwise omap_mbox_irq_t;
16#define IRQ_TX ((__force omap_mbox_irq_t) 1)
17#define IRQ_RX ((__force omap_mbox_irq_t) 2)
18
19typedef int __bitwise omap_mbox_type_t;
20#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
21#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
22
23struct omap_mbox_ops {
24 omap_mbox_type_t type;
25 int (*startup)(struct omap_mbox *mbox);
26 void (*shutdown)(struct omap_mbox *mbox);
27 /* fifo */
28 mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
29 void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
30 int (*fifo_empty)(struct omap_mbox *mbox);
31 int (*fifo_full)(struct omap_mbox *mbox);
32 /* irq */
33 void (*enable_irq)(struct omap_mbox *mbox,
34 omap_mbox_irq_t irq);
35 void (*disable_irq)(struct omap_mbox *mbox,
36 omap_mbox_irq_t irq);
37 void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
38 int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
39 /* ctx */
40 void (*save_ctx)(struct omap_mbox *mbox);
41 void (*restore_ctx)(struct omap_mbox *mbox);
42};
43
44struct omap_mbox_queue {
45 spinlock_t lock;
46 struct kfifo fifo;
47 struct work_struct work;
48 struct tasklet_struct tasklet;
49 struct omap_mbox *mbox;
50 bool full;
51};
52
53struct omap_mbox {
54 char *name;
55 unsigned int irq;
56 struct omap_mbox_queue *txq, *rxq;
57 struct omap_mbox_ops *ops;
58 struct device *dev;
59 void *priv;
60 int use_count;
61 struct blocking_notifier_head notifier;
62};
63
64int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
65void omap_mbox_init_seq(struct omap_mbox *);
66
67struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
68void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
69
70int omap_mbox_register(struct device *parent, struct omap_mbox **);
71int omap_mbox_unregister(void);
72
73static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
74{
75 if (!mbox->ops->save_ctx) {
76 dev_err(mbox->dev, "%s:\tno save\n", __func__);
77 return;
78 }
79
80 mbox->ops->save_ctx(mbox);
81}
82
83static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
84{
85 if (!mbox->ops->restore_ctx) {
86 dev_err(mbox->dev, "%s:\tno restore\n", __func__);
87 return;
88 }
89
90 mbox->ops->restore_ctx(mbox);
91}
92
93static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
94 omap_mbox_irq_t irq)
95{
96 mbox->ops->enable_irq(mbox, irq);
97}
98
99static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
100 omap_mbox_irq_t irq)
101{
102 mbox->ops->disable_irq(mbox, irq);
103}
104
105#endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
deleted file mode 100644
index 42377ef9ea3d..000000000000
--- a/arch/arm/plat-omap/mailbox.c
+++ /dev/null
@@ -1,435 +0,0 @@
1/*
2 * OMAP mailbox driver
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
5 *
6 * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/interrupt.h>
25#include <linux/spinlock.h>
26#include <linux/mutex.h>
27#include <linux/delay.h>
28#include <linux/slab.h>
29#include <linux/kfifo.h>
30#include <linux/err.h>
31#include <linux/notifier.h>
32#include <linux/module.h>
33
34#include <plat/mailbox.h>
35
36static struct omap_mbox **mboxes;
37
38static int mbox_configured;
39static DEFINE_MUTEX(mbox_configured_lock);
40
41static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
42module_param(mbox_kfifo_size, uint, S_IRUGO);
43MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
44
45/* Mailbox FIFO handle functions */
46static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
47{
48 return mbox->ops->fifo_read(mbox);
49}
50static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
51{
52 mbox->ops->fifo_write(mbox, msg);
53}
54static inline int mbox_fifo_empty(struct omap_mbox *mbox)
55{
56 return mbox->ops->fifo_empty(mbox);
57}
58static inline int mbox_fifo_full(struct omap_mbox *mbox)
59{
60 return mbox->ops->fifo_full(mbox);
61}
62
63/* Mailbox IRQ handle functions */
64static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
65{
66 if (mbox->ops->ack_irq)
67 mbox->ops->ack_irq(mbox, irq);
68}
69static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
70{
71 return mbox->ops->is_irq(mbox, irq);
72}
73
74/*
75 * message sender
76 */
77static int __mbox_poll_for_space(struct omap_mbox *mbox)
78{
79 int ret = 0, i = 1000;
80
81 while (mbox_fifo_full(mbox)) {
82 if (mbox->ops->type == OMAP_MBOX_TYPE2)
83 return -1;
84 if (--i == 0)
85 return -1;
86 udelay(1);
87 }
88 return ret;
89}
90
91int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
92{
93 struct omap_mbox_queue *mq = mbox->txq;
94 int ret = 0, len;
95
96 spin_lock_bh(&mq->lock);
97
98 if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
99 ret = -ENOMEM;
100 goto out;
101 }
102
103 if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
104 mbox_fifo_write(mbox, msg);
105 goto out;
106 }
107
108 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
109 WARN_ON(len != sizeof(msg));
110
111 tasklet_schedule(&mbox->txq->tasklet);
112
113out:
114 spin_unlock_bh(&mq->lock);
115 return ret;
116}
117EXPORT_SYMBOL(omap_mbox_msg_send);
118
119static void mbox_tx_tasklet(unsigned long tx_data)
120{
121 struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
122 struct omap_mbox_queue *mq = mbox->txq;
123 mbox_msg_t msg;
124 int ret;
125
126 while (kfifo_len(&mq->fifo)) {
127 if (__mbox_poll_for_space(mbox)) {
128 omap_mbox_enable_irq(mbox, IRQ_TX);
129 break;
130 }
131
132 ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
133 sizeof(msg));
134 WARN_ON(ret != sizeof(msg));
135
136 mbox_fifo_write(mbox, msg);
137 }
138}
139
140/*
141 * Message receiver(workqueue)
142 */
143static void mbox_rx_work(struct work_struct *work)
144{
145 struct omap_mbox_queue *mq =
146 container_of(work, struct omap_mbox_queue, work);
147 mbox_msg_t msg;
148 int len;
149
150 while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
151 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
152 WARN_ON(len != sizeof(msg));
153
154 blocking_notifier_call_chain(&mq->mbox->notifier, len,
155 (void *)msg);
156 spin_lock_irq(&mq->lock);
157 if (mq->full) {
158 mq->full = false;
159 omap_mbox_enable_irq(mq->mbox, IRQ_RX);
160 }
161 spin_unlock_irq(&mq->lock);
162 }
163}
164
165/*
166 * Mailbox interrupt handler
167 */
168static void __mbox_tx_interrupt(struct omap_mbox *mbox)
169{
170 omap_mbox_disable_irq(mbox, IRQ_TX);
171 ack_mbox_irq(mbox, IRQ_TX);
172 tasklet_schedule(&mbox->txq->tasklet);
173}
174
175static void __mbox_rx_interrupt(struct omap_mbox *mbox)
176{
177 struct omap_mbox_queue *mq = mbox->rxq;
178 mbox_msg_t msg;
179 int len;
180
181 while (!mbox_fifo_empty(mbox)) {
182 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
183 omap_mbox_disable_irq(mbox, IRQ_RX);
184 mq->full = true;
185 goto nomem;
186 }
187
188 msg = mbox_fifo_read(mbox);
189
190 len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
191 WARN_ON(len != sizeof(msg));
192
193 if (mbox->ops->type == OMAP_MBOX_TYPE1)
194 break;
195 }
196
197 /* no more messages in the fifo. clear IRQ source. */
198 ack_mbox_irq(mbox, IRQ_RX);
199nomem:
200 schedule_work(&mbox->rxq->work);
201}
202
203static irqreturn_t mbox_interrupt(int irq, void *p)
204{
205 struct omap_mbox *mbox = p;
206
207 if (is_mbox_irq(mbox, IRQ_TX))
208 __mbox_tx_interrupt(mbox);
209
210 if (is_mbox_irq(mbox, IRQ_RX))
211 __mbox_rx_interrupt(mbox);
212
213 return IRQ_HANDLED;
214}
215
216static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
217 void (*work) (struct work_struct *),
218 void (*tasklet)(unsigned long))
219{
220 struct omap_mbox_queue *mq;
221
222 mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
223 if (!mq)
224 return NULL;
225
226 spin_lock_init(&mq->lock);
227
228 if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
229 goto error;
230
231 if (work)
232 INIT_WORK(&mq->work, work);
233
234 if (tasklet)
235 tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
236 return mq;
237error:
238 kfree(mq);
239 return NULL;
240}
241
242static void mbox_queue_free(struct omap_mbox_queue *q)
243{
244 kfifo_free(&q->fifo);
245 kfree(q);
246}
247
248static int omap_mbox_startup(struct omap_mbox *mbox)
249{
250 int ret = 0;
251 struct omap_mbox_queue *mq;
252
253 mutex_lock(&mbox_configured_lock);
254 if (!mbox_configured++) {
255 if (likely(mbox->ops->startup)) {
256 ret = mbox->ops->startup(mbox);
257 if (unlikely(ret))
258 goto fail_startup;
259 } else
260 goto fail_startup;
261 }
262
263 if (!mbox->use_count++) {
264 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
265 mbox->name, mbox);
266 if (unlikely(ret)) {
267 pr_err("failed to register mailbox interrupt:%d\n",
268 ret);
269 goto fail_request_irq;
270 }
271 mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
272 if (!mq) {
273 ret = -ENOMEM;
274 goto fail_alloc_txq;
275 }
276 mbox->txq = mq;
277
278 mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
279 if (!mq) {
280 ret = -ENOMEM;
281 goto fail_alloc_rxq;
282 }
283 mbox->rxq = mq;
284 mq->mbox = mbox;
285
286 omap_mbox_enable_irq(mbox, IRQ_RX);
287 }
288 mutex_unlock(&mbox_configured_lock);
289 return 0;
290
291fail_alloc_rxq:
292 mbox_queue_free(mbox->txq);
293fail_alloc_txq:
294 free_irq(mbox->irq, mbox);
295fail_request_irq:
296 if (mbox->ops->shutdown)
297 mbox->ops->shutdown(mbox);
298 mbox->use_count--;
299fail_startup:
300 mbox_configured--;
301 mutex_unlock(&mbox_configured_lock);
302 return ret;
303}
304
305static void omap_mbox_fini(struct omap_mbox *mbox)
306{
307 mutex_lock(&mbox_configured_lock);
308
309 if (!--mbox->use_count) {
310 omap_mbox_disable_irq(mbox, IRQ_RX);
311 free_irq(mbox->irq, mbox);
312 tasklet_kill(&mbox->txq->tasklet);
313 flush_work(&mbox->rxq->work);
314 mbox_queue_free(mbox->txq);
315 mbox_queue_free(mbox->rxq);
316 }
317
318 if (likely(mbox->ops->shutdown)) {
319 if (!--mbox_configured)
320 mbox->ops->shutdown(mbox);
321 }
322
323 mutex_unlock(&mbox_configured_lock);
324}
325
326struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
327{
328 struct omap_mbox *_mbox, *mbox = NULL;
329 int i, ret;
330
331 if (!mboxes)
332 return ERR_PTR(-EINVAL);
333
334 for (i = 0; (_mbox = mboxes[i]); i++) {
335 if (!strcmp(_mbox->name, name)) {
336 mbox = _mbox;
337 break;
338 }
339 }
340
341 if (!mbox)
342 return ERR_PTR(-ENOENT);
343
344 if (nb)
345 blocking_notifier_chain_register(&mbox->notifier, nb);
346
347 ret = omap_mbox_startup(mbox);
348 if (ret) {
349 blocking_notifier_chain_unregister(&mbox->notifier, nb);
350 return ERR_PTR(-ENODEV);
351 }
352
353 return mbox;
354}
355EXPORT_SYMBOL(omap_mbox_get);
356
357void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
358{
359 blocking_notifier_chain_unregister(&mbox->notifier, nb);
360 omap_mbox_fini(mbox);
361}
362EXPORT_SYMBOL(omap_mbox_put);
363
364static struct class omap_mbox_class = { .name = "mbox", };
365
366int omap_mbox_register(struct device *parent, struct omap_mbox **list)
367{
368 int ret;
369 int i;
370
371 mboxes = list;
372 if (!mboxes)
373 return -EINVAL;
374
375 for (i = 0; mboxes[i]; i++) {
376 struct omap_mbox *mbox = mboxes[i];
377 mbox->dev = device_create(&omap_mbox_class,
378 parent, 0, mbox, "%s", mbox->name);
379 if (IS_ERR(mbox->dev)) {
380 ret = PTR_ERR(mbox->dev);
381 goto err_out;
382 }
383
384 BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
385 }
386 return 0;
387
388err_out:
389 while (i--)
390 device_unregister(mboxes[i]->dev);
391 return ret;
392}
393EXPORT_SYMBOL(omap_mbox_register);
394
395int omap_mbox_unregister(void)
396{
397 int i;
398
399 if (!mboxes)
400 return -EINVAL;
401
402 for (i = 0; mboxes[i]; i++)
403 device_unregister(mboxes[i]->dev);
404 mboxes = NULL;
405 return 0;
406}
407EXPORT_SYMBOL(omap_mbox_unregister);
408
409static int __init omap_mbox_init(void)
410{
411 int err;
412
413 err = class_register(&omap_mbox_class);
414 if (err)
415 return err;
416
417 /* kfifo size sanity check: alignment and minimal size */
418 mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
419 mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
420 sizeof(mbox_msg_t));
421
422 return 0;
423}
424subsys_initcall(omap_mbox_init);
425
426static void __exit omap_mbox_exit(void)
427{
428 class_unregister(&omap_mbox_class);
429}
430module_exit(omap_mbox_exit);
431
432MODULE_LICENSE("GPL v2");
433MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
434MODULE_AUTHOR("Toshihiro Kobayashi");
435MODULE_AUTHOR("Hiroshi DOYU");
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 95509d8eb140..d7e17150028a 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -202,7 +202,7 @@ extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
202extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); 202extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
203extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); 203extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
204 204
205#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS 205#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
206#define s3c_cpufreq_debugfs_call(x) x 206#define s3c_cpufreq_debugfs_call(x) x
207#else 207#else
208#define s3c_cpufreq_debugfs_call(x) NULL 208#define s3c_cpufreq_debugfs_call(x) NULL
@@ -259,17 +259,17 @@ extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
259#define s3c2412_iotiming_set NULL 259#define s3c2412_iotiming_set NULL
260#endif /* CONFIG_S3C2412_IOTIMING */ 260#endif /* CONFIG_S3C2412_IOTIMING */
261 261
262#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG 262#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
263#define s3c_freq_dbg(x...) printk(KERN_INFO x) 263#define s3c_freq_dbg(x...) printk(KERN_INFO x)
264#else 264#else
265#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) 265#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
266#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ 266#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
267 267
268#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG 268#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
269#define s3c_freq_iodbg(x...) printk(KERN_INFO x) 269#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
270#else 270#else
271#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) 271#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
272#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ 272#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
273 273
274static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, 274static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
275 int index, size_t table_size, 275 int index, size_t table_size,
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h
index 80c4a809c721..85517ab962ae 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h
@@ -126,7 +126,7 @@ struct s3c_cpufreq_board {
126}; 126};
127 127
128/* Things depending on frequency scaling. */ 128/* Things depending on frequency scaling. */
129#ifdef CONFIG_CPU_FREQ_S3C 129#ifdef CONFIG_ARM_S3C_CPUFREQ
130#define __init_or_cpufreq 130#define __init_or_cpufreq
131#else 131#else
132#define __init_or_cpufreq __init 132#define __init_or_cpufreq __init
@@ -134,7 +134,7 @@ struct s3c_cpufreq_board {
134 134
135/* Board functions */ 135/* Board functions */
136 136
137#ifdef CONFIG_CPU_FREQ_S3C 137#ifdef CONFIG_ARM_S3C_CPUFREQ
138extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); 138extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
139#else 139#else
140 140
@@ -142,4 +142,4 @@ static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
142{ 142{
143 return 0; 143 return 0;
144} 144}
145#endif /* CONFIG_CPU_FREQ_S3C */ 145#endif /* CONFIG_ARM_S3C_CPUFREQ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 18:24:46 -0400