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Diffstat (limited to 'arch/arm/mach-ux500/devices-db8500.c')
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c123
1 files changed, 1 insertions, 122 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index ddbdcda8306a..516a6f57d159 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
42 } 42 }
43}; 43};
44 44
45/* Default configuration for physcial memcpy */ 45struct stedma40_platform_data dma40_plat_data = {
46struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
47 .mode = STEDMA40_MODE_PHYSICAL,
48 .dir = STEDMA40_MEM_TO_MEM,
49
50 .src_info.data_width = STEDMA40_BYTE_WIDTH,
51 .src_info.psize = STEDMA40_PSIZE_PHY_1,
52 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
53
54 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
55 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
56 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
57};
58/* Default configuration for logical memcpy */
59struct stedma40_chan_cfg dma40_memcpy_conf_log = {
60 .dir = STEDMA40_MEM_TO_MEM,
61
62 .src_info.data_width = STEDMA40_BYTE_WIDTH,
63 .src_info.psize = STEDMA40_PSIZE_LOG_1,
64 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
65
66 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
67 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
68 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
69};
70
71/*
72 * Mapping between destination event lines and physical device address.
73 * The event line is tied to a device and therefore the address is constant.
74 * When the address comes from a primecell it will be configured in runtime
75 * and we set the address to -1 as a placeholder.
76 */
77static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
78 /* MUSB - these will be runtime-reconfigured */
79 [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
80 [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
81 [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
82 [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
83 [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
84 [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
85 [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
86 [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
87 /* PrimeCells - run-time configured */
88 [DB8500_DMA_DEV0_SPI0_TX] = -1,
89 [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
90 [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
91 [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
92 [DB8500_DMA_DEV8_SSP0_TX] = -1,
93 [DB8500_DMA_DEV9_SSP1_TX] = -1,
94 [DB8500_DMA_DEV11_UART2_TX] = -1,
95 [DB8500_DMA_DEV12_UART1_TX] = -1,
96 [DB8500_DMA_DEV13_UART0_TX] = -1,
97 [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
98 [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
99 [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
100 [DB8500_DMA_DEV33_SPI2_TX] = -1,
101 [DB8500_DMA_DEV35_SPI1_TX] = -1,
102 [DB8500_DMA_DEV40_SPI3_TX] = -1,
103 [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
104 [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
105 [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
106 [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
107 [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
108 [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
109 [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
110 [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
111};
112
113/* Mapping between source event lines and physical device address */
114static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
115 /* MUSB - these will be runtime-reconfigured */
116 [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
117 [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
118 [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
119 [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
120 [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
121 [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
122 [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
123 [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
124 /* PrimeCells */
125 [DB8500_DMA_DEV0_SPI0_RX] = -1,
126 [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
127 [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
128 [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
129 [DB8500_DMA_DEV8_SSP0_RX] = -1,
130 [DB8500_DMA_DEV9_SSP1_RX] = -1,
131 [DB8500_DMA_DEV11_UART2_RX] = -1,
132 [DB8500_DMA_DEV12_UART1_RX] = -1,
133 [DB8500_DMA_DEV13_UART0_RX] = -1,
134 [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
135 [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
136 [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
137 [DB8500_DMA_DEV33_SPI2_RX] = -1,
138 [DB8500_DMA_DEV35_SPI1_RX] = -1,
139 [DB8500_DMA_DEV40_SPI3_RX] = -1,
140 [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
141 [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
142 [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
143 [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
144 [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
145 [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
146 [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
147};
148
149/* Reserved event lines for memcpy only */
150static int dma40_memcpy_event[] = {
151 DB8500_DMA_MEMCPY_TX_0,
152 DB8500_DMA_MEMCPY_TX_1,
153 DB8500_DMA_MEMCPY_TX_2,
154 DB8500_DMA_MEMCPY_TX_3,
155 DB8500_DMA_MEMCPY_TX_4,
156 DB8500_DMA_MEMCPY_TX_5,
157};
158
159static struct stedma40_platform_data dma40_plat_data = {
160 .dev_len = DB8500_DMA_NR_DEV,
161 .dev_rx = dma40_rx_map,
162 .dev_tx = dma40_tx_map,
163 .memcpy = dma40_memcpy_event,
164 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
165 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
166 .memcpy_conf_log = &dma40_memcpy_conf_log,
167 .disabled_channels = {-1}, 46 .disabled_channels = {-1},
168}; 47};
169 48
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 20:25:24 -0400