Merge tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC cleanups from Olof Johansson:
 "Cleanups for 3.16.  Among these are:

   - a bunch of misc cleanups for Broadcom platforms, mostly
     housekeeping
   - enabling Common Clock Framework on the older s3c24xx Samsung
     chipsets
   - cleanup of the Versatile Express system controller code, moving it
     to syscon
   - power management cleanups for OMAP platforms

  plus a handful of other cleanups across the place"

* tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
  ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
  clk: samsung: fix build error
  ARM: vexpress: refine dependencies for new code
  clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
  cpufreq: exynos: Fix the compile error
  ARM: S3C24XX: move debug-macro.S into the common space
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: trim down debug uart handling
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
  ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
  ARM: EXYNOS: Remove exynos_subsys registration
  ARM: EXYNOS: Remove duplicate lines in Makefile
  ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
  ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
  ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
  ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
  ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
  ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
  ARM: OMAP2+: PRCM: cleanup some header includes
  ...

160 files changed, 1211 insertions, 4301 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db3c5414223e..860bea828ac4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -314,6 +314,7 @@ config ARCH_MULTIPLATFORM
         select CLKSRC_OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_PCI
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
         select USE_OF
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index eab8ecbe69c1..4678870f8ee8 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -625,6 +625,7 @@ choice
         config DEBUG_S3C_UART0
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S3C24XX_UART if ARCH_S3C24XX
                 bool "Use S3C UART 0 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -637,6 +638,7 @@ choice
         config DEBUG_S3C_UART1
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S3C24XX_UART if ARCH_S3C24XX
                 bool "Use S3C UART 1 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -649,6 +651,7 @@ choice
         config DEBUG_S3C_UART2
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S3C24XX_UART if ARCH_S3C24XX
                 bool "Use S3C UART 2 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -670,6 +673,33 @@ choice
                   The uncompressor code port configuration is now handled
                   by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+        config DEBUG_S3C2410_UART0
+                depends on ARCH_S3C24XX
+                select DEBUG_S3C2410_UART
+                bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 0. The port must have been initialised
+                  by the boot-loader before use.
+
+        config DEBUG_S3C2410_UART1
+                depends on ARCH_S3C24XX
+                select DEBUG_S3C2410_UART
+                bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 1. The port must have been initialised
+                  by the boot-loader before use.
+
+        config DEBUG_S3C2410_UART2
+                depends on ARCH_S3C24XX
+                select DEBUG_S3C2410_UART
+                bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 2. The port must have been initialised
+                  by the boot-loader before use.
+
         config DEBUG_SOCFPGA_UART
                 depends on ARCH_SOCFPGA
                 bool "Use SOCFPGA UART for low-level debug"
@@ -921,6 +951,13 @@ endchoice
 config DEBUG_EXYNOS_UART
         bool
 
+config DEBUG_S3C2410_UART
+        bool
+        select DEBUG_S3C24XX_UART
+
+config DEBUG_S3C24XX_UART
+        bool
+
 config DEBUG_OMAP2PLUS_UART
         bool
         depends on ARCH_OMAP2PLUS
@@ -973,6 +1010,7 @@ config DEBUG_LL_INCLUDE
                                  DEBUG_IMX6SL_UART
         default "debug/msm.S" if DEBUG_MSM_UART
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
+        default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
         default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
         default "debug/sti.S" if DEBUG_STI_UART
         default "debug/tegra.S" if DEBUG_TEGRA_UART
@@ -1029,6 +1067,12 @@ config DEBUG_UART_PHYS
         default 0x40090000 if ARCH_LPC32XX
         default 0x40100000 if DEBUG_PXA_UART1
         default 0x42000000 if ARCH_GEMINI
+        default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
+                                DEBUG_S3C2410_UART0)
+        default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
+                                DEBUG_S3C2410_UART1)
+        default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
+                                DEBUG_S3C2410_UART2)
         default 0x7c0003f8 if FOOTBRIDGE
         default 0x80070000 if DEBUG_IMX23_UART
         default 0x80074000 if DEBUG_IMX28_UART
@@ -1058,7 +1102,7 @@ config DEBUG_UART_PHYS
         default 0xfffff700 if ARCH_IOP33X
         depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                 DEBUG_LL_UART_EFM32 || \
-                DEBUG_UART_8250 || DEBUG_UART_PL01X
+                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
 
 config DEBUG_UART_VIRT
         hex "Virtual base address of debug UART"
@@ -1075,6 +1119,12 @@ config DEBUG_UART_VIRT
         default 0xf2100000 if DEBUG_PXA_UART1
         default 0xf4090000 if ARCH_LPC32XX
         default 0xf4200000 if ARCH_GEMINI
+        default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
+                                DEBUG_S3C2410_UART0)
+        default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
+                                DEBUG_S3C2410_UART1)
+        default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
+                                DEBUG_S3C2410_UART2)
         default 0xf7fc9000 if DEBUG_BERLIN_UART
         default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
         default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
@@ -1116,7 +1166,7 @@ config DEBUG_UART_VIRT
         default 0xff003000 if DEBUG_U300_UART
         default DEBUG_UART_PHYS if !MMU
         depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
-                DEBUG_UART_8250 || DEBUG_UART_PL01X
+                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_S3C24XX_UART
 
 config DEBUG_UART_8250_SHIFT
         int "Register offset shift for the 8250 debug UART"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 066b03480b63..3a8b32df6b31 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -60,11 +60,6 @@
                 add     \rb, \rb, #0x00010000   @ Ser1
 #endif
                 .endm
-#elif defined(CONFIG_ARCH_S3C24XX)
-                .macro loadsp, rb, tmp
-                mov     \rb, #0x50000000
-                add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
-                .endm
 #else
                 .macro  loadsp, rb, tmp
                 addruart \rb, \tmp
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 9d72674049d6..317bc590a4d0 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -195,6 +195,7 @@
                                 compatible = "sirf,prima2-tick";
                                 reg = <0xb0020000 0x1000>;
                                 interrupts = <0>;
+                                clocks = <&clks 11>;
                         };
 
                         nand@b0030000 {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 1e82571d6823..7e7d8843abaf 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -201,6 +201,7 @@
                                 compatible = "sirf,prima2-tick";
                                 reg = <0xb0020000 0x1000>;
                                 interrupts = <0>;
+                                clocks = <&clks 11>;
                         };
 
                         nand@b0030000 {
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index 59594cf15998..ea92fd69529a 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -19,6 +19,19 @@
                 reg =  <0x30000000 0x4000000>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                xti: xti {
+                        compatible = "fixed-clock";
+                        clock-frequency = <12000000>;
+                        clock-output-names = "xti";
+                        #clock-cells = <0>;
+                };
+        };
+
         serial@50000000 {
                 status = "okay";
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index e6555bdd81b8..955e4a4f8c31 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <dt-bindings/clock/s3c2443.h>
 #include "s3c24xx.dtsi"
 #include "s3c2416-pinctrl.dtsi"
 
@@ -28,26 +29,53 @@
                 compatible = "samsung,s3c2416-irq";
         };
 
+        clocks: clock-controller@0x4c000000 {
+                compatible = "samsung,s3c2416-clock";
+                reg = <0x4c000000 0x40>;
+                #clock-cells = <1>;
+        };
+
         pinctrl@56000000 {
                 compatible = "samsung,s3c2416-pinctrl";
         };
 
+        timer@51000000 {
+                clocks = <&clocks PCLK_PWM>;
+                clock-names = "timers";
+        };
+
         serial@50000000 {
                 compatible = "samsung,s3c2440-uart";
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
+                                <&clocks SCLK_UART>;
         };
 
         serial@50004000 {
                 compatible = "samsung,s3c2440-uart";
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
+                                <&clocks SCLK_UART>;
         };
 
         serial@50008000 {
                 compatible = "samsung,s3c2440-uart";
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
+                                <&clocks SCLK_UART>;
         };
 
         serial@5000C000 {
                 compatible = "samsung,s3c2440-uart";
                 reg = <0x5000C000 0x4000>;
                 interrupts = <1 18 24 4>, <1 18 25 4>;
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
+                                <&clocks SCLK_UART>;
                 status = "disabled";
         };
 
@@ -55,6 +83,10 @@
                 compatible = "samsung,s3c6410-sdhci";
                 reg = <0x4AC00000 0x100>;
                 interrupts = <0 0 21 3>;
+                clock-names = "hsmmc", "mmc_busclk.0",
+                                "mmc_busclk.2";
+                clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
+                                <&clocks MUX_HSMMC0>;
                 status = "disabled";
         };
 
@@ -62,18 +94,28 @@
                 compatible = "samsung,s3c6410-sdhci";
                 reg = <0x4A800000 0x100>;
                 interrupts = <0 0 20 3>;
+                clock-names = "hsmmc", "mmc_busclk.0",
+                                "mmc_busclk.2";
+                clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
+                                <&clocks MUX_HSMMC1>;
                 status = "disabled";
         };
 
         watchdog@53000000 {
                 interrupts = <1 9 27 3>;
+                clocks = <&clocks PCLK_WDT>;
+                clock-names = "watchdog";
         };
 
         rtc@57000000 {
                 compatible = "samsung,s3c2416-rtc";
+                clocks = <&clocks PCLK_RTC>;
+                clock-names = "rtc";
         };
 
         i2c@54000000 {
                 compatible = "samsung,s3c2440-i2c";
+                clocks = <&clocks PCLK_I2C0>;
+                clock-names = "i2c";
         };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index ac870fb3fa0d..756c986995a3 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -74,8 +74,24 @@
                         v2m_sysreg: sysreg@010000 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x010000 0x1000>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
+
+                                v2m_led_gpios: sys_led@08 {
+                                        compatible = "arm,vexpress-sysreg,sys_led";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+
+                                v2m_mmc_gpios: sys_mci@48 {
+                                        compatible = "arm,vexpress-sysreg,sys_mci";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+
+                                v2m_flash_gpios: sys_flash@4c {
+                                        compatible = "arm,vexpress-sysreg,sys_flash";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
                         };
 
                         v2m_sysctl: sysctl@020000 {
@@ -113,8 +129,8 @@
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x050000 0x1000>;
                                 interrupts = <9 10>;
-                                cd-gpios = <&v2m_sysreg 0 0>;
-                                wp-gpios = <&v2m_sysreg 1 0>;
+                                cd-gpios = <&v2m_mmc_gpios 0 0>;
+                                wp-gpios = <&v2m_mmc_gpios 1 0>;
                                 max-frequency = <12000000>;
                                 vmmc-supply = <&v2m_fixed_3v3>;
                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
@@ -265,6 +281,58 @@
                         clock-output-names = "v2m:refclk32khz";
                 };
 
+                leds {
+                        compatible = "gpio-leds";
+
+                        user@1 {
+                                label = "v2m:green:user1";
+                                gpios = <&v2m_led_gpios 0 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+
+                        user@2 {
+                                label = "v2m:green:user2";
+                                gpios = <&v2m_led_gpios 1 0>;
+                                linux,default-trigger = "mmc0";
+                        };
+
+                        user@3 {
+                                label = "v2m:green:user3";
+                                gpios = <&v2m_led_gpios 2 0>;
+                                linux,default-trigger = "cpu0";
+                        };
+
+                        user@4 {
+                                label = "v2m:green:user4";
+                                gpios = <&v2m_led_gpios 3 0>;
+                                linux,default-trigger = "cpu1";
+                        };
+
+                        user@5 {
+                                label = "v2m:green:user5";
+                                gpios = <&v2m_led_gpios 4 0>;
+                                linux,default-trigger = "cpu2";
+                        };
+
+                        user@6 {
+                                label = "v2m:green:user6";
+                                gpios = <&v2m_led_gpios 5 0>;
+                                linux,default-trigger = "cpu3";
+                        };
+
+                        user@7 {
+                                label = "v2m:green:user7";
+                                gpios = <&v2m_led_gpios 6 0>;
+                                linux,default-trigger = "cpu4";
+                        };
+
+                        user@8 {
+                                label = "v2m:green:user8";
+                                gpios = <&v2m_led_gpios 7 0>;
+                                linux,default-trigger = "cpu5";
+                        };
+                };
+
                 mcc {
                         compatible = "arm,vexpress,config-bus";
                         arm,vexpress,config-bridge = <&v2m_sysreg>;
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index f1420368355b..ba856d604fb7 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -73,8 +73,24 @@
                         v2m_sysreg: sysreg@00000 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x00000 0x1000>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
+
+                                v2m_led_gpios: sys_led@08 {
+                                        compatible = "arm,vexpress-sysreg,sys_led";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+
+                                v2m_mmc_gpios: sys_mci@48 {
+                                        compatible = "arm,vexpress-sysreg,sys_mci";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+
+                                v2m_flash_gpios: sys_flash@4c {
+                                        compatible = "arm,vexpress-sysreg,sys_flash";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
                         };
 
                         v2m_sysctl: sysctl@01000 {
@@ -112,8 +128,8 @@
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x05000 0x1000>;
                                 interrupts = <9 10>;
-                                cd-gpios = <&v2m_sysreg 0 0>;
-                                wp-gpios = <&v2m_sysreg 1 0>;
+                                cd-gpios = <&v2m_mmc_gpios 0 0>;
+                                wp-gpios = <&v2m_mmc_gpios 1 0>;
                                 max-frequency = <12000000>;
                                 vmmc-supply = <&v2m_fixed_3v3>;
                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
@@ -264,6 +280,58 @@
                         clock-output-names = "v2m:refclk32khz";
                 };
 
+                leds {
+                        compatible = "gpio-leds";
+
+                        user@1 {
+                                label = "v2m:green:user1";
+                                gpios = <&v2m_led_gpios 0 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+
+                        user@2 {
+                                label = "v2m:green:user2";
+                                gpios = <&v2m_led_gpios 1 0>;
+                                linux,default-trigger = "mmc0";
+                        };
+
+                        user@3 {
+                                label = "v2m:green:user3";
+                                gpios = <&v2m_led_gpios 2 0>;
+                                linux,default-trigger = "cpu0";
+                        };
+
+                        user@4 {
+                                label = "v2m:green:user4";
+                                gpios = <&v2m_led_gpios 3 0>;
+                                linux,default-trigger = "cpu1";
+                        };
+
+                        user@5 {
+                                label = "v2m:green:user5";
+                                gpios = <&v2m_led_gpios 4 0>;
+                                linux,default-trigger = "cpu2";
+                        };
+
+                        user@6 {
+                                label = "v2m:green:user6";
+                                gpios = <&v2m_led_gpios 5 0>;
+                                linux,default-trigger = "cpu3";
+                        };
+
+                        user@7 {
+                                label = "v2m:green:user7";
+                                gpios = <&v2m_led_gpios 6 0>;
+                                linux,default-trigger = "cpu4";
+                        };
+
+                        user@8 {
+                                label = "v2m:green:user8";
+                                gpios = <&v2m_led_gpios 7 0>;
+                                linux,default-trigger = "cpu5";
+                        };
+                };
+
                 mcc {
                         compatible = "arm,vexpress,config-bus";
                         arm,vexpress,config-bridge = <&v2m_sysreg>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 15f98cbcb75a..a25c262326dc 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -312,6 +312,7 @@
                         arm,vexpress-sysreg,func = <12 0>;
                         label = "A15 Pcore";
                 };
+
                 power@1 {
                         /* Total power for the three A7 cores */
                         compatible = "arm,vexpress-power";
@@ -322,14 +323,14 @@
                 energy@0 {
                         /* Total energy for the two A15 cores */
                         compatible = "arm,vexpress-energy";
-                        arm,vexpress-sysreg,func = <13 0>;
+                        arm,vexpress-sysreg,func = <13 0>, <13 1>;
                         label = "A15 Jcore";
                 };
 
                 energy@2 {
                         /* Total energy for the three A7 cores */
                         compatible = "arm,vexpress-energy";
-                        arm,vexpress-sysreg,func = <13 2>;
+                        arm,vexpress-sysreg,func = <13 2>, <13 3>;
                         label = "A7 Jcore";
                 };
         };
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index abe61bf379d2..1da5d9e48224 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -76,8 +76,10 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_VERSATILE=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 7079cbe898a8..d02e9d911bb7 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -75,8 +75,10 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_VERSATILE=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 073541a50e23..d52b4ffe2012 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -61,6 +61,9 @@ CONFIG_SND_ARMAACI=m
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=m
 CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_VERSATILE=y
+CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/include/debug/s3c24xx.S b/arch/arm/include/debug/s3c24xx.S
new file mode 100644
index 000000000000..b1f54dc4888c
--- /dev/null
+++ b/arch/arm/include/debug/s3c24xx.S
@@ -0,0 +1,46 @@
+/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Copyright (C) 2005 Simtec Electronics
+ *
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_s3c.h>
+
+#define S3C2410_UART1_OFF (0x4000)
+
+        .macro addruart, rp, rv, tmp
+                ldr     \rp, = CONFIG_DEBUG_UART_PHYS
+                ldr     \rv, = CONFIG_DEBUG_UART_VIRT
+        .endm
+
+        .macro  fifo_full_s3c2410 rd, rx
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+        .endm
+
+        .macro fifo_level_s3c2410 rd, rx
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
+                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
+        .endm
+
+/* Select the correct implementation depending on the configuration. The
+ * S3C2440 will get selected by default, as these are the most widely
+ * used variants of these
+*/
+
+#if defined(CONFIG_DEBUG_S3C2410_UART)
+#define fifo_full  fifo_full_s3c2410
+#define fifo_level fifo_level_s3c2410
+#endif
+
+/* include the reset of the code which will do the work */
+
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 49c914cd9c7a..2113d92c668a 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -10,22 +10,51 @@ if ARCH_BCM
 menu "Broadcom SoC Selection"
 
 config ARCH_BCM_MOBILE
-        bool "Broadcom Mobile SoC" if ARCH_MULTI_V7
-        depends on MMU
+        bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
         select GPIO_BCM_KONA
         select TICK_ONESHOT
-        select CACHE_L2X0
         select HAVE_ARM_ARCH_TIMER
         select PINCTRL
         help
           This enables support for systems based on Broadcom mobile SoCs.
-          It currently supports the 'BCM281XX' family, which includes
-          BCM11130, BCM11140, BCM11351, BCM28145 and
-          BCM28155 variants.
+
+if ARCH_BCM_MOBILE
+
+menu "Broadcom Mobile SoC Selection"
+
+config ARCH_BCM_281XX
+        bool "Broadcom BCM281XX SoC family"
+        default y
+        help
+          Enable support for the the BCM281XX family, which includes
+          BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
+          variants.
+
+config ARCH_BCM_21664
+        bool "Broadcom BCM21664 SoC family"
+        default y
+        help
+          Enable support for the the BCM21664 family, which includes
+          BCM21663 and BCM21664 variants.
+
+config ARCH_BCM_MOBILE_L2_CACHE
+        bool "Broadcom mobile SoC level 2 cache support"
+        depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
+        default y
+        select CACHE_L2X0
+        select ARCH_BCM_MOBILE_SMC
+
+config ARCH_BCM_MOBILE_SMC
+        bool
+        depends on ARCH_BCM_281XX || ARCH_BCM_21664
+
+endmenu
+
+endif
 
 config ARCH_BCM2835
         bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
@@ -33,10 +62,7 @@ config ARCH_BCM2835
         select ARM_AMBA
         select ARM_ERRATA_411920
         select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
         select CLKSRC_OF
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
         select PINCTRL
         select PINCTRL_BCM2835
         help
@@ -45,17 +71,12 @@ config ARCH_BCM2835
 
 config ARCH_BCM_5301X
         bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-        depends on MMU
         select ARM_GIC
         select CACHE_L2X0
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
         select ARM_GLOBAL_TIMER
         select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-        select MIGHT_HAVE_PCI
         help
           Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
 
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index a326b28c4406..731292114975 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,10 +10,23 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
-obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o board_bcm21664.o \
-                                bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+# BCM281XX
+obj-$(CONFIG_ARCH_BCM_281XX)    += board_bcm281xx.o
+
+# BCM21664
+obj-$(CONFIG_ARCH_BCM_21664)    += board_bcm21664.o
+
+# BCM281XX and BCM21664 L2 cache control
+obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
+
+# Support for secure monitor traps
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
+ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec)
+CFLAGS_bcm_kona_smc.o           += -Wa,-march=armv7-a+sec -DREQUIRES_SEC
+endif
+
+# BCM2835
 obj-$(CONFIG_ARCH_BCM2835)      += board_bcm2835.o
 
-plus_sec := $(call as-instr,.arch_extension sec,+sec)
-AFLAGS_bcm_kona_smc_asm.o       :=-Wa,-march=armv7-a$(plus_sec)
+# BCM5301X
 obj-$(CONFIG_ARCH_BCM_5301X)    += bcm_5301x.o
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
index 5e31e918f325..a55a7ecf146a 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -21,11 +21,8 @@
 
 #include "bcm_kona_smc.h"
 
-struct secure_bridge_data {
-        void __iomem *bounce;           /* virtual address */
-        u32 __iomem buffer_addr;        /* physical address */
-        int initialized;
-} bridge_data;
+static u32              bcm_smc_buffer_phys;    /* physical address */
+static void __iomem     *bcm_smc_buffer;        /* virtual address */
 
 struct bcm_kona_smc_data {
         unsigned service_id;
@@ -33,6 +30,7 @@ struct bcm_kona_smc_data {
         unsigned arg1;
         unsigned arg2;
         unsigned arg3;
+        unsigned result;
 };
 
 static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
@@ -41,59 +39,125 @@ static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
         {},
 };
 
-/* Map in the bounce area */
+/* Map in the args buffer area */
 int __init bcm_kona_smc_init(void)
 {
         struct device_node *node;
+        const __be32 *prop_val;
+        u64 prop_size = 0;
+        unsigned long buffer_size;
+        u32 buffer_phys;
 
         /* Read buffer addr and size from the device tree node */
         node = of_find_matching_node(NULL, bcm_kona_smc_ids);
         if (!node)
                 return -ENODEV;
 
-        /* Don't care about size or flags of the DT node */
-        bridge_data.buffer_addr =
-                be32_to_cpu(*of_get_address(node, 0, NULL, NULL));
-        BUG_ON(!bridge_data.buffer_addr);
+        prop_val = of_get_address(node, 0, &prop_size, NULL);
+        if (!prop_val)
+                return -EINVAL;
 
-        bridge_data.bounce = of_iomap(node, 0);
-        BUG_ON(!bridge_data.bounce);
+        /* We assume space for four 32-bit arguments */
+        if (prop_size < 4 * sizeof(u32) || prop_size > (u64)ULONG_MAX)
+                return -EINVAL;
+        buffer_size = (unsigned long)prop_size;
 
-        bridge_data.initialized = 1;
+        buffer_phys = be32_to_cpup(prop_val);
+        if (!buffer_phys)
+                return -EINVAL;
+
+        bcm_smc_buffer = ioremap(buffer_phys, buffer_size);
+        if (!bcm_smc_buffer)
+                return -ENOMEM;
+        bcm_smc_buffer_phys = buffer_phys;
 
         pr_info("Kona Secure API initialized\n");
 
         return 0;
 }
 
+/*
+ * int bcm_kona_do_smc(u32 service_id, u32 buffer_addr)
+ *
+ * Only core 0 can run the secure monitor code.  If an "smc" request
+ * is initiated on a different core it must be redirected to core 0
+ * for execution.  We rely on the caller to handle this.
+ *
+ * Each "smc" request supplies a service id and the address of a
+ * buffer containing parameters related to the service to be
+ * performed.  A flags value defines the behavior of the level 2
+ * cache and interrupt handling while the secure monitor executes.
+ *
+ * Parameters to the "smc" request are passed in r4-r6 as follows:
+ *     r4       service id
+ *     r5       flags (SEC_ROM_*)
+ *     r6       physical address of buffer with other parameters
+ *
+ * Execution of an "smc" request produces two distinct results.
+ *
+ * First, the secure monitor call itself (regardless of the specific
+ * service request) can succeed, or can produce an error.  When an
+ * "smc" request completes this value is found in r12; it should
+ * always be SEC_EXIT_NORMAL.
+ *
+ * In addition, the particular service performed produces a result.
+ * The values that should be expected depend on the service.  We
+ * therefore return this value to the caller, so it can handle the
+ * request result appropriately.  This result value is found in r0
+ * when the "smc" request completes.
+ */
+static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys)
+{
+        register u32 ip asm("ip");      /* Also called r12 */
+        register u32 r0 asm("r0");
+        register u32 r4 asm("r4");
+        register u32 r5 asm("r5");
+        register u32 r6 asm("r6");
+
+        r4 = service_id;
+        r5 = 0x3;               /* Keep IRQ and FIQ off in SM */
+        r6 = buffer_phys;
+
+        asm volatile (
+                /* Make sure we got the registers we want */
+                __asmeq("%0", "ip")
+                __asmeq("%1", "r0")
+                __asmeq("%2", "r4")
+                __asmeq("%3", "r5")
+                __asmeq("%4", "r6")
+#ifdef REQUIRES_SEC
+                ".arch_extension sec\n"
+#endif
+                "       smc    #0\n"
+                : "=r" (ip), "=r" (r0)
+                : "r" (r4), "r" (r5), "r" (r6)
+                : "r1", "r2", "r3", "r7", "lr");
+
+        BUG_ON(ip != SEC_EXIT_NORMAL);
+
+        return r0;
+}
+
 /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
 static void __bcm_kona_smc(void *info)
 {
         struct bcm_kona_smc_data *data = info;
-        u32 *args = bridge_data.bounce;
-        int rc = 0;
+        u32 *args = bcm_smc_buffer;
 
-        /* Must run on CPU 0 */
         BUG_ON(smp_processor_id() != 0);
+        BUG_ON(!args);
 
-        /* Check map in the bounce area */
-        BUG_ON(!bridge_data.initialized);
-
-        /* Copy one 32 bit word into the bounce area */
-        args[0] = data->arg0;
-        args[1] = data->arg1;
-        args[2] = data->arg2;
-        args[3] = data->arg3;
+        /* Copy the four 32 bit argument values into the bounce area */
+        writel_relaxed(data->arg0, args++);
+        writel_relaxed(data->arg1, args++);
+        writel_relaxed(data->arg2, args++);
+        writel(data->arg3, args);
 
         /* Flush caches for input data passed to Secure Monitor */
-        if (data->service_id != SSAPI_BRCM_START_VC_CORE)
-                flush_cache_all();
-
-        /* Trap into Secure Monitor */
-        rc = bcm_kona_smc_asm(data->service_id, bridge_data.buffer_addr);
+        flush_cache_all();
 
-        if (rc != SEC_ROM_RET_OK)
-                pr_err("Secure Monitor call failed (0x%x)!\n", rc);
+        /* Trap into Secure Monitor and record the request result */
+        data->result = bcm_kona_do_smc(data->service_id, bcm_smc_buffer_phys);
 }
 
 unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
@@ -106,17 +170,13 @@ unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
         data.arg1 = arg1;
         data.arg2 = arg2;
         data.arg3 = arg3;
+        data.result = 0;
 
         /*
          * Due to a limitation of the secure monitor, we must use the SMP
          * infrastructure to forward all secure monitor calls to Core 0.
          */
-        if (get_cpu() != 0)
-                smp_call_function_single(0, __bcm_kona_smc, (void *)&data, 1);
-        else
-                __bcm_kona_smc(&data);
+        smp_call_function_single(0, __bcm_kona_smc, &data, 1);
 
-        put_cpu();
-
-        return 0;
+        return data.result;
 }
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h
index d098a7e76744..2e29ec67e414 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.h
+++ b/arch/arm/mach-bcm/bcm_kona_smc.h
@@ -15,55 +15,12 @@
 #define BCM_KONA_SMC_H
 
 #include <linux/types.h>
-#define FLAGS   (SEC_ROM_ICACHE_ENABLE_MASK | SEC_ROM_DCACHE_ENABLE_MASK | \
-                        SEC_ROM_IRQ_ENABLE_MASK | SEC_ROM_FIQ_ENABLE_MASK)
 
-/*!
- * Definitions for IRQ & FIQ Mask for ARM
- */
-
-#define FIQ_IRQ_MASK                                            0xC0
-#define FIQ_MASK                                                0x40
-#define IRQ_MASK                                                0x80
-
-/*!
- * Secure Mode FLAGs
- */
-
-/* When set, enables ICache within the secure mode */
-#define SEC_ROM_ICACHE_ENABLE_MASK                        0x00000001
-
-/* When set, enables DCache within the secure mode */
-#define SEC_ROM_DCACHE_ENABLE_MASK                        0x00000002
-
-/* When set, enables IRQ within the secure mode */
-#define SEC_ROM_IRQ_ENABLE_MASK                           0x00000004
-
-/* When set, enables FIQ within the secure mode */
-#define SEC_ROM_FIQ_ENABLE_MASK                           0x00000008
-
-/* When set, enables Unified L2 cache within the secure mode */
-#define SEC_ROM_UL2_CACHE_ENABLE_MASK                     0x00000010
-
-/* Broadcom Secure Service API Service IDs */
-#define SSAPI_DORMANT_ENTRY_SERV                          0x01000000
-#define SSAPI_PUBLIC_OTP_SERV                             0x01000001
-#define SSAPI_ENABLE_L2_CACHE                             0x01000002
-#define SSAPI_DISABLE_L2_CACHE                            0x01000003
-#define SSAPI_WRITE_SCU_STATUS                            0x01000004
-#define SSAPI_WRITE_PWR_GATE                              0x01000005
-
-/* Broadcom Secure Service API Return Codes */
+/* Broadcom Secure Service API service IDs, return codes, and exit codes */
+#define SSAPI_ENABLE_L2_CACHE           0x01000002
 #define SEC_ROM_RET_OK                  0x00000001
-#define SEC_ROM_RET_FAIL                0x00000009
-
-#define SSAPI_RET_FROM_INT_SERV         0x4
 #define SEC_EXIT_NORMAL                 0x1
 
-#define SSAPI_ROW_AES                   0x0E000006
-#define SSAPI_BRCM_START_VC_CORE        0x0E000008
-
-#ifndef __ASSEMBLY__
 extern int __init bcm_kona_smc_init(void);
 
 extern unsigned bcm_kona_smc(unsigned service_id,
@@ -72,9 +29,4 @@ extern unsigned bcm_kona_smc(unsigned service_id,
                              unsigned arg2,
                              unsigned arg3);
 
-extern int bcm_kona_smc_asm(u32 service_id,
-                            u32 buffer_addr);
-
-#endif  /* __ASSEMBLY__ */
-
 #endif /* BCM_KONA_SMC_H */
diff --git a/arch/arm/mach-bcm/bcm_kona_smc_asm.S b/arch/arm/mach-bcm/bcm_kona_smc_asm.S
deleted file mode 100644
index a1608480d60d..000000000000
--- a/arch/arm/mach-bcm/bcm_kona_smc_asm.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/linkage.h>
-#include "bcm_kona_smc.h"
-
-/*
- * int bcm_kona_smc_asm(u32 service_id, u32 buffer_addr)
- */
-
-ENTRY(bcm_kona_smc_asm)
-        stmfd   sp!, {r4-r12, lr}
-        mov     r4, r0          @ service_id
-        mov     r5, #3          @ Keep IRQ and FIQ off in SM
-        /*
-         * Since interrupts are disabled in the open mode, we must keep
-         * interrupts disabled in secure mode by setting R5=0x3. If interrupts
-         * are enabled in open mode, we can set R5=0x0 to allow interrupts in
-         * secure mode.  If we did this, the secure monitor would return back
-         * control to the open mode to handle the interrupt prior to completing
-         * the secure service. If this happened, R12 would not be
-         * SEC_EXIT_NORMAL and we would need to call SMC again after resetting
-         * R5 (it gets clobbered by the secure monitor) and setting R4 to
-         * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor
-         * to finish up the previous uncompleted secure service.
-         */
-        mov     r6, r1          @ buffer_addr
-        smc     #0
-        /* Check r12 for SEC_EXIT_NORMAL here if interrupts are enabled */
-        ldmfd   sp!, {r4-r12, pc}
-ENDPROC(bcm_kona_smc_asm)
diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c
index acc1573fd005..f0521cc0640d 100644
--- a/arch/arm/mach-bcm/board_bcm21664.c
+++ b/arch/arm/mach-bcm/board_bcm21664.c
@@ -11,14 +11,13 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/clocksource.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 
-#include "bcm_kona_smc.h"
-#include "kona.h"
+#include "kona_l2_cache.h"
 
 #define RSTMGR_DT_STRING                "brcm,bcm21664-resetmgr"
 
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index 6be54c10f8cb..1ac59fc0cb15 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -17,7 +17,7 @@
 
 #include <asm/mach/arch.h>
 
-#include "kona.h"
+#include "kona_l2_cache.h"
 
 #define SECWDOG_OFFSET                  0x00000000
 #define SECWDOG_RESERVED_MASK           0xe2000000
diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona_l2_cache.c
index 768bc2837bf5..b31970377c20 100644
--- a/arch/arm/mach-bcm/kona.c
+++ b/arch/arm/mach-bcm/kona_l2_cache.c
@@ -11,19 +11,18 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/of_platform.h>
+
+#include <linux/init.h>
+#include <linux/printk.h>
 #include <asm/hardware/cache-l2x0.h>
 
 #include "bcm_kona_smc.h"
-#include "kona.h"
 
 void __init kona_l2_cache_init(void)
 {
+        unsigned int result;
         int ret;
 
-        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
-                return;
-
         ret = bcm_kona_smc_init();
         if (ret) {
                 pr_info("Secure API not available (%d). Skipping L2 init.\n",
@@ -31,7 +30,12 @@ void __init kona_l2_cache_init(void)
                 return;
         }
 
-        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
+        result = bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
+        if (result != SEC_ROM_RET_OK) {
+                pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n",
+                        result);
+                return;
+        }
 
         /*
          * The aux_val and aux_mask have no effect since L2 cache is already
diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona_l2_cache.h
index 3a7a017c29cd..46f84a95ab1c 100644
--- a/arch/arm/mach-bcm/kona.h
+++ b/arch/arm/mach-bcm/kona_l2_cache.h
@@ -11,4 +11,8 @@
  * GNU General Public License for more details.
  */
 
-void __init kona_l2_cache_init(void);
+#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE
+void    kona_l2_cache_init(void);
+#else
+#define kona_l2_cache_init() ((void)0)
+#endif
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index dce8decd5d46..66838f42037f 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,7 +1,6 @@
 config ARCH_CNS3XXX
         bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
         select ARM_GIC
-        select MIGHT_HAVE_PCI
         select PCI_DOMAINS if PCI
         help
           Support for Cavium Networks CNS3XXX platform.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index a656dbe3b78c..f6dcc256db56 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,20 +12,15 @@ obj-				:=
 
 # Core
 
-obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o
+obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o pmu.o exynos-smc.o firmware.o
 
 obj-$(CONFIG_PM_SLEEP)          += pm.o sleep.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
-obj-$(CONFIG_ARCH_EXYNOS)       += pmu.o
-
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
-obj-$(CONFIG_ARCH_EXYNOS)       += exynos-smc.o
-obj-$(CONFIG_ARCH_EXYNOS)       += firmware.o
-
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83efaff..c1a2f2207af0 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,6 +15,75 @@
 #include <linux/reboot.h>
 #include <linux/of.h>
 
+#define EXYNOS4210_CPU_ID       0x43210000
+#define EXYNOS4212_CPU_ID       0x43220000
+#define EXYNOS4412_CPU_ID       0xE4412200
+#define EXYNOS4_CPU_MASK        0xFFFE0000
+
+#define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5420_SOC_ID       0xE5420000
+#define EXYNOS5440_SOC_ID       0xE5440000
+#define EXYNOS5_SOC_MASK        0xFFFFF000
+
+extern unsigned long samsung_cpu_id;
+
+#define IS_SAMSUNG_CPU(name, id, mask)          \
+static inline int is_samsung_##name(void)       \
+{                                               \
+        return ((samsung_cpu_id & mask) == (id & mask));        \
+}
+
+IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
+
+#if defined(CONFIG_CPU_EXYNOS4210)
+# define soc_is_exynos4210()    is_samsung_exynos4210()
+#else
+# define soc_is_exynos4210()    0
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212()    is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212()    0
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+# define soc_is_exynos4412()    is_samsung_exynos4412()
+#else
+# define soc_is_exynos4412()    0
+#endif
+
+#define EXYNOS4210_REV_0        (0x0)
+#define EXYNOS4210_REV_1_0      (0x10)
+#define EXYNOS4210_REV_1_1      (0x11)
+
+#if defined(CONFIG_SOC_EXYNOS5250)
+# define soc_is_exynos5250()    is_samsung_exynos5250()
+#else
+# define soc_is_exynos5250()    0
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS5420)
+# define soc_is_exynos5420()    is_samsung_exynos5420()
+#else
+# define soc_is_exynos5420()    0
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS5440)
+# define soc_is_exynos5440()    is_samsung_exynos5440()
+#else
+# define soc_is_exynos5440()    0
+#endif
+
+#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
+                          soc_is_exynos4412())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
+
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 
 struct map_desc;
@@ -63,4 +132,7 @@ struct exynos_pmu_conf {
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
 
+extern void s5p_init_cpu(void __iomem *cpuid_addr);
+extern unsigned int samsung_rev(void);
+
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index c57cae0e8779..3dd385ebf195 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -24,7 +24,6 @@
 #include <asm/unified.h>
 #include <asm/cpuidle.h>
 
-#include <plat/cpu.h>
 #include <plat/pm.h>
 
 #include <mach/map.h>
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907d021d..59aab756702e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -26,8 +26,6 @@
 #include <asm/mach/map.h>
 #include <asm/memory.h>
 
-#include <plat/cpu.h>
-
 #include "common.h"
 #include "mfc.h"
 #include "regs-pmu.h"
@@ -308,17 +306,6 @@ void __init exynos_init_io(void)
         exynos_map_io();
 }
 
-struct bus_type exynos_subsys = {
-        .name           = "exynos-core",
-        .dev_name       = "exynos-core",
-};
-
-static int __init exynos_core_init(void)
-{
-        return subsys_system_register(&exynos_subsys, NULL);
-}
-core_initcall(exynos_core_init);
-
 static int __init exynos4_l2x0_cache_init(void)
 {
         int ret;
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index aa01c4222b40..f6cb510aee85 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -18,8 +18,7 @@
 
 #include <mach/map.h>
 
-#include <plat/cpu.h>
-
+#include "common.h"
 #include "smc.h"
 
 static int exynos_do_idle(void)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead530c6f8..3cab3f506689 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -19,61 +19,9 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
-#include <plat/cpu.h>
-
 #include "common.h"
 #include "regs-pmu.h"
 
-static inline void cpu_enter_lowpower_a9(void)
-{
-        unsigned int v;
-
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, %3\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-          : "cc");
-}
-
-static inline void cpu_enter_lowpower_a15(void)
-{
-        unsigned int v;
-
-        asm volatile(
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-
-        flush_cache_louis();
-
-        asm volatile(
-        /*
-        * Turn off coherency
-        */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        : "=&r" (v)
-        : "Ir" (0x40)
-        : "cc");
-
-        isb();
-        dsb();
-}
-
 static inline void cpu_leave_lowpower(void)
 {
         unsigned int v;
@@ -132,19 +80,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 void __ref exynos_cpu_die(unsigned int cpu)
 {
         int spurious = 0;
-        int primary_part = 0;
 
-        /*
-         * we're ready for shutdown now, so do it.
-         * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
-         * number by reading the Main ID register and then perform the
-         * appropriate sequence for entering low power.
-         */
-        asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-        if ((primary_part & 0xfff0) == 0xc0f0)
-                cpu_enter_lowpower_a15();
-        else
-                cpu_enter_lowpower_a9();
+        v7_exit_coherency_flush(louis);
 
         platform_do_lowpower(cpu, &spurious);
 
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f94705..c28cdb1c82cd 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -26,8 +26,6 @@
 #include <asm/smp_scu.h>
 #include <asm/firmware.h>
 
-#include <plat/cpu.h>
-
 #include "common.h"
 #include "regs-pmu.h"
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ceb0a66..ca672e24b5cd 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -26,7 +26,6 @@
 #include <asm/smp_scu.h>
 #include <asm/suspend.h>
 
-#include <plat/cpu.h>
 #include <plat/pm-common.h>
 #include <plat/pll.h>
 #include <plat/regs-srom.h>
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce15322a..fb0deda3b3a4 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -13,8 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/bug.h>
 
-#include <plat/cpu.h>
-
 #include "common.h"
 #include "regs-pmu.h"
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5740296dc429..50bb546b893a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -796,7 +796,6 @@ config SOC_IMX6Q
         select ARM_ERRATA_764369 if SMP
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select MIGHT_HAVE_PCI
         select PCI_DOMAINS if PCI
         select PINCTRL_IMX6Q
         select SOC_IMX6
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 3f73eecbcfb0..2052a90d9981 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -3,15 +3,12 @@ config ARCH_MVEBU
         select ARCH_SUPPORTS_BIG_ENDIAN
         select CLKSRC_MMIO
         select GENERIC_IRQ_CHIP
-        select IRQ_DOMAIN
         select PINCTRL
         select PLAT_ORION
         select MVEBU_MBUS
         select ZONE_DMA if ARM_LPAE
         select ARCH_REQUIRE_GPIOLIB
-        select MIGHT_HAVE_PCI
         select PCI_QUIRKS if PCI
-        select OF_ADDRESS_PCI
 
 if ARCH_MVEBU
 
@@ -38,7 +35,6 @@ config MACH_ARMADA_375
         select ARM_ERRATA_753970
         select ARM_GIC
         select ARMADA_375_CLK
-        select CPU_V7
         select MACH_MVEBU_V7
         select PINCTRL_ARMADA_375
         help
@@ -51,7 +47,6 @@ config MACH_ARMADA_38X
         select ARM_ERRATA_753970
         select ARM_GIC
         select ARMADA_38X_CLK
-        select CPU_V7
         select MACH_MVEBU_V7
         select PINCTRL_ARMADA_38X
         help
@@ -86,13 +81,11 @@ config MACH_KIRKWOOD
         select ARCH_REQUIRE_GPIOLIB
         select CPU_FEROCEON
         select KIRKWOOD_CLK
-        select OF_IRQ
         select ORION_IRQCHIP
         select ORION_TIMER
         select PCI
         select PCI_QUIRKS
         select PINCTRL_KIRKWOOD
-        select USE_OF
         help
           Say 'Y' here if you want your kernel to support boards based
           on the Marvell Kirkwood device tree.
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index b6885e42c0a0..e87f2a83d6bf 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void)
         if (!fpga_map_addr)
                 return -ENOMEM;
 
-        if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
+        if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
                 /* we dont have an DEBUG FPGA??? */
                 /* Depend on #defines!! default to strata boot return param */
                 goto unmap;
 
         /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
-        cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
+        cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
 
         /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
         if (omap_rev() >= OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 3ff32543493c..59cf310bc1e9 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
                 if (!dd)
                         return -EINVAL;
 
-                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);
                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
                                            dd->div1_mask);
                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 19f54d433490..0717dff1bc04 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk)
 {
         u32 pcc;
 
-        pcc = __raw_readl(prcm_clksrc_ctrl);
+        pcc = readl_relaxed(prcm_clksrc_ctrl);
 
-        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+        writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
 
         return 0;
 }
@@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk)
 {
         u32 pcc;
 
-        pcc = __raw_readl(prcm_clksrc_ctrl);
+        pcc = readl_relaxed(prcm_clksrc_ctrl);
 
-        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+        writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
 }
 
 unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index f467d072cd02..58dd3a9b726c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void)
 {
         u32 div;
 
-        div = __raw_readl(prcm_clksrc_ctrl);
+        div = readl_relaxed(prcm_clksrc_ctrl);
         div &= OMAP_SYSCLKDIV_MASK;
         div >>= OMAP_SYSCLKDIV_SHIFT;
 
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f17f00697cc0..82c37b1becc4 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -18,7 +18,6 @@
 
 #include "powerdomain.h"
 #include "clock.h"
-#include "omap_hwmod.h"
 
 /*
  * Clockdomain flags
@@ -98,6 +97,8 @@ struct clkdm_dep {
 /* Possible flags for struct clockdomain._flags */
 #define _CLKDM_FLAG_HWSUP_ENABLED               BIT(0)
 
+struct omap_hwmod;
+
 /**
  * struct clockdomain - OMAP clockdomain
  * @name: clockdomain name
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ce25abbcffae..8be6ea50c092 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -18,9 +18,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
 #include "prm2xxx.h"
 #include "cm.h"
 #include "cm2xxx.h"
@@ -390,7 +387,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
         tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
                 OMAP24XX_CLKSEL_DSS2_MASK;
         omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
-        if (cpu_is_omap2430())
+        if (mdm)
                 omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
 }
 
@@ -405,19 +402,11 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
 
 int __init omap2xxx_cm_init(void)
 {
-        if (!cpu_is_omap24xx())
-                return 0;
-
         return cm_register(&omap2xxx_cm_ll_data);
 }
 
 static void __exit omap2xxx_cm_exit(void)
 {
-        if (!cpu_is_omap24xx())
-                return;
-
-        /* Should never happen */
-        WARN(cm_unregister(&omap2xxx_cm_ll_data),
-             "%s: cm_ll_data function pointer mismatch\n", __func__);
+        cm_unregister(&omap2xxx_cm_ll_data);
 }
 __exitcall(omap2xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index bfbd16fe9151..72928a3ce2aa 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -52,12 +52,12 @@
 
 static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
 {
-        return __raw_readl(cm_base + module + idx);
+        return readl_relaxed(cm_base + module + idx);
 }
 
 static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-        __raw_writel(val, cm_base + module + idx);
+        writel_relaxed(val, cm_base + module + idx);
 }
 
 /* Read-modify-write a register in a CM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 40a22e5649ae..b3f99e93def0 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -50,13 +50,13 @@
 /* Read a register in a CM instance */
 static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
 {
-        return __raw_readl(cm_base + inst + idx);
+        return readl_relaxed(cm_base + inst + idx);
 }
 
 /* Write into a register in a CM */
 static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
 {
-        __raw_writel(val, cm_base + inst + idx);
+        writel_relaxed(val, cm_base + inst + idx);
 }
 
 /* Read-modify-write a register in CM */
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index cfb8891b0c0e..15a778ce7707 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,11 +17,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 
-#include "common.h"
-
 #include "cm.h"
 #include "cm-regbits-33xx.h"
-#include "iomap.h"
 
 /* CM base address */
 #define AM33XX_CM_BASE          0x44e00000
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index f6f028867bfe..129a4e7f6ef5 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -18,9 +18,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "cm.h"
 #include "cm3xxx.h"
@@ -388,7 +385,8 @@ void omap3_cm_save_context(void)
                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
         cm_context.iva2_cm_clksel2 =
                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
-        cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+        cm_context.cm_sysconfig =
+                omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
         cm_context.sgx_cm_clksel =
                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
         cm_context.dss_cm_clksel =
@@ -418,7 +416,8 @@ void omap3_cm_save_context(void)
                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
         cm_context.pll_cm_clken2 =
                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
-        cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
+        cm_context.cm_polctrl =
+                omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
         cm_context.iva2_cm_fclken =
                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
         cm_context.iva2_cm_clken_pll =
@@ -519,7 +518,8 @@ void omap3_cm_restore_context(void)
                                CM_CLKSEL1);
         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
                                CM_CLKSEL2);
-        __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
+        omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
+                               OMAP3430_CM_SYSCONFIG);
         omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
                                CM_CLKSEL);
         omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
@@ -547,7 +547,8 @@ void omap3_cm_restore_context(void)
                                OMAP3430ES2_CM_CLKSEL5);
         omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
                                OMAP3430ES2_CM_CLKEN2);
-        __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
+        omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
+                               OMAP3430_CM_POLCTRL);
         omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
                                CM_FCLKEN);
         omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
@@ -669,19 +670,11 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
 
 int __init omap3xxx_cm_init(void)
 {
-        if (!cpu_is_omap34xx())
-                return 0;
-
         return cm_register(&omap3xxx_cm_ll_data);
 }
 
 static void __exit omap3xxx_cm_exit(void)
 {
-        if (!cpu_is_omap34xx())
-                return;
-
-        /* Should never happen */
-        WARN(cm_unregister(&omap3xxx_cm_ll_data),
-             "%s: cm_ll_data function pointer mismatch\n", __func__);
+        cm_unregister(&omap3xxx_cm_ll_data);
 }
 __exitcall(omap3xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 8224c91b4d7a..7a16b5598127 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -29,9 +29,8 @@
  * These registers appear once per CM module.
  */
 
-#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3430_CM_SYSCONFIG           0x0010
+#define OMAP3430_CM_POLCTRL             0x009c
 
 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 535d66e2822c..fe5cc7bae489 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,35 +18,32 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "iomap.h"
-#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
 
 /* CM1 hardware module low-level functions */
 
 /* Read a register in CM1 */
 u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
+        return readl_relaxed(cm_base + inst + reg);
 }
 
 /* Write into a register in CM1 */
 void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
+        writel_relaxed(val, cm_base + inst + reg);
 }
 
 /* Read a register in CM2 */
 u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
+        return readl_relaxed(cm2_base + inst + reg);
 }
 
 /* Write into a register in CM2 */
 void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
+        writel_relaxed(val, cm2_base + inst + reg);
 }
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 40b3b5a84458..8f6c4710877e 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -14,11 +14,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/bug.h>
 
 #include "cm2xxx.h"
 #include "cm3xxx.h"
 #include "cm44xx.h"
-#include "common.h"
 
 /*
  * cm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f5c4731b6f06..12aca56942c0 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -21,8 +21,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "iomap.h"
-#include "common.h"
 #include "clockdomain.h"
 #include "cm.h"
 #include "cm1_44xx.h"
@@ -30,12 +28,18 @@
 #include "cm44xx.h"
 #include "cminst44xx.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
 #include "prcm-common.h"
 
+#define OMAP4430_IDLEST_SHIFT           16
+#define OMAP4430_IDLEST_MASK            (0x3 << 16)
+#define OMAP4430_CLKTRCTRL_SHIFT        0
+#define OMAP4430_CLKTRCTRL_MASK         (0x3 << 0)
+#define OMAP4430_MODULEMODE_SHIFT       0
+#define OMAP4430_MODULEMODE_MASK        (0x3 << 0)
+
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
  *
@@ -116,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_cm_bases[part]);
-        return __raw_readl(_cm_bases[part] + inst + idx);
+        return readl_relaxed(_cm_bases[part] + inst + idx);
 }
 
 /* Write into a register in a CM instance */
@@ -125,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_cm_bases[part]);
-        __raw_writel(val, _cm_bases[part] + inst + idx);
+        writel_relaxed(val, _cm_bases[part] + inst + idx);
 }
 
 /* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 44bb4d544dcf..751f3549bf6f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -151,32 +151,32 @@ void __iomem *omap_ctrl_base_get(void)
 
 u8 omap_ctrl_readb(u16 offset)
 {
-        return __raw_readb(OMAP_CTRL_REGADDR(offset));
+        return readb_relaxed(OMAP_CTRL_REGADDR(offset));
 }
 
 u16 omap_ctrl_readw(u16 offset)
 {
-        return __raw_readw(OMAP_CTRL_REGADDR(offset));
+        return readw_relaxed(OMAP_CTRL_REGADDR(offset));
 }
 
 u32 omap_ctrl_readl(u16 offset)
 {
-        return __raw_readl(OMAP_CTRL_REGADDR(offset));
+        return readl_relaxed(OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+        writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+        writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
 }
 
 void omap_ctrl_writel(u32 val, u16 offset)
 {
-        __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+        writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
 }
 
 /*
@@ -188,12 +188,12 @@ void omap_ctrl_writel(u32 val, u16 offset)
 
 u32 omap4_ctrl_pad_readl(u16 offset)
 {
-        return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+        return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 }
 
 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 {
-        __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+        writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
 }
 
 #ifdef CONFIG_ARCH_OMAP3
@@ -222,7 +222,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
          *
          * XXX This should use some omap_ctrl_writel()-type function
          */
-        __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
+        writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 }
 
 #endif
@@ -285,7 +285,7 @@ void omap3_clear_scratchpad_contents(void)
         if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
             OMAP3430_GLOBAL_COLD_RST_MASK) {
                 for ( ; offset <= max_offset; offset += 0x4)
-                        __raw_writel(0x0, (v_addr + offset));
+                        writel_relaxed(0x0, (v_addr + offset));
                 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
                                            OMAP3430_GR_MOD,
                                            OMAP3_PRM_RSTST_OFFSET);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 5689c88d986d..a6d2cf1f8d02 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -91,7 +91,7 @@ static inline void dma_write(u32 val, int reg, int lch)
         addr += reg_map[reg].offset;
         addr += reg_map[reg].stride * lch;
 
-        __raw_writel(val, addr);
+        writel_relaxed(val, addr);
 }
 
 static inline u32 dma_read(int reg, int lch)
@@ -101,7 +101,7 @@ static inline u32 dma_read(int reg, int lch)
         addr += reg_map[reg].offset;
         addr += reg_map[reg].stride * lch;
 
-        return __raw_readl(addr);
+        return readl_relaxed(addr);
 }
 
 static void omap2_clear_dma(int lch)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9fe8c949305c..852b19a367f0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -170,12 +170,12 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 
 static void gpmc_write_reg(int idx, u32 val)
 {
-        __raw_writel(val, gpmc_base + idx);
+        writel_relaxed(val, gpmc_base + idx);
 }
 
 static u32 gpmc_read_reg(int idx)
 {
-        return __raw_readl(gpmc_base + idx);
+        return readl_relaxed(gpmc_base + idx);
 }
 
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
@@ -183,7 +183,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
         void __iomem *reg_addr;
 
         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        __raw_writel(val, reg_addr);
+        writel_relaxed(val, reg_addr);
 }
 
 static u32 gpmc_cs_read_reg(int cs, int idx)
@@ -191,7 +191,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx)
         void __iomem *reg_addr;
 
         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        return __raw_readl(reg_addr);
+        return readl_relaxed(reg_addr);
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 157412e4273a..f61f1bf68df4 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -94,7 +94,7 @@ EXPORT_SYMBOL(omap_type);
 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
 
-#define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
+#define read_tap_reg(reg)       readl_relaxed(tap_base  + (reg))
 
 struct omap_id {
         u16     hawkeye;        /* Silicon type (Hawkeye id) */
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6037a9a01ed5..35b8590c322e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -83,12 +83,12 @@ struct omap3_intc_regs {
 
 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
 {
-        __raw_writel(val, bank->base_reg + reg);
+        writel_relaxed(val, bank->base_reg + reg);
 }
 
 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
 {
-        return __raw_readl(bank->base_reg + reg);
+        return readl_relaxed(bank->base_reg + reg);
 }
 
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 48094b58c88f..fd88edeb027f 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -70,18 +70,18 @@ struct omap_mux_partition *omap_mux_get(const char *name)
 u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
 {
         if (partition->flags & OMAP_MUX_REG_8BIT)
-                return __raw_readb(partition->base + reg);
+                return readb_relaxed(partition->base + reg);
         else
-                return __raw_readw(partition->base + reg);
+                return readw_relaxed(partition->base + reg);
 }
 
 void omap_mux_write(struct omap_mux_partition *partition, u16 val,
                            u16 reg)
 {
         if (partition->flags & OMAP_MUX_REG_8BIT)
-                __raw_writeb(val, partition->base + reg);
+                writeb_relaxed(val, partition->base + reg);
         else
-                __raw_writew(val, partition->base + reg);
+                writew_relaxed(val, partition->base + reg);
 }
 
 void omap_mux_write_array(struct omap_mux_partition *partition,
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 458f72f9dc8f..971791fe9a3f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -39,7 +39,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
                 if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
                         pr_err("Secure clear status failed\n");
         } else {
-                __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+                writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0);
         }
 
 
@@ -53,7 +53,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
                         boot_cpu = omap_read_auxcoreboot0();
                 else
                         boot_cpu =
-                                __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+                                readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5;
 
                 if (boot_cpu == smp_processor_id()) {
                         /*
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 667915d236f3..eb76e47091ad 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -116,7 +116,7 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 {
         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 
-        __raw_writel(addr, pm_info->wkup_sar_addr);
+        writel_relaxed(addr, pm_info->wkup_sar_addr);
 }
 
 /*
@@ -141,7 +141,7 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
                 break;
         }
 
-        __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+        writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
 }
 
 /* Helper functions for MPUSS OSWR */
@@ -179,7 +179,7 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 {
         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 
-        __raw_writel(save_state, pm_info->l2x0_sar_addr);
+        writel_relaxed(save_state, pm_info->l2x0_sar_addr);
 }
 
 /*
@@ -192,10 +192,10 @@ static void save_l2x0_context(void)
         u32 val;
         void __iomem *l2x0_base = omap4_get_l2cache_base();
         if (l2x0_base) {
-                val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
-                __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
-                val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
-                __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+                val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+                writel_relaxed(val, sar_base + L2X0_AUXCTRL_OFFSET);
+                val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+                writel_relaxed(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
         }
 }
 #else
@@ -386,9 +386,9 @@ int __init omap4_mpuss_init(void)
 
         /* Save device type on scratchpad for low level code to use */
         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
-                __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+                writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
         else
-                __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+                writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
 
         save_l2x0_context();
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 17550aa39d0f..256e84ef0f67 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -99,7 +99,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
         if (omap_secure_apis_support())
                 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
         else
-                __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+                writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
 
         if (!cpu1_clkdm && !cpu1_pwrdm) {
                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@@ -227,8 +227,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
         if (omap_secure_apis_support())
                 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
         else
-                __raw_writel(virt_to_phys(omap5_secondary_startup),
-                                                base + OMAP_AUX_CORE_BOOT_1);
+                writel_relaxed(virt_to_phys(omap5_secondary_startup),
+                               base + OMAP_AUX_CORE_BOOT_1);
 
 }
 
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 693fe486e917..37843a7d3639 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -60,19 +60,19 @@ static unsigned int omap_secure_apis;
  */
 static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
 {
-        return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+        return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
                                 (cpu * CPU_ENA_OFFSET) + (idx * 4));
 }
 
 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
 {
-        __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+        writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
                                 (cpu * CPU_ENA_OFFSET) + (idx * 4));
 }
 
 static inline void sar_writel(u32 val, u32 offset, u8 idx)
 {
-        __raw_writel(val, sar_base + offset + (idx * 4));
+        writel_relaxed(val, sar_base + offset + (idx * 4));
 }
 
 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
@@ -231,21 +231,21 @@ static inline void omap4_irq_save_context(void)
         }
 
         /* Save AuxBoot* registers */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
-        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
+        writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
 
         /* Save SyncReq generation logic */
-        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
-        __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
-        __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+        val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+        writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+        val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+        writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
 
         /* Set the Backup Bit Mask status */
-        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+        writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
 
 }
 
@@ -264,15 +264,15 @@ static inline void omap5_irq_save_context(void)
         }
 
         /* Save AuxBoot* registers */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
 
         /* Set the Backup Bit Mask status */
-        val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+        val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+        writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
 
 }
 
@@ -306,9 +306,9 @@ static void irq_sar_clear(void)
         if (soc_is_omap54xx())
                 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
 
-        val = __raw_readl(sar_base + offset);
+        val = readl_relaxed(sar_base + offset);
         val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + offset);
+        writel_relaxed(val, sar_base + offset);
 }
 
 /*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 95e171a055f3..99b0154493a4 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -125,25 +125,25 @@ void __init gic_init_irq(void)
 void gic_dist_disable(void)
 {
         if (gic_dist_base_addr)
-                __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
+                writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
 }
 
 void gic_dist_enable(void)
 {
         if (gic_dist_base_addr)
-                __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
+                writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
 }
 
 bool gic_dist_disabled(void)
 {
-        return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
+        return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
 }
 
 void gic_timer_retrigger(void)
 {
-        u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
-        u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
-        u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+        u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
+        u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
+        u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
 
         if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
                 /*
@@ -151,11 +151,11 @@ void gic_timer_retrigger(void)
                  * disabled.  Ack the pending interrupt, and retrigger it.
                  */
                 pr_warn("%s: lost localtimer interrupt\n", __func__);
-                __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+                writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
                 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
-                        __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
+                        writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
                         twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
-                        __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
+                        writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
                 }
         }
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 66c60fe1104c..f7bb435bb543 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -72,7 +72,7 @@
  *            | (../mach-omap2/omap_hwmod*)   |
  *            +-------------------------------+
  *            | OMAP clock/PRCM/register fns  |
- *            | (__raw_{read,write}l, clk*)   |
+ *            | ({read,write}l_relaxed, clk*) |
  *            +-------------------------------+
  *
  * Device drivers should not contain any OMAP-specific code or data in
@@ -3230,17 +3230,17 @@ static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
 {
         if (oh->flags & HWMOD_16BIT_REG)
-                return __raw_readw(oh->_mpu_rt_va + reg_offs);
+                return readw_relaxed(oh->_mpu_rt_va + reg_offs);
         else
-                return __raw_readl(oh->_mpu_rt_va + reg_offs);
+                return readl_relaxed(oh->_mpu_rt_va + reg_offs);
 }
 
 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 {
         if (oh->flags & HWMOD_16BIT_REG)
-                __raw_writew(v, oh->_mpu_rt_va + reg_offs);
+                writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
         else
-                __raw_writel(v, oh->_mpu_rt_va + reg_offs);
+                writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
 }
 
 /**
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 0f178623e7da..a579b89ce9b7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -24,6 +24,7 @@
 #include "prm33xx.h"
 #include "omap_hwmod_33xx_43xx_common_data.h"
 #include "prcm43xx.h"
+#include "common.h"
 
 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index eb8a25de67ed..50640b38f0bf 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -57,7 +57,7 @@ static int __init omap4430_phy_power_down(void)
         }
 
         /* Power down the phy */
-        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+        writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 
         iounmap(ctrl_base);
 
@@ -162,7 +162,7 @@ void ti81xx_musb_phy_power(u8 on)
                 return;
         }
 
-        usbphycfg = __raw_readl(scm_base + USBCTRL0);
+        usbphycfg = readl_relaxed(scm_base + USBCTRL0);
 
         if (on) {
                 if (cpu_is_ti816x()) {
@@ -181,7 +181,7 @@ void ti81xx_musb_phy_power(u8 on)
                         usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
 
         }
-        __raw_writel(usbphycfg, scm_base + USBCTRL0);
+        writel_relaxed(usbphycfg, scm_base + USBCTRL0);
 
         iounmap(scm_base);
 }
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index c0aeabfcf009..c40e5f009826 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -17,7 +17,6 @@
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 93a2a6e4260f..faebd5f076af 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -32,6 +32,7 @@
 
 #include "powerdomain.h"
 #include "clockdomain.h"
+#include "voltage.h"
 
 #include "soc.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index da5a59ae77b6..f4727117f6cc 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -21,8 +21,6 @@
 #include <linux/list.h>
 #include <linux/spinlock.h>
 
-#include "voltage.h"
-
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF         0x0
 #define PWRDM_POWER_RET         0x1
@@ -75,6 +73,7 @@
 
 struct clockdomain;
 struct powerdomain;
+struct voltagedomain;
 
 /**
  * struct powerdomain - OMAP powerdomain
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0e841fd9498a..a8e4b582c527 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -428,6 +428,28 @@
 #define MAX_IOPAD_LATCH_TIME                    100
 # ifndef __ASSEMBLER__
 
+#include <linux/delay.h>
+
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
+
 /**
  * struct omap_prcm_irq - describes a PRCM interrupt bit
  * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
@@ -458,6 +480,7 @@ struct omap_prcm_irq {
  * @ocp_barrier: fn ptr to force buffered PRM writes to complete
  * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
  * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @reconfigure_io_chain: fn ptr to reconfigure IO chain
  * @saved_mask: IRQENABLE regs are saved here during suspend
  * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
  * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
@@ -479,6 +502,7 @@ struct omap_prcm_irq_setup {
         void (*ocp_barrier)(void);
         void (*save_and_clear_irqen)(u32 *saved_mask);
         void (*restore_irqen)(u32 *saved_mask);
+        void (*reconfigure_io_chain)(void);
         u32 *saved_mask;
         u32 *priority_mask;
         int base_irq;
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index c30e44a7fab0..cdbee6326d29 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -30,12 +30,12 @@ void __iomem *prcm_mpu_base;
 
 u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+        return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
 }
 
 void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+        writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
 }
 
 u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 059bd4f49035..ac9cb4550239 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -26,7 +26,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 
 #include "prcm_mpu_44xx_54xx.h"
-#include "common.h"
 
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
 
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 623db40fdbbd..48480d557b61 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,10 +17,18 @@
 
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
+extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
 int of_prcm_init(void);
 # endif
 
+/*
+ * prm_features flag values
+ *
+ * PRM_HAS_IO_WAKEUP: has IO wakeup capability
+ * PRM_HAS_VOLTAGE: has voltage domains
+ */
+#define PRM_HAS_IO_WAKEUP       (1 << 0)
 
 /*
  * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -118,6 +126,7 @@ struct prm_reset_src_map {
  * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
  * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
  * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
+ * @late_init: ptr to the late init function
  *
  * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
  * deprecated.
@@ -126,6 +135,7 @@ struct prm_ll_data {
         u32 (*read_reset_sources)(void);
         bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
         void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
+        int (*late_init)(void);
 };
 
 extern int prm_register(struct prm_ll_data *pld);
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 418de9c3b319..a3a3cca2bcc4 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -18,9 +18,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 
-#include "soc.h"
-#include "common.h"
-#include "vp.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include "prm2xxx.h"
@@ -201,19 +198,11 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
 
 int __init omap2xxx_prm_init(void)
 {
-        if (!cpu_is_omap24xx())
-                return 0;
-
         return prm_register(&omap2xxx_prm_ll_data);
 }
 
 static void __exit omap2xxx_prm_exit(void)
 {
-        if (!cpu_is_omap24xx())
-                return;
-
-        /* Should never happen */
-        WARN(prm_unregister(&omap2xxx_prm_ll_data),
-             "%s: prm_ll_data function pointer mismatch\n", __func__);
+        prm_unregister(&omap2xxx_prm_ll_data);
 }
 __exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 3194dd87e0e4..d2cb6365716f 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -27,7 +27,7 @@
 
 /*
  * OMAP2-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
+ * Use {read,write}l_relaxed() with these registers.
  *
  * With a few exceptions, these are the register names beginning with
  * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 947f6adfed0c..c13b4e293ffa 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -16,7 +16,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
 #include "powerdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 9624b40836d4..1a3a96392b97 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -55,12 +55,12 @@
 /* Power/reset management domain register get/set */
 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
 {
-        return __raw_readl(prm_base + module + idx);
+        return readl_relaxed(prm_base + module + idx);
 }
 
 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-        __raw_writel(val, prm_base + module + idx);
+        writel_relaxed(val, prm_base + module + idx);
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 720440737744..62709cd2f9c5 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,7 +19,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
 #include "powerdomain.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
@@ -27,13 +26,13 @@
 /* Read a register in a PRM instance */
 u32 am33xx_prm_read_reg(s16 inst, u16 idx)
 {
-        return __raw_readl(prm_base + inst + idx);
+        return readl_relaxed(prm_base + inst + idx);
 }
 
 /* Write into a register in a PRM instance */
 void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
 {
-        __raw_writel(val, prm_base + inst + idx);
+        writel_relaxed(val, prm_base + inst + idx);
 }
 
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 7721990d2006..4bd7a2dca8af 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -43,6 +43,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
         .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
         .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
         .restore_irqen          = &omap3xxx_prm_restore_irqen,
+        .reconfigure_io_chain   = &omap3xxx_prm_reconfigure_io_chain,
 };
 
 /*
@@ -246,7 +247,7 @@ void omap3xxx_prm_reconfigure_io_chain(void)
  */
 static void __init omap3xxx_prm_enable_io_wakeup(void)
 {
-        if (omap3_has_io_wakeup())
+        if (prm_features & PRM_HAS_IO_WAKEUP)
                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
                                            PM_WKEN);
 }
@@ -400,23 +401,26 @@ struct pwrdm_ops omap3_pwrdm_operations = {
  *
  */
 
+static int omap3xxx_prm_late_init(void);
+
 static struct prm_ll_data omap3xxx_prm_ll_data = {
         .read_reset_sources = &omap3xxx_prm_read_reset_sources,
+        .late_init = &omap3xxx_prm_late_init,
 };
 
 int __init omap3xxx_prm_init(void)
 {
-        if (!cpu_is_omap34xx())
-                return 0;
+        if (omap3_has_io_wakeup())
+                prm_features |= PRM_HAS_IO_WAKEUP;
 
         return prm_register(&omap3xxx_prm_ll_data);
 }
 
-static int __init omap3xxx_prm_late_init(void)
+static int omap3xxx_prm_late_init(void)
 {
         int ret;
 
-        if (!cpu_is_omap34xx())
+        if (!(prm_features & PRM_HAS_IO_WAKEUP))
                 return 0;
 
         omap3xxx_prm_enable_io_wakeup();
@@ -427,15 +431,9 @@ static int __init omap3xxx_prm_late_init(void)
 
         return ret;
 }
-omap_subsys_initcall(omap3xxx_prm_late_init);
 
 static void __exit omap3xxx_prm_exit(void)
 {
-        if (!cpu_is_omap34xx())
-                return;
-
-        /* Should never happen */
-        WARN(prm_unregister(&omap3xxx_prm_ll_data),
-             "%s: prm_ll_data function pointer mismatch\n", __func__);
+        prm_unregister(&omap3xxx_prm_ll_data);
 }
 __exitcall(omap3xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index f8eb83323b1a..1dacfc5b1959 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -26,7 +26,7 @@
 
 /*
  * OMAP3-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
+ * Use {read,write}l_relaxed() with these registers.
  *
  * With a few exceptions, these are the register names beginning with
  * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 03a603476cfc..a7f6ea27180a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -47,6 +47,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
         .restore_irqen          = &omap44xx_prm_restore_irqen,
+        .reconfigure_io_chain   = &omap44xx_prm_reconfigure_io_chain,
 };
 
 /*
@@ -81,13 +82,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
 /* Read a register in a CM/PRM instance in the PRM module */
 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(prm_base + inst + reg);
+        return readl_relaxed(prm_base + inst + reg);
 }
 
 /* Write into a register in a CM/PRM instance in the PRM module */
 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, prm_base + inst + reg);
+        writel_relaxed(val, prm_base + inst + reg);
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
@@ -649,6 +650,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
         .pwrdm_has_voltdm       = omap4_check_vcvp,
 };
 
+static int omap44xx_prm_late_init(void);
+
 /*
  * XXX document
  */
@@ -656,34 +659,29 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
         .read_reset_sources = &omap44xx_prm_read_reset_sources,
         .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
         .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
+        .late_init = &omap44xx_prm_late_init,
 };
 
 int __init omap44xx_prm_init(void)
 {
-        if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
-                return 0;
+        if (cpu_is_omap44xx())
+                prm_features |= PRM_HAS_IO_WAKEUP;
 
         return prm_register(&omap44xx_prm_ll_data);
 }
 
-static int __init omap44xx_prm_late_init(void)
+static int omap44xx_prm_late_init(void)
 {
-        if (!cpu_is_omap44xx())
+        if (!(prm_features & PRM_HAS_IO_WAKEUP))
                 return 0;
 
         omap44xx_prm_enable_io_wakeup();
 
         return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 }
-omap_subsys_initcall(omap44xx_prm_late_init);
 
 static void __exit omap44xx_prm_exit(void)
 {
-        if (!cpu_is_omap44xx())
-                return;
-
-        /* Should never happen */
-        WARN(prm_unregister(&omap44xx_prm_ll_data),
-             "%s: prm_ll_data function pointer mismatch\n", __func__);
+        prm_unregister(&omap44xx_prm_ll_data);
 }
 __exitcall(omap44xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b4c4ab9c8044..25e8b8232115 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -62,6 +62,8 @@ static struct omap_prcm_irq_setup *prcm_irq_setup;
 /* prm_base: base virtual address of the PRM IP block */
 void __iomem *prm_base;
 
+u16 prm_features;
+
 /*
  * prm_ll_data: function pointers to SoC-specific implementations of
  * common PRM functions
@@ -330,12 +332,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 
         if (of_have_populated_dt()) {
                 int irq = omap_prcm_event_to_irq("io");
-                if (cpu_is_omap34xx())
-                        omap_pcs_legacy_init(irq,
-                                omap3xxx_prm_reconfigure_io_chain);
-                else
-                        omap_pcs_legacy_init(irq,
-                                omap44xx_prm_reconfigure_io_chain);
+                omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
         }
 
         return 0;
@@ -530,3 +527,11 @@ int __init of_prcm_init(void)
 
         return 0;
 }
+
+static int __init prm_late_init(void)
+{
+        if (prm_ll_data->late_init)
+                return prm_ll_data->late_init();
+        return 0;
+}
+subsys_initcall(prm_late_init);
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 05fcf6de44ee..69f0dd08629c 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -49,7 +49,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_prm_bases[part]);
-        return __raw_readl(_prm_bases[part] + inst + idx);
+        return readl_relaxed(_prm_bases[part] + inst + idx);
 }
 
 /* Write into a register in a PRM instance */
@@ -58,7 +58,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_prm_bases[part]);
-        __raw_writel(val, _prm_bases[part] + inst + idx);
+        writel_relaxed(val, _prm_bases[part] + inst + idx);
 }
 
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 446aa13511fd..645a2a46b213 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -31,24 +31,24 @@ extern void __iomem *omap2_sms_base;
 
 static inline void sdrc_write_reg(u32 val, u16 reg)
 {
-        __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+        writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
 }
 
 static inline u32 sdrc_read_reg(u16 reg)
 {
-        return __raw_readl(OMAP_SDRC_REGADDR(reg));
+        return readl_relaxed(OMAP_SDRC_REGADDR(reg));
 }
 
 /* SMS global register get/set */
 
 static inline void sms_write_reg(u32 val, u16 reg)
 {
-        __raw_writel(val, OMAP_SMS_REGADDR(reg));
+        writel_relaxed(val, OMAP_SMS_REGADDR(reg));
 }
 
 static inline u32 sms_read_reg(u16 reg)
 {
-        return __raw_readl(OMAP_SMS_REGADDR(reg));
+        return readl_relaxed(OMAP_SMS_REGADDR(reg));
 }
 
 extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 907291714643..ae3f1553158d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -103,9 +103,9 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
          * prm2xxx.c function
          */
         if (cpu_is_omap2420())
-                __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
+                writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
         else
-                __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
+                writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
         omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
         curr_perf_level = level;
         local_irq_restore(flags);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d7bc33f15344..1b91ef0c182a 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -57,7 +57,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 
                 /*
                  * In OMAP4 the efuse registers are 24 bit aligned.
-                 * A __raw_readl will fail for non-32 bit aligned address
+                 * A readl_relaxed will fail for non-32 bit aligned address
                  * and hence the 8-bit read and shift.
                  */
                 if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 4bd096836235..ddf1818af228 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -70,16 +70,16 @@ static int is_sram_locked(void)
         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
                 /* RAMFW: R/W access to all initiators for all qualifier sets */
                 if (cpu_is_omap242x()) {
-                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+                        writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+                        writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
+                        writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
                 }
                 if (cpu_is_omap34xx()) {
-                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
-                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
-                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
+                        writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+                        writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
+                        writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+                        writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
+                        writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
                 }
                 return 0;
         } else
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 842b81f31957..43d03fbf4c0b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -546,15 +546,15 @@ static void __init realtime_counter_init(void)
         }
 
         /* Program numerator and denumerator registers */
-        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+        reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
                         NUMERATOR_DENUMERATOR_MASK;
         reg |= num;
-        __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+        writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 
-        reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
+        reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
                         NUMERATOR_DENUMERATOR_MASK;
         reg |= den;
-        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+        writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 
         arch_timer_freq = (rate / den) * num;
         set_cntfreq();
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 49ac7977e03e..267f204559c3 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -462,7 +462,7 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
         val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
                 OMAP4_DOWNTIME_MASK);
 
-        __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
+        writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
 }
 
 /* OMAP4 specific voltage init functions */
@@ -584,7 +584,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
         val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
 
         /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
+        writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
                                 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
 
         /* HSSCLH can always be zero */
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index d15c7bbab8e2..97d6607d447a 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -49,12 +49,12 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
         }
 
         /* sequence required to disable watchdog */
-        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+        writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
+        while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
                 cpu_relax();
 
-        __raw_writel(0x5555, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+        writel_relaxed(0x5555, base + OMAP_WDT_SPR);
+        while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
                 cpu_relax();
 
         return 0;
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 4887a2a4c698..3dffcb2d714e 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -36,27 +36,33 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
 
         if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
                 /*
-                 * Writing 1 to this bit resets corresponding block. Writing 0 to this
-                 * bit de-asserts reset signal of the corresponding block.
-                 * datasheet doesn't require explicit delay between the set and clear
-                 * of reset bit. it could be shorter if tests pass.
+                 * Writing 1 to this bit resets corresponding block.
+                 * Writing 0 to this bit de-asserts reset signal of the
+                 * corresponding block. datasheet doesn't require explicit
+                 * delay between the set and clear of reset bit. it could
+                 * be shorter if tests pass.
                  */
-                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
+                writel(readl(sirfsoc_rstc_base +
+                        (reset_bit / 32) * 4) | (1 << reset_bit),
                         sirfsoc_rstc_base + (reset_bit / 32) * 4);
-                msleep(10);
-                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
+                msleep(20);
+                writel(readl(sirfsoc_rstc_base +
+                        (reset_bit / 32) * 4) & ~(1 << reset_bit),
                         sirfsoc_rstc_base + (reset_bit / 32) * 4);
         } else {
                 /*
                  * For MARCO and POLO
-                 * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
-                 * register de-asserts reset signal of the corresponding block.
-                 * datasheet doesn't require explicit delay between the set and clear
-                 * of reset bit. it could be shorter if tests pass.
+                 * Writing 1 to SET register resets corresponding block.
+                 * Writing 1 to CLEAR register de-asserts reset signal of the
+                 * corresponding block.
+                 * datasheet doesn't require explicit delay between the set and
+                 * clear of reset bit. it could be shorter if tests pass.
                  */
-                writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
-                msleep(10);
-                writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+                writel(1 << reset_bit,
+                        sirfsoc_rstc_base + (reset_bit / 32) * 8);
+                msleep(20);
+                writel(1 << reset_bit,
+                        sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
         }
 
         mutex_unlock(&rstc_lock);
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index a028be234334..6aa22147cace 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -3,8 +3,6 @@ config ARCH_QCOM
         select ARCH_REQUIRE_GPIOLIB
         select ARM_GIC
         select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select HAVE_SMP
         select QCOM_SCM if SMP
         help
           Support for Qualcomm's devicetree based systems.
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 1d5ee5c9a1dc..960b8dd78c44 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -148,6 +148,21 @@ struct platform_device realview_cf_device = {
         },
 };
 
+static struct resource realview_leds_resources[] = {
+        {
+                .start  = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET,
+                .end    = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET + 4,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device realview_leds_device = {
+        .name           = "versatile-leds",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(realview_leds_resources),
+        .resource       = realview_leds_resources,
+};
+
 static struct resource realview_i2c_resource = {
         .start          = REALVIEW_I2C_BASE,
         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 602ca5ec52c5..13dc830ef469 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -37,6 +37,7 @@ struct machine_desc;
 
 extern struct platform_device realview_flash_device;
 extern struct platform_device realview_cf_device;
+extern struct platform_device realview_leds_device;
 extern struct platform_device realview_i2c_device;
 extern struct mmci_platform_data realview_mmc0_plat_data;
 extern struct mmci_platform_data realview_mmc1_plat_data;
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index c85ddb2a0ad0..6bb070e80128 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -452,6 +452,7 @@ static void __init realview_eb_init(void)
         realview_flash_register(&realview_eb_flash_resource, 1);
         platform_device_register(&realview_i2c_device);
         platform_device_register(&char_lcd_device);
+        platform_device_register(&realview_leds_device);
         eth_device_register();
         realview_usb_register(realview_eb_isp1761_resources);
 
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index c5eade76461b..173f2c15de49 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -367,6 +367,7 @@ static void __init realview_pb1176_init(void)
         realview_usb_register(realview_pb1176_isp1761_resources);
         platform_device_register(&pmu_device);
         platform_device_register(&char_lcd_device);
+        platform_device_register(&realview_leds_device);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index f4b0962578fe..bde7e6b1fd44 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -347,6 +347,7 @@ static void __init realview_pb11mp_init(void)
         realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
         platform_device_register(&realview_i2c_device);
         platform_device_register(&realview_cf_device);
+        platform_device_register(&realview_leds_device);
         realview_usb_register(realview_pb11mp_isp1761_resources);
         platform_device_register(&pmu_device);
 
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 10a3e1d76891..4e57a8599265 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -289,6 +289,7 @@ static void __init realview_pba8_init(void)
         realview_eth_register(NULL, realview_pba8_smsc911x_resources);
         platform_device_register(&realview_i2c_device);
         platform_device_register(&realview_cf_device);
+        platform_device_register(&realview_leds_device);
         realview_usb_register(realview_pba8_isp1761_resources);
         platform_device_register(&pmu_device);
 
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 9d75493e3f0c..72c96caebefa 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -385,6 +385,7 @@ static void __init realview_pbx_init(void)
         realview_eth_register(NULL, realview_pbx_smsc911x_resources);
         platform_device_register(&realview_i2c_device);
         platform_device_register(&realview_cf_device);
+        platform_device_register(&realview_leds_device);
         realview_usb_register(realview_pbx_isp1761_resources);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 40cf50b9940c..45a7026e9419 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,18 @@ config PLAT_S3C24XX
         help
           Base platform code for any Samsung S3C24XX device
 
+config S3C2410_COMMON_CLK
+        bool
+        help
+          Build the s3c2410 clock driver based on the common clock framework.
+
+config S3C2410_COMMON_DCLK
+        bool
+        select REGMAP_MMIO
+        help
+          Temporary symbol to build the dclk driver based on the common clock
+          framework.
+
 menu "SAMSUNG S3C24XX SoCs Support"
 
 comment "S3C24XX SoCs"
@@ -25,9 +37,9 @@ comment "S3C24XX SoCs"
 config CPU_S3C2410
         bool "SAMSUNG S3C2410"
         default y
+        select COMMON_CLK
         select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2410
-        select S3C2410_CLOCK
+        select S3C2410_COMMON_CLK
         select S3C2410_DMA if S3C24XX_DMA
         select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
         select S3C2410_PM if PM
@@ -38,8 +50,9 @@ config CPU_S3C2410
 
 config CPU_S3C2412
         bool "SAMSUNG S3C2412"
+        select COMMON_CLK
         select CPU_ARM926T
-        select CPU_LLSERIAL_S3C2440
+        select S3C2412_COMMON_CLK
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
         help
@@ -47,20 +60,19 @@ config CPU_S3C2412
 
 config CPU_S3C2416
         bool "SAMSUNG S3C2416/S3C2450"
+        select COMMON_CLK
         select CPU_ARM926T
-        select CPU_LLSERIAL_S3C2440
         select S3C2416_PM if PM
-        select S3C2443_COMMON
+        select S3C2443_COMMON_CLK
         select S3C2443_DMA if S3C24XX_DMA
-        select SAMSUNG_CLKSRC
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
 config CPU_S3C2440
         bool "SAMSUNG S3C2440"
+        select COMMON_CLK
         select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2440
-        select S3C2410_CLOCK
+        select S3C2410_COMMON_CLK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
         help
@@ -68,9 +80,9 @@ config CPU_S3C2440
 
 config CPU_S3C2442
         bool "SAMSUNG S3C2442"
+        select COMMON_CLK
         select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2440
-        select S3C2410_CLOCK
+        select S3C2410_COMMON_CLK
         select S3C2410_DMA if S3C24XX_DMA
         select S3C2410_PM if PM
         help
@@ -83,27 +95,15 @@ config CPU_S3C244X
 
 config CPU_S3C2443
         bool "SAMSUNG S3C2443"
+        select COMMON_CLK
         select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2440
-        select S3C2443_COMMON
+        select S3C2443_COMMON_CLK
         select S3C2443_DMA if S3C24XX_DMA
-        select SAMSUNG_CLKSRC
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
 # common code
 
-config S3C2410_CLOCK
-        bool
-        help
-          Clock code for the S3C2410, and similar processors which
-          is currently includes the S3C2410, S3C2440, S3C2442.
-
-config S3C24XX_DCLK
-        bool
-        help
-          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
-
 config S3C24XX_SMDK
         bool
         help
@@ -158,28 +158,6 @@ config S3C2410_PM
         help
           Power Management code common to S3C2410 and better
 
-# low-level serial option nodes
-
-config CPU_LLSERIAL_S3C2410_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
-
-config CPU_LLSERIAL_S3C2440_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
-
-config CPU_LLSERIAL_S3C2410
-        bool
-        help
-          Selected if there is an S3C2410 (or register compatible) serial
-          low-level implementation needed
-
-config CPU_LLSERIAL_S3C2440
-        bool
-        help
-          Selected if there is an S3C2440 (or register compatible) serial
-          low-level implementation needed
-
 config S3C24XX_PLL
         bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
         depends on ARM_S3C24XX_CPUFREQ
@@ -258,8 +236,8 @@ config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select ISA
         select MACH_BAST_IDE
+        select S3C2410_COMMON_DCLK if COMMON_CLK
         select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
-        select S3C24XX_DCLK
         select S3C24XX_SIMTEC_NOR
         select S3C24XX_SIMTEC_PM if PM
         select S3C24XX_SIMTEC_USB
@@ -340,7 +318,7 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
         bool "Thorcom VR1000"
         select MACH_BAST_IDE
-        select S3C24XX_DCLK
+        select S3C2410_COMMON_DCLK if COMMON_CLK
         select S3C24XX_SIMTEC_NOR
         select S3C24XX_SIMTEC_PM if PM
         select S3C24XX_SIMTEC_USB
@@ -359,6 +337,11 @@ config S3C2412_PM_SLEEP
 
 if CPU_S3C2412
 
+config S3C2412_COMMON_CLK
+        bool
+        help
+          Build the s3c2412 clock driver based on the common clock framework.
+
 config CPU_S3C2412_ONLY
         bool
         depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
@@ -519,8 +502,8 @@ comment "S3C2440 Boards"
 config MACH_ANUBIS
         bool "Simtec Electronics ANUBIS"
         select HAVE_PATA_PLATFORM
+        select S3C2410_COMMON_DCLK if COMMON_CLK
         select S3C2440_XTAL_12000000
-        select S3C24XX_DCLK
         select S3C24XX_SIMTEC_PM if PM
         select S3C_DEV_USB_HOST
         help
@@ -558,9 +541,9 @@ config MACH_NEXCODER_2440
 
 config MACH_OSIRIS
         bool "Simtec IM2440D20 (OSIRIS) module"
+        select S3C2410_COMMON_DCLK if COMMON_CLK
         select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
         select S3C2440_XTAL_12000000
-        select S3C24XX_DCLK
         select S3C24XX_SIMTEC_PM if PM
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
@@ -629,9 +612,9 @@ config MACH_RX1950
         bool "HP iPAQ rx1950"
         select I2C
         select PM_H1940 if PM
+        select S3C2410_COMMON_DCLK if COMMON_CLK
         select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
         select S3C2440_XTAL_16934400
-        select S3C24XX_DCLK
         select S3C24XX_PWM
         select S3C_DEV_NAND
         help
@@ -641,11 +624,11 @@ endif	# CPU_S3C2442
 
 if CPU_S3C2443 || CPU_S3C2416
 
-config S3C2443_COMMON
+config S3C2443_COMMON_CLK
         bool
         help
-          Common code for the S3C2443 and similar processors, which includes
-          the S3C2416 and S3C2450.
+          Temporary symbol to build the clock driver based on the common clock
+          framework.
 
 config S3C2443_DMA
         bool
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 7f54e5b954ca..2235d0d3b38d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -21,22 +21,22 @@ obj-$(CONFIG_S3C2410_DMA)	+= dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
 
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
 
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o clock-s3c2443.o
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o
 
 # PM
 
@@ -44,16 +44,13 @@ obj-$(CONFIG_PM)		+= pm.o irq-pm.o sleep.o
 
 # common code
 
-obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
 obj-$(CONFIG_S3C24XX_DMA)       += dma.o
 
-obj-$(CONFIG_S3C2410_CLOCK)     += clock-s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
 
 obj-$(CONFIG_S3C2410_IOTIMING)  += iotiming-s3c2410.o
 obj-$(CONFIG_S3C2412_IOTIMING)  += iotiming-s3c2412.o
 
-obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
 
 #
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
deleted file mode 100644
index 1edd9b2369c5..000000000000
--- a/arch/arm/mach-s3c24xx/clock-dclk.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX - definitions for DCLK and CLKOUT registers
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-/* clocks that could be registered by external code */
-
-static int s3c24xx_dclk_enable(struct clk *clk, int enable)
-{
-        unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-        if (enable)
-                dclkcon |= clk->ctrlbit;
-        else
-                dclkcon &= ~clk->ctrlbit;
-
-        __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-        return 0;
-}
-
-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
-{
-        unsigned long dclkcon;
-        unsigned int uclk;
-
-        if (parent == &clk_upll)
-                uclk = 1;
-        else if (parent == &clk_p)
-                uclk = 0;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
-        if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
-                if (uclk)
-                        dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
-                else
-                        dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
-        } else {
-                if (uclk)
-                        dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
-                else
-                        dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
-        }
-
-        __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
-        return 0;
-}
-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
-{
-        unsigned long div;
-
-        if ((rate == 0) || !clk->parent)
-                return 0;
-
-        div = clk_get_rate(clk->parent) / rate;
-        if (div < 2)
-                div = 2;
-        else if (div > 16)
-                div = 16;
-
-        return div;
-}
-
-static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
-        unsigned long rate)
-{
-        unsigned long div = s3c24xx_calc_div(clk, rate);
-
-        if (div == 0)
-                return 0;
-
-        return clk_get_rate(clk->parent) / div;
-}
-
-static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
-
-        if (div == 0)
-                return -EINVAL;
-
-        if (clk == &s3c24xx_dclk0) {
-                mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
-                        S3C2410_DCLKCON_DCLK0_CMP_MASK;
-                data = S3C2410_DCLKCON_DCLK0_DIV(div) |
-                        S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
-        } else if (clk == &s3c24xx_dclk1) {
-                mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
-                        S3C2410_DCLKCON_DCLK1_CMP_MASK;
-                data = S3C2410_DCLKCON_DCLK1_DIV(div) |
-                        S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
-        } else
-                return -EINVAL;
-
-        clk->rate = clk_get_rate(clk->parent) / div;
-        __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
-                S3C24XX_DCLKCON);
-        return clk->rate;
-}
-static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
-{
-        unsigned long mask;
-        unsigned long source;
-
-        /* calculate the MISCCR setting for the clock */
-
-        if (parent == &clk_mpll)
-                source = S3C2410_MISCCR_CLK0_MPLL;
-        else if (parent == &clk_upll)
-                source = S3C2410_MISCCR_CLK0_UPLL;
-        else if (parent == &clk_f)
-                source = S3C2410_MISCCR_CLK0_FCLK;
-        else if (parent == &clk_h)
-                source = S3C2410_MISCCR_CLK0_HCLK;
-        else if (parent == &clk_p)
-                source = S3C2410_MISCCR_CLK0_PCLK;
-        else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
-                source = S3C2410_MISCCR_CLK0_DCLK0;
-        else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
-                source = S3C2410_MISCCR_CLK0_DCLK0;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        if (clk == &s3c24xx_clkout0)
-                mask = S3C2410_MISCCR_CLK0_MASK;
-        else {
-                source <<= 4;
-                mask = S3C2410_MISCCR_CLK1_MASK;
-        }
-
-        s3c2410_modify_misccr(mask, source);
-        return 0;
-}
-
-/* external clock definitions */
-
-static struct clk_ops dclk_ops = {
-        .set_parent     = s3c24xx_dclk_setparent,
-        .set_rate       = s3c24xx_set_dclk_rate,
-        .round_rate     = s3c24xx_round_dclk_rate,
-};
-
-struct clk s3c24xx_dclk0 = {
-        .name           = "dclk0",
-        .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
-        .enable         = s3c24xx_dclk_enable,
-        .ops            = &dclk_ops,
-};
-
-struct clk s3c24xx_dclk1 = {
-        .name           = "dclk1",
-        .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
-        .enable         = s3c24xx_dclk_enable,
-        .ops            = &dclk_ops,
-};
-
-static struct clk_ops clkout_ops = {
-        .set_parent     = s3c24xx_clkout_setparent,
-};
-
-struct clk s3c24xx_clkout0 = {
-        .name           = "clkout0",
-        .ops            = &clkout_ops,
-};
-
-struct clk s3c24xx_clkout1 = {
-        .name           = "clkout1",
-        .ops            = &clkout_ops,
-};
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
deleted file mode 100644
index d1afcf9252d1..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410,S3C2440,S3C2442 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-int s3c2410_clkcon_enable(struct clk *clk, int enable)
-{
-        unsigned int clocks = clk->ctrlbit;
-        unsigned long clkcon;
-
-        clkcon = __raw_readl(S3C2410_CLKCON);
-
-        if (enable)
-                clkcon |= clocks;
-        else
-                clkcon &= ~clocks;
-
-        /* ensure none of the special function bits set */
-        clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
-
-        __raw_writel(clkcon, S3C2410_CLKCON);
-
-        return 0;
-}
-
-static int s3c2410_upll_enable(struct clk *clk, int enable)
-{
-        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
-        unsigned long orig = clkslow;
-
-        if (enable)
-                clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
-        else
-                clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
-
-        __raw_writel(clkslow, S3C2410_CLKSLOW);
-
-        /* if we started the UPLL, then allow to settle */
-
-        if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
-                udelay(200);
-
-        return 0;
-}
-
-/* standard clock definitions */
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "nand",
-                .parent         = &clk_h,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_NAND,
-        }, {
-                .name           = "sdi",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_SDI,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_IIC,
-        }, {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_IIS,
-        }, {
-                .name           = "spi",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_SPI,
-        }
-};
-
-static struct clk clk_lcd = {
-        .name           = "lcd",
-        .parent         = &clk_h,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_LCDC,
-};
-
-static struct clk clk_gpio = {
-        .name           = "gpio",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_GPIO,
-};
-
-static struct clk clk_usb_host = {
-        .name           = "usb-host",
-        .parent         = &clk_h,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_USBH,
-};
-
-static struct clk clk_usb_device = {
-        .name           = "usb-device",
-        .parent         = &clk_h,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_USBD,
-};
-
-static struct clk clk_timers = {
-        .name           = "timers",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_PWMT,
-};
-
-struct clk s3c24xx_clk_uart0 = {
-        .name           = "uart",
-        .devname        = "s3c2410-uart.0",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_UART0,
-};
-
-struct clk s3c24xx_clk_uart1 = {
-        .name           = "uart",
-        .devname        = "s3c2410-uart.1",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_UART1,
-};
-
-struct clk s3c24xx_clk_uart2 = {
-        .name           = "uart",
-        .devname        = "s3c2410-uart.2",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_UART2,
-};
-
-static struct clk clk_rtc = {
-        .name           = "rtc",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_RTC,
-};
-
-static struct clk clk_watchdog = {
-        .name           = "watchdog",
-        .parent         = &clk_p,
-        .ctrlbit        = 0,
-};
-
-static struct clk clk_usb_bus_host = {
-        .name           = "usb-bus-host",
-        .parent         = &clk_usb_bus,
-};
-
-static struct clk clk_usb_bus_gadget = {
-        .name           = "usb-bus-gadget",
-        .parent         = &clk_usb_bus,
-};
-
-static struct clk *init_clocks[] = {
-        &clk_lcd,
-        &clk_gpio,
-        &clk_usb_host,
-        &clk_usb_device,
-        &clk_timers,
-        &s3c24xx_clk_uart0,
-        &s3c24xx_clk_uart1,
-        &s3c24xx_clk_uart2,
-        &clk_rtc,
-        &clk_watchdog,
-        &clk_usb_bus_host,
-        &clk_usb_bus_gadget,
-};
-
-/* s3c2410_baseclk_add()
- *
- * Add all the clocks used by the s3c2410 or compatible CPUs
- * such as the S3C2440 and S3C2442.
- *
- * We cannot use a system device as we are needed before any
- * of the init-calls that initialise the devices are actually
- * done.
-*/
-
-int __init s3c2410_baseclk_add(void)
-{
-        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
-        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
-        struct clk *xtal;
-        int ret;
-        int ptr;
-
-        clk_upll.enable = s3c2410_upll_enable;
-
-        if (s3c24xx_register_clock(&clk_usb_bus) < 0)
-                printk(KERN_ERR "failed to register usb bus clock\n");
-
-        /* register clocks from clock array */
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
-                struct clk *clkp = init_clocks[ptr];
-
-                /* ensure that we note the clock state */
-
-                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-
-        /* We must be careful disabling the clocks we are not intending to
-         * be using at boot time, as subsystems such as the LCD which do
-         * their own DMA requests to the bus can cause the system to lockup
-         * if they where in the middle of requesting bus access.
-         *
-         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * and therefore the bootloader should be careful to not enable
-         * the LCD clock if it is not needed.
-        */
-
-        /* install (and disable) the clocks we do not need immediately */
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        /* show the clock-slow value */
-
-        xtal = clk_get(NULL, "xtal");
-
-        printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
-               print_mhz(clk_get_rate(xtal) /
-                         ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
-               (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
-               (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
-               (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
-
-        return 0;
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
deleted file mode 100644
index 192a5b2550b0..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/clock.c
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2412,S3C2413 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-/* We currently have to assume that the system is running
- * from the XTPll input, and that all ***REFCLKs are being
- * fed from it, as we cannot read the state of OM[4] from
- * software.
- *
- * It would be possible for each board initialisation to
- * set the correct muxing at initialisation
-*/
-
-static int s3c2412_clkcon_enable(struct clk *clk, int enable)
-{
-        unsigned int clocks = clk->ctrlbit;
-        unsigned long clkcon;
-
-        clkcon = __raw_readl(S3C2410_CLKCON);
-
-        if (enable)
-                clkcon |= clocks;
-        else
-                clkcon &= ~clocks;
-
-        __raw_writel(clkcon, S3C2410_CLKCON);
-
-        return 0;
-}
-
-static int s3c2412_upll_enable(struct clk *clk, int enable)
-{
-        unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
-        unsigned long orig = upllcon;
-
-        if (!enable)
-                upllcon |= S3C2412_PLLCON_OFF;
-        else
-                upllcon &= ~S3C2412_PLLCON_OFF;
-
-        __raw_writel(upllcon, S3C2410_UPLLCON);
-
-        /* allow ~150uS for the PLL to settle and lock */
-
-        if (enable && (orig & S3C2412_PLLCON_OFF))
-                udelay(150);
-
-        return 0;
-}
-
-/* clock selections */
-
-static struct clk clk_erefclk = {
-        .name           = "erefclk",
-};
-
-static struct clk clk_urefclk = {
-        .name           = "urefclk",
-};
-
-static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-
-        if (parent == &clk_urefclk)
-                clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
-        else if (parent == &clk_upll)
-                clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-
-static struct clk clk_usysclk = {
-        .name           = "usysclk",
-        .parent         = &clk_xtal,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2412_setparent_usysclk,
-        },
-};
-
-static struct clk clk_mrefclk = {
-        .name           = "mrefclk",
-        .parent         = &clk_xtal,
-};
-
-static struct clk clk_mdivclk = {
-        .name           = "mdivclk",
-        .parent         = &clk_xtal,
-};
-
-static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-
-        if (parent == &clk_usysclk)
-                clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
-        else if (parent == &clk_h)
-                clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-
-static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-
-        if (rate > parent_rate)
-                return parent_rate;
-
-        div = parent_rate / rate;
-        if (div > 2)
-                div = 2;
-
-        return parent_rate / div;
-}
-
-static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-
-        return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
-}
-
-static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-
-        rate = s3c2412_roundrate_usbsrc(clk, rate);
-
-        if ((parent_rate / rate) == 2)
-                clkdivn |= S3C2412_CLKDIVN_USB48DIV;
-        else
-                clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
-
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-
-static struct clk clk_usbsrc = {
-        .name           = "usbsrc",
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_usbsrc,
-                .set_rate       = s3c2412_setrate_usbsrc,
-                .round_rate     = s3c2412_roundrate_usbsrc,
-                .set_parent     = s3c2412_setparent_usbsrc,
-        },
-};
-
-static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-
-        if (parent == &clk_mdivclk)
-                clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
-        else if (parent == &clk_mpll)
-                clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-
-static struct clk clk_msysclk = {
-        .name           = "msysclk",
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2412_setparent_msysclk,
-        },
-};
-
-static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        unsigned long clkdiv;
-        unsigned long dvs;
-
-        /* Note, we current equate fclk andf msysclk for S3C2412 */
-
-        if (parent == &clk_msysclk || parent == &clk_f)
-                dvs = 0;
-        else if (parent == &clk_h)
-                dvs = S3C2412_CLKDIVN_DVSEN;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        /* update this under irq lockdown, clkdivn is not protected
-         * by the clock system. */
-
-        local_irq_save(flags);
-
-        clkdiv  = __raw_readl(S3C2410_CLKDIVN);
-        clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
-        clkdiv |= dvs;
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static struct clk clk_armclk = {
-        .name           = "armclk",
-        .parent         = &clk_msysclk,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2412_setparent_armclk,
-        },
-};
-
-/* these next clocks have an divider immediately after them,
- * so we can register them with their divider and leave out the
- * intermediate clock stage
-*/
-static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-
-        if (rate > parent_rate)
-                return parent_rate;
-
-        /* note, we remove the +/- 1 calculations as they cancel out */
-
-        div = (rate / parent_rate);
-
-        if (div < 1)
-                div = 1;
-        else if (div > 16)
-                div = 16;
-
-        return parent_rate / div;
-}
-
-static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-
-        if (parent == &clk_erefclk)
-                clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
-        else if (parent == &clk_mpll)
-                clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-
-static unsigned long s3c2412_getrate_uart(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-
-        div &= S3C2412_CLKDIVN_UARTDIV_MASK;
-        div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
-
-        return parent_rate / (div + 1);
-}
-
-static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-
-        rate = s3c2412_roundrate_clksrc(clk, rate);
-
-        clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
-        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
-
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-
-static struct clk clk_uart = {
-        .name           = "uartclk",
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_uart,
-                .set_rate       = s3c2412_setrate_uart,
-                .set_parent     = s3c2412_setparent_uart,
-                .round_rate     = s3c2412_roundrate_clksrc,
-        },
-};
-
-static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-
-        if (parent == &clk_erefclk)
-                clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
-        else if (parent == &clk_mpll)
-                clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-
-static unsigned long s3c2412_getrate_i2s(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-
-        div &= S3C2412_CLKDIVN_I2SDIV_MASK;
-        div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
-
-        return parent_rate / (div + 1);
-}
-
-static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-
-        rate = s3c2412_roundrate_clksrc(clk, rate);
-
-        clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
-        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
-
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-
-static struct clk clk_i2s = {
-        .name           = "i2sclk",
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_i2s,
-                .set_rate       = s3c2412_setrate_i2s,
-                .set_parent     = s3c2412_setparent_i2s,
-                .round_rate     = s3c2412_roundrate_clksrc,
-        },
-};
-
-static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-
-        if (parent == &clk_usysclk)
-                clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
-        else if (parent == &clk_h)
-                clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static unsigned long s3c2412_getrate_cam(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-
-        div &= S3C2412_CLKDIVN_CAMDIV_MASK;
-        div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
-
-        return parent_rate / (div + 1);
-}
-
-static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-
-        rate = s3c2412_roundrate_clksrc(clk, rate);
-
-        clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
-        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
-
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-
-static struct clk clk_cam = {
-        .name           = "camif-upll", /* same as 2440 name */
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_cam,
-                .set_rate       = s3c2412_setrate_cam,
-                .set_parent     = s3c2412_setparent_cam,
-                .round_rate     = s3c2412_roundrate_clksrc,
-        },
-};
-
-/* standard clock definitions */
-
-static struct clk init_clocks_disable[] = {
-        {
-                .name           = "nand",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_NAND,
-        }, {
-                .name           = "sdi",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_SDI,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_IIC,
-        }, {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_IIS,
-        }, {
-                .name           = "spi",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_SPI,
-        }
-};
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "dma.0",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA0,
-        }, {
-                .name           = "dma.1",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA1,
-        }, {
-                .name           = "dma.2",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA2,
-        }, {
-                .name           = "dma.3",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA3,
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_LCDC,
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_GPIO,
-        }, {
-                .name           = "usb-host",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USBH,
-        }, {
-                .name           = "usb-device",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USBD,
-        }, {
-                .name           = "timers",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_PWMT,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2412-uart.0",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_UART0,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2412-uart.1",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_UART1,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2412-uart.2",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_UART2,
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_RTC,
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_p,
-                .ctrlbit        = 0,
-        }, {
-                .name           = "usb-bus-gadget",
-                .parent         = &clk_usb_bus,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
-        }, {
-                .name           = "usb-bus-host",
-                .parent         = &clk_usb_bus,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
-        }
-};
-
-/* clocks to add where we need to check their parentage */
-
-struct clk_init {
-        struct clk      *clk;
-        unsigned int     bit;
-        struct clk      *src_0;
-        struct clk      *src_1;
-};
-
-static struct clk_init clks_src[] __initdata = {
-        {
-                .clk    = &clk_usysclk,
-                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
-                .src_0  = &clk_urefclk,
-                .src_1  = &clk_upll,
-        }, {
-                .clk    = &clk_i2s,
-                .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
-                .src_0  = &clk_erefclk,
-                .src_1  = &clk_mpll,
-        }, {
-                .clk    = &clk_cam,
-                .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
-                .src_0  = &clk_usysclk,
-                .src_1  = &clk_h,
-        }, {
-                .clk    = &clk_msysclk,
-                .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
-                .src_0  = &clk_mdivclk,
-                .src_1  = &clk_mpll,
-        }, {
-                .clk    = &clk_uart,
-                .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
-                .src_0  = &clk_erefclk,
-                .src_1  = &clk_mpll,
-        }, {
-                .clk    = &clk_usbsrc,
-                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
-                .src_0  = &clk_usysclk,
-                .src_1  = &clk_h,
-        /* here we assume  OM[4] select xtal */
-        }, {
-                .clk    = &clk_erefclk,
-                .bit    = S3C2412_CLKSRC_EREFCLK_EXTCLK,
-                .src_0  = &clk_xtal,
-                .src_1  = &clk_ext,
-        }, {
-                .clk    = &clk_urefclk,
-                .bit    = S3C2412_CLKSRC_UREFCLK_EXTCLK,
-                .src_0  = &clk_xtal,
-                .src_1  = &clk_ext,
-        },
-};
-
-/* s3c2412_clk_initparents
- *
- * Initialise the parents for the clocks that we get at start-time
-*/
-
-static void __init s3c2412_clk_initparents(void)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        struct clk_init *cip = clks_src;
-        struct clk *src;
-        int ptr;
-        int ret;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
-                ret = s3c24xx_register_clock(cip->clk);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               cip->clk->name, ret);
-                }
-
-                src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
-
-                printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
-                clk_set_parent(cip->clk, src);
-        }
-}
-
-/* clocks to add straight away */
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_usb_bus,
-        &clk_mrefclk,
-        &clk_armclk,
-};
-
-static struct clk_lookup s3c2412_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
-};
-
-int __init s3c2412_baseclk_add(void)
-{
-        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
-        unsigned int dvs;
-        struct clk *clkp;
-        int ret;
-        int ptr;
-
-        clk_upll.enable = s3c2412_upll_enable;
-        clk_usb_bus.parent = &clk_usbsrc;
-        clk_usb_bus.rate = 0x0;
-
-        clk_f.parent = &clk_msysclk;
-
-        s3c2412_clk_initparents();
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
-                clkp = clks[ptr];
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-
-        /* set the dvs state according to what we got at boot time */
-
-        dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
-
-        if (dvs)
-                clk_armclk.parent = &clk_h;
-
-        printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
-
-        /* ensure usb bus clock is within correct rate of 48MHz */
-
-        if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
-                printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
-
-                /* for the moment, let's use the UPLL, and see if we can
-                 * get 48MHz */
-
-                clk_set_parent(&clk_usysclk, &clk_upll);
-                clk_set_parent(&clk_usbsrc, &clk_usysclk);
-                clk_set_rate(&clk_usbsrc, 48*1000*1000);
-        }
-
-        printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
-               print_mhz(clk_get_rate(&clk_upll)),
-               print_mhz(clk_get_rate(&clk_usb_bus)));
-
-        /* register clocks from clock array */
-
-        clkp = init_clocks;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
-                /* ensure that we note the clock state */
-
-                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-
-        /* We must be careful disabling the clocks we are not intending to
-         * be using at boot time, as subsystems such as the LCD which do
-         * their own DMA requests to the bus can cause the system to lockup
-         * if they where in the middle of requesting bus access.
-         *
-         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * and therefore the bootloader should be careful to not enable
-         * the LCD clock if it is not needed.
-        */
-
-        /* install (and disable) the clocks we do not need immediately */
-
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                s3c2412_clkcon_enable(clkp, 0);
-        }
-
-        clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
-        return 0;
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
deleted file mode 100644
index d421a72920a5..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/clock.c
- *
- * Copyright (c) 2010 Simtec Electronics
- * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * S3C2416 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/pll.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/regs-clock.h>
-#include <mach/regs-s3c2443-clock.h>
-
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
- * The real clock definition is done in s3c2443-clock.c,
- * only the armdiv divisor table must be defined here.
-*/
-
-static unsigned int armdiv[8] = {
-        [0] = 1,
-        [1] = 2,
-        [2] = 3,
-        [3] = 4,
-        [5] = 6,
-        [7] = 8,
-};
-
-static struct clksrc_clk hsspi_eplldiv = {
-        .clk = {
-                .name   = "hsspi-eplldiv",
-                .parent = &clk_esysclk.clk,
-                .ctrlbit = (1 << 14),
-                .enable = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
-};
-
-static struct clk *hsspi_sources[] = {
-        [0] = &hsspi_eplldiv.clk,
-        [1] = NULL, /* to fix */
-};
-
-static struct clksrc_clk hsspi_mux = {
-        .clk    = {
-                .name   = "hsspi-if",
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = hsspi_sources,
-                .nr_sources = ARRAY_SIZE(hsspi_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
-};
-
-static struct clksrc_clk hsmmc_div[] = {
-        [0] = {
-                .clk = {
-                        .name   = "hsmmc-div",
-                        .devname        = "s3c-sdhci.0",
-                        .parent = &clk_esysclk.clk,
-                },
-                .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
-        },
-        [1] = {
-                .clk = {
-                        .name   = "hsmmc-div",
-                        .devname        = "s3c-sdhci.1",
-                        .parent = &clk_esysclk.clk,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
-        },
-};
-
-static struct clksrc_clk hsmmc_mux0 = {
-        .clk    = {
-                .name           = "hsmmc-if",
-                .devname        = "s3c-sdhci.0",
-                .ctrlbit        = (1 << 6),
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .sources        = &(struct clksrc_sources) {
-                .nr_sources     = 2,
-                .sources        = (struct clk * []) {
-                        [0]     = &hsmmc_div[0].clk,
-                        [1]     = NULL, /* to fix */
-                },
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
-};
-
-static struct clksrc_clk hsmmc_mux1 = {
-        .clk    = {
-                .name           = "hsmmc-if",
-                .devname        = "s3c-sdhci.1",
-                .ctrlbit        = (1 << 12),
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .sources        = &(struct clksrc_sources) {
-                .nr_sources     = 2,
-                .sources        = (struct clk * []) {
-                        [0]     = &hsmmc_div[1].clk,
-                        [1]     = NULL, /* to fix */
-                },
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
-};
-
-static struct clk hsmmc0_clk = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.0",
-        .parent         = &clk_h,
-        .enable         = s3c2443_clkcon_enable_h,
-        .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
-};
-
-static struct clksrc_clk *clksrcs[] __initdata = {
-        &hsspi_eplldiv,
-        &hsspi_mux,
-        &hsmmc_div[0],
-        &hsmmc_div[1],
-        &hsmmc_mux0,
-        &hsmmc_mux1,
-};
-
-static struct clk_lookup s3c2416_clk_lookup[] = {
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
-        /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
-        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
-};
-
-void __init s3c2416_init_clocks(int xtal)
-{
-        u32 epllcon = __raw_readl(S3C2443_EPLLCON);
-        u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
-        int ptr;
-
-        /* s3c2416 EPLL compatible with s3c64xx */
-        clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
-
-        clk_epll.parent = &clk_epllref.clk;
-
-        s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
-                                   armdiv, ARRAY_SIZE(armdiv),
-                                   S3C2416_CLKDIV0_ARMDIV_MASK);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_register_clksrc(clksrcs[ptr], 1);
-
-        s3c24xx_register_clock(&hsmmc0_clk);
-        clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
-
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
deleted file mode 100644
index 5527226fd61f..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/clock.c
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2440 Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-
-#include <mach/hardware.h>
-#include <linux/atomic.h>
-#include <asm/irq.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-/* S3C2440 extended clock support */
-
-static unsigned long s3c2440_camif_upll_round(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-
-        if (rate > parent_rate)
-                return parent_rate;
-
-        /* note, we remove the +/- 1 calculations for the divisor */
-
-        div = (parent_rate / rate) / 2;
-
-        if (div < 1)
-                div = 1;
-        else if (div > 16)
-                div = 16;
-
-        return parent_rate / (div * 2);
-}
-
-static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
-
-        rate = s3c2440_camif_upll_round(clk, rate);
-
-        camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
-
-        if (rate != parent_rate) {
-                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
-                camdivn |= (((parent_rate / rate) / 2) - 1);
-        }
-
-        __raw_writel(camdivn, S3C2440_CAMDIVN);
-
-        return 0;
-}
-
-static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
-
-        if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
-                return parent_rate;
-
-        camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
-
-        return parent_rate / (camdivn + 1) / 2;
-}
-
-/* Extra S3C2440 clocks */
-
-static struct clk s3c2440_clk_cam = {
-        .name           = "camif",
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_CAMERA,
-};
-
-static struct clk s3c2440_clk_cam_upll = {
-        .name           = "camif-upll",
-        .ops            = &(struct clk_ops) {
-                .set_rate       = s3c2440_camif_upll_setrate,
-                .get_rate       = s3c2440_camif_upll_getrate,
-                .round_rate     = s3c2440_camif_upll_round,
-        },
-};
-
-static struct clk s3c2440_clk_ac97 = {
-        .name           = "ac97",
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_AC97,
-};
-
-#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
-
-static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
-{
-        unsigned long ucon0, ucon1, ucon2, divisor;
-
-        /* the fun of calculating the uart divisors on the s3c2440 */
-        ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
-        ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
-        ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
-
-        ucon0 &= S3C2440_UCON0_DIVMASK;
-        ucon1 &= S3C2440_UCON1_DIVMASK;
-        ucon2 &= S3C2440_UCON2_DIVMASK;
-
-        if (ucon0 != 0)
-                divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
-        else if (ucon1 != 0)
-                divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
-        else if (ucon2 != 0)
-                divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
-        else
-                /* manual calims 44, seems to be 9 */
-                divisor = 9;
-
-        return clk_get_rate(clk->parent) / divisor;
-}
-
-static struct clk s3c2440_clk_fclk_n = {
-        .name           = "fclk_n",
-        .parent         = &clk_f,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2440_fclk_n_getrate,
-        },
-};
-
-static struct clk_lookup s3c2440_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
-        CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
-        CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
-        CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
-        CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
-};
-
-static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
-{
-        struct clk *clock_upll;
-        struct clk *clock_h;
-        struct clk *clock_p;
-
-        clock_p = clk_get(NULL, "pclk");
-        clock_h = clk_get(NULL, "hclk");
-        clock_upll = clk_get(NULL, "upll");
-
-        if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
-                printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
-                return -EINVAL;
-        }
-
-        s3c2440_clk_cam.parent = clock_h;
-        s3c2440_clk_ac97.parent = clock_p;
-        s3c2440_clk_cam_upll.parent = clock_upll;
-        s3c24xx_register_clock(&s3c2440_clk_fclk_n);
-
-        s3c24xx_register_clock(&s3c2440_clk_ac97);
-        s3c24xx_register_clock(&s3c2440_clk_cam);
-        s3c24xx_register_clock(&s3c2440_clk_cam_upll);
-        clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
-
-        clk_disable(&s3c2440_clk_ac97);
-        clk_disable(&s3c2440_clk_cam);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_clk_interface = {
-        .name           = "s3c2440_clk",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_clk_add,
-};
-
-static __init int s3c24xx_clk_init(void)
-{
-        return subsys_interface_register(&s3c2440_clk_interface);
-}
-
-arch_initcall(s3c24xx_clk_init);
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
deleted file mode 100644
index 76cd31f7804e..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* linux/arch/arm/mach-s3c2443/clock.c
- *
- * Copyright (c) 2007, 2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2443 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/init.h>
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/serial_core.h>
-#include <linux/io.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-
-#include <mach/regs-s3c2443-clock.h>
-
-#include <plat/cpu-freq.h>
-
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-
-/* We currently have to assume that the system is running
- * from the XTPll input, and that all ***REFCLKs are being
- * fed from it, as we cannot read the state of OM[4] from
- * software.
- *
- * It would be possible for each board initialisation to
- * set the correct muxing at initialisation
-*/
-
-/* clock selections */
-
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
- * The real clock definition is done in s3c2443-clock.c,
- * only the armdiv divisor table must be defined here.
-*/
-
-static unsigned int armdiv[16] = {
-        [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 1,
-        [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 2,
-        [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 3,
-        [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 4,
-        [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 6,
-        [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 8,
-        [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 12,
-        [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 16,
-};
-
-/* hsspi
- *
- * high-speed spi clock, sourced from esysclk
-*/
-
-static struct clksrc_clk clk_hsspi = {
-        .clk    = {
-                .name           = "hsspi-if",
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_HSSPICLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
-};
-
-
-/* clk_hsmcc_div
- *
- * this clock is sourced from epll, and is fed through a divider,
- * to a mux controlled by sclkcon where either it or a extclk can
- * be fed to the hsmmc block
-*/
-
-static struct clksrc_clk clk_hsmmc_div = {
-        .clk    = {
-                .name           = "hsmmc-div",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
-};
-
-static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
-
-        clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
-                    S3C2443_SCLKCON_HSMMCCLK_EPLL);
-
-        if (parent == &clk_epll)
-                clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
-        else if (parent == &clk_ext)
-                clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
-        else
-                return -EINVAL;
-
-        if (clk->usage > 0) {
-                __raw_writel(clksrc, S3C2443_SCLKCON);
-        }
-
-        clk->parent = parent;
-        return 0;
-}
-
-static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
-{
-        return s3c2443_setparent_hsmmc(clk, clk->parent);
-}
-
-static struct clk clk_hsmmc = {
-        .name           = "hsmmc-if",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_hsmmc_div.clk,
-        .enable         = s3c2443_enable_hsmmc,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2443_setparent_hsmmc,
-        },
-};
-
-/* standard clock definitions */
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sdi",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_SDI,
-        }, {
-                .name           = "spi",
-                .devname        = "s3c2410-spi.0",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_SPI1,
-        }
-};
-
-/* clocks to add straight away */
-
-static struct clksrc_clk *clksrcs[] __initdata = {
-        &clk_hsspi,
-        &clk_hsmmc_div,
-};
-
-static struct clk *clks[] __initdata = {
-        &clk_hsmmc,
-};
-
-static struct clk_lookup s3c2443_clk_lookup[] = {
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
-        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
-};
-
-void __init s3c2443_init_clocks(int xtal)
-{
-        unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-        int ptr;
-
-        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
-        clk_epll.parent = &clk_epllref.clk;
-
-        s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
-                                   armdiv, ARRAY_SIZE(armdiv),
-                                   S3C2443_CLKDIV0_ARMDIV_MASK);
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_register_clksrc(clksrcs[ptr], 1);
-
-        /* We must be careful disabling the clocks we are not intending to
-         * be using at boot time, as subsystems such as the LCD which do
-         * their own DMA requests to the bus can cause the system to lockup
-         * if they where in the middle of requesting bus access.
-         *
-         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * and therefore the bootloader should be careful to not enable
-         * the LCD clock if it is not needed.
-        */
-
-        /* install (and disable) the clocks we do not need immediately */
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c244x.c b/arch/arm/mach-s3c24xx/clock-s3c244x.c
deleted file mode 100644
index 6d9b688c442b..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c244x.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
- *
- * Copyright (c) 2004-2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2440/S3C2442 Common clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <linux/atomic.h>
-#include <asm/irq.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long camdivn;
-        unsigned long dvs;
-
-        if (parent == &clk_f)
-                dvs = 0;
-        else if (parent == &clk_h)
-                dvs = S3C2440_CAMDIVN_DVSEN;
-        else
-                return -EINVAL;
-
-        clk->parent = parent;
-
-        camdivn  = __raw_readl(S3C2440_CAMDIVN);
-        camdivn &= ~S3C2440_CAMDIVN_DVSEN;
-        camdivn |= dvs;
-        __raw_writel(camdivn, S3C2440_CAMDIVN);
-
-        return 0;
-}
-
-static struct clk clk_arm = {
-        .name           = "armclk",
-        .id             = -1,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2440_setparent_armclk,
-        },
-};
-
-static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
-        unsigned long clkdivn;
-        struct clk *clock_upll;
-        int ret;
-
-        printk("S3C244X: Clock Support, DVS %s\n",
-               (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
-
-        clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
-
-        ret = s3c24xx_register_clock(&clk_arm);
-        if (ret < 0) {
-                printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
-                return ret;
-        }
-
-        clock_upll = clk_get(NULL, "upll");
-        if (IS_ERR(clock_upll)) {
-                printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
-                return -ENOENT;
-        }
-
-        /* check rate of UPLL, and if it is near 96MHz, then change
-         * to using half the UPLL rate for the system */
-
-        if (clk_get_rate(clock_upll) > (94 * MHZ)) {
-                clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
-
-                spin_lock(&clocks_lock);
-
-                clkdivn = __raw_readl(S3C2410_CLKDIVN);
-                clkdivn |= S3C2440_CLKDIVN_UCLK;
-                __raw_writel(clkdivn, S3C2410_CLKDIVN);
-
-                spin_unlock(&clocks_lock);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_clk_interface = {
-        .name           = "s3c2440_clk",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c244x_clk_add,
-};
-
-static int s3c2440_clk_init(void)
-{
-        return subsys_interface_register(&s3c2440_clk_interface);
-}
-
-arch_initcall(s3c2440_clk_init);
-
-static struct subsys_interface s3c2442_clk_interface = {
-        .name           = "s3c2442_clk",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c244x_clk_add,
-};
-
-static int s3c2442_clk_init(void)
-{
-        return subsys_interface_register(&s3c2442_clk_interface);
-}
-
-arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
deleted file mode 100644
index 65d3eef73090..000000000000
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Common code for SoCs starting with the S3C2443
- *
- * Copyright (c) 2007, 2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/regs-s3c2443-clock.h>
-
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-
-#include <plat/cpu-freq.h>
-
-
-static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
-{
-        u32 ctrlbit = clk->ctrlbit;
-        u32 con = __raw_readl(reg);
-
-        if (enable)
-                con |= ctrlbit;
-        else
-                con &= ~ctrlbit;
-
-        __raw_writel(con, reg);
-        return 0;
-}
-
-int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
-}
-
-int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
-}
-
-int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
-}
-
-/* mpllref is a direct descendant of clk_xtal by default, but it is not
- * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
- * such directly equating the two source clocks is impossible.
- */
-static struct clk clk_mpllref = {
-        .name           = "mpllref",
-        .parent         = &clk_xtal,
-};
-
-static struct clk *clk_epllref_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpllref,
-        [2] = &clk_xtal,
-        [3] = &clk_ext,
-};
-
-struct clksrc_clk clk_epllref = {
-        .clk    = {
-                .name           = "epllref",
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_epllref_sources,
-                .nr_sources = ARRAY_SIZE(clk_epllref_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
-};
-
-/* esysclk
- *
- * this is sourced from either the EPLL or the EPLLref clock
-*/
-
-static struct clk *clk_sysclk_sources[] = {
-        [0] = &clk_epllref.clk,
-        [1] = &clk_epll,
-};
-
-struct clksrc_clk clk_esysclk = {
-        .clk    = {
-                .name           = "esysclk",
-                .parent         = &clk_epll,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_sysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
-};
-
-static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2443_CLKDIV0);
-
-        div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
-        div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);       /* x2 */
-
-        return parent_rate / (div + 1);
-}
-
-static struct clk clk_mdivclk = {
-        .name           = "mdivclk",
-        .parent         = &clk_mpllref,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_getrate_mdivclk,
-        },
-};
-
-static struct clk *clk_msysclk_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpll,
-        [2] = &clk_mdivclk,
-        [3] = &clk_mpllref,
-};
-
-static struct clksrc_clk clk_msysclk = {
-        .clk    = {
-                .name           = "msysclk",
-                .parent         = &clk_xtal,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_msysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
-};
-
-/* prediv
- *
- * this divides the msysclk down to pass to h/p/etc.
- */
-
-static unsigned long s3c2443_prediv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-
-        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
-        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
-
-        return rate / (clkdiv0 + 1);
-}
-
-static struct clk clk_prediv = {
-        .name           = "prediv",
-        .parent         = &clk_msysclk.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_prediv_getrate,
-        },
-};
-
-/* hclk divider
- *
- * divides the prediv and provides the hclk.
- */
-
-static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-
-        clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-
-        return rate / (clkdiv0 + 1);
-}
-
-static struct clk_ops clk_h_ops = {
-        .get_rate       = s3c2443_hclkdiv_getrate,
-};
-
-/* pclk divider
- *
- * divides the hclk and provides the pclk.
- */
-
-static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-
-        clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
-
-        return rate / (clkdiv0 + 1);
-}
-
-static struct clk_ops clk_p_ops = {
-        .get_rate       = s3c2443_pclkdiv_getrate,
-};
-
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
-*/
-
-static unsigned int *armdiv;
-static int nr_armdiv;
-static int armdivmask;
-
-static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        unsigned long calc;
-        unsigned best = 256; /* bigger than any value */
-        unsigned div;
-        int ptr;
-
-        if (!nr_armdiv)
-                return -EINVAL;
-
-        for (ptr = 0; ptr < nr_armdiv; ptr++) {
-                div = armdiv[ptr];
-                if (div) {
-                        /* cpufreq provides 266mhz as 266666000 not 266666666 */
-                        calc = (parent / div / 1000) * 1000;
-                        if (calc <= rate && div < best)
-                                best = div;
-                }
-        }
-
-        return parent / best;
-}
-
-static unsigned long s3c2443_armclk_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkcon0;
-        int val;
-
-        if (!nr_armdiv || !armdivmask)
-                return -EINVAL;
-
-        clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-        clkcon0 &= armdivmask;
-        val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
-
-        return rate / armdiv[val];
-}
-
-static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        unsigned long calc;
-        unsigned div;
-        unsigned best = 256; /* bigger than any value */
-        int ptr;
-        int val = -1;
-
-        if (!nr_armdiv || !armdivmask)
-                return -EINVAL;
-
-        for (ptr = 0; ptr < nr_armdiv; ptr++) {
-                div = armdiv[ptr];
-                if (div) {
-                        /* cpufreq provides 266mhz as 266666000 not 266666666 */
-                        calc = (parent / div / 1000) * 1000;
-                        if (calc <= rate && div < best) {
-                                best = div;
-                                val = ptr;
-                        }
-                }
-        }
-
-        if (val >= 0) {
-                unsigned long clkcon0;
-
-                clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-                clkcon0 &= ~armdivmask;
-                clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
-                __raw_writel(clkcon0, S3C2443_CLKDIV0);
-        }
-
-        return (val == -1) ? -EINVAL : 0;
-}
-
-static struct clk clk_armdiv = {
-        .name           = "armdiv",
-        .parent         = &clk_msysclk.clk,
-        .ops            = &(struct clk_ops) {
-                .round_rate = s3c2443_armclk_roundrate,
-                .get_rate = s3c2443_armclk_getrate,
-                .set_rate = s3c2443_armclk_setrate,
-        },
-};
-
-/* armclk
- *
- * this is the clock fed into the ARM core itself, from armdiv or from hclk.
- */
-
-static struct clk *clk_arm_sources[] = {
-        [0] = &clk_armdiv,
-        [1] = &clk_h,
-};
-
-static struct clksrc_clk clk_arm = {
-        .clk    = {
-                .name           = "armclk",
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_arm_sources,
-                .nr_sources = ARRAY_SIZE(clk_arm_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
-};
-
-/* usbhost
- *
- * usb host bus-clock, usually 48MHz to provide USB bus clock timing
-*/
-
-static struct clksrc_clk clk_usb_bus_host = {
-        .clk    = {
-                .name           = "usb-bus-host-parent",
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_USBHOST,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
-};
-
-/* common clksrc clocks */
-
-static struct clksrc_clk clksrc_clks[] = {
-        {
-                /* camera interface bus-clock, divided down from esysclk */
-                .clk    = {
-                        .name           = "camif-upll", /* same as 2440 name */
-                        .parent         = &clk_esysclk.clk,
-                        .ctrlbit        = S3C2443_SCLKCON_CAMCLK,
-                        .enable         = s3c2443_clkcon_enable_s,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
-        }, {
-                .clk    = {
-                        .name           = "display-if",
-                        .parent         = &clk_esysclk.clk,
-                        .ctrlbit        = S3C2443_SCLKCON_DISPCLK,
-                        .enable         = s3c2443_clkcon_enable_s,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
-        },
-};
-
-static struct clksrc_clk clk_esys_uart = {
-        /* ART baud-rate clock sourced from esysclk via a divisor */
-        .clk    = {
-                .name           = "uartclk",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
-};
-
-static struct clk clk_i2s_ext = {
-        .name           = "i2s-ext",
-};
-
-/* i2s_eplldiv
- *
- * This clock is the output from the I2S divisor of ESYSCLK, and is separate
- * from the mux that comes after it (cannot merge into one single clock)
-*/
-
-static struct clksrc_clk clk_i2s_eplldiv = {
-        .clk    = {
-                .name           = "i2s-eplldiv",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
-};
-
-/* i2s-ref
- *
- * i2s bus reference clock, selectable from external, esysclk or epllref
- *
- * Note, this used to be two clocks, but was compressed into one.
-*/
-
-static struct clk *clk_i2s_srclist[] = {
-        [0] = &clk_i2s_eplldiv.clk,
-        [1] = &clk_i2s_ext,
-        [2] = &clk_epllref.clk,
-        [3] = &clk_epllref.clk,
-};
-
-static struct clksrc_clk clk_i2s = {
-        .clk    = {
-                .name           = "i2s-if",
-                .ctrlbit        = S3C2443_SCLKCON_I2SCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_i2s_srclist,
-                .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIS,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIC,
-        }
-};
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "dma.0",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA0,
-        }, {
-                .name           = "dma.1",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA1,
-        }, {
-                .name           = "dma.2",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA2,
-        }, {
-                .name           = "dma.3",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA3,
-        }, {
-                .name           = "dma.4",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA4,
-        }, {
-                .name           = "dma.5",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA5,
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_GPIO,
-        }, {
-                .name           = "usb-host",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBH,
-        }, {
-                .name           = "usb-device",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBD,
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_LCDC,
-
-        }, {
-                .name           = "timers",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_PWMT,
-        }, {
-                .name           = "cfc",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_CFC,
-        }, {
-                .name           = "ssmc",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_SSMC,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.0",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART0,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.1",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART1,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.2",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART2,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.3",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART3,
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_RTC,
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_WDT,
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_AC97,
-        }, {
-                .name           = "nand",
-                .parent         = &clk_h,
-        }, {
-                .name           = "usb-bus-host",
-                .parent         = &clk_usb_bus_host.clk,
-        }
-};
-
-static struct clk hsmmc1_clk = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_h,
-        .enable         = s3c2443_clkcon_enable_h,
-        .ctrlbit        = S3C2443_HCLKCON_HSMMC,
-};
-
-static struct clk hsspi_clk = {
-        .name           = "spi",
-        .devname        = "s3c2443-spi.0",
-        .parent         = &clk_p,
-        .enable         = s3c2443_clkcon_enable_p,
-        .ctrlbit        = S3C2443_PCLKCON_HSSPI,
-};
-
-/* EPLLCON compatible enough to get on/off information */
-
-void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
-{
-        unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-        unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long pll;
-        int ptr;
-
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        pll = get_mpll(mpllcon, xtal);
-        clk_msysclk.clk.rate = pll;
-        clk_mpll.rate = pll;
-
-        printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
-               (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
-               print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
-               print_mhz(clk_get_rate(&clk_h)),
-               print_mhz(clk_get_rate(&clk_p)));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
-                s3c_set_clksrc(&clksrc_clks[ptr], true);
-
-        /* ensure usb bus clock is within correct rate of 48MHz */
-
-        if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
-                printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
-                clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
-        }
-
-        printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
-               print_mhz(clk_get_rate(&clk_epll)),
-               print_mhz(clk_get_rate(&clk_usb_bus)));
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_prediv,
-        &clk_mpllref,
-        &clk_mdivclk,
-        &clk_ext,
-        &clk_epll,
-        &clk_usb_bus,
-        &clk_armdiv,
-        &hsmmc1_clk,
-        &hsspi_clk,
-};
-
-static struct clksrc_clk *clksrcs[] __initdata = {
-        &clk_i2s_eplldiv,
-        &clk_i2s,
-        &clk_usb_bus_host,
-        &clk_epllref,
-        &clk_esysclk,
-        &clk_msysclk,
-        &clk_arm,
-};
-
-static struct clk_lookup s3c2443_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
-        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
-};
-
-void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-                                       unsigned int *divs, int nr_divs,
-                                       int divmask)
-{
-        int ptr;
-
-        armdiv = divs;
-        nr_armdiv = nr_divs;
-        armdivmask = divmask;
-
-        /* s3c2443 parents h clock from prediv */
-        clk_h.parent = &clk_prediv;
-        clk_h.ops = &clk_h_ops;
-
-        /* and p clock from h clock */
-        clk_p.parent = &clk_h;
-        clk_p.ops = &clk_p_ops;
-
-        clk_usb_bus.parent = &clk_usb_bus_host.clk;
-        clk_epll.parent = &clk_epllref.clk;
-
-        s3c24xx_register_baseclocks(xtal);
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_register_clksrc(clksrcs[ptr], 1);
-
-        s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        /* See s3c2443/etc notes on disabling clocks at init time */
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
-
-        s3c2443_common_setup_clocks(get_mpll);
-}
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 1bc8e73c94f9..c0763b837745 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -53,6 +53,7 @@
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
 #include <plat/pwm-core.h>
+#include <plat/watchdog-reset.h>
 
 #include "common.h"
 
@@ -73,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32410000,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2410_map_io,
-                .init_clocks    = s3c2410_init_clocks,
                 .init_uarts     = s3c2410_init_uarts,
                 .init           = s3c2410_init,
                 .name           = name_s3c2410
@@ -82,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32410002,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2410_map_io,
-                .init_clocks    = s3c2410_init_clocks,
                 .init_uarts     = s3c2410_init_uarts,
                 .init           = s3c2410a_init,
                 .name           = name_s3c2410a
@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32440000,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2440_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2440_init,
                 .name           = name_s3c2440
@@ -100,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32440001,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2440_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2440_init,
                 .name           = name_s3c2440a
@@ -109,7 +106,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32440aaa,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2442_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2442_init,
                 .name           = name_s3c2442
@@ -118,7 +114,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32440aab,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2442_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2442_init,
                 .name           = name_s3c2442b
@@ -127,7 +122,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32412001,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2412_map_io,
-                .init_clocks    = s3c2412_init_clocks,
                 .init_uarts     = s3c2412_init_uarts,
                 .init           = s3c2412_init,
                 .name           = name_s3c2412,
@@ -136,7 +130,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32412003,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2412_map_io,
-                .init_clocks    = s3c2412_init_clocks,
                 .init_uarts     = s3c2412_init_uarts,
                 .init           = s3c2412_init,
                 .name           = name_s3c2412,
@@ -145,7 +138,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32450003,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2416_map_io,
-                .init_clocks    = s3c2416_init_clocks,
                 .init_uarts     = s3c2416_init_uarts,
                 .init           = s3c2416_init,
                 .name           = name_s3c2416,
@@ -154,7 +146,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = 0x32443001,
                 .idmask         = 0xffffffff,
                 .map_io         = s3c2443_map_io,
-                .init_clocks    = s3c2443_init_clocks,
                 .init_uarts     = s3c2443_init_uarts,
                 .init           = s3c2443_init,
                 .name           = name_s3c2443,
@@ -316,21 +307,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
         },
 };
 
-/* initialise all the clocks */
-
-void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
-                                           unsigned long hclk,
-                                           unsigned long pclk)
-{
-        clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
-                                        clk_xtal.rate);
-
-        clk_mpll.rate = fclk;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-        clk_f.rate = fclk;
-}
-
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
         defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 static struct resource s3c2410_dma_resource[] = {
@@ -534,3 +510,62 @@ struct platform_device s3c2443_device_dma = {
         },
 };
 #endif
+
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
+void __init s3c2410_init_clocks(int xtal)
+{
+        s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+void __init s3c2412_init_clocks(int xtal)
+{
+        s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2416
+void __init s3c2416_init_clocks(int xtal)
+{
+        s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+}
+#endif
+
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
+void __init s3c2440_init_clocks(int xtal)
+{
+        s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
+void __init s3c2442_init_clocks(int xtal)
+{
+        s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+void __init s3c2443_init_clocks(int xtal)
+{
+        s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+}
+#endif
+
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
+        defined(CONFIG_CPU_S3C2442)
+static struct resource s3c2410_dclk_resource[] = {
+        [0] = DEFINE_RES_MEM(0x56000084, 0x4),
+};
+
+struct platform_device s3c2410_device_dclk = {
+        .name           = "s3c2410-dclk",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
+        .resource       = s3c2410_dclk_resource,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index e46c10417216..ac3ff12a0601 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -67,16 +67,15 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s3c244x_init_clocks(int xtal);
 extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
-#define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
 #endif
 
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
 extern void s3c2440_map_io(void);
+extern void s3c2440_init_clocks(int xtal);
 extern void s3c2440_init_irq(void);
 #else
 #define s3c2440_init NULL
@@ -86,6 +85,7 @@ extern void s3c2440_init_irq(void);
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
 extern void s3c2442_map_io(void);
+extern void s3c2442_init_clocks(int xtal);
 extern void s3c2442_init_irq(void);
 #else
 #define s3c2442_init NULL
@@ -114,4 +114,21 @@ extern struct platform_device s3c2412_device_dma;
 extern struct platform_device s3c2440_device_dma;
 extern struct platform_device s3c2443_device_dma;
 
+extern struct platform_device s3c2410_device_dclk;
+
+#ifdef CONFIG_S3C2410_COMMON_CLK
+void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
+                                    int current_soc,
+                                    void __iomem *reg_base);
+#endif
+#ifdef CONFIG_S3C2412_COMMON_CLK
+void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
+                                unsigned long ext_f, void __iomem *reg_base);
+#endif
+#ifdef CONFIG_S3C2443_COMMON_CLK
+void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
+                                    int current_soc,
+                                    void __iomem *reg_base);
+#endif
+
 #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 2a0aa5684e72..d4d9514335f4 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -14,6 +14,7 @@
 #include <linux/errno.h>
 #include <linux/cpufreq.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -60,5 +61,6 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
  */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
-        __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
+        if (!IS_ERR(cfg->mpll))
+                clk_set_rate(cfg->mpll, cfg->pll.frequency);
 }
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
deleted file mode 100644
index 2f39737544c0..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,101 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Copyright (C) 2005 Simtec Electronics
- *
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <linux/serial_s3c.h>
-
-#define S3C2410_UART1_OFF (0x4000)
-#define SHIFT_2440TXF (14-9)
-
-        .macro addruart, rp, rv, tmp
-                ldr     \rp, = S3C24XX_PA_UART
-                ldr     \rv, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-                add     \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-        .macro fifo_full_s3c24xx rd, rx
-                @ check for arm920 vs arm926. currently assume all arm926
-                @ devices have an 64 byte FIFO identical to the s3c2440
-                mrc     p15, 0, \rd, c0, c0
-                and     \rd, \rd, #0xff0
-                teq     \rd, #0x260
-                beq     1004f
-                mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1
-                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-                bic     \rd, \rd, #0xff000
-                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
-                and     \rd, \rd, #0x00ff0000
-                teq     \rd, #0x00440000                @ is it 2440?
-1004:
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                moveq   \rd, \rd, lsr #SHIFT_2440TXF
-                tst     \rd, #S3C2410_UFSTAT_TXFULL
-        .endm
-
-        .macro  fifo_full_s3c2410 rd, rx
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                tst     \rd, #S3C2410_UFSTAT_TXFULL
-        .endm
-
-/* fifo level reading */
-
-        .macro fifo_level_s3c24xx rd, rx
-                @ check for arm920 vs arm926. currently assume all arm926
-                @ devices have an 64 byte FIFO identical to the s3c2440
-                mrc     p15, 0, \rd, c0, c0
-                and     \rd, \rd, #0xff0
-                teq     \rd, #0x260
-                beq     10000f
-                mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1
-                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-                bic     \rd, \rd, #0xff000
-                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
-                and     \rd, \rd, #0x00ff0000
-                teq     \rd, #0x00440000                @ is it 2440?
-
-10000:
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
-                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
-        .endm
-
-        .macro fifo_level_s3c2410 rd, rx
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
-        .endm
-
-/* Select the correct implementation depending on the configuration. The
- * S3C2440 will get selected by default, as these are the most widely
- * used variants of these
-*/
-
-#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
-#define fifo_full  fifo_full_s3c2410
-#define fifo_level fifo_level_s3c2410
-#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
-#define fifo_full  fifo_full_s3c24xx
-#define fifo_level fifo_level_s3c24xx
-#endif
-
-/* include the reset of the code which will do the work */
-
-#include <debug/samsung.S>
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
index 3415b60082d7..3db6c10de023 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
@@ -42,24 +42,6 @@
 #define S3C2410_CLKCON_IIS           (1<<17)
 #define S3C2410_CLKCON_SPI           (1<<18)
 
-/* DCLKCON register addresses in gpio.h */
-
-#define S3C2410_DCLKCON_DCLK0EN      (1<<0)
-#define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
-#define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
-#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
-#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
-#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
-#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
-
-#define S3C2410_DCLKCON_DCLK1EN      (1<<16)
-#define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
-#define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
-#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
-#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
-#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
-#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
-
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index c2ef016032ab..c6583cfa5835 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -457,9 +457,6 @@
 
 /* miscellaneous control */
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
-#define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
-
-#define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
 
 /* see clock.h for dclk definitions */
 
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 8ac9554aa996..5157e250dd13 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -161,11 +161,16 @@ static struct platform_device *amlm5900_devices[] __initdata = {
 static void __init amlm5900_map_io(void)
 {
         s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init amlm5900_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 #ifdef CONFIG_FB_S3C2410
 static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
         .width          = 160,
@@ -241,6 +246,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
         .map_io         = amlm5900_map_io,
         .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = amlm5900_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 81a270af2336..e053581cab0b 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -46,7 +46,6 @@
 
 #include <net/ax88796.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
@@ -352,6 +351,7 @@ static struct platform_device anubis_device_sm501 = {
 /* Standard Anubis devices */
 
 static struct platform_device *anubis_devices[] __initdata = {
+        &s3c2410_device_dclk,
         &s3c_device_ohci,
         &s3c_device_wdt,
         &s3c_device_adc,
@@ -364,14 +364,6 @@ static struct platform_device *anubis_devices[] __initdata = {
         &anubis_device_sm501,
 };
 
-static struct clk *anubis_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
-
 /* I2C devices. */
 
 static struct i2c_board_info anubis_i2c_devs[] __initdata = {
@@ -394,23 +386,7 @@ static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
 
 static void __init anubis_map_io(void)
 {
-        /* initialise the clocks */
-
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-
-        s3c24xx_dclk1.parent = &clk_upll;
-        s3c24xx_dclk1.rate   = 24*1000*1000;
-
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-
-        s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
-
         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
@@ -428,6 +404,12 @@ static void __init anubis_map_io(void)
         }
 }
 
+static void __init anubis_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init anubis_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -447,6 +429,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
         .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = anubis_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index d8f6bb1096cb..9db768f448a5 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -45,7 +45,6 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
@@ -192,11 +191,16 @@ static struct platform_device *at2440evb_devices[] __initdata = {
 static void __init at2440evb_map_io(void)
 {
         s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
-        s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init at2440evb_init_time(void)
+{
+        s3c2440_init_clocks(16934400);
+        samsung_timer_init();
+}
+
 static void __init at2440evb_init(void)
 {
         s3c24xx_fb_set_platdata(&at2440evb_fb_info);
@@ -213,6 +217,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
         .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = at2440evb_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index e371ff53a408..f9112b801a33 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -51,7 +51,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
@@ -523,6 +522,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = {
 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 
 static struct platform_device *bast_devices[] __initdata = {
+        &s3c2410_device_dclk,
         &s3c_device_ohci,
         &s3c_device_lcd,
         &s3c_device_wdt,
@@ -537,14 +537,6 @@ static struct platform_device *bast_devices[] __initdata = {
         &bast_sio,
 };
 
-static struct clk *bast_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
-
 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
         .refresh        = 7800, /* 7.8usec */
         .auto_io        = 1,
@@ -558,29 +550,19 @@ static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 
 static void __init bast_map_io(void)
 {
-        /* initialise the clocks */
-
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-
-        s3c24xx_dclk1.parent = &clk_upll;
-        s3c24xx_dclk1.rate   = 24*1000*1000;
-
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-
-        s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
-
         s3c_hwmon_set_platdata(&bast_hwmon_info);
 
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init bast_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init bast_init(void)
 {
         register_syscore_ops(&bast_pm_syscore_ops);
@@ -608,6 +590,6 @@ MACHINE_START(BAST, "Simtec-BAST")
         .map_io         = bast_map_io,
         .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = bast_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index dc4db849f0fd..fc3a08d0cb3f 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -501,7 +501,6 @@ static struct platform_device gta02_buttons_device = {
 static void __init gta02_map_io(void)
 {
         s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
@@ -585,6 +584,11 @@ static void __init gta02_machine_init(void)
         regulator_has_full_constraints();
 }
 
+static void __init gta02_init_time(void)
+{
+        s3c2442_init_clocks(12000000);
+        samsung_timer_init();
+}
 
 MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
@@ -592,6 +596,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         .map_io         = gta02_map_io,
         .init_irq       = s3c2442_init_irq,
         .init_machine   = gta02_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = gta02_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index e453acd92cbf..fbf5487ae5d1 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -57,7 +57,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
@@ -646,7 +645,6 @@ static struct platform_device *h1940_devices[] __initdata = {
 static void __init h1940_map_io(void)
 {
         s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
@@ -662,6 +660,12 @@ static void __init h1940_map_io(void)
         WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
 }
 
+static void __init h1940_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 /* H1940 and RX3715 need to reserve this for suspend */
 static void __init h1940_reserve(void)
 {
@@ -739,6 +743,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .reserve        = h1940_reserve,
         .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = h1940_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 5faa7239e7d6..e81ea82c55f9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -507,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = {
 static void __init jive_map_io(void)
 {
         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init jive_init_time(void)
+{
+        s3c2412_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void jive_power_off(void)
 {
         printk(KERN_INFO "powering system down...\n");
@@ -665,6 +670,6 @@ MACHINE_START(JIVE, "JIVE")
         .init_irq       = s3c2412_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = jive_init_time,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 9e57fd9f4f3b..5cc40ec1d254 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -54,7 +54,6 @@
 #include <linux/mtd/partitions.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
@@ -525,11 +524,16 @@ static struct platform_device *mini2440_devices[] __initdata = {
 static void __init mini2440_map_io(void)
 {
         s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init mini2440_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 /*
  * mini2440_features string
  *
@@ -690,6 +694,6 @@ MACHINE_START(MINI2440, "MINI2440")
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
         .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = mini2440_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 4cccaad34847..3ac2a54348d6 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -45,7 +45,6 @@
 
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
@@ -535,11 +534,16 @@ static void __init n30_map_io(void)
 {
         s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
         n30_hwinit();
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init n30_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
 
 static void __init n30_init(void)
@@ -591,7 +595,7 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .init_time      = samsung_timer_init,
+        .init_time      = n30_init_time,
         .init_machine   = n30_init,
         .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
@@ -602,7 +606,7 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .init_time      = samsung_timer_init,
+        .init_time      = n30_init_time,
         .init_machine   = n30_init,
         .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 3066851f584d..c82c281ce351 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
@@ -135,13 +134,18 @@ static void __init nexcoder_sensorboard_init(void)
 static void __init nexcoder_map_io(void)
 {
         s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         nexcoder_sensorboard_init();
 }
 
+static void __init nexcoder_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init nexcoder_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -154,6 +158,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
         .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = nexcoder_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index a4ae4bb3666d..189147b80eca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -40,7 +40,6 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
@@ -344,20 +343,13 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 /* Standard Osiris devices */
 
 static struct platform_device *osiris_devices[] __initdata = {
+        &s3c2410_device_dclk,
         &s3c_device_i2c0,
         &s3c_device_wdt,
         &s3c_device_nand,
         &osiris_pcmcia,
 };
 
-static struct clk *osiris_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
-
 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
         .refresh        = 7800, /* refresh period is 7.8usec */
         .auto_io        = 1,
@@ -368,23 +360,7 @@ static void __init osiris_map_io(void)
 {
         unsigned long flags;
 
-        /* initialise the clocks */
-
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-
-        s3c24xx_dclk1.parent = &clk_upll;
-        s3c24xx_dclk1.rate   = 24*1000*1000;
-
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-
-        s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
-
         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
@@ -408,6 +384,12 @@ static void __init osiris_map_io(void)
         local_irq_restore(flags);
 }
 
+static void __init osiris_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init osiris_init(void)
 {
         register_syscore_ops(&osiris_pm_syscore_ops);
@@ -429,6 +411,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         .map_io         = osiris_map_io,
         .init_irq       = s3c2440_init_irq,
         .init_machine   = osiris_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = osiris_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bdb3faac2d9b..45833001186d 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -30,7 +30,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/samsung-time.h>
@@ -100,11 +99,16 @@ static struct platform_device *otom11_devices[] __initdata = {
 static void __init otom11_map_io(void)
 {
         s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init otom11_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init otom11_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -117,6 +121,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
         .init_irq       = s3c2410_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = otom11_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 8c12787a8fd3..228c9094519d 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -304,11 +304,16 @@ __setup("tft=", qt2410_tft_setup);
 static void __init qt2410_map_io(void)
 {
         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
-        s3c24xx_init_clocks(12*1000*1000);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init qt2410_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init qt2410_machine_init(void)
 {
         s3c_nand_set_platdata(&qt2410_nand_info);
@@ -346,6 +351,6 @@ MACHINE_START(QT2410, "QT2410")
         .map_io         = qt2410_map_io,
         .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = qt2410_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index afb784e934c8..e2c6541909c1 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -54,7 +54,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
@@ -710,6 +709,7 @@ static struct i2c_board_info rx1950_i2c_devices[] = {
 };
 
 static struct platform_device *rx1950_devices[] __initdata = {
+        &s3c2410_device_dclk,
         &s3c_device_lcd,
         &s3c_device_wdt,
         &s3c_device_i2c0,
@@ -728,20 +728,9 @@ static struct platform_device *rx1950_devices[] __initdata = {
         &rx1950_leds,
 };
 
-static struct clk *rx1950_clocks[] __initdata = {
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-};
-
 static void __init rx1950_map_io(void)
 {
-        s3c24xx_clkout0.parent  = &clk_h;
-        s3c24xx_clkout1.parent  = &clk_f;
-
-        s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
-
         s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
-        s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
@@ -754,6 +743,12 @@ static void __init rx1950_map_io(void)
         s3c_pm_init();
 }
 
+static void __init rx1950_init_time(void)
+{
+        s3c2442_init_clocks(16934000);
+        samsung_timer_init();
+}
+
 static void __init rx1950_init_machine(void)
 {
         int i;
@@ -816,6 +811,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .reserve        = rx1950_reserve,
         .init_irq       = s3c2442_init_irq,
         .init_machine = rx1950_init_machine,
-        .init_time      = samsung_timer_init,
+        .init_time      = rx1950_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index e6535ce1bc5c..6e749ec3a2ea 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -46,7 +46,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
@@ -179,11 +178,16 @@ static struct platform_device *rx3715_devices[] __initdata = {
 static void __init rx3715_map_io(void)
 {
         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
-        s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init rx3715_init_time(void)
+{
+        s3c2440_init_clocks(16934000);
+        samsung_timer_init();
+}
+
 /* H1940 and RX3715 need to reserve this for suspend */
 static void __init rx3715_reserve(void)
 {
@@ -210,6 +214,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .reserve        = rx3715_reserve,
         .init_irq       = s3c2440_init_irq,
         .init_machine   = rx3715_init_machine,
-        .init_time      = samsung_timer_init,
+        .init_time      = rx3715_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index 70f0900d4bca..e4dcb9aa2ca2 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -18,7 +18,6 @@
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <linux/serial_core.h>
 #include <linux/serial_s3c.h>
 
 #include <asm/mach/arch.h>
@@ -29,48 +28,14 @@
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the S3C2416 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
-                                "s3c2440-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
-                                "s3c2440-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
-                                "s3c2440-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
-                                "s3c2440-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
-                                "s3c-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
-                                "s3c-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
-                                "s3c2440-i2c.0", NULL),
-        {},
-};
-
 static void __init s3c2416_dt_map_io(void)
 {
         s3c24xx_init_io(NULL, 0);
-        s3c24xx_init_clocks(12000000);
 }
 
 static void __init s3c2416_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                s3c2416_auxdata_lookup, NULL);
-
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         s3c_pm_init();
 }
 
@@ -86,6 +51,5 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
         .map_io         = s3c2416_dt_map_io,
         .init_irq       = irqchip_init,
         .init_machine   = s3c2416_dt_machine_init,
-         .init_time     = clocksource_of_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index f32924ee0e9f..419fadd6e446 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -99,11 +99,16 @@ static struct platform_device *smdk2410_devices[] __initdata = {
 static void __init smdk2410_map_io(void)
 {
         s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init smdk2410_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init smdk2410_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -118,6 +123,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         .map_io         = smdk2410_map_io,
         .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2410_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 233fe52d2015..a38f8a049e22 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -106,11 +106,16 @@ static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
 static void __init smdk2413_map_io(void)
 {
         s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init smdk2413_init_time(void)
+{
+        s3c2412_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init smdk2413_machine_init(void)
 {       /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
@@ -159,6 +164,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2413_init_time,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index b3b54d8e1410..fa6f30d23601 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -219,10 +219,15 @@ static struct platform_device *smdk2416_devices[] __initdata = {
         &s3c2443_device_dma,
 };
 
+static void __init smdk2416_init_time(void)
+{
+        s3c2416_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init smdk2416_map_io(void)
 {
         s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
@@ -257,6 +262,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2416_init_time,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index d071dcfea548..5fb89c0ae17a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,7 +38,6 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
@@ -159,11 +158,16 @@ static struct platform_device *smdk2440_devices[] __initdata = {
 static void __init smdk2440_map_io(void)
 {
         s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
-        s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init smdk2440_init_time(void)
+{
+        s3c2440_init_clocks(16934400);
+        samsung_timer_init();
+}
+
 static void __init smdk2440_machine_init(void)
 {
         s3c24xx_fb_set_platdata(&smdk2440_fb_info);
@@ -180,6 +184,6 @@ MACHINE_START(S3C2440, "SMDK2440")
         .init_irq       = s3c2440_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2440_init_time,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 06c4d77de3a5..ef5d5ea33182 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -121,11 +121,16 @@ static struct platform_device *smdk2443_devices[] __initdata = {
 static void __init smdk2443_map_io(void)
 {
         s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init smdk2443_init_time(void)
+{
+        s3c2443_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init smdk2443_machine_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -145,6 +150,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2443_init_time,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 4108b2f0cede..c616ca2d409e 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -135,11 +135,16 @@ static struct platform_device *tct_hammer_devices[] __initdata = {
 static void __init tct_hammer_map_io(void)
 {
         s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init tct_hammer_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init tct_hammer_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -151,6 +156,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .map_io         = tct_hammer_map_io,
         .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = tct_hammer_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 1cc5b1bd51cd..f88c584c3001 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -43,7 +43,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
 
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/samsung-time.h>
@@ -286,6 +285,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
 /* devices for this board */
 
 static struct platform_device *vr1000_devices[] __initdata = {
+        &s3c2410_device_dclk,
         &s3c_device_ohci,
         &s3c_device_lcd,
         &s3c_device_wdt,
@@ -299,14 +299,6 @@ static struct platform_device *vr1000_devices[] __initdata = {
         &vr1000_led3,
 };
 
-static struct clk *vr1000_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
-
 static void vr1000_power_off(void)
 {
         gpio_direction_output(S3C2410_GPB(9), 1);
@@ -314,29 +306,19 @@ static void vr1000_power_off(void)
 
 static void __init vr1000_map_io(void)
 {
-        /* initialise clock sources */
-
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-
-        s3c24xx_dclk1.parent = NULL;
-        s3c24xx_dclk1.rate   = 3692307;
-
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-
-        s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
-
         pm_power_off = vr1000_power_off;
 
         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
-        s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init vr1000_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init vr1000_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -357,6 +339,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
         .init_irq       = s3c2410_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = vr1000_init_time,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 40868c0e0a68..6b706c915387 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -142,11 +142,16 @@ static void __init vstms_fixup(struct tag *tags, char **cmdline,
 static void __init vstms_map_io(void)
 {
         s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
-        s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
+static void __init vstms_init_time(void)
+{
+        s3c2412_init_clocks(12000000);
+        samsung_timer_init();
+}
+
 static void __init vstms_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
@@ -162,6 +167,6 @@ MACHINE_START(VSTMS, "VSTMS")
         .init_irq       = s3c2412_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .init_time      = samsung_timer_init,
+        .init_time      = vstms_init_time,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 68ea5b7e5dc7..b19256ec8d40 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -51,9 +51,6 @@
 #define PFX "s3c24xx-pm: "
 
 static struct sleep_save core_save[] = {
-        SAVE_ITEM(S3C2410_LOCKTIME),
-        SAVE_ITEM(S3C2410_CLKCON),
-
         /* we restore the timings here, with the proviso that the board
          * brings the system up in an slower, or equal frequency setting
          * to the original system.
@@ -69,18 +66,6 @@ static struct sleep_save core_save[] = {
         SAVE_ITEM(S3C2410_BANKCON3),
         SAVE_ITEM(S3C2410_BANKCON4),
         SAVE_ITEM(S3C2410_BANKCON5),
-
-#ifndef CONFIG_CPU_FREQ
-        SAVE_ITEM(S3C2410_CLKDIVN),
-        SAVE_ITEM(S3C2410_MPLLCON),
-        SAVE_ITEM(S3C2410_REFRESH),
-#endif
-        SAVE_ITEM(S3C2410_UPLLCON),
-        SAVE_ITEM(S3C2410_CLKSLOW),
-};
-
-static struct sleep_save misc_save[] = {
-        SAVE_ITEM(S3C2410_DCLKCON),
 };
 
 /* s3c_pm_check_resume_pin
@@ -140,12 +125,10 @@ void s3c_pm_configure_extint(void)
 void s3c_pm_restore_core(void)
 {
         s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
-        s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
 }
 
 void s3c_pm_save_core(void)
 {
-        s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
         s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
 }
 
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 04b58cb49888..7eab88829883 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -85,62 +85,6 @@ void __init s3c2410_map_io(void)
 
 void __init_or_cpufreq s3c2410_setup_clocks(void)
 {
-        struct clk *xtal_clk;
-        unsigned long tmp;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
-
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        /* now we've got our machine bits initialised, work out what
-         * clocks we've got */
-
-        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
-
-        tmp = __raw_readl(S3C2410_CLKDIVN);
-
-        /* work out clock scalings */
-
-        hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
-        pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
-
-        /* print brieft summary of clocks, etc */
-
-        printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
-               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
-
-        /* initialise the clocks here, to allow other things like the
-         * console to use them
-         */
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-}
-
-/* fake ARMCLK for use with cpufreq, etc. */
-
-static struct clk s3c2410_armclk = {
-        .name   = "armclk",
-        .parent = &clk_f,
-        .id     = -1,
-};
-
-static struct clk_lookup s3c2410_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-};
-
-void __init s3c2410_init_clocks(int xtal)
-{
-        s3c24xx_register_baseclocks(xtal);
-        s3c2410_setup_clocks();
-        s3c2410_baseclk_add();
-        s3c24xx_register_clock(&s3c2410_armclk);
-        clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 
 struct bus_type s3c2410_subsys = {
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 657cbaca80ac..d49f52fbc842 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -173,49 +173,6 @@ void __init s3c2412_map_io(void)
 
 void __init_or_cpufreq s3c2412_setup_clocks(void)
 {
-        struct clk *xtal_clk;
-        unsigned long tmp;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
-
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        /* now we've got our machine bits initialised, work out what
-         * clocks we've got */
-
-        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
-
-        clk_mpll.rate = fclk;
-
-        tmp = __raw_readl(S3C2410_CLKDIVN);
-
-        /* work out clock scalings */
-
-        hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
-        hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
-        pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
-
-        /* print brieft summary of clocks, etc */
-
-        printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
-               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-}
-
-void __init s3c2412_init_clocks(int xtal)
-{
-        /* initialise the clocks here, to allow other things like the
-         * console to use them
-         */
-
-        s3c24xx_register_baseclocks(xtal);
-        s3c2412_setup_clocks();
-        s3c2412_baseclk_add();
 }
 
 /* need to register the subsystem before we actually register the device, and
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 2c8adc028538..fb9da2b603a2 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -53,117 +53,6 @@
 
 #include "common.h"
 
-/* S3C2442 extended clock support */
-
-static unsigned long s3c2442_camif_upll_round(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-
-        if (rate > parent_rate)
-                return parent_rate;
-
-        div = parent_rate / rate;
-
-        if (div == 3)
-                return parent_rate / 3;
-
-        /* note, we remove the +/- 1 calculations for the divisor */
-
-        div /= 2;
-
-        if (div < 1)
-                div = 1;
-        else if (div > 16)
-                div = 16;
-
-        return parent_rate / (div * 2);
-}
-
-static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
-
-        rate = s3c2442_camif_upll_round(clk, rate);
-
-        camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
-
-        if (rate == parent_rate) {
-                camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
-        } else if ((parent_rate / rate) == 3) {
-                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
-                camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
-        } else {
-                camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
-                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
-                camdivn |= (((parent_rate / rate) / 2) - 1);
-        }
-
-        __raw_writel(camdivn, S3C2440_CAMDIVN);
-
-        return 0;
-}
-
-/* Extra S3C2442 clocks */
-
-static struct clk s3c2442_clk_cam = {
-        .name           = "camif",
-        .id             = -1,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_CAMERA,
-};
-
-static struct clk s3c2442_clk_cam_upll = {
-        .name           = "camif-upll",
-        .id             = -1,
-        .ops            = &(struct clk_ops) {
-                .set_rate       = s3c2442_camif_upll_setrate,
-                .round_rate     = s3c2442_camif_upll_round,
-        },
-};
-
-static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
-{
-        struct clk *clock_upll;
-        struct clk *clock_h;
-        struct clk *clock_p;
-
-        clock_p = clk_get(NULL, "pclk");
-        clock_h = clk_get(NULL, "hclk");
-        clock_upll = clk_get(NULL, "upll");
-
-        if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
-                printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
-                return -EINVAL;
-        }
-
-        s3c2442_clk_cam.parent = clock_h;
-        s3c2442_clk_cam_upll.parent = clock_upll;
-
-        s3c24xx_register_clock(&s3c2442_clk_cam);
-        s3c24xx_register_clock(&s3c2442_clk_cam_upll);
-
-        clk_disable(&s3c2442_clk_cam);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2442_clk_interface = {
-        .name           = "s3c2442_clk",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c2442_clk_add,
-};
-
-static __init int s3c2442_clk_init(void)
-{
-        return subsys_interface_register(&s3c2442_clk_interface);
-}
-
-arch_initcall(s3c2442_clk_init);
-
-
 static struct device s3c2442_dev = {
         .bus            = &s3c2442_subsys,
 };
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index fe30ebb234d2..4a64bcc9eb51 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -46,6 +46,7 @@
 #include <plat/nand-core.h>
 #include <plat/watchdog-reset.h>
 
+#include "common.h"
 #include "regs-dsc.h"
 
 static struct map_desc s3c244x_iodesc[] __initdata = {
@@ -74,67 +75,11 @@ void __init s3c244x_map_io(void)
         s3c_nand_setname("s3c2440-nand");
         s3c_device_ts.name = "s3c2440-ts";
         s3c_device_usbgadget.name = "s3c2440-usbgadget";
+        s3c2410_device_dclk.name = "s3c2440-dclk";
 }
 
 void __init_or_cpufreq s3c244x_setup_clocks(void)
 {
-        struct clk *xtal_clk;
-        unsigned long clkdiv;
-        unsigned long camdiv;
-        unsigned long xtal;
-        unsigned long hclk, fclk, pclk;
-        int hdiv = 1;
-
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
-
-        clkdiv = __raw_readl(S3C2410_CLKDIVN);
-        camdiv = __raw_readl(S3C2440_CAMDIVN);
-
-        /* work out clock scalings */
-
-        switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
-        case S3C2440_CLKDIVN_HDIVN_1:
-                hdiv = 1;
-                break;
-
-        case S3C2440_CLKDIVN_HDIVN_2:
-                hdiv = 2;
-                break;
-
-        case S3C2440_CLKDIVN_HDIVN_4_8:
-                hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
-                break;
-
-        case S3C2440_CLKDIVN_HDIVN_3_6:
-                hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
-                break;
-        }
-
-        hclk = fclk / hdiv;
-        pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
-
-        /* print brief summary of clocks, etc */
-
-        printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
-               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-}
-
-void __init s3c244x_init_clocks(int xtal)
-{
-        /* initialise the clocks here, to allow other things like the
-         * console to use them, and to add new ones after the initialisation
-         */
-
-        s3c24xx_register_baseclocks(xtal);
-        s3c244x_setup_clocks();
-        s3c2410_baseclk_add();
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 
 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0f92ba8e7884..62eaa42cb13a 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -8,7 +8,6 @@ config ARCH_SHMOBILE_MULTI
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select ARM_GIC
-        select MIGHT_HAVE_PCI
         select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
         select NO_IOPORT_MAP
         select PINCTRL
@@ -205,8 +204,8 @@ config MACH_ARMADILLO800EVA_REFERENCE
         select SND_SOC_WM8978 if SND_SIMPLE_CARD
         select USE_OF
         ---help---
-           Use reference implementation of Aramdillo800 EVA board support
-           which makes a greater use of device tree at the expense
+           Use reference implementation of Armadillo800 EVA board support
+           which makes greater use of device tree at the expense
            of not supporting a number of devices.
 
            This is intended to aid developers
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8f3c68101d59..a177a7b3bdbd 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -765,7 +765,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
  *      "Media RAM (MERAM)" on r8a7740 documentation
  */
 #define MEBUFCNTR       0xFE950098
-void r8a7740_meram_workaround(void)
+void __init r8a7740_meram_workaround(void)
 {
         void __iomem *reg;
 
@@ -869,17 +869,6 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init r8a7740_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-
-        early_platform_add_devices(r8a7740_early_devices,
-                                   ARRAY_SIZE(r8a7740_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-
 void __init r8a7740_add_standard_devices_dt(void)
 {
         platform_add_devices(r8a7740_devices_dt,
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 27301278c208..f8176b051be4 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -1037,11 +1037,7 @@ void __init sh7372_add_early_devices_dt(void)
 {
         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
 
-        early_platform_add_devices(sh7372_early_devices,
-                                   ARRAY_SIZE(sh7372_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
+        sh7372_add_early_devices();
 }
 
 void __init sh7372_add_standard_devices_dt(void)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 55b305d51669..e16999e5b735 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -7,7 +7,6 @@ config ARCH_TEGRA
         select CLKSRC_MMIO
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select MIGHT_HAVE_PCI
         select PINCTRL
         select ARCH_HAS_RESET_CONTROLLER
         select RESET_CONTROLLER
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index f2c89fb8fca9..be83ba25f81b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -310,6 +310,21 @@ static struct platform_device char_lcd_device = {
         .resource       =       char_lcd_resources,
 };
 
+static struct resource leds_resources[] = {
+        {
+                .start  = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET,
+                .end    = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET + 4,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device leds_device = {
+        .name           = "versatile-leds",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(leds_resources),
+        .resource       = leds_resources,
+};
+
 /*
  * Clock handling
  */
@@ -795,6 +810,7 @@ void __init versatile_init(void)
         platform_device_register(&versatile_i2c_device);
         platform_device_register(&smc91x_device);
         platform_device_register(&char_lcd_device);
+        platform_device_register(&leds_device);
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 657d52d0391f..b8ac752fd24b 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -18,6 +18,8 @@ config ARCH_VEXPRESS
         select POWER_SUPPLY
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select VEXPRESS_CONFIG
+        select VEXPRESS_SYSCFG
+        select MFD_VEXPRESS_SYSREG
         help
           This option enables support for systems using Cortex processor based
           ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index bde4374ab6d5..152fad91b3ae 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -4,10 +4,9 @@
 /* Tile's peripherals static mappings should start here */
 #define V2T_PERIPH 0xf8200000
 
-void vexpress_dt_smp_map_io(void);
-
 bool vexpress_smp_init_ops(void);
 
 extern struct smp_operations    vexpress_smp_ops;
+extern struct smp_operations    vexpress_smp_dt_ops;
 
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6f34497a4245..494d70bfddad 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -128,6 +128,10 @@ static struct platform_device pmu_device = {
         .resource       = pmu_resources,
 };
 
+static struct clk_lookup osc1_lookup = {
+        .dev_id         = "ct:clcd",
+};
+
 static struct platform_device osc1_device = {
         .name           = "vexpress-osc",
         .id             = 1,
@@ -135,6 +139,7 @@ static struct platform_device osc1_device = {
         .resource       = (struct resource []) {
                 VEXPRESS_RES_FUNC(0xf, 1),
         },
+        .dev.platform_data = &osc1_lookup,
 };
 
 static void __init ct_ca9x4_init(void)
@@ -155,10 +160,7 @@ static void __init ct_ca9x4_init(void)
                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 
         platform_device_register(&pmu_device);
-        platform_device_register(&osc1_device);
-
-        WARN_ON(clk_register_clkdev(vexpress_osc_setup(&osc1_device.dev),
-                        NULL, "ct:clcd"));
+        vexpress_syscfg_device_register(&osc1_device);
 }
 
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 993c9ae5dc5e..a1f3804fd5a5 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,8 +12,7 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_fdt.h>
+#include <linux/of_address.h>
 #include <linux/vexpress.h>
 
 #include <asm/mcpm.h>
@@ -26,154 +25,13 @@
 
 #include "core.h"
 
-#if defined(CONFIG_OF)
-
-static enum {
-        GENERIC_SCU,
-        CORTEX_A9_SCU,
-} vexpress_dt_scu __initdata = GENERIC_SCU;
-
-static struct map_desc vexpress_dt_cortex_a9_scu_map __initdata = {
-        .virtual        = V2T_PERIPH,
-        /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
-        .length         = SZ_128,
-        .type           = MT_DEVICE,
-};
-
-static void *vexpress_dt_cortex_a9_scu_base __initdata;
-
-const static char *vexpress_dt_cortex_a9_match[] __initconst = {
-        "arm,cortex-a5-scu",
-        "arm,cortex-a9-scu",
-        NULL
-};
-
-static int __init vexpress_dt_find_scu(unsigned long node,
-                const char *uname, int depth, void *data)
-{
-        if (of_flat_dt_match(node, vexpress_dt_cortex_a9_match)) {
-                phys_addr_t phys_addr;
-                __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL);
-
-                if (WARN_ON(!reg))
-                        return -EINVAL;
-
-                phys_addr = be32_to_cpup(reg);
-                vexpress_dt_scu = CORTEX_A9_SCU;
-
-                vexpress_dt_cortex_a9_scu_map.pfn = __phys_to_pfn(phys_addr);
-                iotable_init(&vexpress_dt_cortex_a9_scu_map, 1);
-                vexpress_dt_cortex_a9_scu_base = ioremap(phys_addr, SZ_256);
-                if (WARN_ON(!vexpress_dt_cortex_a9_scu_base))
-                        return -EFAULT;
-        }
-
-        return 0;
-}
-
-void __init vexpress_dt_smp_map_io(void)
-{
-        if (initial_boot_params)
-                WARN_ON(of_scan_flat_dt(vexpress_dt_find_scu, NULL));
-}
-
-static int __init vexpress_dt_cpus_num(unsigned long node, const char *uname,
-                int depth, void *data)
-{
-        static int prev_depth = -1;
-        static int nr_cpus = -1;
-
-        if (prev_depth > depth && nr_cpus > 0)
-                return nr_cpus;
-
-        if (nr_cpus < 0 && strcmp(uname, "cpus") == 0)
-                nr_cpus = 0;
-
-        if (nr_cpus >= 0) {
-                const char *device_type = of_get_flat_dt_prop(node,
-                                "device_type", NULL);
-
-                if (device_type && strcmp(device_type, "cpu") == 0)
-                        nr_cpus++;
-        }
-
-        prev_depth = depth;
-
-        return 0;
-}
-
-static void __init vexpress_dt_smp_init_cpus(void)
-{
-        int ncores = 0, i;
-
-        switch (vexpress_dt_scu) {
-        case GENERIC_SCU:
-                ncores = of_scan_flat_dt(vexpress_dt_cpus_num, NULL);
-                break;
-        case CORTEX_A9_SCU:
-                ncores = scu_get_core_count(vexpress_dt_cortex_a9_scu_base);
-                break;
-        default:
-                WARN_ON(1);
-                break;
-        }
-
-        if (ncores < 2)
-                return;
-
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                                ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-
-        for (i = 0; i < ncores; ++i)
-                set_cpu_possible(i, true);
-}
-
-static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
-{
-        int i;
-
-        switch (vexpress_dt_scu) {
-        case GENERIC_SCU:
-                for (i = 0; i < max_cpus; i++)
-                        set_cpu_present(i, true);
-                break;
-        case CORTEX_A9_SCU:
-                scu_enable(vexpress_dt_cortex_a9_scu_base);
-                break;
-        default:
-                WARN_ON(1);
-                break;
-        }
-}
-
-#else
-
-static void __init vexpress_dt_smp_init_cpus(void)
-{
-        WARN_ON(1);
-}
-
-void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
-{
-        WARN_ON(1);
-}
-
-#endif
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 static void __init vexpress_smp_init_cpus(void)
 {
-        if (ct_desc)
-                ct_desc->init_cpu_map();
-        else
-                vexpress_dt_smp_init_cpus();
-
+        ct_desc->init_cpu_map();
 }
 
 static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
@@ -182,10 +40,7 @@ static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
          * Initialise the present map, which describes the set of CPUs
          * actually populated at the present time.
          */
-        if (ct_desc)
-                ct_desc->smp_enable(max_cpus);
-        else
-                vexpress_dt_smp_prepare_cpus(max_cpus);
+        ct_desc->smp_enable(max_cpus);
 
         /*
          * Write the address of secondary startup into the
@@ -223,3 +78,39 @@ bool __init vexpress_smp_init_ops(void)
 #endif
         return false;
 }
+
+#if defined(CONFIG_OF)
+
+static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = {
+        { .compatible = "arm,cortex-a5-scu", },
+        { .compatible = "arm,cortex-a9-scu", },
+        {}
+};
+
+static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *scu = of_find_matching_node(NULL,
+                        vexpress_smp_dt_scu_match);
+
+        if (scu)
+                scu_enable(of_iomap(scu, 0));
+
+        /*
+         * Write the address of secondary startup into the
+         * system-wide flags register. The boot monitor waits
+         * until it receives a soft interrupt, and then the
+         * secondary CPU branches to this address.
+         */
+        vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
+}
+
+struct smp_operations __initdata vexpress_smp_dt_ops = {
+        .smp_prepare_cpus       = vexpress_smp_dt_prepare_cpus,
+        .smp_secondary_init     = versatile_secondary_init,
+        .smp_boot_secondary     = versatile_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = vexpress_cpu_die,
+#endif
+};
+
+#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 4f8b8cb17ff5..38f4f6f37770 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -201,8 +201,9 @@ static struct platform_device v2m_cf_device = {
 
 static struct mmci_platform_data v2m_mmci_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .gpio_wp        = VEXPRESS_GPIO_MMC_WPROT,
-        .gpio_cd        = VEXPRESS_GPIO_MMC_CARDIN,
+        .status         = vexpress_get_mci_cardin,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
 };
 
 static struct resource v2m_sysreg_resources[] = {
@@ -340,11 +341,6 @@ static void __init v2m_init(void)
         regulator_register_fixed(0, v2m_eth_supplies,
                         ARRAY_SIZE(v2m_eth_supplies));
 
-        platform_device_register(&v2m_muxfpga_device);
-        platform_device_register(&v2m_shutdown_device);
-        platform_device_register(&v2m_reboot_device);
-        platform_device_register(&v2m_dvimode_device);
-
         platform_device_register(&v2m_sysreg_device);
         platform_device_register(&v2m_pcie_i2c_device);
         platform_device_register(&v2m_ddc_i2c_device);
@@ -356,6 +352,11 @@ static void __init v2m_init(void)
         for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
                 amba_device_register(v2m_amba_devs[i], &iomem_resource);
 
+        vexpress_syscfg_device_register(&v2m_muxfpga_device);
+        vexpress_syscfg_device_register(&v2m_shutdown_device);
+        vexpress_syscfg_device_register(&v2m_reboot_device);
+        vexpress_syscfg_device_register(&v2m_dvimode_device);
+
         ct_desc->init_tile();
 }
 
@@ -369,71 +370,10 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .init_machine   = v2m_init,
 MACHINE_END
 
-static struct map_desc v2m_rs1_io_desc __initdata = {
-        .virtual        = V2M_PERIPH,
-        .pfn            = __phys_to_pfn(0x1c000000),
-        .length         = SZ_2M,
-        .type           = MT_DEVICE,
-};
-
-static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
-                int depth, void *data)
-{
-        const char **map = data;
-
-        if (strcmp(uname, "motherboard") != 0)
-                return 0;
-
-        *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
-
-        return 1;
-}
-
-void __init v2m_dt_map_io(void)
-{
-        const char *map = NULL;
-
-        of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
-
-        if (map && strcmp(map, "rs1") == 0)
-                iotable_init(&v2m_rs1_io_desc, 1);
-        else
-                iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
-
-#if defined(CONFIG_SMP)
-        vexpress_dt_smp_map_io();
-#endif
-}
-
-void __init v2m_dt_init_early(void)
-{
-        u32 dt_hbi;
-
-        vexpress_sysreg_of_early_init();
-
-        /* Confirm board type against DT property, if available */
-        if (of_property_read_u32(of_allnodes, "arm,hbi", &dt_hbi) == 0) {
-                u32 hbi = vexpress_get_hbi(VEXPRESS_SITE_MASTER);
-
-                if (WARN_ON(dt_hbi != hbi))
-                        pr_warning("vexpress: DT HBI (%x) is not matching "
-                                        "hardware (%x)!\n", dt_hbi, hbi);
-        }
-
-        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000);
-}
-
-static const struct of_device_id v2m_dt_bus_match[] __initconst = {
-        { .compatible = "simple-bus", },
-        { .compatible = "arm,amba-bus", },
-        { .compatible = "arm,vexpress,config-bus", },
-        {}
-};
-
 static void __init v2m_dt_init(void)
 {
         l2x0_of_init(0x00400000, 0xfe0fffff);
-        of_platform_populate(NULL, v2m_dt_bus_match, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const v2m_dt_match[] __initconst = {
@@ -443,9 +383,7 @@ static const char * const v2m_dt_match[] __initconst = {
 
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .dt_compat      = v2m_dt_match,
-        .smp            = smp_ops(vexpress_smp_ops),
+        .smp            = smp_ops(vexpress_smp_dt_ops),
         .smp_init       = smp_init_ops(vexpress_smp_init_ops),
-        .map_io         = v2m_dt_map_io,
-        .init_early     = v2m_dt_init_early,
         .init_machine   = v2m_dt_init,
 MACHINE_END
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 384a776d8eb2..61b4d705c267 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -40,7 +40,7 @@ static void __iomem *sync32k_cnt_reg;
 
 static u64 notrace omap_32k_read_sched_clock(void)
 {
-        return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
+        return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
 }
 
 /**
@@ -64,7 +64,7 @@ static void omap_read_persistent_clock(struct timespec *ts)
         spin_lock_irqsave(&read_persistent_clock_lock, flags);
 
         last_cycles = cycles;
-        cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
+        cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
 
         nsecs = clocksource_cyc2ns(cycles - last_cycles,
                                         persistent_mult, persistent_shift);
@@ -95,7 +95,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
          * The 'SCHEME' bits(30-31) of the revision register is used
          * to identify the version.
          */
-        if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
+        if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
                                                 OMAP2_32KSYNCNT_REV_SCHEME)
                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
         else
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index aa7ebc6bcd65..48b69de89a5d 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -85,12 +85,12 @@ static void dbg_led_set(struct led_classdev *cdev,
         struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
         u16 reg;
 
-        reg = __raw_readw(&fpga->leds);
+        reg = readw_relaxed(&fpga->leds);
         if (b != LED_OFF)
                 reg |= led->mask;
         else
                 reg &= ~led->mask;
-        __raw_writew(reg, &fpga->leds);
+        writew_relaxed(reg, &fpga->leds);
 }
 
 static enum led_brightness dbg_led_get(struct led_classdev *cdev)
@@ -98,7 +98,7 @@ static enum led_brightness dbg_led_get(struct led_classdev *cdev)
         struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
         u16 reg;
 
-        reg = __raw_readw(&fpga->leds);
+        reg = readw_relaxed(&fpga->leds);
         return (reg & led->mask) ? LED_FULL : LED_OFF;
 }
 
@@ -112,7 +112,7 @@ static int fpga_probe(struct platform_device *pdev)
                 return -ENODEV;
 
         fpga = ioremap(iomem->start, resource_size(iomem));
-        __raw_writew(0xff, &fpga->leds);
+        writew_relaxed(0xff, &fpga->leds);
 
         for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
                 struct dbg_led *led;
@@ -138,15 +138,15 @@ static int fpga_probe(struct platform_device *pdev)
 
 static int fpga_suspend_noirq(struct device *dev)
 {
-        fpga_led_state = __raw_readw(&fpga->leds);
-        __raw_writew(0xff, &fpga->leds);
+        fpga_led_state = readw_relaxed(&fpga->leds);
+        writew_relaxed(0xff, &fpga->leds);
 
         return 0;
 }
 
 static int fpga_resume_noirq(struct device *dev)
 {
-        __raw_writew(~fpga_led_state, &fpga->leds);
+        writew_relaxed(~fpga_led_state, &fpga->leds);
         return 0;
 }
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 869254cebf84..db10169a08de 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -103,7 +103,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
                                 timer->context.tmar);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
                                 timer->context.tsicr);
-        __raw_writel(timer->context.tier, timer->irq_ena);
+        writel_relaxed(timer->context.tier, timer->irq_ena);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
                                 timer->context.tclr);
 }
@@ -699,9 +699,9 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
         omap_dm_timer_enable(timer);
 
         if (timer->revision == 1)
-                l = __raw_readl(timer->irq_ena) & ~mask;
+                l = readl_relaxed(timer->irq_ena) & ~mask;
 
-        __raw_writel(l, timer->irq_dis);
+        writel_relaxed(l, timer->irq_dis);
         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
 
@@ -722,7 +722,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
                 return 0;
         }
 
-        l = __raw_readl(timer->irq_stat);
+        l = readl_relaxed(timer->irq_stat);
 
         return l;
 }
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 2861b155485a..dd79f3005cdf 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -280,20 +280,20 @@ static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
                                                 int posted)
 {
         if (posted)
-                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+                while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
                         cpu_relax();
 
-        return __raw_readl(timer->func_base + (reg & 0xff));
+        return readl_relaxed(timer->func_base + (reg & 0xff));
 }
 
 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
                                         u32 reg, u32 val, int posted)
 {
         if (posted)
-                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+                while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
                         cpu_relax();
 
-        __raw_writel(val, timer->func_base + (reg & 0xff));
+        writel_relaxed(val, timer->func_base + (reg & 0xff));
 }
 
 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
@@ -301,7 +301,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
         u32 tidr;
 
         /* Assume v1 ip if bits [31:16] are zero */
-        tidr = __raw_readl(timer->io_base);
+        tidr = readl_relaxed(timer->io_base);
         if (!(tidr >> 16)) {
                 timer->revision = 1;
                 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
@@ -385,7 +385,7 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
         }
 
         /* Ack possibly pending interrupt */
-        __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+        writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
 }
 
 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
@@ -399,7 +399,7 @@ static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
                                                 unsigned int value)
 {
-        __raw_writel(value, timer->irq_ena);
+        writel_relaxed(value, timer->irq_ena);
         __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 }
 
@@ -412,7 +412,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
                                                 unsigned int value)
 {
-        __raw_writel(value, timer->irq_stat);
+        writel_relaxed(value, timer->irq_stat);
 }
 
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 7231c8e4975e..72d4178ad23b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -119,6 +119,7 @@ struct s3c_plltab {
 struct s3c_cpufreq_config {
         struct s3c_freq         freq;
         struct s3c_freq         max;
+        struct clk              *mpll;
         struct cpufreq_frequency_table pll;
         struct s3c_clkdivs      divs;
         struct s3c_cpufreq_info *info;  /* for core, not drivers */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8dd9b89..5a237db9f9eb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,16 +43,6 @@ extern unsigned long samsung_cpu_id;
 #define S5PV210_CPU_ID          0x43110000
 #define S5PV210_CPU_MASK        0xFFFFF000
 
-#define EXYNOS4210_CPU_ID       0x43210000
-#define EXYNOS4212_CPU_ID       0x43220000
-#define EXYNOS4412_CPU_ID       0xE4412200
-#define EXYNOS4_CPU_MASK        0xFFFE0000
-
-#define EXYNOS5250_SOC_ID       0x43520000
-#define EXYNOS5420_SOC_ID       0xE5420000
-#define EXYNOS5440_SOC_ID       0xE5440000
-#define EXYNOS5_SOC_MASK        0xFFFFF000
-
 #define IS_SAMSUNG_CPU(name, id, mask)          \
 static inline int is_samsung_##name(void)       \
 {                                               \
@@ -68,12 +58,6 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
-IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
-IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -126,50 +110,6 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s5pv210()       0
 #endif
 
-#if defined(CONFIG_CPU_EXYNOS4210)
-# define soc_is_exynos4210()    is_samsung_exynos4210()
-#else
-# define soc_is_exynos4210()    0
-#endif
-
-#if defined(CONFIG_SOC_EXYNOS4212)
-# define soc_is_exynos4212()    is_samsung_exynos4212()
-#else
-# define soc_is_exynos4212()    0
-#endif
-
-#if defined(CONFIG_SOC_EXYNOS4412)
-# define soc_is_exynos4412()    is_samsung_exynos4412()
-#else
-# define soc_is_exynos4412()    0
-#endif
-
-#define EXYNOS4210_REV_0        (0x0)
-#define EXYNOS4210_REV_1_0      (0x10)
-#define EXYNOS4210_REV_1_1      (0x11)
-
-#if defined(CONFIG_SOC_EXYNOS5250)
-# define soc_is_exynos5250()    is_samsung_exynos5250()
-#else
-# define soc_is_exynos5250()    0
-#endif
-
-#if defined(CONFIG_SOC_EXYNOS5420)
-# define soc_is_exynos5420()    is_samsung_exynos5420()
-#else
-# define soc_is_exynos5420()    0
-#endif
-
-#if defined(CONFIG_SOC_EXYNOS5440)
-# define soc_is_exynos5440()    is_samsung_exynos5440()
-#else
-# define soc_is_exynos5440()    0
-#endif
-
-#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
-                          soc_is_exynos4412())
-#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
-
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef KHZ
@@ -239,7 +179,6 @@ extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
 extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos_subsys;
 
 extern void (*s5pc1xx_idle)(void);
 
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 2c4332b9f948..fce41e93b6a4 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -6,12 +6,6 @@ config PLAT_VERSATILE_CLOCK
 config PLAT_VERSATILE_CLCD
         bool
 
-config PLAT_VERSATILE_LEDS
-        def_bool y if NEW_LEDS
-        depends on ARCH_REALVIEW || ARCH_VERSATILE
-        select LEDS_CLASS
-        select LEDS_TRIGGERS
-
 config PLAT_VERSATILE_SCHED_CLOCK
         def_bool y
 
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index f88d448b629c..2e0c472958ae 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,6 +2,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
-obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
 obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
deleted file mode 100644
index d2490d00b46c..000000000000
--- a/arch/arm/plat-versatile/leds.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Driver for the 8 user LEDs found on the RealViews and Versatiles
- * Based on DaVinci's DM365 board code
- *
- * License terms: GNU General Public License (GPL) version 2
- * Author: Linus Walleij <triad@df.lth.se>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-
-#include <mach/hardware.h>
-#include <mach/platform.h>
-
-#ifdef VERSATILE_SYS_BASE
-#define LEDREG  (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
-#endif
-
-#ifdef REALVIEW_SYS_BASE
-#define LEDREG  (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
-#endif
-
-struct versatile_led {
-        struct led_classdev     cdev;
-        u8                      mask;
-};
-
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
-        const char *name;
-        const char *trigger;
-} versatile_leds[] = {
-        { "versatile:0", "heartbeat", },
-        { "versatile:1", "mmc0", },
-        { "versatile:2", "cpu0" },
-        { "versatile:3", "cpu1" },
-        { "versatile:4", "cpu2" },
-        { "versatile:5", "cpu3" },
-        { "versatile:6", },
-        { "versatile:7", },
-};
-
-static void versatile_led_set(struct led_classdev *cdev,
-                              enum led_brightness b)
-{
-        struct versatile_led *led = container_of(cdev,
-                                                 struct versatile_led, cdev);
-        u32 reg = readl(LEDREG);
-
-        if (b != LED_OFF)
-                reg |= led->mask;
-        else
-                reg &= ~led->mask;
-        writel(reg, LEDREG);
-}
-
-static enum led_brightness versatile_led_get(struct led_classdev *cdev)
-{
-        struct versatile_led *led = container_of(cdev,
-                                                 struct versatile_led, cdev);
-        u32 reg = readl(LEDREG);
-
-        return (reg & led->mask) ? LED_FULL : LED_OFF;
-}
-
-static int __init versatile_leds_init(void)
-{
-        int i;
-
-        /* All ON */
-        writel(0xff, LEDREG);
-        for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) {
-                struct versatile_led *led;
-
-                led = kzalloc(sizeof(*led), GFP_KERNEL);
-                if (!led)
-                        break;
-
-                led->cdev.name = versatile_leds[i].name;
-                led->cdev.brightness_set = versatile_led_set;
-                led->cdev.brightness_get = versatile_led_get;
-                led->cdev.default_trigger = versatile_leds[i].trigger;
-                led->mask = BIT(i);
-
-                if (led_classdev_register(NULL, &led->cdev) < 0) {
-                        kfree(led);
-                        break;
-                }
-        }
-
-        return 0;
-}
-
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(versatile_leds_init);