[ARM] 3473/1: Use numbers 0-15 for the VFP double registers

Patch from Catalin Marinas

This patch changes the double registers numbering to 0-15 from even 0-30,
in preparation for future VFP extensions. It also fixes the VFP_REG_ZERO
bug (value 16 actually represents the 8th double register with the original
numbering).

The original mcrr/mrrc on CP10 were generating FMRRS/FMSRR instead of
FMRRD/FMDRR. The patch changes to CP11 for the correct instructions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 4 deletions

diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index b7ed57e00cd4..a3f65b47aea9 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -189,11 +189,10 @@ vfp_put_float:
 
         .globl  vfp_get_double
 vfp_get_double:
-        mov     r0, r0, lsr #1
         add     pc, pc, r0, lsl #3
         mov     r0, r0
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrrc    p10, 1, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
+        mrrc    p11, 1, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
         mov     pc, lr
         .endr
 
@@ -204,10 +203,9 @@ vfp_get_double:
 
         .globl  vfp_put_double
 vfp_put_double:
-        mov     r0, r0, lsr #1
         add     pc, pc, r0, lsl #3
         mov     r0, r0
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcrr    p10, 1, r1, r2, c\dr    @ fmrrd r1, r2, d\dr
+        mcrr    p11, 1, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
         mov     pc, lr
         .endr