diff options
author | Jon Hunter <jon-hunter@ti.com> | 2012-07-06 17:45:04 -0400 |
---|---|---|
committer | Jon Hunter <jon-hunter@ti.com> | 2012-11-12 17:23:50 -0500 |
commit | 7b44cf2c15f81caf5c3a4ac59f0677edd64b9aeb (patch) | |
tree | f8bfe5d2eb26fe82874bea7bcc3b80377486b8d4 /arch/arm/plat-omap | |
parent | bfd6d021120d5994c4cc94d87ec03642be1540e7 (diff) |
ARM: OMAP: Fix timer posted mode support
Currently the dmtimer posted mode is being enabled when the function
omap_dm_timer_enable_posted() is called. This function is only being called
for OMAP1 timers and OMAP2+ timers that are being used as system timers. Hence,
for OMAP2+ timers that are NOT being used as a system timer, posted mode is
not enabled but the "timer->posted" variable is still set (incorrectly) in
the omap_dm_timer_prepare() function.
This is a regression introduced by commit 3392cdd3 (ARM: OMAP: dmtimer:
switch-over to platform device driver) which was before the
omap_dm_timer_enable_posted() function was introduced. Although this is a
regression from the original code it only impacts performance and so is not
needed for stable.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r-- | arch/arm/plat-omap/dmtimer.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 381a612e6a1d..10ec31b8a3a2 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
@@ -121,21 +121,16 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) | |||
121 | 121 | ||
122 | static void omap_dm_timer_reset(struct omap_dm_timer *timer) | 122 | static void omap_dm_timer_reset(struct omap_dm_timer *timer) |
123 | { | 123 | { |
124 | omap_dm_timer_enable(timer); | ||
125 | if (timer->pdev->id != 1) { | 124 | if (timer->pdev->id != 1) { |
126 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); | 125 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
127 | omap_dm_timer_wait_for_reset(timer); | 126 | omap_dm_timer_wait_for_reset(timer); |
128 | } | 127 | } |
129 | 128 | ||
130 | __omap_dm_timer_reset(timer, 0, 0); | 129 | __omap_dm_timer_reset(timer, 0, 0); |
131 | __omap_dm_timer_enable_posted(timer); | ||
132 | omap_dm_timer_disable(timer); | ||
133 | } | 130 | } |
134 | 131 | ||
135 | int omap_dm_timer_prepare(struct omap_dm_timer *timer) | 132 | int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
136 | { | 133 | { |
137 | int ret; | ||
138 | |||
139 | /* | 134 | /* |
140 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | 135 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so |
141 | * do not call clk_get() for these devices. | 136 | * do not call clk_get() for these devices. |
@@ -149,13 +144,15 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer) | |||
149 | } | 144 | } |
150 | } | 145 | } |
151 | 146 | ||
147 | omap_dm_timer_enable(timer); | ||
148 | |||
152 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) | 149 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) |
153 | omap_dm_timer_reset(timer); | 150 | omap_dm_timer_reset(timer); |
154 | 151 | ||
155 | ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | 152 | __omap_dm_timer_enable_posted(timer); |
153 | omap_dm_timer_disable(timer); | ||
156 | 154 | ||
157 | timer->posted = 1; | 155 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); |
158 | return ret; | ||
159 | } | 156 | } |
160 | 157 | ||
161 | static inline u32 omap_dm_timer_reserved_systimer(int id) | 158 | static inline u32 omap_dm_timer_reserved_systimer(int id) |