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authorZebediah C. McClure <zmc@lurian.net>2009-03-23 21:07:40 -0400
committerTony Lindgren <tony@atomide.com>2009-03-23 21:07:40 -0400
commit56739a692946d4c2630cf287646ccaa67c828f47 (patch)
tree1f3733d85229847bb9060ef32b55679a5e7530ec /arch/arm/plat-omap
parentae302f40061235f6bc58ae9ba02aa849d60223b5 (diff)
[OMAP850] Changes to base IO subsystem, v2
Changes to base IO subsystem. Signed-off-by: Zebediah C. McClure <zmc@lurian.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/gpio.c111
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h3
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h52
3 files changed, 158 insertions, 8 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index f856a90b264e..d3fa41e3d8c5 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -81,6 +81,22 @@
81#define OMAP730_GPIO_INT_STATUS 0x14 81#define OMAP730_GPIO_INT_STATUS 0x14
82 82
83/* 83/*
84 * OMAP850 specific GPIO registers
85 */
86#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
87#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
88#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
89#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
90#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
91#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
92#define OMAP850_GPIO_DATA_INPUT 0x00
93#define OMAP850_GPIO_DATA_OUTPUT 0x04
94#define OMAP850_GPIO_DIR_CONTROL 0x08
95#define OMAP850_GPIO_INT_CONTROL 0x0c
96#define OMAP850_GPIO_INT_MASK 0x10
97#define OMAP850_GPIO_INT_STATUS 0x14
98
99/*
84 * omap24xx specific GPIO registers 100 * omap24xx specific GPIO registers
85 */ 101 */
86#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) 102#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
@@ -159,7 +175,8 @@ struct gpio_bank {
159#define METHOD_GPIO_1510 1 175#define METHOD_GPIO_1510 1
160#define METHOD_GPIO_1610 2 176#define METHOD_GPIO_1610 2
161#define METHOD_GPIO_730 3 177#define METHOD_GPIO_730 3
162#define METHOD_GPIO_24XX 4 178#define METHOD_GPIO_850 4
179#define METHOD_GPIO_24XX 5
163 180
164#ifdef CONFIG_ARCH_OMAP16XX 181#ifdef CONFIG_ARCH_OMAP16XX
165static struct gpio_bank gpio_bank_1610[5] = { 182static struct gpio_bank gpio_bank_1610[5] = {
@@ -190,6 +207,19 @@ static struct gpio_bank gpio_bank_730[7] = {
190}; 207};
191#endif 208#endif
192 209
210#ifdef CONFIG_ARCH_OMAP850
211static struct gpio_bank gpio_bank_850[7] = {
212 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
213 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
214 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
215 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
216 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
217 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
218 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
219};
220#endif
221
222
193#ifdef CONFIG_ARCH_OMAP24XX 223#ifdef CONFIG_ARCH_OMAP24XX
194 224
195static struct gpio_bank gpio_bank_242x[4] = { 225static struct gpio_bank gpio_bank_242x[4] = {
@@ -236,7 +266,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
236 return &gpio_bank[0]; 266 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)]; 267 return &gpio_bank[1 + (gpio >> 4)];
238 } 268 }
239 if (cpu_is_omap730()) { 269 if (cpu_is_omap7xx()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio)) 270 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0]; 271 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)]; 272 return &gpio_bank[1 + (gpio >> 5)];
@@ -251,7 +281,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
251 281
252static inline int get_gpio_index(int gpio) 282static inline int get_gpio_index(int gpio)
253{ 283{
254 if (cpu_is_omap730()) 284 if (cpu_is_omap7xx())
255 return gpio & 0x1f; 285 return gpio & 0x1f;
256 if (cpu_is_omap24xx()) 286 if (cpu_is_omap24xx())
257 return gpio & 0x1f; 287 return gpio & 0x1f;
@@ -273,7 +303,7 @@ static inline int gpio_valid(int gpio)
273 return 0; 303 return 0;
274 if ((cpu_is_omap16xx()) && gpio < 64) 304 if ((cpu_is_omap16xx()) && gpio < 64)
275 return 0; 305 return 0;
276 if (cpu_is_omap730() && gpio < 192) 306 if (cpu_is_omap7xx() && gpio < 192)
277 return 0; 307 return 0;
278 if (cpu_is_omap24xx() && gpio < 128) 308 if (cpu_is_omap24xx() && gpio < 128)
279 return 0; 309 return 0;
@@ -318,6 +348,11 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
318 reg += OMAP730_GPIO_DIR_CONTROL; 348 reg += OMAP730_GPIO_DIR_CONTROL;
319 break; 349 break;
320#endif 350#endif
351#ifdef CONFIG_ARCH_OMAP850
352 case METHOD_GPIO_850:
353 reg += OMAP850_GPIO_DIR_CONTROL;
354 break;
355#endif
321#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 356#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
322 case METHOD_GPIO_24XX: 357 case METHOD_GPIO_24XX:
323 reg += OMAP24XX_GPIO_OE; 358 reg += OMAP24XX_GPIO_OE;
@@ -380,6 +415,16 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
380 l &= ~(1 << gpio); 415 l &= ~(1 << gpio);
381 break; 416 break;
382#endif 417#endif
418#ifdef CONFIG_ARCH_OMAP850
419 case METHOD_GPIO_850:
420 reg += OMAP850_GPIO_DATA_OUTPUT;
421 l = __raw_readl(reg);
422 if (enable)
423 l |= 1 << gpio;
424 else
425 l &= ~(1 << gpio);
426 break;
427#endif
383#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 428#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
384 case METHOD_GPIO_24XX: 429 case METHOD_GPIO_24XX:
385 if (enable) 430 if (enable)
@@ -426,6 +471,11 @@ static int __omap_get_gpio_datain(int gpio)
426 reg += OMAP730_GPIO_DATA_INPUT; 471 reg += OMAP730_GPIO_DATA_INPUT;
427 break; 472 break;
428#endif 473#endif
474#ifdef CONFIG_ARCH_OMAP850
475 case METHOD_GPIO_850:
476 reg += OMAP850_GPIO_DATA_INPUT;
477 break;
478#endif
429#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 479#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
430 case METHOD_GPIO_24XX: 480 case METHOD_GPIO_24XX:
431 reg += OMAP24XX_GPIO_DATAIN; 481 reg += OMAP24XX_GPIO_DATAIN;
@@ -598,6 +648,18 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
598 goto bad; 648 goto bad;
599 break; 649 break;
600#endif 650#endif
651#ifdef CONFIG_ARCH_OMAP850
652 case METHOD_GPIO_850:
653 reg += OMAP850_GPIO_INT_CONTROL;
654 l = __raw_readl(reg);
655 if (trigger & IRQ_TYPE_EDGE_RISING)
656 l |= 1 << gpio;
657 else if (trigger & IRQ_TYPE_EDGE_FALLING)
658 l &= ~(1 << gpio);
659 else
660 goto bad;
661 break;
662#endif
601#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 663#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
602 case METHOD_GPIO_24XX: 664 case METHOD_GPIO_24XX:
603 set_24xx_gpio_triggering(bank, gpio, trigger); 665 set_24xx_gpio_triggering(bank, gpio, trigger);
@@ -678,6 +740,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
678 reg += OMAP730_GPIO_INT_STATUS; 740 reg += OMAP730_GPIO_INT_STATUS;
679 break; 741 break;
680#endif 742#endif
743#ifdef CONFIG_ARCH_OMAP850
744 case METHOD_GPIO_850:
745 reg += OMAP850_GPIO_INT_STATUS;
746 break;
747#endif
681#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 748#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
682 case METHOD_GPIO_24XX: 749 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQSTATUS1; 750 reg += OMAP24XX_GPIO_IRQSTATUS1;
@@ -736,6 +803,13 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
736 inv = 1; 803 inv = 1;
737 break; 804 break;
738#endif 805#endif
806#ifdef CONFIG_ARCH_OMAP850
807 case METHOD_GPIO_850:
808 reg += OMAP850_GPIO_INT_MASK;
809 mask = 0xffffffff;
810 inv = 1;
811 break;
812#endif
739#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 813#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
740 case METHOD_GPIO_24XX: 814 case METHOD_GPIO_24XX:
741 reg += OMAP24XX_GPIO_IRQENABLE1; 815 reg += OMAP24XX_GPIO_IRQENABLE1;
@@ -799,6 +873,16 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
799 l |= gpio_mask; 873 l |= gpio_mask;
800 break; 874 break;
801#endif 875#endif
876#ifdef CONFIG_ARCH_OMAP850
877 case METHOD_GPIO_850:
878 reg += OMAP850_GPIO_INT_MASK;
879 l = __raw_readl(reg);
880 if (enable)
881 l &= ~(gpio_mask);
882 else
883 l |= gpio_mask;
884 break;
885#endif
802#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 886#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
803 case METHOD_GPIO_24XX: 887 case METHOD_GPIO_24XX:
804 if (enable) 888 if (enable)
@@ -983,6 +1067,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
983 if (bank->method == METHOD_GPIO_730) 1067 if (bank->method == METHOD_GPIO_730)
984 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1068 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
985#endif 1069#endif
1070#ifdef CONFIG_ARCH_OMAP850
1071 if (bank->method == METHOD_GPIO_850)
1072 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1073#endif
986#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1074#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
987 if (bank->method == METHOD_GPIO_24XX) 1075 if (bank->method == METHOD_GPIO_24XX)
988 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1076 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
@@ -1372,6 +1460,13 @@ static int __init _omap_gpio_init(void)
1372 gpio_bank = gpio_bank_730; 1460 gpio_bank = gpio_bank_730;
1373 } 1461 }
1374#endif 1462#endif
1463#ifdef CONFIG_ARCH_OMAP850
1464 if (cpu_is_omap850()) {
1465 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1466 gpio_bank_count = 7;
1467 gpio_bank = gpio_bank_850;
1468 }
1469#endif
1375 1470
1376#ifdef CONFIG_ARCH_OMAP24XX 1471#ifdef CONFIG_ARCH_OMAP24XX
1377 if (cpu_is_omap242x()) { 1472 if (cpu_is_omap242x()) {
@@ -1420,7 +1515,7 @@ static int __init _omap_gpio_init(void)
1420 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1515 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1421 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1516 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1422 } 1517 }
1423 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { 1518 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1424 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1519 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1425 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1520 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1426 1521
@@ -1743,6 +1838,9 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1743 case METHOD_GPIO_730: 1838 case METHOD_GPIO_730:
1744 reg += OMAP730_GPIO_DIR_CONTROL; 1839 reg += OMAP730_GPIO_DIR_CONTROL;
1745 break; 1840 break;
1841 case METHOD_GPIO_850:
1842 reg += OMAP850_GPIO_DIR_CONTROL;
1843 break;
1746 case METHOD_GPIO_24XX: 1844 case METHOD_GPIO_24XX:
1747 reg += OMAP24XX_GPIO_OE; 1845 reg += OMAP24XX_GPIO_OE;
1748 break; 1846 break;
@@ -1762,7 +1860,8 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
1762 1860
1763 if (bank_is_mpuio(bank)) 1861 if (bank_is_mpuio(bank))
1764 gpio = OMAP_MPUIO(0); 1862 gpio = OMAP_MPUIO(0);
1765 else if (cpu_class_is_omap2() || cpu_is_omap730()) 1863 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1864 cpu_is_omap850())
1766 bankwidth = 32; 1865 bankwidth = 32;
1767 1866
1768 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 1867 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 8d9dfe314387..2b22a8799bc6 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -31,7 +31,8 @@
31 31
32#define OMAP_MPUIO_BASE 0xfffb5000 32#define OMAP_MPUIO_BASE 0xfffb5000
33 33
34#ifdef CONFIG_ARCH_OMAP730 34#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
35
35#define OMAP_MPUIO_INPUT_LATCH 0x00 36#define OMAP_MPUIO_INPUT_LATCH 0x00
36#define OMAP_MPUIO_OUTPUT 0x02 37#define OMAP_MPUIO_OUTPUT 0x02
37#define OMAP_MPUIO_IO_CNTL 0x04 38#define OMAP_MPUIO_IO_CNTL 0x04
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index f4362b8682c7..6a02f8f4c8bf 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -61,6 +61,16 @@
61 .pull_bit = bit, \ 61 .pull_bit = bit, \
62 .pull_val = status, 62 .pull_val = status,
63 63
64#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
65 .mux_reg = OMAP850_IO_CONF_##reg, \
66 .mask_offset = mode_offset, \
67 .mask = mode,
68
69#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
70 .pull_reg = OMAP850_IO_CONF_##reg, \
71 .pull_bit = bit, \
72 .pull_val = status,
73
64#else 74#else
65 75
66#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ 76#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
@@ -83,6 +93,15 @@
83 .pull_bit = bit, \ 93 .pull_bit = bit, \
84 .pull_val = status, 94 .pull_val = status,
85 95
96#define MUX_REG_850(reg, mode_offset, mode) \
97 .mux_reg = OMAP850_IO_CONF_##reg, \
98 .mask_offset = mode_offset, \
99 .mask = mode,
100
101#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
102 .pull_bit = bit, \
103 .pull_val = status,
104
86#endif /* CONFIG_OMAP_MUX_DEBUG */ 105#endif /* CONFIG_OMAP_MUX_DEBUG */
87 106
88#define MUX_CFG(desc, mux_reg, mode_offset, mode, \ 107#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
@@ -98,7 +117,7 @@
98 117
99 118
100/* 119/*
101 * OMAP730 has a slightly different config for the pin mux. 120 * OMAP730/850 has a slightly different config for the pin mux.
102 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and 121 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
103 * not the FUNC_MUX_CTRL_x regs from hardware.h 122 * not the FUNC_MUX_CTRL_x regs from hardware.h
104 * - for pull-up/down, only has one enable bit which is is in the same register 123 * - for pull-up/down, only has one enable bit which is is in the same register
@@ -114,6 +133,17 @@
114 PU_PD_REG(NA, 0) \ 133 PU_PD_REG(NA, 0) \
115}, 134},
116 135
136#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
137 pull_bit, pull_status, debug_status)\
138{ \
139 .name = desc, \
140 .debug = debug_status, \
141 MUX_REG_850(mux_reg, mode_offset, mode) \
142 PULL_REG_850(mux_reg, pull_bit, pull_status) \
143 PU_PD_REG(NA, 0) \
144},
145
146
117#define MUX_CFG_24XX(desc, reg_offset, mode, \ 147#define MUX_CFG_24XX(desc, reg_offset, mode, \
118 pull_en, pull_mode, dbg) \ 148 pull_en, pull_mode, dbg) \
119{ \ 149{ \
@@ -221,6 +251,26 @@ enum omap730_index {
221 W17_730_USB_VBUSI, 251 W17_730_USB_VBUSI,
222}; 252};
223 253
254enum omap850_index {
255 /* OMAP 850 keyboard */
256 E2_850_KBR0,
257 J7_850_KBR1,
258 E1_850_KBR2,
259 F3_850_KBR3,
260 D2_850_KBR4,
261 C2_850_KBC0,
262 D3_850_KBC1,
263 E4_850_KBC2,
264 F4_850_KBC3,
265 E3_850_KBC4,
266
267 /* USB */
268 AA17_850_USB_DM,
269 W16_850_USB_PU_EN,
270 W17_850_USB_VBUSI,
271};
272
273
224enum omap1xxx_index { 274enum omap1xxx_index {
225 /* UART1 (BT_UART_GATING)*/ 275 /* UART1 (BT_UART_GATING)*/
226 UART1_TX = 0, 276 UART1_TX = 0,