diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-24 02:24:29 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-24 02:24:29 -0500 |
commit | 2a85927c79634e89b9cd683dd2bae65966d9b216 (patch) | |
tree | 5e922b0f26e4099b6bcad65d2d5ea42e166ff068 /arch/arm/plat-mxc | |
parent | 3561d43fd289f590fdae672e5eb831b8d5cf0bf6 (diff) | |
parent | 124bf94a9f9b52341562628cd56b252e7d820ee8 (diff) |
Merge branch 'imx-for-2.6.38' of git://git.pengutronix.de/git/ukl/linux-2.6 into imx-for-2.6.38
Diffstat (limited to 'arch/arm/plat-mxc')
45 files changed, 1486 insertions, 936 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 64e3a64520e0..a31fa161bb6d 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
@@ -21,10 +21,6 @@ config ARCH_MX2 | |||
21 | 21 | ||
22 | config ARCH_MX25 | 22 | config ARCH_MX25 |
23 | bool "MX25-based" | 23 | bool "MX25-based" |
24 | select CPU_ARM926T | ||
25 | select ARCH_MXC_IOMUX_V3 | ||
26 | select HAVE_FB_IMX | ||
27 | select ARCH_MXC_AUDMUX_V2 | ||
28 | help | 24 | help |
29 | This enables support for systems based on the Freescale i.MX25 family | 25 | This enables support for systems based on the Freescale i.MX25 family |
30 | 26 | ||
@@ -51,7 +47,6 @@ endchoice | |||
51 | 47 | ||
52 | source "arch/arm/mach-imx/Kconfig" | 48 | source "arch/arm/mach-imx/Kconfig" |
53 | source "arch/arm/mach-mx3/Kconfig" | 49 | source "arch/arm/mach-mx3/Kconfig" |
54 | source "arch/arm/mach-mx25/Kconfig" | ||
55 | source "arch/arm/mach-mxc91231/Kconfig" | 50 | source "arch/arm/mach-mxc91231/Kconfig" |
56 | source "arch/arm/mach-mx5/Kconfig" | 51 | source "arch/arm/mach-mx5/Kconfig" |
57 | 52 | ||
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0be1ac7f421b..175e3647bb27 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c | |||
@@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void) | |||
209 | audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); | 209 | audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); |
210 | } | 210 | } |
211 | #endif | 211 | #endif |
212 | #if defined(CONFIG_ARCH_MX25) | 212 | #if defined(CONFIG_SOC_IMX25) |
213 | if (cpu_is_mx25()) { | 213 | if (cpu_is_mx25()) { |
214 | audmux_clk = clk_get(NULL, "audmux"); | 214 | audmux_clk = clk_get(NULL, "audmux"); |
215 | if (IS_ERR(audmux_clk)) { | 215 | if (IS_ERR(audmux_clk)) { |
@@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void) | |||
220 | } | 220 | } |
221 | audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); | 221 | audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); |
222 | } | 222 | } |
223 | #endif | 223 | #endif /* if defined(CONFIG_SOC_IMX25) */ |
224 | audmux_debugfs_init(); | 224 | audmux_debugfs_init(); |
225 | 225 | ||
226 | return 0; | 226 | return 0; |
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 735776d84956..e9bcefe79a43 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c | |||
@@ -17,6 +17,7 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
20 | #include <linux/slab.h> | ||
20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
21 | #include <linux/err.h> | 22 | #include <linux/err.h> |
22 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
@@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) | |||
36 | return ret; | 37 | return ret; |
37 | } | 38 | } |
38 | 39 | ||
39 | struct platform_device *__init imx_add_platform_device(const char *name, int id, | 40 | struct platform_device *__init imx_add_platform_device_dmamask( |
41 | const char *name, int id, | ||
40 | const struct resource *res, unsigned int num_resources, | 42 | const struct resource *res, unsigned int num_resources, |
41 | const void *data, size_t size_data) | 43 | const void *data, size_t size_data, u64 dmamask) |
42 | { | 44 | { |
43 | int ret = -ENOMEM; | 45 | int ret = -ENOMEM; |
44 | struct platform_device *pdev; | 46 | struct platform_device *pdev; |
@@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id, | |||
47 | if (!pdev) | 49 | if (!pdev) |
48 | goto err; | 50 | goto err; |
49 | 51 | ||
52 | if (dmamask) { | ||
53 | /* | ||
54 | * This memory isn't freed when the device is put, | ||
55 | * I don't have a nice idea for that though. Conceptually | ||
56 | * dma_mask in struct device should not be a pointer. | ||
57 | * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 | ||
58 | */ | ||
59 | pdev->dev.dma_mask = | ||
60 | kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); | ||
61 | if (!pdev->dev.dma_mask) | ||
62 | /* ret is still -ENOMEM; */ | ||
63 | goto err; | ||
64 | |||
65 | *pdev->dev.dma_mask = dmamask; | ||
66 | pdev->dev.coherent_dma_mask = dmamask; | ||
67 | } | ||
68 | |||
50 | if (res) { | 69 | if (res) { |
51 | ret = platform_device_add_resources(pdev, res, num_resources); | 70 | ret = platform_device_add_resources(pdev, res, num_resources); |
52 | if (ret) | 71 | if (ret) |
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9aa6f3ea9012..b391f4dcfcc2 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig | |||
@@ -1,29 +1,73 @@ | |||
1 | config IMX_HAVE_PLATFORM_ESDHC | ||
2 | bool | ||
3 | |||
4 | config IMX_HAVE_PLATFORM_FEC | 1 | config IMX_HAVE_PLATFORM_FEC |
5 | bool | 2 | bool |
6 | default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 | 3 | default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || ARCH_MX51 |
7 | 4 | ||
8 | config IMX_HAVE_PLATFORM_FLEXCAN | 5 | config IMX_HAVE_PLATFORM_FLEXCAN |
9 | select HAVE_CAN_FLEXCAN if CAN | 6 | select HAVE_CAN_FLEXCAN if CAN |
10 | bool | 7 | bool |
11 | 8 | ||
9 | config IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
10 | bool | ||
11 | |||
12 | config IMX_HAVE_PLATFORM_GPIO_KEYS | 12 | config IMX_HAVE_PLATFORM_GPIO_KEYS |
13 | bool | 13 | bool |
14 | default y if ARCH_MX51 | 14 | default y if ARCH_MX51 |
15 | |||
16 | config IMX_HAVE_PLATFORM_IMX21_HCD | ||
17 | bool | ||
15 | 18 | ||
19 | config IMX_HAVE_PLATFORM_IMX2_WDT | ||
20 | bool | ||
21 | |||
22 | config IMX_HAVE_PLATFORM_IMXDI_RTC | ||
23 | bool | ||
24 | |||
25 | config IMX_HAVE_PLATFORM_IMX_FB | ||
26 | bool | ||
27 | select HAVE_FB_IMX | ||
28 | |||
16 | config IMX_HAVE_PLATFORM_IMX_I2C | 29 | config IMX_HAVE_PLATFORM_IMX_I2C |
17 | bool | 30 | bool |
18 | 31 | ||
32 | config IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
33 | bool | ||
34 | |||
19 | config IMX_HAVE_PLATFORM_IMX_SSI | 35 | config IMX_HAVE_PLATFORM_IMX_SSI |
20 | bool | 36 | bool |
21 | 37 | ||
22 | config IMX_HAVE_PLATFORM_IMX_UART | 38 | config IMX_HAVE_PLATFORM_IMX_UART |
23 | bool | 39 | bool |
24 | 40 | ||
41 | config IMX_HAVE_PLATFORM_IMX_UDC | ||
42 | bool | ||
43 | |||
44 | config IMX_HAVE_PLATFORM_MX1_CAMERA | ||
45 | bool | ||
46 | |||
47 | config IMX_HAVE_PLATFORM_MX2_CAMERA | ||
48 | bool | ||
49 | |||
50 | config IMX_HAVE_PLATFORM_MXC_EHCI | ||
51 | bool | ||
52 | |||
53 | config IMX_HAVE_PLATFORM_MXC_MMC | ||
54 | bool | ||
55 | |||
25 | config IMX_HAVE_PLATFORM_MXC_NAND | 56 | config IMX_HAVE_PLATFORM_MXC_NAND |
26 | bool | 57 | bool |
27 | 58 | ||
59 | config IMX_HAVE_PLATFORM_MXC_PWM | ||
60 | bool | ||
61 | |||
62 | config IMX_HAVE_PLATFORM_MXC_RNGA | ||
63 | bool | ||
64 | select ARCH_HAS_RNGA | ||
65 | |||
66 | config IMX_HAVE_PLATFORM_MXC_W1 | ||
67 | bool | ||
68 | |||
69 | config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
70 | bool | ||
71 | |||
28 | config IMX_HAVE_PLATFORM_SPI_IMX | 72 | config IMX_HAVE_PLATFORM_SPI_IMX |
29 | bool | 73 | bool |
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 45aefeb283ba..75cd2ece9053 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile | |||
@@ -1,10 +1,24 @@ | |||
1 | obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o | ||
2 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o | 1 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o |
3 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o | 2 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o |
3 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o | ||
4 | obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o | 4 | obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o |
5 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o | ||
6 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o | ||
7 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o | ||
5 | obj-y += platform-imx-dma.o | 8 | obj-y += platform-imx-dma.o |
9 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o | ||
6 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o | 10 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o |
11 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o | ||
7 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o | 12 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o |
8 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o | 13 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o |
14 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o | ||
15 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o | ||
16 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o | ||
17 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o | ||
18 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o | ||
9 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o | 19 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o |
20 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o | ||
21 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o | ||
22 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o | ||
23 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o | ||
10 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o | 24 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o |
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 2605bfa0dfb0..000000000000 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null | |||
@@ -1,71 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it under | ||
5 | * the terms of the GNU General Public License version 2 as published by the | ||
6 | * Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | #include <mach/esdhc.h> | ||
12 | |||
13 | #define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \ | ||
14 | { \ | ||
15 | .id = _id, \ | ||
16 | .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ | ||
17 | .irq = soc ## _INT_ESDHC ## hwid, \ | ||
18 | } | ||
19 | |||
20 | #define imx_esdhc_imx_data_entry(soc, id, hwid) \ | ||
21 | [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) | ||
22 | |||
23 | #ifdef CONFIG_ARCH_MX25 | ||
24 | const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { | ||
25 | #define imx25_esdhc_data_entry(_id, _hwid) \ | ||
26 | imx_esdhc_imx_data_entry(MX25, _id, _hwid) | ||
27 | imx25_esdhc_data_entry(0, 1), | ||
28 | imx25_esdhc_data_entry(1, 2), | ||
29 | }; | ||
30 | #endif /* ifdef CONFIG_ARCH_MX25 */ | ||
31 | |||
32 | #ifdef CONFIG_ARCH_MX35 | ||
33 | const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { | ||
34 | #define imx35_esdhc_data_entry(_id, _hwid) \ | ||
35 | imx_esdhc_imx_data_entry(MX35, _id, _hwid) | ||
36 | imx35_esdhc_data_entry(0, 1), | ||
37 | imx35_esdhc_data_entry(1, 2), | ||
38 | imx35_esdhc_data_entry(2, 3), | ||
39 | }; | ||
40 | #endif /* ifdef CONFIG_ARCH_MX35 */ | ||
41 | |||
42 | #ifdef CONFIG_ARCH_MX51 | ||
43 | const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { | ||
44 | #define imx51_esdhc_data_entry(_id, _hwid) \ | ||
45 | imx_esdhc_imx_data_entry(MX51, _id, _hwid) | ||
46 | imx51_esdhc_data_entry(0, 1), | ||
47 | imx51_esdhc_data_entry(1, 2), | ||
48 | imx51_esdhc_data_entry(2, 3), | ||
49 | imx51_esdhc_data_entry(3, 4), | ||
50 | }; | ||
51 | #endif /* ifdef CONFIG_ARCH_MX51 */ | ||
52 | |||
53 | struct platform_device *__init imx_add_esdhc( | ||
54 | const struct imx_esdhc_imx_data *data, | ||
55 | const struct esdhc_platform_data *pdata) | ||
56 | { | ||
57 | struct resource res[] = { | ||
58 | { | ||
59 | .start = data->iobase, | ||
60 | .end = data->iobase + SZ_16K - 1, | ||
61 | .flags = IORESOURCE_MEM, | ||
62 | }, { | ||
63 | .start = data->irq, | ||
64 | .end = data->irq, | ||
65 | .flags = IORESOURCE_IRQ, | ||
66 | }, | ||
67 | }; | ||
68 | |||
69 | return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, | ||
70 | ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
71 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 11d087f4e219..8d78aedf8a93 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c | |||
@@ -16,17 +16,17 @@ | |||
16 | .irq = soc ## _INT_FEC, \ | 16 | .irq = soc ## _INT_FEC, \ |
17 | } | 17 | } |
18 | 18 | ||
19 | #ifdef CONFIG_ARCH_MX25 | 19 | #ifdef CONFIG_SOC_IMX25 |
20 | const struct imx_fec_data imx25_fec_data __initconst = | 20 | const struct imx_fec_data imx25_fec_data __initconst = |
21 | imx_fec_data_entry_single(MX25); | 21 | imx_fec_data_entry_single(MX25); |
22 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 22 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
23 | 23 | ||
24 | #ifdef CONFIG_SOC_IMX27 | 24 | #ifdef CONFIG_SOC_IMX27 |
25 | const struct imx_fec_data imx27_fec_data __initconst = | 25 | const struct imx_fec_data imx27_fec_data __initconst = |
26 | imx_fec_data_entry_single(MX27); | 26 | imx_fec_data_entry_single(MX27); |
27 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 27 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
28 | 28 | ||
29 | #ifdef CONFIG_ARCH_MX35 | 29 | #ifdef CONFIG_SOC_IMX35 |
30 | const struct imx_fec_data imx35_fec_data __initconst = | 30 | const struct imx_fec_data imx35_fec_data __initconst = |
31 | imx_fec_data_entry_single(MX35); | 31 | imx_fec_data_entry_single(MX35); |
32 | #endif | 32 | #endif |
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5e97a01f14f3..4e8497af2eb1 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c | |||
@@ -5,26 +5,54 @@ | |||
5 | * the terms of the GNU General Public License version 2 as published by the | 5 | * the terms of the GNU General Public License version 2 as published by the |
6 | * Free Software Foundation. | 6 | * Free Software Foundation. |
7 | */ | 7 | */ |
8 | 8 | #include <mach/hardware.h> | |
9 | #include <mach/devices-common.h> | 9 | #include <mach/devices-common.h> |
10 | 10 | ||
11 | struct platform_device *__init imx_add_flexcan(int id, | 11 | #define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ |
12 | resource_size_t iobase, resource_size_t iosize, | 12 | { \ |
13 | resource_size_t irq, | 13 | .id = _id, \ |
14 | .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ | ||
15 | .iosize = _size, \ | ||
16 | .irq = soc ## _INT_CAN ## _hwid, \ | ||
17 | } | ||
18 | |||
19 | #define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ | ||
20 | [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) | ||
21 | |||
22 | #ifdef CONFIG_SOC_IMX25 | ||
23 | const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { | ||
24 | #define imx25_flexcan_data_entry(_id, _hwid) \ | ||
25 | imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) | ||
26 | imx25_flexcan_data_entry(0, 1), | ||
27 | imx25_flexcan_data_entry(1, 2), | ||
28 | }; | ||
29 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
30 | |||
31 | #ifdef CONFIG_SOC_IMX35 | ||
32 | const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { | ||
33 | #define imx35_flexcan_data_entry(_id, _hwid) \ | ||
34 | imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) | ||
35 | imx35_flexcan_data_entry(0, 1), | ||
36 | imx35_flexcan_data_entry(1, 2), | ||
37 | }; | ||
38 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
39 | |||
40 | struct platform_device *__init imx_add_flexcan( | ||
41 | const struct imx_flexcan_data *data, | ||
14 | const struct flexcan_platform_data *pdata) | 42 | const struct flexcan_platform_data *pdata) |
15 | { | 43 | { |
16 | struct resource res[] = { | 44 | struct resource res[] = { |
17 | { | 45 | { |
18 | .start = iobase, | 46 | .start = data->iobase, |
19 | .end = iobase + iosize - 1, | 47 | .end = data->iobase + data->iosize - 1, |
20 | .flags = IORESOURCE_MEM, | 48 | .flags = IORESOURCE_MEM, |
21 | }, { | 49 | }, { |
22 | .start = irq, | 50 | .start = data->irq, |
23 | .end = irq, | 51 | .end = data->irq, |
24 | .flags = IORESOURCE_IRQ, | 52 | .flags = IORESOURCE_IRQ, |
25 | }, | 53 | }, |
26 | }; | 54 | }; |
27 | 55 | ||
28 | return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), | 56 | return imx_add_platform_device("flexcan", data->id, |
29 | pdata, sizeof(*pdata)); | 57 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); |
30 | } | 58 | } |
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 000000000000..59c33f6e401c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_fsl_usb2_udc_data_entry_single(soc) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _USB_OTG_BASE_ADDR, \ | ||
15 | .irq = soc ## _INT_USB_OTG, \ | ||
16 | } | ||
17 | |||
18 | #ifdef CONFIG_SOC_IMX25 | ||
19 | const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = | ||
20 | imx_fsl_usb2_udc_data_entry_single(MX25); | ||
21 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
22 | |||
23 | #ifdef CONFIG_SOC_IMX27 | ||
24 | const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = | ||
25 | imx_fsl_usb2_udc_data_entry_single(MX27); | ||
26 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
27 | |||
28 | #ifdef CONFIG_SOC_IMX31 | ||
29 | const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = | ||
30 | imx_fsl_usb2_udc_data_entry_single(MX31); | ||
31 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
32 | |||
33 | #ifdef CONFIG_SOC_IMX35 | ||
34 | const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = | ||
35 | imx_fsl_usb2_udc_data_entry_single(MX35); | ||
36 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
37 | |||
38 | struct platform_device *__init imx_add_fsl_usb2_udc( | ||
39 | const struct imx_fsl_usb2_udc_data *data, | ||
40 | const struct fsl_usb2_platform_data *pdata) | ||
41 | { | ||
42 | struct resource res[] = { | ||
43 | { | ||
44 | .start = data->iobase, | ||
45 | .end = data->iobase + SZ_512 - 1, | ||
46 | .flags = IORESOURCE_MEM, | ||
47 | }, { | ||
48 | .start = data->irq, | ||
49 | .end = data->irq, | ||
50 | .flags = IORESOURCE_IRQ, | ||
51 | }, | ||
52 | }; | ||
53 | return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, | ||
54 | res, ARRAY_SIZE(res), | ||
55 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
56 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 02d989018059..10f41ccf4146 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c | |||
@@ -39,20 +39,20 @@ struct imx_imx_sdma_data { | |||
39 | }, \ | 39 | }, \ |
40 | } | 40 | } |
41 | 41 | ||
42 | #ifdef CONFIG_ARCH_MX25 | 42 | #ifdef CONFIG_SOC_IMX25 |
43 | const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = | 43 | const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = |
44 | imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); | 44 | imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); |
45 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 45 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
46 | 46 | ||
47 | #ifdef CONFIG_ARCH_MX31 | 47 | #ifdef CONFIG_SOC_IMX31 |
48 | struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = | 48 | struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = |
49 | imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); | 49 | imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); |
50 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 50 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
51 | 51 | ||
52 | #ifdef CONFIG_ARCH_MX35 | 52 | #ifdef CONFIG_SOC_IMX35 |
53 | struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = | 53 | struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = |
54 | imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); | 54 | imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); |
55 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 55 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
56 | 56 | ||
57 | #ifdef CONFIG_ARCH_MX51 | 57 | #ifdef CONFIG_ARCH_MX51 |
58 | const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = | 58 | const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = |
@@ -94,20 +94,20 @@ static int __init imxXX_add_imx_dma(void) | |||
94 | else | 94 | else |
95 | #endif | 95 | #endif |
96 | 96 | ||
97 | #if defined(CONFIG_ARCH_MX25) | 97 | #if defined(CONFIG_SOC_IMX25) |
98 | if (cpu_is_mx25()) | 98 | if (cpu_is_mx25()) |
99 | ret = imx_add_imx_sdma(&imx25_imx_sdma_data); | 99 | ret = imx_add_imx_sdma(&imx25_imx_sdma_data); |
100 | else | 100 | else |
101 | #endif | 101 | #endif |
102 | 102 | ||
103 | #if defined(CONFIG_ARCH_MX31) | 103 | #if defined(CONFIG_SOC_IMX31) |
104 | if (cpu_is_mx31()) { | 104 | if (cpu_is_mx31()) { |
105 | imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; | 105 | imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; |
106 | ret = imx_add_imx_sdma(&imx31_imx_sdma_data); | 106 | ret = imx_add_imx_sdma(&imx31_imx_sdma_data); |
107 | } else | 107 | } else |
108 | #endif | 108 | #endif |
109 | 109 | ||
110 | #if defined(CONFIG_ARCH_MX35) | 110 | #if defined(CONFIG_SOC_IMX35) |
111 | if (cpu_is_mx35()) { | 111 | if (cpu_is_mx35()) { |
112 | imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; | 112 | imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; |
113 | ret = imx_add_imx_sdma(&imx35_imx_sdma_data); | 113 | ret = imx_add_imx_sdma(&imx35_imx_sdma_data); |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 000000000000..6100a7d824dd --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_imx_fb_data_entry_single(soc, _size) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _LCDC_BASE_ADDR, \ | ||
15 | .iosize = _size, \ | ||
16 | .irq = soc ## _INT_LCDC, \ | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_SOC_IMX21 | ||
20 | const struct imx_imx_fb_data imx21_imx_fb_data __initconst = | ||
21 | imx_imx_fb_data_entry_single(MX21, SZ_4K); | ||
22 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
23 | |||
24 | #ifdef CONFIG_SOC_IMX25 | ||
25 | const struct imx_imx_fb_data imx25_imx_fb_data __initconst = | ||
26 | imx_imx_fb_data_entry_single(MX25, SZ_16K); | ||
27 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
28 | |||
29 | #ifdef CONFIG_SOC_IMX27 | ||
30 | const struct imx_imx_fb_data imx27_imx_fb_data __initconst = | ||
31 | imx_imx_fb_data_entry_single(MX27, SZ_4K); | ||
32 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
33 | |||
34 | struct platform_device *__init imx_add_imx_fb( | ||
35 | const struct imx_imx_fb_data *data, | ||
36 | const struct imx_fb_platform_data *pdata) | ||
37 | { | ||
38 | struct resource res[] = { | ||
39 | { | ||
40 | .start = data->iobase, | ||
41 | .end = data->iobase + data->iosize - 1, | ||
42 | .flags = IORESOURCE_MEM, | ||
43 | }, { | ||
44 | .start = data->irq, | ||
45 | .end = data->irq, | ||
46 | .flags = IORESOURCE_IRQ, | ||
47 | }, | ||
48 | }; | ||
49 | return imx_add_platform_device_dmamask("imx-fb", 0, | ||
50 | res, ARRAY_SIZE(res), | ||
51 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
52 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 679588453aad..075bd8e337f8 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c | |||
@@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = | |||
30 | imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); | 30 | imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); |
31 | #endif /* ifdef CONFIG_SOC_IMX21 */ | 31 | #endif /* ifdef CONFIG_SOC_IMX21 */ |
32 | 32 | ||
33 | #ifdef CONFIG_ARCH_MX25 | 33 | #ifdef CONFIG_SOC_IMX25 |
34 | const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { | 34 | const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { |
35 | #define imx25_imx_i2c_data_entry(_id, _hwid) \ | 35 | #define imx25_imx_i2c_data_entry(_id, _hwid) \ |
36 | imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) | 36 | imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) |
@@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { | |||
38 | imx25_imx_i2c_data_entry(1, 2), | 38 | imx25_imx_i2c_data_entry(1, 2), |
39 | imx25_imx_i2c_data_entry(2, 3), | 39 | imx25_imx_i2c_data_entry(2, 3), |
40 | }; | 40 | }; |
41 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 41 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
42 | 42 | ||
43 | #ifdef CONFIG_SOC_IMX27 | 43 | #ifdef CONFIG_SOC_IMX27 |
44 | const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { | 44 | const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { |
@@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { | |||
49 | }; | 49 | }; |
50 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 50 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
51 | 51 | ||
52 | #ifdef CONFIG_ARCH_MX31 | 52 | #ifdef CONFIG_SOC_IMX31 |
53 | const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { | 53 | const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { |
54 | #define imx31_imx_i2c_data_entry(_id, _hwid) \ | 54 | #define imx31_imx_i2c_data_entry(_id, _hwid) \ |
55 | imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) | 55 | imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) |
@@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { | |||
57 | imx31_imx_i2c_data_entry(1, 2), | 57 | imx31_imx_i2c_data_entry(1, 2), |
58 | imx31_imx_i2c_data_entry(2, 3), | 58 | imx31_imx_i2c_data_entry(2, 3), |
59 | }; | 59 | }; |
60 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 60 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
61 | 61 | ||
62 | #ifdef CONFIG_ARCH_MX35 | 62 | #ifdef CONFIG_SOC_IMX35 |
63 | const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { | 63 | const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { |
64 | #define imx35_imx_i2c_data_entry(_id, _hwid) \ | 64 | #define imx35_imx_i2c_data_entry(_id, _hwid) \ |
65 | imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) | 65 | imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) |
@@ -67,7 +67,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { | |||
67 | imx35_imx_i2c_data_entry(1, 2), | 67 | imx35_imx_i2c_data_entry(1, 2), |
68 | imx35_imx_i2c_data_entry(2, 3), | 68 | imx35_imx_i2c_data_entry(2, 3), |
69 | }; | 69 | }; |
70 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 70 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
71 | 71 | ||
72 | #ifdef CONFIG_ARCH_MX51 | 72 | #ifdef CONFIG_ARCH_MX51 |
73 | const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { | 73 | const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 000000000000..40238f0b8643 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c | |||
@@ -0,0 +1,62 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_imx_keypad_data_entry_single(soc, _size) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _KPP_BASE_ADDR, \ | ||
15 | .iosize = _size, \ | ||
16 | .irq = soc ## _INT_KPP, \ | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_SOC_IMX21 | ||
20 | const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = | ||
21 | imx_imx_keypad_data_entry_single(MX21, SZ_16); | ||
22 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
23 | |||
24 | #ifdef CONFIG_SOC_IMX25 | ||
25 | const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = | ||
26 | imx_imx_keypad_data_entry_single(MX25, SZ_16K); | ||
27 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
28 | |||
29 | #ifdef CONFIG_SOC_IMX27 | ||
30 | const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = | ||
31 | imx_imx_keypad_data_entry_single(MX27, SZ_16); | ||
32 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
33 | |||
34 | #ifdef CONFIG_SOC_IMX31 | ||
35 | const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = | ||
36 | imx_imx_keypad_data_entry_single(MX31, SZ_16); | ||
37 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
38 | |||
39 | #ifdef CONFIG_SOC_IMX35 | ||
40 | const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = | ||
41 | imx_imx_keypad_data_entry_single(MX35, SZ_16); | ||
42 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
43 | |||
44 | struct platform_device *__init imx_add_imx_keypad( | ||
45 | const struct imx_imx_keypad_data *data, | ||
46 | const struct matrix_keymap_data *pdata) | ||
47 | { | ||
48 | struct resource res[] = { | ||
49 | { | ||
50 | .start = data->iobase, | ||
51 | .end = data->iobase + data->iosize - 1, | ||
52 | .flags = IORESOURCE_MEM, | ||
53 | }, { | ||
54 | .start = data->irq, | ||
55 | .end = data->irq, | ||
56 | .flags = IORESOURCE_IRQ, | ||
57 | }, | ||
58 | }; | ||
59 | |||
60 | return imx_add_platform_device("imx-keypad", -1, | ||
61 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
62 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 38a7a0b8f2f1..02002fc9ea24 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c | |||
@@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { | |||
30 | }; | 30 | }; |
31 | #endif /* ifdef CONFIG_SOC_IMX21 */ | 31 | #endif /* ifdef CONFIG_SOC_IMX21 */ |
32 | 32 | ||
33 | #ifdef CONFIG_ARCH_MX25 | 33 | #ifdef CONFIG_SOC_IMX25 |
34 | const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { | 34 | const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { |
35 | #define imx25_imx_ssi_data_entry(_id, _hwid) \ | 35 | #define imx25_imx_ssi_data_entry(_id, _hwid) \ |
36 | imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) | 36 | imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) |
37 | imx25_imx_ssi_data_entry(0, 1), | 37 | imx25_imx_ssi_data_entry(0, 1), |
38 | imx25_imx_ssi_data_entry(1, 2), | 38 | imx25_imx_ssi_data_entry(1, 2), |
39 | }; | 39 | }; |
40 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 40 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
41 | 41 | ||
42 | #ifdef CONFIG_SOC_IMX27 | 42 | #ifdef CONFIG_SOC_IMX27 |
43 | const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { | 43 | const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { |
@@ -48,23 +48,23 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { | |||
48 | }; | 48 | }; |
49 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 49 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
50 | 50 | ||
51 | #ifdef CONFIG_ARCH_MX31 | 51 | #ifdef CONFIG_SOC_IMX31 |
52 | const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { | 52 | const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { |
53 | #define imx31_imx_ssi_data_entry(_id, _hwid) \ | 53 | #define imx31_imx_ssi_data_entry(_id, _hwid) \ |
54 | imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) | 54 | imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) |
55 | imx31_imx_ssi_data_entry(0, 1), | 55 | imx31_imx_ssi_data_entry(0, 1), |
56 | imx31_imx_ssi_data_entry(1, 2), | 56 | imx31_imx_ssi_data_entry(1, 2), |
57 | }; | 57 | }; |
58 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 58 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
59 | 59 | ||
60 | #ifdef CONFIG_ARCH_MX35 | 60 | #ifdef CONFIG_SOC_IMX35 |
61 | const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { | 61 | const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { |
62 | #define imx35_imx_ssi_data_entry(_id, _hwid) \ | 62 | #define imx35_imx_ssi_data_entry(_id, _hwid) \ |
63 | imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) | 63 | imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) |
64 | imx35_imx_ssi_data_entry(0, 1), | 64 | imx35_imx_ssi_data_entry(0, 1), |
65 | imx35_imx_ssi_data_entry(1, 2), | 65 | imx35_imx_ssi_data_entry(1, 2), |
66 | }; | 66 | }; |
67 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 67 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
68 | 68 | ||
69 | #ifdef CONFIG_ARCH_MX51 | 69 | #ifdef CONFIG_ARCH_MX51 |
70 | const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { | 70 | const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640adf27..08bbd65ee019 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c | |||
@@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { | |||
47 | }; | 47 | }; |
48 | #endif | 48 | #endif |
49 | 49 | ||
50 | #ifdef CONFIG_ARCH_MX25 | 50 | #ifdef CONFIG_SOC_IMX25 |
51 | const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { | 51 | const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { |
52 | #define imx25_imx_uart_data_entry(_id, _hwid) \ | 52 | #define imx25_imx_uart_data_entry(_id, _hwid) \ |
53 | imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) | 53 | imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) |
@@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { | |||
57 | imx25_imx_uart_data_entry(3, 4), | 57 | imx25_imx_uart_data_entry(3, 4), |
58 | imx25_imx_uart_data_entry(4, 5), | 58 | imx25_imx_uart_data_entry(4, 5), |
59 | }; | 59 | }; |
60 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 60 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
61 | 61 | ||
62 | #ifdef CONFIG_SOC_IMX27 | 62 | #ifdef CONFIG_SOC_IMX27 |
63 | const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { | 63 | const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { |
@@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { | |||
72 | }; | 72 | }; |
73 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 73 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
74 | 74 | ||
75 | #ifdef CONFIG_ARCH_MX31 | 75 | #ifdef CONFIG_SOC_IMX31 |
76 | const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { | 76 | const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { |
77 | #define imx31_imx_uart_data_entry(_id, _hwid) \ | 77 | #define imx31_imx_uart_data_entry(_id, _hwid) \ |
78 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) | 78 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) |
@@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { | |||
82 | imx31_imx_uart_data_entry(3, 4), | 82 | imx31_imx_uart_data_entry(3, 4), |
83 | imx31_imx_uart_data_entry(4, 5), | 83 | imx31_imx_uart_data_entry(4, 5), |
84 | }; | 84 | }; |
85 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 85 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
86 | 86 | ||
87 | #ifdef CONFIG_ARCH_MX35 | 87 | #ifdef CONFIG_SOC_IMX35 |
88 | const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { | 88 | const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { |
89 | #define imx35_imx_uart_data_entry(_id, _hwid) \ | 89 | #define imx35_imx_uart_data_entry(_id, _hwid) \ |
90 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) | 90 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) |
@@ -92,7 +92,7 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { | |||
92 | imx35_imx_uart_data_entry(1, 2), | 92 | imx35_imx_uart_data_entry(1, 2), |
93 | imx35_imx_uart_data_entry(2, 3), | 93 | imx35_imx_uart_data_entry(2, 3), |
94 | }; | 94 | }; |
95 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 95 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
96 | 96 | ||
97 | #ifdef CONFIG_ARCH_MX51 | 97 | #ifdef CONFIG_ARCH_MX51 |
98 | const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { | 98 | const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { |
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 000000000000..c61bd4e63149 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <asm/sizes.h> | ||
10 | #include <mach/hardware.h> | ||
11 | #include <mach/devices-common.h> | ||
12 | |||
13 | #define imx_imx2_wdt_data_entry_single(soc, _size) \ | ||
14 | { \ | ||
15 | .iobase = soc ## _WDOG_BASE_ADDR, \ | ||
16 | .iosize = _size, \ | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_SOC_IMX21 | ||
20 | const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = | ||
21 | imx_imx2_wdt_data_entry_single(MX21, SZ_4K); | ||
22 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
23 | |||
24 | #ifdef CONFIG_SOC_IMX25 | ||
25 | const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = | ||
26 | imx_imx2_wdt_data_entry_single(MX25, SZ_16K); | ||
27 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
28 | |||
29 | #ifdef CONFIG_SOC_IMX27 | ||
30 | const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = | ||
31 | imx_imx2_wdt_data_entry_single(MX27, SZ_4K); | ||
32 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
33 | |||
34 | #ifdef CONFIG_SOC_IMX31 | ||
35 | const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = | ||
36 | imx_imx2_wdt_data_entry_single(MX31, SZ_16K); | ||
37 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
38 | |||
39 | #ifdef CONFIG_SOC_IMX35 | ||
40 | const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = | ||
41 | imx_imx2_wdt_data_entry_single(MX35, SZ_16K); | ||
42 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
43 | |||
44 | struct platform_device *__init imx_add_imx2_wdt( | ||
45 | const struct imx_imx2_wdt_data *data) | ||
46 | { | ||
47 | struct resource res[] = { | ||
48 | { | ||
49 | .start = data->iobase, | ||
50 | .end = data->iobase + data->iosize - 1, | ||
51 | .flags = IORESOURCE_MEM, | ||
52 | }, | ||
53 | }; | ||
54 | return imx_add_platform_device("imx2-wdt", 0, | ||
55 | res, ARRAY_SIZE(res), NULL, 0); | ||
56 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 000000000000..5770a42f33bf --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_imx21_hcd_data_entry_single(soc) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _USBOTG_BASE_ADDR, \ | ||
15 | .irq = soc ## _INT_USBHOST, \ | ||
16 | } | ||
17 | |||
18 | #ifdef CONFIG_SOC_IMX21 | ||
19 | const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = | ||
20 | imx_imx21_hcd_data_entry_single(MX21); | ||
21 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
22 | |||
23 | struct platform_device *__init imx_add_imx21_hcd( | ||
24 | const struct imx_imx21_hcd_data *data, | ||
25 | const struct mx21_usbh_platform_data *pdata) | ||
26 | { | ||
27 | struct resource res[] = { | ||
28 | { | ||
29 | .start = data->iobase, | ||
30 | .end = data->iobase + SZ_8K - 1, | ||
31 | .flags = IORESOURCE_MEM, | ||
32 | }, { | ||
33 | .start = data->irq, | ||
34 | .end = data->irq, | ||
35 | .flags = IORESOURCE_IRQ, | ||
36 | }, | ||
37 | }; | ||
38 | return imx_add_platform_device_dmamask("imx21-hcd", 0, | ||
39 | res, ARRAY_SIZE(res), | ||
40 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
41 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 000000000000..6fd675dfce14 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c | |||
@@ -0,0 +1,75 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_imx_udc_data_entry_single(soc, _size) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _USBD_BASE_ADDR, \ | ||
15 | .iosize = _size, \ | ||
16 | .irq0 = soc ## _INT_USBD0, \ | ||
17 | .irq1 = soc ## _INT_USBD1, \ | ||
18 | .irq2 = soc ## _INT_USBD2, \ | ||
19 | .irq3 = soc ## _INT_USBD3, \ | ||
20 | .irq4 = soc ## _INT_USBD4, \ | ||
21 | .irq5 = soc ## _INT_USBD5, \ | ||
22 | .irq6 = soc ## _INT_USBD6, \ | ||
23 | } | ||
24 | |||
25 | #define imx_imx_udc_data_entry(soc, _size) \ | ||
26 | [_id] = imx_imx_udc_data_entry_single(soc, _size) | ||
27 | |||
28 | #ifdef CONFIG_SOC_IMX1 | ||
29 | const struct imx_imx_udc_data imx1_imx_udc_data __initconst = | ||
30 | imx_imx_udc_data_entry_single(MX1, SZ_4K); | ||
31 | #endif /* ifdef CONFIG_SOC_IMX1 */ | ||
32 | |||
33 | struct platform_device *__init imx_add_imx_udc( | ||
34 | const struct imx_imx_udc_data *data, | ||
35 | const struct imxusb_platform_data *pdata) | ||
36 | { | ||
37 | struct resource res[] = { | ||
38 | { | ||
39 | .start = data->iobase, | ||
40 | .end = data->iobase + data->iosize - 1, | ||
41 | .flags = IORESOURCE_MEM, | ||
42 | }, { | ||
43 | .start = data->irq0, | ||
44 | .end = data->irq0, | ||
45 | .flags = IORESOURCE_IRQ, | ||
46 | }, { | ||
47 | .start = data->irq1, | ||
48 | .end = data->irq1, | ||
49 | .flags = IORESOURCE_IRQ, | ||
50 | }, { | ||
51 | .start = data->irq2, | ||
52 | .end = data->irq2, | ||
53 | .flags = IORESOURCE_IRQ, | ||
54 | }, { | ||
55 | .start = data->irq3, | ||
56 | .end = data->irq3, | ||
57 | .flags = IORESOURCE_IRQ, | ||
58 | }, { | ||
59 | .start = data->irq4, | ||
60 | .end = data->irq4, | ||
61 | .flags = IORESOURCE_IRQ, | ||
62 | }, { | ||
63 | .start = data->irq5, | ||
64 | .end = data->irq5, | ||
65 | .flags = IORESOURCE_IRQ, | ||
66 | }, { | ||
67 | .start = data->irq6, | ||
68 | .end = data->irq6, | ||
69 | .flags = IORESOURCE_IRQ, | ||
70 | }, | ||
71 | }; | ||
72 | |||
73 | return imx_add_platform_device("imx_udc", 0, | ||
74 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
75 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 000000000000..10653cc8d1fa --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <asm/sizes.h> | ||
10 | #include <mach/hardware.h> | ||
11 | #include <mach/devices-common.h> | ||
12 | |||
13 | #define imx_imxdi_rtc_data_entry_single(soc) \ | ||
14 | { \ | ||
15 | .iobase = soc ## _DRYICE_BASE_ADDR, \ | ||
16 | .irq = soc ## _INT_DRYICE, \ | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_SOC_IMX25 | ||
20 | const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = | ||
21 | imx_imxdi_rtc_data_entry_single(MX25); | ||
22 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
23 | |||
24 | struct platform_device *__init imx_add_imxdi_rtc( | ||
25 | const struct imx_imxdi_rtc_data *data) | ||
26 | { | ||
27 | struct resource res[] = { | ||
28 | { | ||
29 | .start = data->iobase, | ||
30 | .end = data->iobase + SZ_16K, | ||
31 | .flags = IORESOURCE_MEM, | ||
32 | }, { | ||
33 | .start = data->irq, | ||
34 | .end = data->irq, | ||
35 | .flags = IORESOURCE_IRQ, | ||
36 | }, | ||
37 | }; | ||
38 | |||
39 | return imx_add_platform_device("imxdi_rtc", 0, | ||
40 | res, ARRAY_SIZE(res), NULL, 0); | ||
41 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 000000000000..edcc581a30a9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_mx1_camera_data_entry_single(soc, _size) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _CSI ## _BASE_ADDR, \ | ||
15 | .iosize = _size, \ | ||
16 | .irq = soc ## _INT_CSI, \ | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_SOC_IMX1 | ||
20 | const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = | ||
21 | imx_mx1_camera_data_entry_single(MX1, 10); | ||
22 | #endif /* ifdef CONFIG_SOC_IMX1 */ | ||
23 | |||
24 | struct platform_device *__init imx_add_mx1_camera( | ||
25 | const struct imx_mx1_camera_data *data, | ||
26 | const struct mx1_camera_pdata *pdata) | ||
27 | { | ||
28 | struct resource res[] = { | ||
29 | { | ||
30 | .start = data->iobase, | ||
31 | .end = data->iobase + data->iosize - 1, | ||
32 | .flags = IORESOURCE_MEM, | ||
33 | }, { | ||
34 | .start = data->irq, | ||
35 | .end = data->irq, | ||
36 | .flags = IORESOURCE_IRQ, | ||
37 | }, | ||
38 | }; | ||
39 | return imx_add_platform_device_dmamask("mx1-camera", 0, | ||
40 | res, ARRAY_SIZE(res), | ||
41 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
42 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 000000000000..b3f4828dc447 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_mx2_camera_data_entry_single(soc) \ | ||
13 | { \ | ||
14 | .iobasecsi = soc ## _CSI_BASE_ADDR, \ | ||
15 | .iosizecsi = SZ_4K, \ | ||
16 | .irqcsi = soc ## _INT_CSI, \ | ||
17 | } | ||
18 | #define imx_mx2_camera_data_entry_single_emma(soc) \ | ||
19 | { \ | ||
20 | .iobasecsi = soc ## _CSI_BASE_ADDR, \ | ||
21 | .iosizecsi = SZ_32, \ | ||
22 | .irqcsi = soc ## _INT_CSI, \ | ||
23 | .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ | ||
24 | .iosizeemmaprp = SZ_32, \ | ||
25 | .irqemmaprp = soc ## _INT_EMMAPRP, \ | ||
26 | } | ||
27 | |||
28 | #ifdef CONFIG_SOC_IMX25 | ||
29 | const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = | ||
30 | imx_mx2_camera_data_entry_single(MX25); | ||
31 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
32 | |||
33 | #ifdef CONFIG_SOC_IMX27 | ||
34 | const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = | ||
35 | imx_mx2_camera_data_entry_single_emma(MX27); | ||
36 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
37 | |||
38 | struct platform_device *__init imx_add_mx2_camera( | ||
39 | const struct imx_mx2_camera_data *data, | ||
40 | const struct mx2_camera_platform_data *pdata) | ||
41 | { | ||
42 | struct resource res[] = { | ||
43 | { | ||
44 | .start = data->iobasecsi, | ||
45 | .end = data->iobasecsi + data->iosizecsi - 1, | ||
46 | .flags = IORESOURCE_MEM, | ||
47 | }, { | ||
48 | .start = data->irqcsi, | ||
49 | .end = data->irqcsi, | ||
50 | .flags = IORESOURCE_IRQ, | ||
51 | }, { | ||
52 | .start = data->iobaseemmaprp, | ||
53 | .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, | ||
54 | .flags = IORESOURCE_MEM, | ||
55 | }, { | ||
56 | .start = data->irqemmaprp, | ||
57 | .end = data->irqemmaprp, | ||
58 | .flags = IORESOURCE_IRQ, | ||
59 | }, | ||
60 | }; | ||
61 | return imx_add_platform_device_dmamask("mx2-camera", 0, | ||
62 | res, data->iobaseemmaprp ? 4 : 2, | ||
63 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
64 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 000000000000..cc488f4b6204 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ | ||
13 | { \ | ||
14 | .id = _id, \ | ||
15 | .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ | ||
16 | .irq = soc ## _INT_USB_ ## hs, \ | ||
17 | } | ||
18 | |||
19 | #ifdef CONFIG_SOC_IMX25 | ||
20 | const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = | ||
21 | imx_mxc_ehci_data_entry_single(MX25, 0, OTG); | ||
22 | const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = | ||
23 | imx_mxc_ehci_data_entry_single(MX25, 1, HS); | ||
24 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
25 | |||
26 | #ifdef CONFIG_SOC_IMX27 | ||
27 | const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = | ||
28 | imx_mxc_ehci_data_entry_single(MX27, 0, OTG); | ||
29 | const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { | ||
30 | imx_mxc_ehci_data_entry_single(MX27, 1, HS1), | ||
31 | imx_mxc_ehci_data_entry_single(MX27, 2, HS2), | ||
32 | }; | ||
33 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
34 | |||
35 | #ifdef CONFIG_SOC_IMX31 | ||
36 | const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = | ||
37 | imx_mxc_ehci_data_entry_single(MX31, 0, OTG); | ||
38 | const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { | ||
39 | imx_mxc_ehci_data_entry_single(MX31, 1, HS1), | ||
40 | imx_mxc_ehci_data_entry_single(MX31, 2, HS2), | ||
41 | }; | ||
42 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
43 | |||
44 | #ifdef CONFIG_SOC_IMX35 | ||
45 | const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = | ||
46 | imx_mxc_ehci_data_entry_single(MX35, 0, OTG); | ||
47 | const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = | ||
48 | imx_mxc_ehci_data_entry_single(MX35, 1, HS); | ||
49 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
50 | |||
51 | struct platform_device *__init imx_add_mxc_ehci( | ||
52 | const struct imx_mxc_ehci_data *data, | ||
53 | const struct mxc_usbh_platform_data *pdata) | ||
54 | { | ||
55 | struct resource res[] = { | ||
56 | { | ||
57 | .start = data->iobase, | ||
58 | .end = data->iobase + SZ_512 - 1, | ||
59 | .flags = IORESOURCE_MEM, | ||
60 | }, { | ||
61 | .start = data->irq, | ||
62 | .end = data->irq, | ||
63 | .flags = IORESOURCE_IRQ, | ||
64 | }, | ||
65 | }; | ||
66 | return imx_add_platform_device_dmamask("mxc-ehci", data->id, | ||
67 | res, ARRAY_SIZE(res), | ||
68 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
69 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 000000000000..90d762f6f93b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c | |||
@@ -0,0 +1,72 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ | ||
13 | { \ | ||
14 | .id = _id, \ | ||
15 | .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ | ||
16 | .iosize = _size, \ | ||
17 | .irq = soc ## _INT_SDHC ## _hwid, \ | ||
18 | .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ | ||
19 | } | ||
20 | #define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ | ||
21 | [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) | ||
22 | |||
23 | #ifdef CONFIG_SOC_IMX21 | ||
24 | const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { | ||
25 | #define imx21_mxc_mmc_data_entry(_id, _hwid) \ | ||
26 | imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) | ||
27 | imx21_mxc_mmc_data_entry(0, 1), | ||
28 | imx21_mxc_mmc_data_entry(1, 2), | ||
29 | }; | ||
30 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
31 | |||
32 | #ifdef CONFIG_SOC_IMX27 | ||
33 | const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { | ||
34 | #define imx27_mxc_mmc_data_entry(_id, _hwid) \ | ||
35 | imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) | ||
36 | imx27_mxc_mmc_data_entry(0, 1), | ||
37 | imx27_mxc_mmc_data_entry(1, 2), | ||
38 | }; | ||
39 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
40 | |||
41 | #ifdef CONFIG_SOC_IMX31 | ||
42 | const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { | ||
43 | #define imx31_mxc_mmc_data_entry(_id, _hwid) \ | ||
44 | imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) | ||
45 | imx31_mxc_mmc_data_entry(0, 1), | ||
46 | imx31_mxc_mmc_data_entry(1, 2), | ||
47 | }; | ||
48 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
49 | |||
50 | struct platform_device *__init imx_add_mxc_mmc( | ||
51 | const struct imx_mxc_mmc_data *data, | ||
52 | const struct imxmmc_platform_data *pdata) | ||
53 | { | ||
54 | struct resource res[] = { | ||
55 | { | ||
56 | .start = data->iobase, | ||
57 | .end = data->iobase + SZ_4K - 1, | ||
58 | .flags = IORESOURCE_MEM, | ||
59 | }, { | ||
60 | .start = data->irq, | ||
61 | .end = data->irq, | ||
62 | .flags = IORESOURCE_IRQ, | ||
63 | }, { | ||
64 | .start = data->dmareq, | ||
65 | .end = data->dmareq, | ||
66 | .flags = IORESOURCE_DMA, | ||
67 | }, | ||
68 | }; | ||
69 | return imx_add_platform_device_dmamask("mxc-mmc", data->id, | ||
70 | res, ARRAY_SIZE(res), | ||
71 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
72 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32e3d67..f5beac0cdde7 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c | |||
@@ -31,22 +31,22 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = | |||
31 | imx_mxc_nand_data_entry_single(MX21, SZ_4K); | 31 | imx_mxc_nand_data_entry_single(MX21, SZ_4K); |
32 | #endif /* ifdef CONFIG_SOC_IMX21 */ | 32 | #endif /* ifdef CONFIG_SOC_IMX21 */ |
33 | 33 | ||
34 | #ifdef CONFIG_ARCH_MX25 | 34 | #ifdef CONFIG_SOC_IMX25 |
35 | const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = | 35 | const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = |
36 | imx_mxc_nand_data_entry_single(MX25, SZ_8K); | 36 | imx_mxc_nand_data_entry_single(MX25, SZ_8K); |
37 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 37 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
38 | 38 | ||
39 | #ifdef CONFIG_SOC_IMX27 | 39 | #ifdef CONFIG_SOC_IMX27 |
40 | const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = | 40 | const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = |
41 | imx_mxc_nand_data_entry_single(MX27, SZ_4K); | 41 | imx_mxc_nand_data_entry_single(MX27, SZ_4K); |
42 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 42 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
43 | 43 | ||
44 | #ifdef CONFIG_ARCH_MX31 | 44 | #ifdef CONFIG_SOC_IMX31 |
45 | const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = | 45 | const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = |
46 | imx_mxc_nand_data_entry_single(MX31, SZ_4K); | 46 | imx_mxc_nand_data_entry_single(MX31, SZ_4K); |
47 | #endif | 47 | #endif |
48 | 48 | ||
49 | #ifdef CONFIG_ARCH_MX35 | 49 | #ifdef CONFIG_SOC_IMX35 |
50 | const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = | 50 | const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = |
51 | imx_mxc_nand_data_entry_single(MX35, SZ_8K); | 51 | imx_mxc_nand_data_entry_single(MX35, SZ_8K); |
52 | #endif | 52 | #endif |
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100644 index 000000000000..3d8ebdba38ee --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c | |||
@@ -0,0 +1,60 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009-2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ | ||
13 | { \ | ||
14 | .id = _id, \ | ||
15 | .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ | ||
16 | .iosize = _size, \ | ||
17 | .irq = soc ## _INT_PWM ## _hwid, \ | ||
18 | } | ||
19 | #define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ | ||
20 | [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) | ||
21 | |||
22 | #ifdef CONFIG_SOC_IMX21 | ||
23 | const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = | ||
24 | imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); | ||
25 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
26 | |||
27 | #ifdef CONFIG_SOC_IMX25 | ||
28 | const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { | ||
29 | #define imx25_mxc_pwm_data_entry(_id, _hwid) \ | ||
30 | imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) | ||
31 | imx25_mxc_pwm_data_entry(0, 1), | ||
32 | imx25_mxc_pwm_data_entry(1, 2), | ||
33 | imx25_mxc_pwm_data_entry(2, 3), | ||
34 | imx25_mxc_pwm_data_entry(3, 4), | ||
35 | }; | ||
36 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
37 | |||
38 | #ifdef CONFIG_SOC_IMX27 | ||
39 | const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = | ||
40 | imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); | ||
41 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
42 | |||
43 | struct platform_device *__init imx_add_mxc_pwm( | ||
44 | const struct imx_mxc_pwm_data *data) | ||
45 | { | ||
46 | struct resource res[] = { | ||
47 | { | ||
48 | .start = data->iobase, | ||
49 | .end = data->iobase + data->iosize - 1, | ||
50 | .flags = IORESOURCE_MEM, | ||
51 | }, { | ||
52 | .start = data->irq, | ||
53 | .end = data->irq, | ||
54 | .flags = IORESOURCE_IRQ, | ||
55 | }, | ||
56 | }; | ||
57 | |||
58 | return imx_add_platform_device("mxc_pwm", data->id, | ||
59 | res, ARRAY_SIZE(res), NULL, 0); | ||
60 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 000000000000..b4b7612b6e17 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c | |||
@@ -0,0 +1,56 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | struct imx_mxc_rnga_data { | ||
13 | resource_size_t iobase; | ||
14 | }; | ||
15 | |||
16 | #define imx_mxc_rnga_data_entry_single(soc) \ | ||
17 | { \ | ||
18 | .iobase = soc ## _RNGA_BASE_ADDR, \ | ||
19 | } | ||
20 | |||
21 | #ifdef CONFIG_SOC_IMX31 | ||
22 | static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = | ||
23 | imx_mxc_rnga_data_entry_single(MX31); | ||
24 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
25 | |||
26 | static struct platform_device *__init imx_add_mxc_rnga( | ||
27 | const struct imx_mxc_rnga_data *data) | ||
28 | { | ||
29 | struct resource res[] = { | ||
30 | { | ||
31 | .start = data->iobase, | ||
32 | .end = data->iobase + SZ_16K - 1, | ||
33 | .flags = IORESOURCE_MEM, | ||
34 | }, | ||
35 | }; | ||
36 | return imx_add_platform_device("mxc_rnga", -1, | ||
37 | res, ARRAY_SIZE(res), NULL, 0); | ||
38 | } | ||
39 | |||
40 | static int __init imxXX_add_mxc_rnga(void) | ||
41 | { | ||
42 | struct platform_device *ret; | ||
43 | |||
44 | #if defined(CONFIG_SOC_IMX31) | ||
45 | if (cpu_is_mx31()) | ||
46 | ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); | ||
47 | else | ||
48 | #endif /* if defined(CONFIG_SOC_IMX31) */ | ||
49 | ret = ERR_PTR(-ENODEV); | ||
50 | |||
51 | if (IS_ERR(ret)) | ||
52 | return PTR_ERR(ret); | ||
53 | |||
54 | return 0; | ||
55 | } | ||
56 | arch_initcall(imxXX_add_mxc_rnga); | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 000000000000..96fa5ea91fe8 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it under | ||
6 | * the terms of the GNU General Public License version 2 as published by the | ||
7 | * Free Software Foundation. | ||
8 | */ | ||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | |||
12 | #define imx_mxc_w1_data_entry_single(soc) \ | ||
13 | { \ | ||
14 | .iobase = soc ## _OWIRE_BASE_ADDR, \ | ||
15 | } | ||
16 | |||
17 | #ifdef CONFIG_SOC_IMX21 | ||
18 | const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = | ||
19 | imx_mxc_w1_data_entry_single(MX21); | ||
20 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
21 | |||
22 | #ifdef CONFIG_SOC_IMX27 | ||
23 | const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = | ||
24 | imx_mxc_w1_data_entry_single(MX27); | ||
25 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
26 | |||
27 | #ifdef CONFIG_SOC_IMX31 | ||
28 | const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = | ||
29 | imx_mxc_w1_data_entry_single(MX31); | ||
30 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
31 | |||
32 | #ifdef CONFIG_SOC_IMX35 | ||
33 | const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = | ||
34 | imx_mxc_w1_data_entry_single(MX35); | ||
35 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
36 | |||
37 | struct platform_device *__init imx_add_mxc_w1( | ||
38 | const struct imx_mxc_w1_data *data) | ||
39 | { | ||
40 | struct resource res[] = { | ||
41 | { | ||
42 | .start = data->iobase, | ||
43 | .end = data->iobase + SZ_4K - 1, | ||
44 | .flags = IORESOURCE_MEM, | ||
45 | }, | ||
46 | }; | ||
47 | |||
48 | return imx_add_platform_device("mxc_w1", 0, | ||
49 | res, ARRAY_SIZE(res), NULL, 0); | ||
50 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100644 index 000000000000..167cce89e7c7 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it under | ||
5 | * the terms of the GNU General Public License version 2 as published by the | ||
6 | * Free Software Foundation. | ||
7 | */ | ||
8 | |||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/devices-common.h> | ||
11 | #include <mach/esdhc.h> | ||
12 | |||
13 | #define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ | ||
14 | { \ | ||
15 | .id = _id, \ | ||
16 | .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ | ||
17 | .irq = soc ## _INT_ESDHC ## hwid, \ | ||
18 | } | ||
19 | |||
20 | #define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ | ||
21 | [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) | ||
22 | |||
23 | #ifdef CONFIG_SOC_IMX25 | ||
24 | const struct imx_sdhci_esdhc_imx_data | ||
25 | imx25_sdhci_esdhc_imx_data[] __initconst = { | ||
26 | #define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
27 | imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) | ||
28 | imx25_sdhci_esdhc_imx_data_entry(0, 1), | ||
29 | imx25_sdhci_esdhc_imx_data_entry(1, 2), | ||
30 | }; | ||
31 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
32 | |||
33 | #ifdef CONFIG_SOC_IMX35 | ||
34 | const struct imx_sdhci_esdhc_imx_data | ||
35 | imx35_sdhci_esdhc_imx_data[] __initconst = { | ||
36 | #define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
37 | imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) | ||
38 | imx35_sdhci_esdhc_imx_data_entry(0, 1), | ||
39 | imx35_sdhci_esdhc_imx_data_entry(1, 2), | ||
40 | imx35_sdhci_esdhc_imx_data_entry(2, 3), | ||
41 | }; | ||
42 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
43 | |||
44 | #ifdef CONFIG_ARCH_MX51 | ||
45 | const struct imx_sdhci_esdhc_imx_data | ||
46 | imx51_sdhci_esdhc_imx_data[] __initconst = { | ||
47 | #define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
48 | imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) | ||
49 | imx51_sdhci_esdhc_imx_data_entry(0, 1), | ||
50 | imx51_sdhci_esdhc_imx_data_entry(1, 2), | ||
51 | imx51_sdhci_esdhc_imx_data_entry(2, 3), | ||
52 | imx51_sdhci_esdhc_imx_data_entry(3, 4), | ||
53 | }; | ||
54 | #endif /* ifdef CONFIG_ARCH_MX51 */ | ||
55 | |||
56 | struct platform_device *__init imx_add_sdhci_esdhc_imx( | ||
57 | const struct imx_sdhci_esdhc_imx_data *data, | ||
58 | const struct esdhc_platform_data *pdata) | ||
59 | { | ||
60 | struct resource res[] = { | ||
61 | { | ||
62 | .start = data->iobase, | ||
63 | .end = data->iobase + SZ_16K - 1, | ||
64 | .flags = IORESOURCE_MEM, | ||
65 | }, { | ||
66 | .start = data->irq, | ||
67 | .end = data->irq, | ||
68 | .flags = IORESOURCE_IRQ, | ||
69 | }, | ||
70 | }; | ||
71 | |||
72 | return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, | ||
73 | ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
74 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index e48340ec331e..8f2b60a6396e 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c | |||
@@ -29,7 +29,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { | |||
29 | imx21_cspi_data_entry(1, 2), | 29 | imx21_cspi_data_entry(1, 2), |
30 | #endif | 30 | #endif |
31 | 31 | ||
32 | #ifdef CONFIG_ARCH_MX25 | 32 | #ifdef CONFIG_SOC_IMX25 |
33 | const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { | 33 | const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { |
34 | #define imx25_cspi_data_entry(_id, _hwid) \ | 34 | #define imx25_cspi_data_entry(_id, _hwid) \ |
35 | imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) | 35 | imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) |
@@ -37,7 +37,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { | |||
37 | imx25_cspi_data_entry(1, 2), | 37 | imx25_cspi_data_entry(1, 2), |
38 | imx25_cspi_data_entry(2, 3), | 38 | imx25_cspi_data_entry(2, 3), |
39 | }; | 39 | }; |
40 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 40 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
41 | 41 | ||
42 | #ifdef CONFIG_SOC_IMX27 | 42 | #ifdef CONFIG_SOC_IMX27 |
43 | const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { | 43 | const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { |
@@ -49,7 +49,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { | |||
49 | }; | 49 | }; |
50 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 50 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
51 | 51 | ||
52 | #ifdef CONFIG_ARCH_MX31 | 52 | #ifdef CONFIG_SOC_IMX31 |
53 | const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { | 53 | const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { |
54 | #define imx31_cspi_data_entry(_id, _hwid) \ | 54 | #define imx31_cspi_data_entry(_id, _hwid) \ |
55 | imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) | 55 | imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) |
@@ -57,16 +57,16 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { | |||
57 | imx31_cspi_data_entry(1, 2), | 57 | imx31_cspi_data_entry(1, 2), |
58 | imx31_cspi_data_entry(2, 3), | 58 | imx31_cspi_data_entry(2, 3), |
59 | }; | 59 | }; |
60 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 60 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
61 | 61 | ||
62 | #ifdef CONFIG_ARCH_MX35 | 62 | #ifdef CONFIG_SOC_IMX35 |
63 | const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { | 63 | const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { |
64 | #define imx35_cspi_data_entry(_id, _hwid) \ | 64 | #define imx35_cspi_data_entry(_id, _hwid) \ |
65 | imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) | 65 | imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) |
66 | imx35_cspi_data_entry(0, 1), | 66 | imx35_cspi_data_entry(0, 1), |
67 | imx35_cspi_data_entry(1, 2), | 67 | imx35_cspi_data_entry(1, 2), |
68 | }; | 68 | }; |
69 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 69 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
70 | 70 | ||
71 | #ifdef CONFIG_ARCH_MX51 | 71 | #ifdef CONFIG_ARCH_MX51 |
72 | const struct imx_spi_imx_data imx51_cspi_data __initconst = | 72 | const struct imx_spi_imx_data imx51_cspi_data __initconst = |
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607683de..4bac3d5545d3 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c | |||
@@ -69,9 +69,9 @@ | |||
69 | int mxc_initialize_usb_hw(int port, unsigned int flags) | 69 | int mxc_initialize_usb_hw(int port, unsigned int flags) |
70 | { | 70 | { |
71 | unsigned int v; | 71 | unsigned int v; |
72 | #if defined(CONFIG_ARCH_MX25) | 72 | #if defined(CONFIG_SOC_IMX25) |
73 | if (cpu_is_mx25()) { | 73 | if (cpu_is_mx25()) { |
74 | v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + | 74 | v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + |
75 | USBCTRL_OTGBASE_OFFSET)); | 75 | USBCTRL_OTGBASE_OFFSET)); |
76 | 76 | ||
77 | switch (port) { | 77 | switch (port) { |
@@ -108,11 +108,11 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
108 | return -EINVAL; | 108 | return -EINVAL; |
109 | } | 109 | } |
110 | 110 | ||
111 | writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + | 111 | writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + |
112 | USBCTRL_OTGBASE_OFFSET)); | 112 | USBCTRL_OTGBASE_OFFSET)); |
113 | return 0; | 113 | return 0; |
114 | } | 114 | } |
115 | #endif /* CONFIG_ARCH_MX25 */ | 115 | #endif /* if defined(CONFIG_SOC_IMX25) */ |
116 | #if defined(CONFIG_ARCH_MX3) | 116 | #if defined(CONFIG_ARCH_MX3) |
117 | if (cpu_is_mx31()) { | 117 | if (cpu_is_mx31()) { |
118 | v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + | 118 | v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9c3e36232b5b..93a8d93dcc2e 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) | |||
175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) | 175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
176 | { | 176 | { |
177 | u32 irq_stat; | 177 | u32 irq_stat; |
178 | struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); | 178 | struct mxc_gpio_port *port = get_irq_data(irq); |
179 | 179 | ||
180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & | 180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & |
181 | __raw_readl(port->base + GPIO_IMR); | 181 | __raw_readl(port->base + GPIO_IMR); |
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |||
188 | { | 188 | { |
189 | int i; | 189 | int i; |
190 | u32 irq_msk, irq_stat; | 190 | u32 irq_msk, irq_stat; |
191 | struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); | 191 | struct mxc_gpio_port *port = get_irq_data(irq); |
192 | 192 | ||
193 | /* walk through all interrupt status registers */ | 193 | /* walk through all interrupt status registers */ |
194 | for (i = 0; i < gpio_table_size; i++) { | 194 | for (i = 0; i < gpio_table_size; i++) { |
@@ -349,3 +349,96 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
349 | 349 | ||
350 | return 0; | 350 | return 0; |
351 | } | 351 | } |
352 | |||
353 | #define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ | ||
354 | { \ | ||
355 | .chip.label = "gpio-" #_id, \ | ||
356 | .irq = _irq, \ | ||
357 | .base = soc ## _IO_ADDRESS( \ | ||
358 | soc ## _GPIO ## _hwid ## _BASE_ADDR), \ | ||
359 | .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ | ||
360 | } | ||
361 | |||
362 | #define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ | ||
363 | DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) | ||
364 | |||
365 | #define DEFINE_REGISTER_FUNCTION(prefix) \ | ||
366 | int __init prefix ## _register_gpios(void) \ | ||
367 | { \ | ||
368 | return mxc_gpio_init(prefix ## _gpio_ports, \ | ||
369 | ARRAY_SIZE(prefix ## _gpio_ports)); \ | ||
370 | } | ||
371 | |||
372 | #if defined(CONFIG_SOC_IMX1) | ||
373 | static struct mxc_gpio_port imx1_gpio_ports[] = { | ||
374 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), | ||
375 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), | ||
376 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), | ||
377 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), | ||
378 | }; | ||
379 | |||
380 | DEFINE_REGISTER_FUNCTION(imx1) | ||
381 | |||
382 | #endif /* if defined(CONFIG_SOC_IMX1) */ | ||
383 | |||
384 | #if defined(CONFIG_SOC_IMX21) | ||
385 | static struct mxc_gpio_port imx21_gpio_ports[] = { | ||
386 | DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), | ||
387 | DEFINE_IMX_GPIO_PORT(MX21, 1, 2), | ||
388 | DEFINE_IMX_GPIO_PORT(MX21, 2, 3), | ||
389 | DEFINE_IMX_GPIO_PORT(MX21, 3, 4), | ||
390 | DEFINE_IMX_GPIO_PORT(MX21, 4, 5), | ||
391 | DEFINE_IMX_GPIO_PORT(MX21, 5, 6), | ||
392 | }; | ||
393 | |||
394 | DEFINE_REGISTER_FUNCTION(imx21) | ||
395 | |||
396 | #endif /* if defined(CONFIG_SOC_IMX21) */ | ||
397 | |||
398 | #if defined(CONFIG_SOC_IMX25) | ||
399 | static struct mxc_gpio_port imx25_gpio_ports[] = { | ||
400 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), | ||
401 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), | ||
402 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), | ||
403 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), | ||
404 | }; | ||
405 | |||
406 | DEFINE_REGISTER_FUNCTION(imx25) | ||
407 | |||
408 | #endif /* if defined(CONFIG_SOC_IMX25) */ | ||
409 | |||
410 | #if defined(CONFIG_SOC_IMX27) | ||
411 | static struct mxc_gpio_port imx27_gpio_ports[] = { | ||
412 | DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), | ||
413 | DEFINE_IMX_GPIO_PORT(MX27, 1, 2), | ||
414 | DEFINE_IMX_GPIO_PORT(MX27, 2, 3), | ||
415 | DEFINE_IMX_GPIO_PORT(MX27, 3, 4), | ||
416 | DEFINE_IMX_GPIO_PORT(MX27, 4, 5), | ||
417 | DEFINE_IMX_GPIO_PORT(MX27, 5, 6), | ||
418 | }; | ||
419 | |||
420 | DEFINE_REGISTER_FUNCTION(imx27) | ||
421 | |||
422 | #endif /* if defined(CONFIG_SOC_IMX27) */ | ||
423 | |||
424 | #if defined(CONFIG_SOC_IMX31) | ||
425 | static struct mxc_gpio_port imx31_gpio_ports[] = { | ||
426 | DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), | ||
427 | DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), | ||
428 | DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), | ||
429 | }; | ||
430 | |||
431 | DEFINE_REGISTER_FUNCTION(imx31) | ||
432 | |||
433 | #endif /* if defined(CONFIG_SOC_IMX31) */ | ||
434 | |||
435 | #if defined(CONFIG_SOC_IMX35) | ||
436 | static struct mxc_gpio_port imx35_gpio_ports[] = { | ||
437 | DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), | ||
438 | DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), | ||
439 | DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), | ||
440 | }; | ||
441 | |||
442 | DEFINE_REGISTER_FUNCTION(imx35) | ||
443 | |||
444 | #endif /* if defined(CONFIG_SOC_IMX35) */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index d56213fb901b..3b3a37c25c56 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S | |||
@@ -10,58 +10,49 @@ | |||
10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | #define IMX_NEEDS_DEPRECATED_SYMBOLS | 13 | #include <mach/hardware.h> |
14 | 14 | ||
15 | #ifdef CONFIG_ARCH_MX1 | 15 | #ifdef CONFIG_ARCH_MX1 |
16 | #include <mach/mx1.h> | 16 | #define UART_PADDR MX1_UART1_BASE_ADDR |
17 | #define UART_PADDR UART1_BASE_ADDR | ||
18 | #define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) | ||
19 | #endif | 17 | #endif |
20 | 18 | ||
21 | #ifdef CONFIG_ARCH_MX25 | 19 | #ifdef CONFIG_ARCH_MX25 |
22 | #ifdef UART_PADDR | 20 | #ifdef UART_PADDR |
23 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 21 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
24 | #endif | 22 | #endif |
25 | #include <mach/mx25.h> | ||
26 | #define UART_PADDR MX25_UART1_BASE_ADDR | 23 | #define UART_PADDR MX25_UART1_BASE_ADDR |
27 | #define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) | ||
28 | #endif | 24 | #endif |
29 | 25 | ||
30 | #ifdef CONFIG_ARCH_MX2 | 26 | #ifdef CONFIG_ARCH_MX2 |
31 | #ifdef UART_PADDR | 27 | #ifdef UART_PADDR |
32 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 28 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
33 | #endif | 29 | #endif |
34 | #include <mach/mx2x.h> | 30 | #define UART_PADDR MX2x_UART1_BASE_ADDR |
35 | #define UART_PADDR UART1_BASE_ADDR | ||
36 | #define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) | ||
37 | #endif | 31 | #endif |
38 | 32 | ||
39 | #ifdef CONFIG_ARCH_MX3 | 33 | #ifdef CONFIG_ARCH_MX3 |
40 | #ifdef UART_PADDR | 34 | #ifdef UART_PADDR |
41 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 35 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
42 | #endif | 36 | #endif |
43 | #include <mach/mx3x.h> | 37 | #define UART_PADDR MX3x_UART1_BASE_ADDR |
44 | #define UART_PADDR UART1_BASE_ADDR | ||
45 | #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
46 | #endif | 38 | #endif |
47 | 39 | ||
48 | #ifdef CONFIG_ARCH_MX5 | 40 | #ifdef CONFIG_ARCH_MX5 |
49 | #ifdef UART_PADDR | 41 | #ifdef UART_PADDR |
50 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 42 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
51 | #endif | 43 | #endif |
52 | #include <mach/mx51.h> | ||
53 | #define UART_PADDR MX51_UART1_BASE_ADDR | 44 | #define UART_PADDR MX51_UART1_BASE_ADDR |
54 | #define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) | ||
55 | #endif | 45 | #endif |
56 | 46 | ||
57 | #ifdef CONFIG_ARCH_MXC91231 | 47 | #ifdef CONFIG_ARCH_MXC91231 |
58 | #ifdef UART_PADDR | 48 | #ifdef UART_PADDR |
59 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 49 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
60 | #endif | 50 | #endif |
61 | #include <mach/mxc91231.h> | ||
62 | #define UART_PADDR MXC91231_UART2_BASE_ADDR | 51 | #define UART_PADDR MXC91231_UART2_BASE_ADDR |
63 | #define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) | ||
64 | #endif | 52 | #endif |
53 | |||
54 | #define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) | ||
55 | |||
65 | .macro addruart, rp, rv | 56 | .macro addruart, rp, rv |
66 | ldr \rp, =UART_PADDR @ physical | 57 | ldr \rp, =UART_PADDR @ physical |
67 | ldr \rv, =UART_VADDR @ virtual | 58 | ldr \rv, =UART_VADDR @ virtual |
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8c6896fd1e5f..3640eaf88c02 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h | |||
@@ -10,9 +10,19 @@ | |||
10 | #include <linux/platform_device.h> | 10 | #include <linux/platform_device.h> |
11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
12 | 12 | ||
13 | struct platform_device *imx_add_platform_device(const char *name, int id, | 13 | struct platform_device *imx_add_platform_device_dmamask( |
14 | const char *name, int id, | ||
14 | const struct resource *res, unsigned int num_resources, | 15 | const struct resource *res, unsigned int num_resources, |
15 | const void *data, size_t size_data); | 16 | const void *data, size_t size_data, u64 dmamask); |
17 | |||
18 | static inline struct platform_device *imx_add_platform_device( | ||
19 | const char *name, int id, | ||
20 | const struct resource *res, unsigned int num_resources, | ||
21 | const void *data, size_t size_data) | ||
22 | { | ||
23 | return imx_add_platform_device_dmamask( | ||
24 | name, id, res, num_resources, data, size_data, 0); | ||
25 | } | ||
16 | 26 | ||
17 | #include <linux/fec.h> | 27 | #include <linux/fec.h> |
18 | struct imx_fec_data { | 28 | struct imx_fec_data { |
@@ -24,15 +34,62 @@ struct platform_device *__init imx_add_fec( | |||
24 | const struct fec_platform_data *pdata); | 34 | const struct fec_platform_data *pdata); |
25 | 35 | ||
26 | #include <linux/can/platform/flexcan.h> | 36 | #include <linux/can/platform/flexcan.h> |
27 | struct platform_device *__init imx_add_flexcan(int id, | 37 | struct imx_flexcan_data { |
28 | resource_size_t iobase, resource_size_t iosize, | 38 | int id; |
29 | resource_size_t irq, | 39 | resource_size_t iobase; |
40 | resource_size_t iosize; | ||
41 | resource_size_t irq; | ||
42 | }; | ||
43 | struct platform_device *__init imx_add_flexcan( | ||
44 | const struct imx_flexcan_data *data, | ||
30 | const struct flexcan_platform_data *pdata); | 45 | const struct flexcan_platform_data *pdata); |
31 | 46 | ||
47 | #include <linux/fsl_devices.h> | ||
48 | struct imx_fsl_usb2_udc_data { | ||
49 | resource_size_t iobase; | ||
50 | resource_size_t irq; | ||
51 | }; | ||
52 | struct platform_device *__init imx_add_fsl_usb2_udc( | ||
53 | const struct imx_fsl_usb2_udc_data *data, | ||
54 | const struct fsl_usb2_platform_data *pdata); | ||
55 | |||
32 | #include <linux/gpio_keys.h> | 56 | #include <linux/gpio_keys.h> |
33 | struct platform_device *__init imx_add_gpio_keys( | 57 | struct platform_device *__init imx_add_gpio_keys( |
34 | const struct gpio_keys_platform_data *pdata); | 58 | const struct gpio_keys_platform_data *pdata); |
35 | 59 | ||
60 | #include <mach/mx21-usbhost.h> | ||
61 | struct imx_imx21_hcd_data { | ||
62 | resource_size_t iobase; | ||
63 | resource_size_t irq; | ||
64 | }; | ||
65 | struct platform_device *__init imx_add_imx21_hcd( | ||
66 | const struct imx_imx21_hcd_data *data, | ||
67 | const struct mx21_usbh_platform_data *pdata); | ||
68 | |||
69 | struct imx_imx2_wdt_data { | ||
70 | resource_size_t iobase; | ||
71 | resource_size_t iosize; | ||
72 | }; | ||
73 | struct platform_device *__init imx_add_imx2_wdt( | ||
74 | const struct imx_imx2_wdt_data *data); | ||
75 | |||
76 | struct imx_imxdi_rtc_data { | ||
77 | resource_size_t iobase; | ||
78 | resource_size_t irq; | ||
79 | }; | ||
80 | struct platform_device *__init imx_add_imxdi_rtc( | ||
81 | const struct imx_imxdi_rtc_data *data); | ||
82 | |||
83 | #include <mach/imxfb.h> | ||
84 | struct imx_imx_fb_data { | ||
85 | resource_size_t iobase; | ||
86 | resource_size_t iosize; | ||
87 | resource_size_t irq; | ||
88 | }; | ||
89 | struct platform_device *__init imx_add_imx_fb( | ||
90 | const struct imx_imx_fb_data *data, | ||
91 | const struct imx_fb_platform_data *pdata); | ||
92 | |||
36 | #include <mach/i2c.h> | 93 | #include <mach/i2c.h> |
37 | struct imx_imx_i2c_data { | 94 | struct imx_imx_i2c_data { |
38 | int id; | 95 | int id; |
@@ -44,6 +101,16 @@ struct platform_device *__init imx_add_imx_i2c( | |||
44 | const struct imx_imx_i2c_data *data, | 101 | const struct imx_imx_i2c_data *data, |
45 | const struct imxi2c_platform_data *pdata); | 102 | const struct imxi2c_platform_data *pdata); |
46 | 103 | ||
104 | #include <linux/input/matrix_keypad.h> | ||
105 | struct imx_imx_keypad_data { | ||
106 | resource_size_t iobase; | ||
107 | resource_size_t iosize; | ||
108 | resource_size_t irq; | ||
109 | }; | ||
110 | struct platform_device *__init imx_add_imx_keypad( | ||
111 | const struct imx_imx_keypad_data *data, | ||
112 | const struct matrix_keymap_data *pdata); | ||
113 | |||
47 | #include <mach/ssi.h> | 114 | #include <mach/ssi.h> |
48 | struct imx_imx_ssi_data { | 115 | struct imx_imx_ssi_data { |
49 | int id; | 116 | int id; |
@@ -82,6 +149,67 @@ struct platform_device *__init imx_add_imx_uart_1irq( | |||
82 | const struct imx_imx_uart_1irq_data *data, | 149 | const struct imx_imx_uart_1irq_data *data, |
83 | const struct imxuart_platform_data *pdata); | 150 | const struct imxuart_platform_data *pdata); |
84 | 151 | ||
152 | #include <mach/usb.h> | ||
153 | struct imx_imx_udc_data { | ||
154 | resource_size_t iobase; | ||
155 | resource_size_t iosize; | ||
156 | resource_size_t irq0; | ||
157 | resource_size_t irq1; | ||
158 | resource_size_t irq2; | ||
159 | resource_size_t irq3; | ||
160 | resource_size_t irq4; | ||
161 | resource_size_t irq5; | ||
162 | resource_size_t irq6; | ||
163 | }; | ||
164 | struct platform_device *__init imx_add_imx_udc( | ||
165 | const struct imx_imx_udc_data *data, | ||
166 | const struct imxusb_platform_data *pdata); | ||
167 | |||
168 | #include <mach/mx1_camera.h> | ||
169 | struct imx_mx1_camera_data { | ||
170 | resource_size_t iobase; | ||
171 | resource_size_t iosize; | ||
172 | resource_size_t irq; | ||
173 | }; | ||
174 | struct platform_device *__init imx_add_mx1_camera( | ||
175 | const struct imx_mx1_camera_data *data, | ||
176 | const struct mx1_camera_pdata *pdata); | ||
177 | |||
178 | #include <mach/mx2_cam.h> | ||
179 | struct imx_mx2_camera_data { | ||
180 | resource_size_t iobasecsi; | ||
181 | resource_size_t iosizecsi; | ||
182 | resource_size_t irqcsi; | ||
183 | resource_size_t iobaseemmaprp; | ||
184 | resource_size_t iosizeemmaprp; | ||
185 | resource_size_t irqemmaprp; | ||
186 | }; | ||
187 | struct platform_device *__init imx_add_mx2_camera( | ||
188 | const struct imx_mx2_camera_data *data, | ||
189 | const struct mx2_camera_platform_data *pdata); | ||
190 | |||
191 | #include <mach/mxc_ehci.h> | ||
192 | struct imx_mxc_ehci_data { | ||
193 | int id; | ||
194 | resource_size_t iobase; | ||
195 | resource_size_t irq; | ||
196 | }; | ||
197 | struct platform_device *__init imx_add_mxc_ehci( | ||
198 | const struct imx_mxc_ehci_data *data, | ||
199 | const struct mxc_usbh_platform_data *pdata); | ||
200 | |||
201 | #include <mach/mmc.h> | ||
202 | struct imx_mxc_mmc_data { | ||
203 | int id; | ||
204 | resource_size_t iobase; | ||
205 | resource_size_t iosize; | ||
206 | resource_size_t irq; | ||
207 | resource_size_t dmareq; | ||
208 | }; | ||
209 | struct platform_device *__init imx_add_mxc_mmc( | ||
210 | const struct imx_mxc_mmc_data *data, | ||
211 | const struct imxmmc_platform_data *pdata); | ||
212 | |||
85 | #include <mach/mxc_nand.h> | 213 | #include <mach/mxc_nand.h> |
86 | struct imx_mxc_nand_data { | 214 | struct imx_mxc_nand_data { |
87 | /* | 215 | /* |
@@ -99,24 +227,39 @@ struct platform_device *__init imx_add_mxc_nand( | |||
99 | const struct imx_mxc_nand_data *data, | 227 | const struct imx_mxc_nand_data *data, |
100 | const struct mxc_nand_platform_data *pdata); | 228 | const struct mxc_nand_platform_data *pdata); |
101 | 229 | ||
102 | #include <mach/spi.h> | 230 | struct imx_mxc_pwm_data { |
103 | struct imx_spi_imx_data { | ||
104 | const char *devid; | ||
105 | int id; | 231 | int id; |
106 | resource_size_t iobase; | 232 | resource_size_t iobase; |
107 | resource_size_t iosize; | 233 | resource_size_t iosize; |
108 | int irq; | 234 | resource_size_t irq; |
109 | }; | 235 | }; |
110 | struct platform_device *__init imx_add_spi_imx( | 236 | struct platform_device *__init imx_add_mxc_pwm( |
111 | const struct imx_spi_imx_data *data, | 237 | const struct imx_mxc_pwm_data *data); |
112 | const struct spi_imx_master *pdata); | 238 | |
239 | struct imx_mxc_w1_data { | ||
240 | resource_size_t iobase; | ||
241 | }; | ||
242 | struct platform_device *__init imx_add_mxc_w1( | ||
243 | const struct imx_mxc_w1_data *data); | ||
113 | 244 | ||
114 | #include <mach/esdhc.h> | 245 | #include <mach/esdhc.h> |
115 | struct imx_esdhc_imx_data { | 246 | struct imx_sdhci_esdhc_imx_data { |
116 | int id; | 247 | int id; |
117 | resource_size_t iobase; | 248 | resource_size_t iobase; |
118 | resource_size_t irq; | 249 | resource_size_t irq; |
119 | }; | 250 | }; |
120 | struct platform_device *__init imx_add_esdhc( | 251 | struct platform_device *__init imx_add_sdhci_esdhc_imx( |
121 | const struct imx_esdhc_imx_data *data, | 252 | const struct imx_sdhci_esdhc_imx_data *data, |
122 | const struct esdhc_platform_data *pdata); | 253 | const struct esdhc_platform_data *pdata); |
254 | |||
255 | #include <mach/spi.h> | ||
256 | struct imx_spi_imx_data { | ||
257 | const char *devid; | ||
258 | int id; | ||
259 | resource_size_t iobase; | ||
260 | resource_size_t iosize; | ||
261 | int irq; | ||
262 | }; | ||
263 | struct platform_device *__init imx_add_spi_imx( | ||
264 | const struct imx_spi_imx_data *data, | ||
265 | const struct spi_imx_master *pdata); | ||
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4ac43fc..dde777c10176 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h | |||
@@ -22,10 +22,82 @@ | |||
22 | 22 | ||
23 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
24 | 24 | ||
25 | #define IMX_IO_ADDRESS(addr, module) \ | 25 | #ifdef __ASSEMBLER__ |
26 | ((void __force __iomem *) \ | 26 | #define IOMEM(addr) (addr) |
27 | (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ | 27 | #else |
28 | (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) | 28 | #define IOMEM(addr) ((void __force __iomem *)(addr)) |
29 | #endif | ||
30 | |||
31 | #define IMX_IO_P2V_MODULE(addr, module) \ | ||
32 | (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ | ||
33 | (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) | ||
34 | |||
35 | /* | ||
36 | * This is rather complicated for humans and ugly to verify, but for a machine | ||
37 | * it's OK. Still more as it is usually only applied to constants. The upsides | ||
38 | * on using this approach are: | ||
39 | * | ||
40 | * - same mapping on all i.MX machines | ||
41 | * - works for assembler, too | ||
42 | * - no need to nurture #defines for virtual addresses | ||
43 | * | ||
44 | * The downside it, it's hard to verify (but I have a script for that). | ||
45 | * | ||
46 | * Obviously this needs to be injective for each SoC. In general it maps the | ||
47 | * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] | ||
48 | * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). | ||
49 | * | ||
50 | * It applies the following mappings for the different SoCs: | ||
51 | * | ||
52 | * mx1: | ||
53 | * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 | ||
54 | * mx21: | ||
55 | * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 | ||
56 | * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 | ||
57 | * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 | ||
58 | * mx25: | ||
59 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
60 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
61 | * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 | ||
62 | * mx27: | ||
63 | * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 | ||
64 | * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 | ||
65 | * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 | ||
66 | * mx31: | ||
67 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
68 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
69 | * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 | ||
70 | * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 | ||
71 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
72 | * mx35: | ||
73 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
74 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
75 | * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 | ||
76 | * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 | ||
77 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
78 | * mx51: | ||
79 | * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 | ||
80 | * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 | ||
81 | * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 | ||
82 | * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 | ||
83 | * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 | ||
84 | * mxc91231: | ||
85 | * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 | ||
86 | * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 | ||
87 | * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 | ||
88 | * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 | ||
89 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
90 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
91 | * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 | ||
92 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
93 | */ | ||
94 | #define IMX_IO_P2V(x) ( \ | ||
95 | 0xf4000000 + \ | ||
96 | (((x) & 0x50000000) >> 6) + \ | ||
97 | (((x) & 0x0b000000) >> 4) + \ | ||
98 | (((x) & 0x000fffff))) | ||
99 | |||
100 | #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) | ||
29 | 101 | ||
30 | #ifdef CONFIG_ARCH_MX5 | 102 | #ifdef CONFIG_ARCH_MX5 |
31 | #include <mach/mx51.h> | 103 | #include <mach/mx51.h> |
@@ -61,4 +133,11 @@ | |||
61 | 133 | ||
62 | #include <mach/mxc.h> | 134 | #include <mach/mxc.h> |
63 | 135 | ||
136 | #define imx_map_entry(soc, name, _type) { \ | ||
137 | .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ | ||
138 | .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ | ||
139 | .length = soc ## _ ## name ## _SIZE, \ | ||
140 | .type = _type, \ | ||
141 | } | ||
142 | |||
64 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ | 143 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 5263506b7ddf..9de8f062ad5d 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h | |||
@@ -1,6 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * This structure describes the machine which we are running on. | 2 | * This structure describes the machine which we are running on. |
3 | */ | 3 | */ |
4 | #ifndef __MACH_IMXFB_H__ | ||
5 | #define __MACH_IMXFB_H__ | ||
4 | 6 | ||
5 | #include <linux/fb.h> | 7 | #include <linux/fb.h> |
6 | 8 | ||
@@ -79,3 +81,4 @@ struct imx_fb_platform_data { | |||
79 | }; | 81 | }; |
80 | 82 | ||
81 | void set_imx_fb_info(struct imx_fb_platform_data *); | 83 | void set_imx_fb_info(struct imx_fb_platform_data *); |
84 | #endif /* ifndef __MACH_IMXFB_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 641b24618239..75d96214b831 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h | |||
@@ -19,7 +19,6 @@ | |||
19 | */ | 19 | */ |
20 | #define MX1_IO_BASE_ADDR 0x00200000 | 20 | #define MX1_IO_BASE_ADDR 0x00200000 |
21 | #define MX1_IO_SIZE SZ_1M | 21 | #define MX1_IO_SIZE SZ_1M |
22 | #define MX1_IO_BASE_ADDR_VIRT VMALLOC_END | ||
23 | 22 | ||
24 | #define MX1_CS0_PHYS 0x10000000 | 23 | #define MX1_CS0_PHYS 0x10000000 |
25 | #define MX1_CS0_SIZE 0x02000000 | 24 | #define MX1_CS0_SIZE 0x02000000 |
@@ -66,6 +65,10 @@ | |||
66 | #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) | 65 | #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) |
67 | #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) | 66 | #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) |
68 | #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) | 67 | #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) |
68 | #define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) | ||
69 | #define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) | ||
70 | #define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) | ||
71 | #define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) | ||
69 | #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) | 72 | #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) |
70 | #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) | 73 | #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) |
71 | #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) | 74 | #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) |
@@ -73,12 +76,12 @@ | |||
73 | #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) | 76 | #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) |
74 | 77 | ||
75 | /* macro to get at IO space when running virtually */ | 78 | /* macro to get at IO space when running virtually */ |
76 | #define MX1_IO_ADDRESS(x) ( \ | 79 | #define MX1_IO_P2V(x) IMX_IO_P2V(x) |
77 | IMX_IO_ADDRESS(x, MX1_IO)) | 80 | #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) |
78 | 81 | ||
79 | /* fixed interrput numbers */ | 82 | /* fixed interrput numbers */ |
80 | #define MX1_INT_SOFTINT 0 | 83 | #define MX1_INT_SOFTINT 0 |
81 | #define MX1_CSI_INT 6 | 84 | #define MX1_INT_CSI 6 |
82 | #define MX1_DSPA_MAC_INT 7 | 85 | #define MX1_DSPA_MAC_INT 7 |
83 | #define MX1_DSPA_INT 8 | 86 | #define MX1_DSPA_INT 8 |
84 | #define MX1_COMP_INT 9 | 87 | #define MX1_COMP_INT 9 |
@@ -115,13 +118,13 @@ | |||
115 | #define MX1_SSI_RX_INT 44 | 118 | #define MX1_SSI_RX_INT 44 |
116 | #define MX1_SSI_RX_ERR_INT 45 | 119 | #define MX1_SSI_RX_ERR_INT 45 |
117 | #define MX1_TOUCH_INT 46 | 120 | #define MX1_TOUCH_INT 46 |
118 | #define MX1_USBD_INT0 47 | 121 | #define MX1_INT_USBD0 47 |
119 | #define MX1_USBD_INT1 48 | 122 | #define MX1_INT_USBD1 48 |
120 | #define MX1_USBD_INT2 49 | 123 | #define MX1_INT_USBD2 49 |
121 | #define MX1_USBD_INT3 50 | 124 | #define MX1_INT_USBD3 50 |
122 | #define MX1_USBD_INT4 51 | 125 | #define MX1_INT_USBD4 51 |
123 | #define MX1_USBD_INT5 52 | 126 | #define MX1_INT_USBD5 52 |
124 | #define MX1_USBD_INT6 53 | 127 | #define MX1_INT_USBD6 53 |
125 | #define MX1_BTSYS_INT 55 | 128 | #define MX1_BTSYS_INT 55 |
126 | #define MX1_BTTIM_INT 56 | 129 | #define MX1_BTTIM_INT 56 |
127 | #define MX1_BTWUI_INT 57 | 130 | #define MX1_BTWUI_INT 57 |
@@ -164,134 +167,6 @@ | |||
164 | * to not break drivers/usb/gadget/imx_udc. Should go | 167 | * to not break drivers/usb/gadget/imx_udc. Should go |
165 | * away after this driver uses the new name. | 168 | * away after this driver uses the new name. |
166 | */ | 169 | */ |
167 | #define USBD_INT0 MX1_USBD_INT0 | 170 | #define USBD_INT0 MX1_INT_USBD0 |
168 | |||
169 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
170 | /* these should go away */ | ||
171 | #define IMX_IO_PHYS MX1_IO_BASE_ADDR | ||
172 | #define IMX_IO_SIZE MX1_IO_SIZE | ||
173 | #define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT | ||
174 | #define IMX_CS0_PHYS MX1_CS0_PHYS | ||
175 | #define IMX_CS0_SIZE MX1_CS0_SIZE | ||
176 | #define IMX_CS1_PHYS MX1_CS1_PHYS | ||
177 | #define IMX_CS1_SIZE MX1_CS1_SIZE | ||
178 | #define IMX_CS2_PHYS MX1_CS2_PHYS | ||
179 | #define IMX_CS2_SIZE MX1_CS2_SIZE | ||
180 | #define IMX_CS3_PHYS MX1_CS3_PHYS | ||
181 | #define IMX_CS3_SIZE MX1_CS3_SIZE | ||
182 | #define IMX_CS4_PHYS MX1_CS4_PHYS | ||
183 | #define IMX_CS4_SIZE MX1_CS4_SIZE | ||
184 | #define IMX_CS5_PHYS MX1_CS5_PHYS | ||
185 | #define IMX_CS5_SIZE MX1_CS5_SIZE | ||
186 | #define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR | ||
187 | #define WDT_BASE_ADDR MX1_WDT_BASE_ADDR | ||
188 | #define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR | ||
189 | #define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR | ||
190 | #define RTC_BASE_ADDR MX1_RTC_BASE_ADDR | ||
191 | #define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR | ||
192 | #define UART1_BASE_ADDR MX1_UART1_BASE_ADDR | ||
193 | #define UART2_BASE_ADDR MX1_UART2_BASE_ADDR | ||
194 | #define PWM_BASE_ADDR MX1_PWM_BASE_ADDR | ||
195 | #define DMA_BASE_ADDR MX1_DMA_BASE_ADDR | ||
196 | #define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR | ||
197 | #define SIM_BASE_ADDR MX1_SIM_BASE_ADDR | ||
198 | #define USBD_BASE_ADDR MX1_USBD_BASE_ADDR | ||
199 | #define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR | ||
200 | #define MMC_BASE_ADDR MX1_MMC_BASE_ADDR | ||
201 | #define ASP_BASE_ADDR MX1_ASP_BASE_ADDR | ||
202 | #define BTA_BASE_ADDR MX1_BTA_BASE_ADDR | ||
203 | #define I2C_BASE_ADDR MX1_I2C_BASE_ADDR | ||
204 | #define SSI_BASE_ADDR MX1_SSI_BASE_ADDR | ||
205 | #define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR | ||
206 | #define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR | ||
207 | #define CCM_BASE_ADDR MX1_CCM_BASE_ADDR | ||
208 | #define SCM_BASE_ADDR MX1_SCM_BASE_ADDR | ||
209 | #define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR | ||
210 | #define EIM_BASE_ADDR MX1_EIM_BASE_ADDR | ||
211 | #define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR | ||
212 | #define MMA_BASE_ADDR MX1_MMA_BASE_ADDR | ||
213 | #define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR | ||
214 | #define CSI_BASE_ADDR MX1_CSI_BASE_ADDR | ||
215 | #define IO_ADDRESS(x) MX1_IO_ADDRESS(x) | ||
216 | #define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) | ||
217 | #define INT_SOFTINT MX1_INT_SOFTINT | ||
218 | #define CSI_INT MX1_CSI_INT | ||
219 | #define DSPA_MAC_INT MX1_DSPA_MAC_INT | ||
220 | #define DSPA_INT MX1_DSPA_INT | ||
221 | #define COMP_INT MX1_COMP_INT | ||
222 | #define MSHC_XINT MX1_MSHC_XINT | ||
223 | #define GPIO_INT_PORTA MX1_GPIO_INT_PORTA | ||
224 | #define GPIO_INT_PORTB MX1_GPIO_INT_PORTB | ||
225 | #define GPIO_INT_PORTC MX1_GPIO_INT_PORTC | ||
226 | #define LCDC_INT MX1_LCDC_INT | ||
227 | #define SIM_INT MX1_SIM_INT | ||
228 | #define SIM_DATA_INT MX1_SIM_DATA_INT | ||
229 | #define RTC_INT MX1_RTC_INT | ||
230 | #define RTC_SAMINT MX1_RTC_SAMINT | ||
231 | #define UART2_MINT_PFERR MX1_UART2_MINT_PFERR | ||
232 | #define UART2_MINT_RTS MX1_UART2_MINT_RTS | ||
233 | #define UART2_MINT_DTR MX1_UART2_MINT_DTR | ||
234 | #define UART2_MINT_UARTC MX1_UART2_MINT_UARTC | ||
235 | #define UART2_MINT_TX MX1_UART2_MINT_TX | ||
236 | #define UART2_MINT_RX MX1_UART2_MINT_RX | ||
237 | #define UART1_MINT_PFERR MX1_UART1_MINT_PFERR | ||
238 | #define UART1_MINT_RTS MX1_UART1_MINT_RTS | ||
239 | #define UART1_MINT_DTR MX1_UART1_MINT_DTR | ||
240 | #define UART1_MINT_UARTC MX1_UART1_MINT_UARTC | ||
241 | #define UART1_MINT_TX MX1_UART1_MINT_TX | ||
242 | #define UART1_MINT_RX MX1_UART1_MINT_RX | ||
243 | #define VOICE_DAC_INT MX1_VOICE_DAC_INT | ||
244 | #define VOICE_ADC_INT MX1_VOICE_ADC_INT | ||
245 | #define PEN_DATA_INT MX1_PEN_DATA_INT | ||
246 | #define PWM_INT MX1_PWM_INT | ||
247 | #define SDHC_INT MX1_SDHC_INT | ||
248 | #define I2C_INT MX1_INT_I2C | ||
249 | #define CSPI_INT MX1_CSPI_INT | ||
250 | #define SSI_TX_INT MX1_SSI_TX_INT | ||
251 | #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT | ||
252 | #define SSI_RX_INT MX1_SSI_RX_INT | ||
253 | #define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT | ||
254 | #define TOUCH_INT MX1_TOUCH_INT | ||
255 | #define USBD_INT1 MX1_USBD_INT1 | ||
256 | #define USBD_INT2 MX1_USBD_INT2 | ||
257 | #define USBD_INT3 MX1_USBD_INT3 | ||
258 | #define USBD_INT4 MX1_USBD_INT4 | ||
259 | #define USBD_INT5 MX1_USBD_INT5 | ||
260 | #define USBD_INT6 MX1_USBD_INT6 | ||
261 | #define BTSYS_INT MX1_BTSYS_INT | ||
262 | #define BTTIM_INT MX1_BTTIM_INT | ||
263 | #define BTWUI_INT MX1_BTWUI_INT | ||
264 | #define TIM2_INT MX1_TIM2_INT | ||
265 | #define TIM1_INT MX1_TIM1_INT | ||
266 | #define DMA_ERR MX1_DMA_ERR | ||
267 | #define DMA_INT MX1_DMA_INT | ||
268 | #define GPIO_INT_PORTD MX1_GPIO_INT_PORTD | ||
269 | #define WDT_INT MX1_WDT_INT | ||
270 | #define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T | ||
271 | #define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R | ||
272 | #define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T | ||
273 | #define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R | ||
274 | #define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT | ||
275 | #define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R | ||
276 | #define DMA_REQ_MSHC MX1_DMA_REQ_MSHC | ||
277 | #define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT | ||
278 | #define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN | ||
279 | #define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC | ||
280 | #define DMA_REQ_EXT MX1_DMA_REQ_EXT | ||
281 | #define DMA_REQ_SDHC MX1_DMA_REQ_SDHC | ||
282 | #define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R | ||
283 | #define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T | ||
284 | #define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T | ||
285 | #define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R | ||
286 | #define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC | ||
287 | #define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC | ||
288 | #define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) | ||
289 | #define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R | ||
290 | #define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T | ||
291 | #define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T | ||
292 | #define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R | ||
293 | #define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T | ||
294 | #define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R | ||
295 | #endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ | ||
296 | 171 | ||
297 | #endif /* ifndef __MACH_MX1_H__ */ | 172 | #endif /* ifndef __MACH_MX1_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc59720b6e4..6cd049ebbd8d 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
@@ -26,7 +26,6 @@ | |||
26 | #define __MACH_MX21_H__ | 26 | #define __MACH_MX21_H__ |
27 | 27 | ||
28 | #define MX21_AIPI_BASE_ADDR 0x10000000 | 28 | #define MX21_AIPI_BASE_ADDR 0x10000000 |
29 | #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
30 | #define MX21_AIPI_SIZE SZ_1M | 29 | #define MX21_AIPI_SIZE SZ_1M |
31 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) | 30 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) |
32 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) | 31 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) |
@@ -49,6 +48,12 @@ | |||
49 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) | 48 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) |
50 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) | 49 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) |
51 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) | 50 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) |
51 | #define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) | ||
52 | #define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) | ||
53 | #define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) | ||
54 | #define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) | ||
55 | #define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) | ||
56 | #define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) | ||
52 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) | 57 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) |
53 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) | 58 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) |
54 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) | 59 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) |
@@ -64,7 +69,6 @@ | |||
64 | #define MX21_AVIC_BASE_ADDR 0x10040000 | 69 | #define MX21_AVIC_BASE_ADDR 0x10040000 |
65 | 70 | ||
66 | #define MX21_SAHB1_BASE_ADDR 0x80000000 | 71 | #define MX21_SAHB1_BASE_ADDR 0x80000000 |
67 | #define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
68 | #define MX21_SAHB1_SIZE SZ_1M | 72 | #define MX21_SAHB1_SIZE SZ_1M |
69 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | 73 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) |
70 | 74 | ||
@@ -82,7 +86,6 @@ | |||
82 | 86 | ||
83 | /* NAND, SDRAM, WEIM etc controllers */ | 87 | /* NAND, SDRAM, WEIM etc controllers */ |
84 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 | 88 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 |
85 | #define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 | ||
86 | #define MX21_X_MEMC_SIZE SZ_256K | 89 | #define MX21_X_MEMC_SIZE SZ_256K |
87 | 90 | ||
88 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) | 91 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) |
@@ -92,10 +95,8 @@ | |||
92 | 95 | ||
93 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ | 96 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ |
94 | 97 | ||
95 | #define MX21_IO_ADDRESS(x) ( \ | 98 | #define MX21_IO_P2V(x) IMX_IO_P2V(x) |
96 | IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ | 99 | #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) |
97 | IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ | ||
98 | IMX_IO_ADDRESS(x, MX21_X_MEMC)) | ||
99 | 100 | ||
100 | /* fixed interrupt numbers */ | 101 | /* fixed interrupt numbers */ |
101 | #define MX21_INT_CSPI3 6 | 102 | #define MX21_INT_CSPI3 6 |
@@ -184,39 +185,4 @@ | |||
184 | #define MX21_DMA_REQ_CSI_STAT 30 | 185 | #define MX21_DMA_REQ_CSI_STAT 30 |
185 | #define MX21_DMA_REQ_CSI_RX 31 | 186 | #define MX21_DMA_REQ_CSI_RX 31 |
186 | 187 | ||
187 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
188 | /* these should go away */ | ||
189 | #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR | ||
190 | #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR | ||
191 | #define CS0_BASE_ADDR MX21_CS0_BASE_ADDR | ||
192 | #define CS1_BASE_ADDR MX21_CS1_BASE_ADDR | ||
193 | #define CS2_BASE_ADDR MX21_CS2_BASE_ADDR | ||
194 | #define CS3_BASE_ADDR MX21_CS3_BASE_ADDR | ||
195 | #define CS4_BASE_ADDR MX21_CS4_BASE_ADDR | ||
196 | #define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR | ||
197 | #define CS5_BASE_ADDR MX21_CS5_BASE_ADDR | ||
198 | #define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR | ||
199 | #define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT | ||
200 | #define X_MEMC_SIZE MX21_X_MEMC_SIZE | ||
201 | #define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR | ||
202 | #define EIM_BASE_ADDR MX21_EIM_BASE_ADDR | ||
203 | #define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR | ||
204 | #define NFC_BASE_ADDR MX21_NFC_BASE_ADDR | ||
205 | #define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR | ||
206 | #define MXC_INT_FIRI MX21_INT_FIRI | ||
207 | #define MXC_INT_BMI MX21_INT_BMI | ||
208 | #define MXC_INT_EMMAENC MX21_INT_EMMAENC | ||
209 | #define MXC_INT_EMMADEC MX21_INT_EMMADEC | ||
210 | #define MXC_INT_USBWKUP MX21_INT_USBWKUP | ||
211 | #define MXC_INT_USBDMA MX21_INT_USBDMA | ||
212 | #define MXC_INT_USBHOST MX21_INT_USBHOST | ||
213 | #define MXC_INT_USBFUNC MX21_INT_USBFUNC | ||
214 | #define MXC_INT_USBMNP MX21_INT_USBMNP | ||
215 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
216 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
217 | #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX | ||
218 | #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX | ||
219 | #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX | ||
220 | #endif | ||
221 | |||
222 | #endif /* ifndef __MACH_MX21_H__ */ | 188 | #endif /* ifndef __MACH_MX21_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cf46a45b0d4e..024bebe4da11 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h | |||
@@ -2,13 +2,10 @@ | |||
2 | #define __MACH_MX25_H__ | 2 | #define __MACH_MX25_H__ |
3 | 3 | ||
4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 | 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
5 | #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
6 | #define MX25_AIPS1_SIZE SZ_1M | 5 | #define MX25_AIPS1_SIZE SZ_1M |
7 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 | 6 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
8 | #define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
9 | #define MX25_AIPS2_SIZE SZ_1M | 7 | #define MX25_AIPS2_SIZE SZ_1M |
10 | #define MX25_AVIC_BASE_ADDR 0x68000000 | 8 | #define MX25_AVIC_BASE_ADDR 0x68000000 |
11 | #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
12 | #define MX25_AVIC_SIZE SZ_1M | 9 | #define MX25_AVIC_SIZE SZ_1M |
13 | 10 | ||
14 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) | 11 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) |
@@ -21,20 +18,15 @@ | |||
21 | 18 | ||
22 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | 19 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) |
23 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | 20 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) |
21 | #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) | ||
22 | #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) | ||
23 | #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) | ||
24 | #define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) | ||
25 | #define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) | ||
26 | #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) | ||
27 | #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) | ||
24 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) | 28 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) |
25 | 29 | #define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) | |
26 | #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) | ||
27 | #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) | ||
28 | #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) | ||
29 | #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) | ||
30 | |||
31 | #define MX25_IO_ADDRESS(x) ( \ | ||
32 | IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ | ||
33 | IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ | ||
34 | IMX_IO_ADDRESS(x, MX25_AVIC)) | ||
35 | |||
36 | #define MX25_AIPS1_IO_ADDRESS(x) \ | ||
37 | (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) | ||
38 | 30 | ||
39 | #define MX25_UART1_BASE_ADDR 0x43f90000 | 31 | #define MX25_UART1_BASE_ADDR 0x43f90000 |
40 | #define MX25_UART2_BASE_ADDR 0x43f94000 | 32 | #define MX25_UART2_BASE_ADDR 0x43f94000 |
@@ -55,9 +47,14 @@ | |||
55 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 | 47 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 |
56 | #define MX25_KPP_BASE_ADDR 0x43fa8000 | 48 | #define MX25_KPP_BASE_ADDR 0x43fa8000 |
57 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 | 49 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 |
58 | #define MX25_OTG_BASE_ADDR 0x53ff4000 | 50 | #define MX25_USB_BASE_ADDR 0x53ff4000 |
51 | #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) | ||
52 | #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200) | ||
59 | #define MX25_CSI_BASE_ADDR 0x53ff8000 | 53 | #define MX25_CSI_BASE_ADDR 0x53ff8000 |
60 | 54 | ||
55 | #define MX25_IO_P2V(x) IMX_IO_P2V(x) | ||
56 | #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) | ||
57 | |||
61 | #define MX25_INT_CSPI3 0 | 58 | #define MX25_INT_CSPI3 0 |
62 | #define MX25_INT_I2C1 3 | 59 | #define MX25_INT_I2C1 3 |
63 | #define MX25_INT_I2C2 4 | 60 | #define MX25_INT_I2C2 4 |
@@ -69,18 +66,28 @@ | |||
69 | #define MX25_INT_SSI1 12 | 66 | #define MX25_INT_SSI1 12 |
70 | #define MX25_INT_CSPI2 13 | 67 | #define MX25_INT_CSPI2 13 |
71 | #define MX25_INT_CSPI1 14 | 68 | #define MX25_INT_CSPI1 14 |
69 | #define MX25_INT_GPIO3 16 | ||
72 | #define MX25_INT_CSI 17 | 70 | #define MX25_INT_CSI 17 |
73 | #define MX25_INT_UART3 18 | 71 | #define MX25_INT_UART3 18 |
72 | #define MX25_INT_GPIO4 23 | ||
74 | #define MX25_INT_KPP 24 | 73 | #define MX25_INT_KPP 24 |
75 | #define MX25_INT_DRYICE 25 | 74 | #define MX25_INT_DRYICE 25 |
75 | #define MX25_INT_PWM1 26 | ||
76 | #define MX25_INT_UART2 32 | 76 | #define MX25_INT_UART2 32 |
77 | #define MX25_INT_NFC 33 | 77 | #define MX25_INT_NFC 33 |
78 | #define MX25_INT_SDMA 34 | 78 | #define MX25_INT_SDMA 34 |
79 | #define MX25_INT_USB_HS 35 | ||
80 | #define MX25_INT_PWM2 36 | ||
81 | #define MX25_INT_USB_OTG 37 | ||
79 | #define MX25_INT_LCDC 39 | 82 | #define MX25_INT_LCDC 39 |
80 | #define MX25_INT_UART5 40 | 83 | #define MX25_INT_UART5 40 |
84 | #define MX25_INT_PWM3 41 | ||
85 | #define MX25_INT_PWM4 42 | ||
81 | #define MX25_INT_CAN1 43 | 86 | #define MX25_INT_CAN1 43 |
82 | #define MX25_INT_CAN2 44 | 87 | #define MX25_INT_CAN2 44 |
83 | #define MX25_INT_UART1 45 | 88 | #define MX25_INT_UART1 45 |
89 | #define MX25_INT_GPIO2 51 | ||
90 | #define MX25_INT_GPIO1 52 | ||
84 | #define MX25_INT_FEC 57 | 91 | #define MX25_INT_FEC 57 |
85 | 92 | ||
86 | #define MX25_DMA_REQ_SSI2_RX1 22 | 93 | #define MX25_DMA_REQ_SSI2_RX1 22 |
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2e5351..eb09ec09dbe5 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
@@ -29,7 +29,6 @@ | |||
29 | #endif | 29 | #endif |
30 | 30 | ||
31 | #define MX27_AIPI_BASE_ADDR 0x10000000 | 31 | #define MX27_AIPI_BASE_ADDR 0x10000000 |
32 | #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
33 | #define MX27_AIPI_SIZE SZ_1M | 32 | #define MX27_AIPI_SIZE SZ_1M |
34 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) | 33 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) |
35 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) | 34 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) |
@@ -52,6 +51,12 @@ | |||
52 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) | 51 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) |
53 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) | 52 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) |
54 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) | 53 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) |
54 | #define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) | ||
55 | #define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) | ||
56 | #define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) | ||
57 | #define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) | ||
58 | #define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) | ||
59 | #define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) | ||
55 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) | 60 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) |
56 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) | 61 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) |
57 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) | 62 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) |
@@ -65,11 +70,13 @@ | |||
65 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) | 70 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) |
66 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) | 71 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) |
67 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) | 72 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) |
68 | #define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) | 73 | #define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) |
69 | #define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR | 74 | #define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) |
75 | #define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) | ||
76 | #define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) | ||
70 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) | 77 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) |
71 | #define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) | 78 | #define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) |
72 | #define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) | 79 | #define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) |
73 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) | 80 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) |
74 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) | 81 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) |
75 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) | 82 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) |
@@ -87,7 +94,6 @@ | |||
87 | #define MX27_ROMP_BASE_ADDR 0x10041000 | 94 | #define MX27_ROMP_BASE_ADDR 0x10041000 |
88 | 95 | ||
89 | #define MX27_SAHB1_BASE_ADDR 0x80000000 | 96 | #define MX27_SAHB1_BASE_ADDR 0x80000000 |
90 | #define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
91 | #define MX27_SAHB1_SIZE SZ_1M | 97 | #define MX27_SAHB1_SIZE SZ_1M |
92 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) | 98 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) |
93 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) | 99 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) |
@@ -105,7 +111,6 @@ | |||
105 | 111 | ||
106 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ | 112 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
107 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 | 113 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 |
108 | #define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 | ||
109 | #define MX27_X_MEMC_SIZE SZ_1M | 114 | #define MX27_X_MEMC_SIZE SZ_1M |
110 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) | 115 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) |
111 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) | 116 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) |
@@ -123,10 +128,8 @@ | |||
123 | /* IRAM */ | 128 | /* IRAM */ |
124 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ | 129 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ |
125 | 130 | ||
126 | #define MX27_IO_ADDRESS(x) ( \ | 131 | #define MX27_IO_P2V(x) IMX_IO_P2V(x) |
127 | IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ | 132 | #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) |
128 | IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ | ||
129 | IMX_IO_ADDRESS(x, MX27_X_MEMC)) | ||
130 | 133 | ||
131 | #ifndef __ASSEMBLER__ | 134 | #ifndef __ASSEMBLER__ |
132 | static inline void mx27_setup_weimcs(size_t cs, | 135 | static inline void mx27_setup_weimcs(size_t cs, |
@@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs, | |||
192 | #define MX27_INT_EMMAPRP 51 | 195 | #define MX27_INT_EMMAPRP 51 |
193 | #define MX27_INT_EMMAPP 52 | 196 | #define MX27_INT_EMMAPP 52 |
194 | #define MX27_INT_VPU 53 | 197 | #define MX27_INT_VPU 53 |
195 | #define MX27_INT_USB1 54 | 198 | #define MX27_INT_USB_HS1 54 |
196 | #define MX27_INT_USB2 55 | 199 | #define MX27_INT_USB_HS2 55 |
197 | #define MX27_INT_USB3 56 | 200 | #define MX27_INT_USB_OTG 56 |
198 | #define MX27_INT_SCC_SMN 57 | 201 | #define MX27_INT_SCC_SMN 57 |
199 | #define MX27_INT_SCC_SCM 58 | 202 | #define MX27_INT_SCC_SCM 58 |
200 | #define MX27_INT_SAHARA 59 | 203 | #define MX27_INT_SAHARA 59 |
@@ -249,74 +252,4 @@ static inline void mx27_setup_weimcs(size_t cs, | |||
249 | extern int mx27_revision(void); | 252 | extern int mx27_revision(void); |
250 | #endif | 253 | #endif |
251 | 254 | ||
252 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
253 | /* these should go away */ | ||
254 | #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR | ||
255 | #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR | ||
256 | #define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR | ||
257 | #define UART5_BASE_ADDR MX27_UART5_BASE_ADDR | ||
258 | #define UART6_BASE_ADDR MX27_UART6_BASE_ADDR | ||
259 | #define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR | ||
260 | #define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR | ||
261 | #define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR | ||
262 | #define VPU_BASE_ADDR MX27_VPU_BASE_ADDR | ||
263 | #define OTG_BASE_ADDR MX27_OTG_BASE_ADDR | ||
264 | #define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR | ||
265 | #define IIM_BASE_ADDR MX27_IIM_BASE_ADDR | ||
266 | #define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR | ||
267 | #define FEC_BASE_ADDR MX27_FEC_BASE_ADDR | ||
268 | #define SCC_BASE_ADDR MX27_SCC_BASE_ADDR | ||
269 | #define ETB_BASE_ADDR MX27_ETB_BASE_ADDR | ||
270 | #define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR | ||
271 | #define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR | ||
272 | #define ATA_BASE_ADDR MX27_ATA_BASE_ADDR | ||
273 | #define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR | ||
274 | #define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR | ||
275 | #define CS0_BASE_ADDR MX27_CS0_BASE_ADDR | ||
276 | #define CS1_BASE_ADDR MX27_CS1_BASE_ADDR | ||
277 | #define CS2_BASE_ADDR MX27_CS2_BASE_ADDR | ||
278 | #define CS3_BASE_ADDR MX27_CS3_BASE_ADDR | ||
279 | #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR | ||
280 | #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR | ||
281 | #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR | ||
282 | #define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT | ||
283 | #define X_MEMC_SIZE MX27_X_MEMC_SIZE | ||
284 | #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR | ||
285 | #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR | ||
286 | #define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR | ||
287 | #define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR | ||
288 | #define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR | ||
289 | #define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR | ||
290 | #define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR | ||
291 | #define MXC_INT_I2C2 MX27_INT_I2C2 | ||
292 | #define MXC_INT_GPT6 MX27_INT_GPT6 | ||
293 | #define MXC_INT_GPT5 MX27_INT_GPT5 | ||
294 | #define MXC_INT_GPT4 MX27_INT_GPT4 | ||
295 | #define MXC_INT_RTIC MX27_INT_RTIC | ||
296 | #define MXC_INT_SDHC MX27_INT_SDHC | ||
297 | #define MXC_INT_SDHC3 MX27_INT_SDHC3 | ||
298 | #define MXC_INT_ATA MX27_INT_ATA | ||
299 | #define MXC_INT_UART6 MX27_INT_UART6 | ||
300 | #define MXC_INT_UART5 MX27_INT_UART5 | ||
301 | #define MXC_INT_FEC MX27_INT_FEC | ||
302 | #define MXC_INT_VPU MX27_INT_VPU | ||
303 | #define MXC_INT_USB1 MX27_INT_USB1 | ||
304 | #define MXC_INT_USB2 MX27_INT_USB2 | ||
305 | #define MXC_INT_USB3 MX27_INT_USB3 | ||
306 | #define MXC_INT_SCC_SMN MX27_INT_SCC_SMN | ||
307 | #define MXC_INT_SCC_SCM MX27_INT_SCC_SCM | ||
308 | #define MXC_INT_SAHARA MX27_INT_SAHARA | ||
309 | #define MXC_INT_IIM MX27_INT_IIM | ||
310 | #define MXC_INT_CCM MX27_INT_CCM | ||
311 | #define DMA_REQ_MSHC MX27_DMA_REQ_MSHC | ||
312 | #define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX | ||
313 | #define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV | ||
314 | #define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX | ||
315 | #define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX | ||
316 | #define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX | ||
317 | #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX | ||
318 | #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 | ||
319 | #define DMA_REQ_NFC MX27_DMA_REQ_NFC | ||
320 | #endif | ||
321 | |||
322 | #endif /* ifndef __MACH_MX27_H__ */ | 255 | #endif /* ifndef __MACH_MX27_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index afb895a0b5b8..6d07839fdec2 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h | |||
@@ -27,7 +27,6 @@ | |||
27 | 27 | ||
28 | /* Register offsets */ | 28 | /* Register offsets */ |
29 | #define MX2x_AIPI_BASE_ADDR 0x10000000 | 29 | #define MX2x_AIPI_BASE_ADDR 0x10000000 |
30 | #define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
31 | #define MX2x_AIPI_SIZE SZ_1M | 30 | #define MX2x_AIPI_SIZE SZ_1M |
32 | #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) | 31 | #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) |
33 | #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) | 32 | #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) |
@@ -65,43 +64,9 @@ | |||
65 | #define MX2x_AVIC_BASE_ADDR 0x10040000 | 64 | #define MX2x_AVIC_BASE_ADDR 0x10040000 |
66 | 65 | ||
67 | #define MX2x_SAHB1_BASE_ADDR 0x80000000 | 66 | #define MX2x_SAHB1_BASE_ADDR 0x80000000 |
68 | #define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
69 | #define MX2x_SAHB1_SIZE SZ_1M | 67 | #define MX2x_SAHB1_SIZE SZ_1M |
70 | #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | 68 | #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) |
71 | 69 | ||
72 | /* | ||
73 | * This macro defines the physical to virtual address mapping for all the | ||
74 | * peripheral modules. It is used by passing in the physical address as x | ||
75 | * and returning the virtual address. If the physical address is not mapped, | ||
76 | * it returns 0xDEADBEEF | ||
77 | */ | ||
78 | #define IO_ADDRESS(x) \ | ||
79 | (void __force __iomem *) \ | ||
80 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
81 | AIPI_IO_ADDRESS(x) : \ | ||
82 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
83 | SAHB1_IO_ADDRESS(x) : \ | ||
84 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
85 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
86 | |||
87 | /* define the address mapping macros: in physical address order */ | ||
88 | #define AIPI_IO_ADDRESS(x) \ | ||
89 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
90 | |||
91 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
92 | |||
93 | #define SAHB1_IO_ADDRESS(x) \ | ||
94 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
95 | |||
96 | #define CS4_IO_ADDRESS(x) \ | ||
97 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
98 | |||
99 | #define X_MEMC_IO_ADDRESS(x) \ | ||
100 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
101 | |||
102 | #define PCMCIA_IO_ADDRESS(x) \ | ||
103 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
104 | |||
105 | /* fixed interrupt numbers */ | 70 | /* fixed interrupt numbers */ |
106 | #define MX2x_INT_CSPI3 6 | 71 | #define MX2x_INT_CSPI3 6 |
107 | #define MX2x_INT_GPIO 8 | 72 | #define MX2x_INT_GPIO 8 |
@@ -176,118 +141,4 @@ | |||
176 | #define MX2x_DMA_REQ_CSI_STAT 30 | 141 | #define MX2x_DMA_REQ_CSI_STAT 30 |
177 | #define MX2x_DMA_REQ_CSI_RX 31 | 142 | #define MX2x_DMA_REQ_CSI_RX 31 |
178 | 143 | ||
179 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
180 | /* these should go away */ | ||
181 | #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR | ||
182 | #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT | ||
183 | #define AIPI_SIZE MX2x_AIPI_SIZE | ||
184 | #define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR | ||
185 | #define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR | ||
186 | #define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR | ||
187 | #define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR | ||
188 | #define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR | ||
189 | #define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR | ||
190 | #define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR | ||
191 | #define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR | ||
192 | #define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR | ||
193 | #define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR | ||
194 | #define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR | ||
195 | #define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR | ||
196 | #define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR | ||
197 | #define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR | ||
198 | #define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR | ||
199 | #define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR | ||
200 | #define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR | ||
201 | #define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR | ||
202 | #define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR | ||
203 | #define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR | ||
204 | #define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR | ||
205 | #define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR | ||
206 | #define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR | ||
207 | #define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR | ||
208 | #define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR | ||
209 | #define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR | ||
210 | #define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR | ||
211 | #define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR | ||
212 | #define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR | ||
213 | #define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR | ||
214 | #define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR | ||
215 | #define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR | ||
216 | #define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR | ||
217 | #define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR | ||
218 | #define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT | ||
219 | #define SAHB1_SIZE MX2x_SAHB1_SIZE | ||
220 | #define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR | ||
221 | #define MXC_INT_CSPI3 MX2x_INT_CSPI3 | ||
222 | #define MXC_INT_GPIO MX2x_INT_GPIO | ||
223 | #define MXC_INT_SDHC2 MX2x_INT_SDHC2 | ||
224 | #define MXC_INT_SDHC1 MX2x_INT_SDHC1 | ||
225 | #define MXC_INT_I2C MX2x_INT_I2C | ||
226 | #define MXC_INT_SSI2 MX2x_INT_SSI2 | ||
227 | #define MXC_INT_SSI1 MX2x_INT_SSI1 | ||
228 | #define MXC_INT_CSPI2 MX2x_INT_CSPI2 | ||
229 | #define MXC_INT_CSPI1 MX2x_INT_CSPI1 | ||
230 | #define MXC_INT_UART4 MX2x_INT_UART4 | ||
231 | #define MXC_INT_UART3 MX2x_INT_UART3 | ||
232 | #define MXC_INT_UART2 MX2x_INT_UART2 | ||
233 | #define MXC_INT_UART1 MX2x_INT_UART1 | ||
234 | #define MXC_INT_KPP MX2x_INT_KPP | ||
235 | #define MXC_INT_RTC MX2x_INT_RTC | ||
236 | #define MXC_INT_PWM MX2x_INT_PWM | ||
237 | #define MXC_INT_GPT3 MX2x_INT_GPT3 | ||
238 | #define MXC_INT_GPT2 MX2x_INT_GPT2 | ||
239 | #define MXC_INT_GPT1 MX2x_INT_GPT1 | ||
240 | #define MXC_INT_WDOG MX2x_INT_WDOG | ||
241 | #define MXC_INT_PCMCIA MX2x_INT_PCMCIA | ||
242 | #define MXC_INT_NANDFC MX2x_INT_NANDFC | ||
243 | #define MXC_INT_CSI MX2x_INT_CSI | ||
244 | #define MXC_INT_DMACH0 MX2x_INT_DMACH0 | ||
245 | #define MXC_INT_DMACH1 MX2x_INT_DMACH1 | ||
246 | #define MXC_INT_DMACH2 MX2x_INT_DMACH2 | ||
247 | #define MXC_INT_DMACH3 MX2x_INT_DMACH3 | ||
248 | #define MXC_INT_DMACH4 MX2x_INT_DMACH4 | ||
249 | #define MXC_INT_DMACH5 MX2x_INT_DMACH5 | ||
250 | #define MXC_INT_DMACH6 MX2x_INT_DMACH6 | ||
251 | #define MXC_INT_DMACH7 MX2x_INT_DMACH7 | ||
252 | #define MXC_INT_DMACH8 MX2x_INT_DMACH8 | ||
253 | #define MXC_INT_DMACH9 MX2x_INT_DMACH9 | ||
254 | #define MXC_INT_DMACH10 MX2x_INT_DMACH10 | ||
255 | #define MXC_INT_DMACH11 MX2x_INT_DMACH11 | ||
256 | #define MXC_INT_DMACH12 MX2x_INT_DMACH12 | ||
257 | #define MXC_INT_DMACH13 MX2x_INT_DMACH13 | ||
258 | #define MXC_INT_DMACH14 MX2x_INT_DMACH14 | ||
259 | #define MXC_INT_DMACH15 MX2x_INT_DMACH15 | ||
260 | #define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP | ||
261 | #define MXC_INT_EMMAPP MX2x_INT_EMMAPP | ||
262 | #define MXC_INT_SLCDC MX2x_INT_SLCDC | ||
263 | #define MXC_INT_LCDC MX2x_INT_LCDC | ||
264 | #define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX | ||
265 | #define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX | ||
266 | #define DMA_REQ_EXT MX2x_DMA_REQ_EXT | ||
267 | #define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 | ||
268 | #define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 | ||
269 | #define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 | ||
270 | #define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 | ||
271 | #define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 | ||
272 | #define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 | ||
273 | #define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 | ||
274 | #define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 | ||
275 | #define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 | ||
276 | #define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 | ||
277 | #define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX | ||
278 | #define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX | ||
279 | #define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX | ||
280 | #define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX | ||
281 | #define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX | ||
282 | #define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX | ||
283 | #define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX | ||
284 | #define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX | ||
285 | #define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX | ||
286 | #define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX | ||
287 | #define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX | ||
288 | #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX | ||
289 | #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT | ||
290 | #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX | ||
291 | #endif | ||
292 | |||
293 | #endif /* ifndef __MACH_MX2x_H__ */ | 144 | #endif /* ifndef __MACH_MX2x_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 61cfe827498b..092323144e2b 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -15,7 +15,6 @@ | |||
15 | #define MX31_L2CC_SIZE SZ_1M | 15 | #define MX31_L2CC_SIZE SZ_1M |
16 | 16 | ||
17 | #define MX31_AIPS1_BASE_ADDR 0x43f00000 | 17 | #define MX31_AIPS1_BASE_ADDR 0x43f00000 |
18 | #define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
19 | #define MX31_AIPS1_SIZE SZ_1M | 18 | #define MX31_AIPS1_SIZE SZ_1M |
20 | #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) | 19 | #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) |
21 | #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) | 20 | #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) |
@@ -25,7 +24,10 @@ | |||
25 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) | 24 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) |
26 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) | 25 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) |
27 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) | 26 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) |
28 | #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) | 27 | #define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) |
28 | #define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) | ||
29 | #define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) | ||
30 | #define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) | ||
29 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) | 31 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) |
30 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) | 32 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) |
31 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) | 33 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) |
@@ -41,10 +43,9 @@ | |||
41 | #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) | 43 | #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) |
42 | 44 | ||
43 | #define MX31_SPBA0_BASE_ADDR 0x50000000 | 45 | #define MX31_SPBA0_BASE_ADDR 0x50000000 |
44 | #define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
45 | #define MX31_SPBA0_SIZE SZ_1M | 46 | #define MX31_SPBA0_SIZE SZ_1M |
46 | #define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) | 47 | #define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) |
47 | #define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) | 48 | #define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) |
48 | #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) | 49 | #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) |
49 | #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) | 50 | #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) |
50 | #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) | 51 | #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) |
@@ -55,7 +56,6 @@ | |||
55 | #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) | 56 | #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) |
56 | 57 | ||
57 | #define MX31_AIPS2_BASE_ADDR 0x53f00000 | 58 | #define MX31_AIPS2_BASE_ADDR 0x53f00000 |
58 | #define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
59 | #define MX31_AIPS2_SIZE SZ_1M | 59 | #define MX31_AIPS2_SIZE SZ_1M |
60 | #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) | 60 | #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) |
61 | #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) | 61 | #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) |
@@ -84,7 +84,6 @@ | |||
84 | #define MX31_ROMP_SIZE SZ_1M | 84 | #define MX31_ROMP_SIZE SZ_1M |
85 | 85 | ||
86 | #define MX31_AVIC_BASE_ADDR 0x68000000 | 86 | #define MX31_AVIC_BASE_ADDR 0x68000000 |
87 | #define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
88 | #define MX31_AVIC_SIZE SZ_1M | 87 | #define MX31_AVIC_SIZE SZ_1M |
89 | 88 | ||
90 | #define MX31_IPU_MEM_BASE_ADDR 0x70000000 | 89 | #define MX31_IPU_MEM_BASE_ADDR 0x70000000 |
@@ -97,15 +96,14 @@ | |||
97 | #define MX31_CS3_BASE_ADDR 0xb2000000 | 96 | #define MX31_CS3_BASE_ADDR 0xb2000000 |
98 | 97 | ||
99 | #define MX31_CS4_BASE_ADDR 0xb4000000 | 98 | #define MX31_CS4_BASE_ADDR 0xb4000000 |
100 | #define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 | 99 | #define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 |
101 | #define MX31_CS4_SIZE SZ_32M | 100 | #define MX31_CS4_SIZE SZ_32M |
102 | 101 | ||
103 | #define MX31_CS5_BASE_ADDR 0xb6000000 | 102 | #define MX31_CS5_BASE_ADDR 0xb6000000 |
104 | #define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 | 103 | #define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 |
105 | #define MX31_CS5_SIZE SZ_32M | 104 | #define MX31_CS5_SIZE SZ_32M |
106 | 105 | ||
107 | #define MX31_X_MEMC_BASE_ADDR 0xb8000000 | 106 | #define MX31_X_MEMC_BASE_ADDR 0xb8000000 |
108 | #define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
109 | #define MX31_X_MEMC_SIZE SZ_64K | 107 | #define MX31_X_MEMC_SIZE SZ_64K |
110 | #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) | 108 | #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) |
111 | #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) | 109 | #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) |
@@ -121,12 +119,8 @@ | |||
121 | 119 | ||
122 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 120 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
123 | 121 | ||
124 | #define MX31_IO_ADDRESS(x) ( \ | 122 | #define MX31_IO_P2V(x) IMX_IO_P2V(x) |
125 | IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ | 123 | #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) |
126 | IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ | ||
127 | IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ | ||
128 | IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ | ||
129 | IMX_IO_ADDRESS(x, MX31_SPBA0)) | ||
130 | 124 | ||
131 | #ifndef __ASSEMBLER__ | 125 | #ifndef __ASSEMBLER__ |
132 | static inline void mx31_setup_weimcs(size_t cs, | 126 | static inline void mx31_setup_weimcs(size_t cs, |
@@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
143 | #define MX31_INT_MPEG4_ENCODER 5 | 137 | #define MX31_INT_MPEG4_ENCODER 5 |
144 | #define MX31_INT_RTIC 6 | 138 | #define MX31_INT_RTIC 6 |
145 | #define MX31_INT_FIRI 7 | 139 | #define MX31_INT_FIRI 7 |
146 | #define MX31_INT_MMC_SDHC2 8 | 140 | #define MX31_INT_SDHC2 8 |
147 | #define MX31_INT_MMC_SDHC1 9 | 141 | #define MX31_INT_SDHC1 9 |
148 | #define MX31_INT_I2C1 10 | 142 | #define MX31_INT_I2C1 10 |
149 | #define MX31_INT_SSI2 11 | 143 | #define MX31_INT_SSI2 11 |
150 | #define MX31_INT_SSI1 12 | 144 | #define MX31_INT_SSI1 12 |
@@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
170 | #define MX31_INT_UART2 32 | 164 | #define MX31_INT_UART2 32 |
171 | #define MX31_INT_NFC 33 | 165 | #define MX31_INT_NFC 33 |
172 | #define MX31_INT_SDMA 34 | 166 | #define MX31_INT_SDMA 34 |
173 | #define MX31_INT_USB1 35 | 167 | #define MX31_INT_USB_HS1 35 |
174 | #define MX31_INT_USB2 36 | 168 | #define MX31_INT_USB_HS2 36 |
175 | #define MX31_INT_USB3 37 | 169 | #define MX31_INT_USB_OTG 37 |
176 | #define MX31_INT_USB4 38 | ||
177 | #define MX31_INT_MSHC1 39 | 170 | #define MX31_INT_MSHC1 39 |
178 | #define MX31_INT_MSHC2 40 | 171 | #define MX31_INT_MSHC2 40 |
179 | #define MX31_INT_IPU_ERR 41 | 172 | #define MX31_INT_IPU_ERR 41 |
@@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
197 | #define MX31_INT_EXT_WDOG 62 | 190 | #define MX31_INT_EXT_WDOG 62 |
198 | #define MX31_INT_EXT_TV 63 | 191 | #define MX31_INT_EXT_TV 63 |
199 | 192 | ||
193 | #define MX31_DMA_REQ_SDHC1 20 | ||
194 | #define MX31_DMA_REQ_SDHC2 21 | ||
200 | #define MX31_DMA_REQ_SSI2_RX1 22 | 195 | #define MX31_DMA_REQ_SSI2_RX1 22 |
201 | #define MX31_DMA_REQ_SSI2_TX1 23 | 196 | #define MX31_DMA_REQ_SSI2_TX1 23 |
202 | #define MX31_DMA_REQ_SSI2_RX0 24 | 197 | #define MX31_DMA_REQ_SSI2_RX0 24 |
@@ -224,36 +219,4 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
224 | #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 | 219 | #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 |
225 | #define MX31_SYSTEM_REV_NUM 3 | 220 | #define MX31_SYSTEM_REV_NUM 3 |
226 | 221 | ||
227 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
228 | /* these should go away */ | ||
229 | #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR | ||
230 | #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR | ||
231 | #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR | ||
232 | #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR | ||
233 | #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR | ||
234 | #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR | ||
235 | #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR | ||
236 | #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR | ||
237 | #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR | ||
238 | #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR | ||
239 | #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR | ||
240 | #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR | ||
241 | #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER | ||
242 | #define MXC_INT_FIRI MX31_INT_FIRI | ||
243 | #define MXC_INT_MBX MX31_INT_MBX | ||
244 | #define MXC_INT_CSPI3 MX31_INT_CSPI3 | ||
245 | #define MXC_INT_SIM2 MX31_INT_SIM2 | ||
246 | #define MXC_INT_SIM1 MX31_INT_SIM1 | ||
247 | #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS | ||
248 | #define MXC_INT_USB1 MX31_INT_USB1 | ||
249 | #define MXC_INT_USB2 MX31_INT_USB2 | ||
250 | #define MXC_INT_USB3 MX31_INT_USB3 | ||
251 | #define MXC_INT_USB4 MX31_INT_USB4 | ||
252 | #define MXC_INT_MSHC2 MX31_INT_MSHC2 | ||
253 | #define MXC_INT_UART4 MX31_INT_UART4 | ||
254 | #define MXC_INT_UART5 MX31_INT_UART5 | ||
255 | #define MXC_INT_CCM MX31_INT_CCM | ||
256 | #define MXC_INT_PCMCIA MX31_INT_PCMCIA | ||
257 | #endif | ||
258 | |||
259 | #endif /* ifndef __MACH_MX31_H__ */ | 222 | #endif /* ifndef __MACH_MX31_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6267cff6035d..0fa3f6855349 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
@@ -11,7 +11,6 @@ | |||
11 | #define MX35_L2CC_SIZE SZ_1M | 11 | #define MX35_L2CC_SIZE SZ_1M |
12 | 12 | ||
13 | #define MX35_AIPS1_BASE_ADDR 0x43f00000 | 13 | #define MX35_AIPS1_BASE_ADDR 0x43f00000 |
14 | #define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
15 | #define MX35_AIPS1_SIZE SZ_1M | 14 | #define MX35_AIPS1_SIZE SZ_1M |
16 | #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) | 15 | #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) |
17 | #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) | 16 | #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) |
@@ -33,7 +32,6 @@ | |||
33 | #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) | 32 | #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) |
34 | 33 | ||
35 | #define MX35_SPBA0_BASE_ADDR 0x50000000 | 34 | #define MX35_SPBA0_BASE_ADDR 0x50000000 |
36 | #define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
37 | #define MX35_SPBA0_SIZE SZ_1M | 35 | #define MX35_SPBA0_SIZE SZ_1M |
38 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) | 36 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) |
39 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) | 37 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) |
@@ -44,7 +42,6 @@ | |||
44 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) | 42 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) |
45 | 43 | ||
46 | #define MX35_AIPS2_BASE_ADDR 0x53f00000 | 44 | #define MX35_AIPS2_BASE_ADDR 0x53f00000 |
47 | #define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
48 | #define MX35_AIPS2_SIZE SZ_1M | 45 | #define MX35_AIPS2_SIZE SZ_1M |
49 | #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) | 46 | #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) |
50 | #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) | 47 | #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) |
@@ -68,15 +65,19 @@ | |||
68 | #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) | 65 | #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) |
69 | #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) | 66 | #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) |
70 | #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) | 67 | #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) |
71 | 68 | #define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) | |
72 | #define MX35_OTG_BASE_ADDR 0x53ff4000 | 69 | #define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) |
70 | /* | ||
71 | * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for | ||
72 | * HS. When host support was implemented only a preliminary document was | ||
73 | * available, which told 0x400. This works fine. | ||
74 | */ | ||
75 | #define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) | ||
73 | 76 | ||
74 | #define MX35_ROMP_BASE_ADDR 0x60000000 | 77 | #define MX35_ROMP_BASE_ADDR 0x60000000 |
75 | #define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 | ||
76 | #define MX35_ROMP_SIZE SZ_1M | 78 | #define MX35_ROMP_SIZE SZ_1M |
77 | 79 | ||
78 | #define MX35_AVIC_BASE_ADDR 0x68000000 | 80 | #define MX35_AVIC_BASE_ADDR 0x68000000 |
79 | #define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
80 | #define MX35_AVIC_SIZE SZ_1M | 81 | #define MX35_AVIC_SIZE SZ_1M |
81 | 82 | ||
82 | /* | 83 | /* |
@@ -92,18 +93,17 @@ | |||
92 | #define MX35_CS3_BASE_ADDR 0xb2000000 | 93 | #define MX35_CS3_BASE_ADDR 0xb2000000 |
93 | 94 | ||
94 | #define MX35_CS4_BASE_ADDR 0xb4000000 | 95 | #define MX35_CS4_BASE_ADDR 0xb4000000 |
95 | #define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 | 96 | #define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 |
96 | #define MX35_CS4_SIZE SZ_32M | 97 | #define MX35_CS4_SIZE SZ_32M |
97 | 98 | ||
98 | #define MX35_CS5_BASE_ADDR 0xb6000000 | 99 | #define MX35_CS5_BASE_ADDR 0xb6000000 |
99 | #define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 | 100 | #define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 |
100 | #define MX35_CS5_SIZE SZ_32M | 101 | #define MX35_CS5_SIZE SZ_32M |
101 | 102 | ||
102 | /* | 103 | /* |
103 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 104 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
104 | */ | 105 | */ |
105 | #define MX35_X_MEMC_BASE_ADDR 0xb8000000 | 106 | #define MX35_X_MEMC_BASE_ADDR 0xb8000000 |
106 | #define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
107 | #define MX35_X_MEMC_SIZE SZ_64K | 107 | #define MX35_X_MEMC_SIZE SZ_64K |
108 | #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) | 108 | #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) |
109 | #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) | 109 | #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) |
@@ -114,12 +114,8 @@ | |||
114 | #define MX35_NFC_BASE_ADDR 0xbb000000 | 114 | #define MX35_NFC_BASE_ADDR 0xbb000000 |
115 | #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 115 | #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
116 | 116 | ||
117 | #define MX35_IO_ADDRESS(x) ( \ | 117 | #define MX35_IO_P2V(x) IMX_IO_P2V(x) |
118 | IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ | 118 | #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) |
119 | IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ | ||
120 | IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ | ||
121 | IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ | ||
122 | IMX_IO_ADDRESS(x, MX35_SPBA0)) | ||
123 | 119 | ||
124 | /* | 120 | /* |
125 | * Interrupt numbers | 121 | * Interrupt numbers |
@@ -153,8 +149,8 @@ | |||
153 | #define MX35_INT_UART2 32 | 149 | #define MX35_INT_UART2 32 |
154 | #define MX35_INT_NFC 33 | 150 | #define MX35_INT_NFC 33 |
155 | #define MX35_INT_SDMA 34 | 151 | #define MX35_INT_SDMA 34 |
156 | #define MX35_INT_USBHS 35 | 152 | #define MX35_INT_USB_HS 35 |
157 | #define MX35_INT_USBOTG 37 | 153 | #define MX35_INT_USB_OTG 37 |
158 | #define MX35_INT_MSHC1 39 | 154 | #define MX35_INT_MSHC1 39 |
159 | #define MX35_INT_ESAI 40 | 155 | #define MX35_INT_ESAI 40 |
160 | #define MX35_INT_IPU_ERR 41 | 156 | #define MX35_INT_IPU_ERR 41 |
@@ -193,20 +189,4 @@ | |||
193 | #define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 | 189 | #define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 |
194 | #define MX35_SYSTEM_REV_NUM 3 | 190 | #define MX35_SYSTEM_REV_NUM 3 |
195 | 191 | ||
196 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
197 | /* these should go away */ | ||
198 | #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR | ||
199 | #define MXC_INT_OWIRE MX35_INT_OWIRE | ||
200 | #define MXC_INT_GPU2D MX35_INT_GPU2D | ||
201 | #define MXC_INT_ASRC MX35_INT_ASRC | ||
202 | #define MXC_INT_USBHS MX35_INT_USBHS | ||
203 | #define MXC_INT_USBOTG MX35_INT_USBOTG | ||
204 | #define MXC_INT_ESAI MX35_INT_ESAI | ||
205 | #define MXC_INT_CAN1 MX35_INT_CAN1 | ||
206 | #define MXC_INT_CAN2 MX35_INT_CAN2 | ||
207 | #define MXC_INT_MLB MX35_INT_MLB | ||
208 | #define MXC_INT_SPDIF MX35_INT_SPDIF | ||
209 | #define MXC_INT_FEC MX35_INT_FEC | ||
210 | #endif | ||
211 | |||
212 | #endif /* ifndef __MACH_MX35_H__ */ | 192 | #endif /* ifndef __MACH_MX35_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d7b8a6..8c7f34e737d0 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
@@ -44,7 +44,6 @@ | |||
44 | * AIPS 1 | 44 | * AIPS 1 |
45 | */ | 45 | */ |
46 | #define MX3x_AIPS1_BASE_ADDR 0x43f00000 | 46 | #define MX3x_AIPS1_BASE_ADDR 0x43f00000 |
47 | #define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
48 | #define MX3x_AIPS1_SIZE SZ_1M | 47 | #define MX3x_AIPS1_SIZE SZ_1M |
49 | #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) | 48 | #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) |
50 | #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) | 49 | #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) |
@@ -69,7 +68,6 @@ | |||
69 | * SPBA global module enabled #0 | 68 | * SPBA global module enabled #0 |
70 | */ | 69 | */ |
71 | #define MX3x_SPBA0_BASE_ADDR 0x50000000 | 70 | #define MX3x_SPBA0_BASE_ADDR 0x50000000 |
72 | #define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
73 | #define MX3x_SPBA0_SIZE SZ_1M | 71 | #define MX3x_SPBA0_SIZE SZ_1M |
74 | #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) | 72 | #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) |
75 | #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) | 73 | #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) |
@@ -82,7 +80,6 @@ | |||
82 | * AIPS 2 | 80 | * AIPS 2 |
83 | */ | 81 | */ |
84 | #define MX3x_AIPS2_BASE_ADDR 0x53f00000 | 82 | #define MX3x_AIPS2_BASE_ADDR 0x53f00000 |
85 | #define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
86 | #define MX3x_AIPS2_SIZE SZ_1M | 83 | #define MX3x_AIPS2_SIZE SZ_1M |
87 | #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) | 84 | #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) |
88 | #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) | 85 | #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) |
@@ -105,11 +102,9 @@ | |||
105 | * ROMP and AVIC | 102 | * ROMP and AVIC |
106 | */ | 103 | */ |
107 | #define MX3x_ROMP_BASE_ADDR 0x60000000 | 104 | #define MX3x_ROMP_BASE_ADDR 0x60000000 |
108 | #define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 | ||
109 | #define MX3x_ROMP_SIZE SZ_1M | 105 | #define MX3x_ROMP_SIZE SZ_1M |
110 | 106 | ||
111 | #define MX3x_AVIC_BASE_ADDR 0x68000000 | 107 | #define MX3x_AVIC_BASE_ADDR 0x68000000 |
112 | #define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
113 | #define MX3x_AVIC_SIZE SZ_1M | 108 | #define MX3x_AVIC_SIZE SZ_1M |
114 | 109 | ||
115 | /* | 110 | /* |
@@ -125,18 +120,17 @@ | |||
125 | #define MX3x_CS3_BASE_ADDR 0xb2000000 | 120 | #define MX3x_CS3_BASE_ADDR 0xb2000000 |
126 | 121 | ||
127 | #define MX3x_CS4_BASE_ADDR 0xb4000000 | 122 | #define MX3x_CS4_BASE_ADDR 0xb4000000 |
128 | #define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 | 123 | #define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 |
129 | #define MX3x_CS4_SIZE SZ_32M | 124 | #define MX3x_CS4_SIZE SZ_32M |
130 | 125 | ||
131 | #define MX3x_CS5_BASE_ADDR 0xb6000000 | 126 | #define MX3x_CS5_BASE_ADDR 0xb6000000 |
132 | #define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 | 127 | #define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 |
133 | #define MX3x_CS5_SIZE SZ_32M | 128 | #define MX3x_CS5_SIZE SZ_32M |
134 | 129 | ||
135 | /* | 130 | /* |
136 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 131 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
137 | */ | 132 | */ |
138 | #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 | 133 | #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 |
139 | #define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
140 | #define MX3x_X_MEMC_SIZE SZ_64K | 134 | #define MX3x_X_MEMC_SIZE SZ_64K |
141 | #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) | 135 | #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) |
142 | #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) | 136 | #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) |
@@ -146,56 +140,6 @@ | |||
146 | 140 | ||
147 | #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 141 | #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
148 | 142 | ||
149 | /*! | ||
150 | * This macro defines the physical to virtual address mapping for all the | ||
151 | * peripheral modules. It is used by passing in the physical address as x | ||
152 | * and returning the virtual address. If the physical address is not mapped, | ||
153 | * it returns 0xDEADBEEF | ||
154 | */ | ||
155 | #define IO_ADDRESS(x) \ | ||
156 | (void __force __iomem *) \ | ||
157 | (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
158 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
159 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
160 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
161 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
162 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
163 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
164 | 0xDEADBEEF) | ||
165 | |||
166 | /* | ||
167 | * define the address mapping macros: in physical address order | ||
168 | */ | ||
169 | #define L2CC_IO_ADDRESS(x) \ | ||
170 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
171 | |||
172 | #define AIPS1_IO_ADDRESS(x) \ | ||
173 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
174 | |||
175 | #define SPBA0_IO_ADDRESS(x) \ | ||
176 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
177 | |||
178 | #define AIPS2_IO_ADDRESS(x) \ | ||
179 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
180 | |||
181 | #define ROMP_IO_ADDRESS(x) \ | ||
182 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
183 | |||
184 | #define AVIC_IO_ADDRESS(x) \ | ||
185 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
186 | |||
187 | #define CS4_IO_ADDRESS(x) \ | ||
188 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
189 | |||
190 | #define CS5_IO_ADDRESS(x) \ | ||
191 | (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) | ||
192 | |||
193 | #define X_MEMC_IO_ADDRESS(x) \ | ||
194 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
195 | |||
196 | #define PCMCIA_IO_ADDRESS(x) \ | ||
197 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
198 | |||
199 | /* | 143 | /* |
200 | * Interrupt numbers | 144 | * Interrupt numbers |
201 | */ | 145 | */ |
@@ -277,126 +221,4 @@ static inline int mx35_revision(void) | |||
277 | } | 221 | } |
278 | #endif | 222 | #endif |
279 | 223 | ||
280 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
281 | /* these should go away */ | ||
282 | #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR | ||
283 | #define L2CC_SIZE MX3x_L2CC_SIZE | ||
284 | #define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR | ||
285 | #define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT | ||
286 | #define AIPS1_SIZE MX3x_AIPS1_SIZE | ||
287 | #define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR | ||
288 | #define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR | ||
289 | #define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR | ||
290 | #define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR | ||
291 | #define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR | ||
292 | #define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR | ||
293 | #define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR | ||
294 | #define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR | ||
295 | #define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR | ||
296 | #define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR | ||
297 | #define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR | ||
298 | #define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR | ||
299 | #define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR | ||
300 | #define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR | ||
301 | #define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR | ||
302 | #define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR | ||
303 | #define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR | ||
304 | #define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR | ||
305 | #define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR | ||
306 | #define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT | ||
307 | #define SPBA0_SIZE MX3x_SPBA0_SIZE | ||
308 | #define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR | ||
309 | #define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR | ||
310 | #define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR | ||
311 | #define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR | ||
312 | #define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR | ||
313 | #define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR | ||
314 | #define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR | ||
315 | #define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT | ||
316 | #define AIPS2_SIZE MX3x_AIPS2_SIZE | ||
317 | #define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR | ||
318 | #define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR | ||
319 | #define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR | ||
320 | #define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR | ||
321 | #define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR | ||
322 | #define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR | ||
323 | #define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR | ||
324 | #define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR | ||
325 | #define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR | ||
326 | #define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR | ||
327 | #define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR | ||
328 | #define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR | ||
329 | #define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR | ||
330 | #define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR | ||
331 | #define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR | ||
332 | #define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR | ||
333 | #define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR | ||
334 | #define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT | ||
335 | #define ROMP_SIZE MX3x_ROMP_SIZE | ||
336 | #define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR | ||
337 | #define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT | ||
338 | #define AVIC_SIZE MX3x_AVIC_SIZE | ||
339 | #define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR | ||
340 | #define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR | ||
341 | #define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR | ||
342 | #define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR | ||
343 | #define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR | ||
344 | #define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR | ||
345 | #define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR | ||
346 | #define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR | ||
347 | #define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT | ||
348 | #define CS4_SIZE MX3x_CS4_SIZE | ||
349 | #define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR | ||
350 | #define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT | ||
351 | #define CS5_SIZE MX3x_CS5_SIZE | ||
352 | #define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR | ||
353 | #define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT | ||
354 | #define X_MEMC_SIZE MX3x_X_MEMC_SIZE | ||
355 | #define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR | ||
356 | #define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR | ||
357 | #define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR | ||
358 | #define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR | ||
359 | #define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR | ||
360 | #define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR | ||
361 | #define MXC_INT_I2C3 MX3x_INT_I2C3 | ||
362 | #define MXC_INT_I2C2 MX3x_INT_I2C2 | ||
363 | #define MXC_INT_RTIC MX3x_INT_RTIC | ||
364 | #define MXC_INT_I2C MX3x_INT_I2C | ||
365 | #define MXC_INT_CSPI2 MX3x_INT_CSPI2 | ||
366 | #define MXC_INT_CSPI1 MX3x_INT_CSPI1 | ||
367 | #define MXC_INT_ATA MX3x_INT_ATA | ||
368 | #define MXC_INT_UART3 MX3x_INT_UART3 | ||
369 | #define MXC_INT_IIM MX3x_INT_IIM | ||
370 | #define MXC_INT_RNGA MX3x_INT_RNGA | ||
371 | #define MXC_INT_EVTMON MX3x_INT_EVTMON | ||
372 | #define MXC_INT_KPP MX3x_INT_KPP | ||
373 | #define MXC_INT_RTC MX3x_INT_RTC | ||
374 | #define MXC_INT_PWM MX3x_INT_PWM | ||
375 | #define MXC_INT_EPIT2 MX3x_INT_EPIT2 | ||
376 | #define MXC_INT_EPIT1 MX3x_INT_EPIT1 | ||
377 | #define MXC_INT_GPT MX3x_INT_GPT | ||
378 | #define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL | ||
379 | #define MXC_INT_UART2 MX3x_INT_UART2 | ||
380 | #define MXC_INT_NANDFC MX3x_INT_NANDFC | ||
381 | #define MXC_INT_SDMA MX3x_INT_SDMA | ||
382 | #define MXC_INT_MSHC1 MX3x_INT_MSHC1 | ||
383 | #define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR | ||
384 | #define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN | ||
385 | #define MXC_INT_UART1 MX3x_INT_UART1 | ||
386 | #define MXC_INT_ECT MX3x_INT_ECT | ||
387 | #define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM | ||
388 | #define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN | ||
389 | #define MXC_INT_GPIO2 MX3x_INT_GPIO2 | ||
390 | #define MXC_INT_GPIO1 MX3x_INT_GPIO1 | ||
391 | #define MXC_INT_WDOG MX3x_INT_WDOG | ||
392 | #define MXC_INT_GPIO3 MX3x_INT_GPIO3 | ||
393 | #define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER | ||
394 | #define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER | ||
395 | #define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 | ||
396 | #define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 | ||
397 | #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG | ||
398 | #define MXC_INT_EXT_TV MX3x_INT_EXT_TV | ||
399 | #define PROD_SIGNATURE MX3x_PROD_SIGNATURE | ||
400 | #endif | ||
401 | |||
402 | #endif /* ifndef __MACH_MX3x_H__ */ | 224 | #endif /* ifndef __MACH_MX3x_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 2af7a1056fc1..636347c3fa88 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
@@ -2,31 +2,6 @@ | |||
2 | #define __MACH_MX51_H__ | 2 | #define __MACH_MX51_H__ |
3 | 3 | ||
4 | /* | 4 | /* |
5 | * MX51 memory map: | ||
6 | * | ||
7 | * | ||
8 | * Virt Phys Size What | ||
9 | * --------------------------------------------------------------------------- | ||
10 | * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) | ||
11 | * 30000000 256M GPU | ||
12 | * 40000000 512M IPU | ||
13 | * fa200000 60000000 1M DEBUG | ||
14 | * fb100000 70000000 1M SPBA 0 | ||
15 | * fb000000 73f00000 1M AIPS 1 | ||
16 | * fb200000 83f00000 1M AIPS 2 | ||
17 | * 8fffc000 16K TZIC (interrupt controller) | ||
18 | * 90000000 256M CSD0 SDRAM/DDR | ||
19 | * a0000000 256M CSD1 SDRAM/DDR | ||
20 | * b0000000 128M CS0 Flash | ||
21 | * b8000000 128M CS1 Flash | ||
22 | * c0000000 128M CS2 Flash | ||
23 | * c8000000 64M CS3 Flash | ||
24 | * cc000000 32M CS4 SRAM | ||
25 | * ce000000 32M CS5 SRAM | ||
26 | * cfff0000 64K NFC (NAND Flash AXI) | ||
27 | */ | ||
28 | |||
29 | /* | ||
30 | * IROM | 5 | * IROM |
31 | */ | 6 | */ |
32 | #define MX51_IROM_BASE_ADDR 0x0 | 7 | #define MX51_IROM_BASE_ADDR 0x0 |
@@ -36,7 +11,6 @@ | |||
36 | * IRAM | 11 | * IRAM |
37 | */ | 12 | */ |
38 | #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ | 13 | #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ |
39 | #define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 | ||
40 | #define MX51_IRAM_PARTITIONS 16 | 14 | #define MX51_IRAM_PARTITIONS 16 |
41 | #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ | 15 | #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ |
42 | 16 | ||
@@ -45,7 +19,6 @@ | |||
45 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 | 19 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 |
46 | 20 | ||
47 | #define MX51_DEBUG_BASE_ADDR 0x60000000 | 21 | #define MX51_DEBUG_BASE_ADDR 0x60000000 |
48 | #define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 | ||
49 | #define MX51_DEBUG_SIZE SZ_1M | 22 | #define MX51_DEBUG_SIZE SZ_1M |
50 | 23 | ||
51 | #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) | 24 | #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) |
@@ -61,7 +34,6 @@ | |||
61 | * SPBA global module enabled #0 | 34 | * SPBA global module enabled #0 |
62 | */ | 35 | */ |
63 | #define MX51_SPBA0_BASE_ADDR 0x70000000 | 36 | #define MX51_SPBA0_BASE_ADDR 0x70000000 |
64 | #define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 | ||
65 | #define MX51_SPBA0_SIZE SZ_1M | 37 | #define MX51_SPBA0_SIZE SZ_1M |
66 | 38 | ||
67 | #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) | 39 | #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) |
@@ -81,7 +53,6 @@ | |||
81 | * AIPS 1 | 53 | * AIPS 1 |
82 | */ | 54 | */ |
83 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 | 55 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 |
84 | #define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 | ||
85 | #define MX51_AIPS1_SIZE SZ_1M | 56 | #define MX51_AIPS1_SIZE SZ_1M |
86 | 57 | ||
87 | #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) | 58 | #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) |
@@ -109,7 +80,6 @@ | |||
109 | * AIPS 2 | 80 | * AIPS 2 |
110 | */ | 81 | */ |
111 | #define MX51_AIPS2_BASE_ADDR 0x83f00000 | 82 | #define MX51_AIPS2_BASE_ADDR 0x83f00000 |
112 | #define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 | ||
113 | #define MX51_AIPS2_SIZE SZ_1M | 83 | #define MX51_AIPS2_SIZE SZ_1M |
114 | 84 | ||
115 | #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) | 85 | #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) |
@@ -163,16 +133,8 @@ | |||
163 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 | 133 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 |
164 | #define MX51_TZIC_BASE_ADDR 0xe0000000 | 134 | #define MX51_TZIC_BASE_ADDR 0xe0000000 |
165 | 135 | ||
166 | #define MX51_IO_ADDRESS(x) ( \ | 136 | #define MX51_IO_P2V(x) IMX_IO_P2V(x) |
167 | IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ | 137 | #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) |
168 | IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ | ||
169 | IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ | ||
170 | IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ | ||
171 | IMX_IO_ADDRESS(x, MX51_AIPS2)) | ||
172 | |||
173 | /* This is currently used in <mach/debug-macro.S>, but should go away */ | ||
174 | #define MX51_AIPS1_IO_ADDRESS(x) \ | ||
175 | (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) | ||
176 | 138 | ||
177 | /* | 139 | /* |
178 | * defines for SPBA modules | 140 | * defines for SPBA modules |
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101ebf36..765190fe6332 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h | |||
@@ -21,14 +21,12 @@ | |||
21 | * L2CC | 21 | * L2CC |
22 | */ | 22 | */ |
23 | #define MXC91231_L2CC_BASE_ADDR 0x30000000 | 23 | #define MXC91231_L2CC_BASE_ADDR 0x30000000 |
24 | #define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 | ||
25 | #define MXC91231_L2CC_SIZE SZ_64K | 24 | #define MXC91231_L2CC_SIZE SZ_64K |
26 | 25 | ||
27 | /* | 26 | /* |
28 | * AIPS 1 | 27 | * AIPS 1 |
29 | */ | 28 | */ |
30 | #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 | 29 | #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 |
31 | #define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
32 | #define MXC91231_AIPS1_SIZE SZ_1M | 30 | #define MXC91231_AIPS1_SIZE SZ_1M |
33 | 31 | ||
34 | #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR | 32 | #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR |
@@ -53,7 +51,6 @@ | |||
53 | * AIPS 2 | 51 | * AIPS 2 |
54 | */ | 52 | */ |
55 | #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 | 53 | #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 |
56 | #define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 | ||
57 | #define MXC91231_AIPS2_SIZE SZ_1M | 54 | #define MXC91231_AIPS2_SIZE SZ_1M |
58 | 55 | ||
59 | #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) | 56 | #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) |
@@ -79,7 +76,6 @@ | |||
79 | * SPBA global module 0 | 76 | * SPBA global module 0 |
80 | */ | 77 | */ |
81 | #define MXC91231_SPBA0_BASE_ADDR 0x50000000 | 78 | #define MXC91231_SPBA0_BASE_ADDR 0x50000000 |
82 | #define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 | ||
83 | #define MXC91231_SPBA0_SIZE SZ_1M | 79 | #define MXC91231_SPBA0_SIZE SZ_1M |
84 | 80 | ||
85 | #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) | 81 | #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) |
@@ -109,7 +105,6 @@ | |||
109 | * SPBA global module 1 | 105 | * SPBA global module 1 |
110 | */ | 106 | */ |
111 | #define MXC91231_SPBA1_BASE_ADDR 0x52000000 | 107 | #define MXC91231_SPBA1_BASE_ADDR 0x52000000 |
112 | #define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 | ||
113 | #define MXC91231_SPBA1_SIZE SZ_1M | 108 | #define MXC91231_SPBA1_SIZE SZ_1M |
114 | 109 | ||
115 | #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) | 110 | #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) |
@@ -144,18 +139,15 @@ | |||
144 | * ROMP and AVIC | 139 | * ROMP and AVIC |
145 | */ | 140 | */ |
146 | #define MXC91231_ROMP_BASE_ADDR 0x60000000 | 141 | #define MXC91231_ROMP_BASE_ADDR 0x60000000 |
147 | #define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 | ||
148 | #define MXC91231_ROMP_SIZE SZ_64K | 142 | #define MXC91231_ROMP_SIZE SZ_64K |
149 | 143 | ||
150 | #define MXC91231_AVIC_BASE_ADDR 0x68000000 | 144 | #define MXC91231_AVIC_BASE_ADDR 0x68000000 |
151 | #define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 | ||
152 | #define MXC91231_AVIC_SIZE SZ_64K | 145 | #define MXC91231_AVIC_SIZE SZ_64K |
153 | 146 | ||
154 | /* | 147 | /* |
155 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 148 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
156 | */ | 149 | */ |
157 | #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 | 150 | #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 |
158 | #define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 | ||
159 | #define MXC91231_X_MEMC_SIZE SZ_64K | 151 | #define MXC91231_X_MEMC_SIZE SZ_64K |
160 | 152 | ||
161 | #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) | 153 | #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) |
@@ -183,19 +175,10 @@ | |||
183 | /* | 175 | /* |
184 | * This macro defines the physical to virtual address mapping for all the | 176 | * This macro defines the physical to virtual address mapping for all the |
185 | * peripheral modules. It is used by passing in the physical address as x | 177 | * peripheral modules. It is used by passing in the physical address as x |
186 | * and returning the virtual address. If the physical address is not mapped, | 178 | * and returning the virtual address. |
187 | * it returns 0. | ||
188 | */ | 179 | */ |
189 | 180 | #define MXC91231_IO_P2V(x) IMX_IO_P2V(x) | |
190 | #define MXC91231_IO_ADDRESS(x) ( \ | 181 | #define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) |
191 | IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ | ||
192 | IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ | ||
193 | IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ | ||
194 | IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ | ||
195 | IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ | ||
196 | IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ | ||
197 | IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ | ||
198 | IMX_IO_ADDRESS(x, MXC91231_AIPS2)) | ||
199 | 182 | ||
200 | /* | 183 | /* |
201 | * Interrupt numbers | 184 | * Interrupt numbers |