Merge branch 'v6v7' into devel

Conflicts:
	arch/arm/include/asm/cacheflush.h
	arch/arm/include/asm/proc-fns.h
	arch/arm/mm/Kconfig

1 files changed, 29 insertions, 21 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 05b26a03c209..89266382b536 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -390,7 +390,7 @@ config CPU_PJ4
 
 # ARMv6
 config CPU_V6
-        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
+        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
         select CPU_32v6
         select CPU_ABRT_EV6
         select CPU_PABRT_V6
@@ -402,16 +402,18 @@ config CPU_V6
         select CPU_TLB_V6 if MMU
 
 # ARMv6k
-config CPU_32v6K
-        bool "Support ARM V6K processor extensions" if !SMP
-        depends on CPU_V6 || CPU_V7
-        default y if SMP
-        help
-          Say Y here if your ARMv6 processor supports the 'K' extension.
-          This enables the kernel to use some instructions not present
-          on previous processors, and as such a kernel build with this
-          enabled will not boot on processors with do not support these
-          instructions.
+config CPU_V6K
+        bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+        select CPU_32v6
+        select CPU_32v6K
+        select CPU_ABRT_EV6
+        select CPU_PABRT_V6
+        select CPU_CACHE_V6
+        select CPU_CACHE_VIPT
+        select CPU_CP15_MMU
+        select CPU_HAS_ASID if MMU
+        select CPU_COPY_V6 if MMU
+        select CPU_TLB_V6 if MMU
 
 # ARMv7
 config CPU_V7
@@ -433,25 +435,33 @@ config CPU_32v3
         bool
         select TLS_REG_EMUL if SMP || !MMU
         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
+        select CPU_USE_DOMAINS if MMU
 
 config CPU_32v4
         bool
         select TLS_REG_EMUL if SMP || !MMU
         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
+        select CPU_USE_DOMAINS if MMU
 
 config CPU_32v4T
         bool
         select TLS_REG_EMUL if SMP || !MMU
         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
+        select CPU_USE_DOMAINS if MMU
 
 config CPU_32v5
         bool
         select TLS_REG_EMUL if SMP || !MMU
         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
+        select CPU_USE_DOMAINS if MMU
 
 config CPU_32v6
         bool
         select TLS_REG_EMUL if !CPU_32v6K && !MMU
+        select CPU_USE_DOMAINS if CPU_V6 && MMU
+
+config CPU_32v6K
+        bool
 
 config CPU_32v7
         bool
@@ -607,8 +617,6 @@ config CPU_CP15_MPU
 
 config CPU_USE_DOMAINS
         bool
-        depends on MMU
-        default y if !CPU_32v6K
         help
           This option enables or disables the use of domain switching
           via the set_fs() function.
@@ -623,7 +631,7 @@ comment "Processor Features"
 
 config ARM_THUMB
         bool "Support Thumb user binaries"
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
         default y
         help
           Say Y if you want to include kernel support for running user space
@@ -644,7 +652,7 @@ config ARM_THUMBEE
 
 config SWP_EMULATE
         bool "Emulate SWP/SWPB instructions"
-        depends on !CPU_USE_DOMAINS && CPU_V7 && !CPU_V6
+        depends on !CPU_USE_DOMAINS && CPU_V7
         select HAVE_PROC_CPU if PROC_FS
         default y if SMP
         help
@@ -681,7 +689,7 @@ config CPU_BIG_ENDIAN
 config CPU_ENDIAN_BE8
         bool
         depends on CPU_BIG_ENDIAN
-        default CPU_V6 || CPU_V7
+        default CPU_V6 || CPU_V6K || CPU_V7
         help
           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 
@@ -747,7 +755,7 @@ config CPU_CACHE_ROUND_ROBIN
 
 config CPU_BPREDICT_DISABLE
         bool "Disable branch prediction"
-        depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
+        depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
         help
           Say Y here to disable branch prediction.  If unsure, say N.
 
@@ -767,7 +775,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 
 config DMA_CACHE_RWFO
         bool "Enable read/write for ownership DMA cache maintenance"
-        depends on CPU_V6 && SMP
+        depends on CPU_V6K && SMP
         default y
         help
           The Snoop Control Unit on ARM11MPCore does not detect the
@@ -823,7 +831,7 @@ config CACHE_L2X0
 config CACHE_PL310
         bool
         depends on CACHE_L2X0
-        default y if CPU_V7 && !CPU_V6
+        default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
         help
           This option enables optimisations for the PL310 cache
           controller.
@@ -856,10 +864,10 @@ config ARM_L1_CACHE_SHIFT
         default 5
 
 config ARM_DMA_MEM_BUFFERABLE
-        bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+        bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
                      MACH_REALVIEW_PB11MP)
-        default y if CPU_V6 || CPU_V7
+        default y if CPU_V6 || CPU_V6K || CPU_V7
         help
           Historically, the kernel has used strongly ordered mappings to
           provide DMA coherent memory.  With the advent of ARMv7, mapping