28 files changed, 191 insertions, 189 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1fd3f280b584..ababf41517d6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -7,7 +7,7 @@ config ARM
         select HAVE_MEMBLOCK
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
-        select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
+        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
         select HAVE_ARCH_KGDB
         select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
@@ -24,7 +24,7 @@ config ARM
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
         select HAVE_REGS_AND_STACK_ACCESS_API
-        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
+        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
         select HAVE_C_RECORDMCOUNT
         select HAVE_GENERIC_HARDIRQS
         select HAVE_SPARSE_IRQ
@@ -456,6 +456,7 @@ config ARCH_IXP4XX
 
 config ARCH_DOVE
         bool "Marvell Dove"
+        select CPU_V6K
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
@@ -1059,7 +1060,7 @@ config XSCALE_PMU
         default y
 
 config CPU_HAS_PMU
-        depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
+        depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
                    (!ARCH_OMAP3 || OMAP3_EMU)
         default y
         bool
@@ -1075,7 +1076,7 @@ endif
 
 config ARM_ERRATA_411920
         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-        depends on CPU_V6
+        depends on CPU_V6 || CPU_V6K
         help
           Invalidation of the Instruction Cache operation can
           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
@@ -1318,6 +1319,7 @@ source "kernel/time/Kconfig"
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
         depends on EXPERIMENTAL
+        depends on CPU_V6K || CPU_V7
         depends on GENERIC_CLOCKEVENTS
         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
                  MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
@@ -1429,7 +1431,7 @@ config HZ
 
 config THUMB2_KERNEL
         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
-        depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
+        depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
         select AEABI
         select ARM_ASM_UNIFIED
         help
@@ -1963,7 +1965,7 @@ config FPE_FASTFPE
 
 config VFP
         bool "VFP-format floating point maths"
-        depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
+        depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
         help
           Say Y to include VFP support code in the kernel. This is needed
           if your hardware includes a VFP unit.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 55eca9ed7604..1e20c414d5cf 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -89,6 +89,7 @@ tune-$(CONFIG_CPU_XSCALE)	:=$(call cc-option,-mtune=xscale,-mtune=strongarm110)
 tune-$(CONFIG_CPU_XSC3)         :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
 tune-$(CONFIG_CPU_FEROCEON)     :=$(call cc-option,-mtune=marvell-f,-mtune=xscale)
 tune-$(CONFIG_CPU_V6)           :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_V6K)          :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
 
 ifeq ($(CONFIG_AEABI),y)
 CFLAGS_ABI      :=-mabi=aapcs-linux -mno-thumb-interwork
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 39859216af00..84ac4d656310 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -21,7 +21,7 @@
 
 #if defined(CONFIG_DEBUG_ICEDCC)
 
-#ifdef CONFIG_CPU_V6
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
                 .macro  loadsp, rb, tmp
                 .endm
                 .macro  writeb, ch, rb
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index e653a6d3c8d9..4657e877bf8f 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -36,7 +36,7 @@ extern void error(char *x);
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
-#ifdef CONFIG_CPU_V6
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
 
 static void icedcc_putc(int ch)
 {
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 7b1bb2bbaf88..af54ed102f5f 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -149,14 +149,18 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
  */
 
 /*
+ * Native endian assembly bitops.  nr = 0 -> word 0 bit 0.
+ */
+extern void _set_bit(int nr, volatile unsigned long * p);
+extern void _clear_bit(int nr, volatile unsigned long * p);
+extern void _change_bit(int nr, volatile unsigned long * p);
+extern int _test_and_set_bit(int nr, volatile unsigned long * p);
+extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
+extern int _test_and_change_bit(int nr, volatile unsigned long * p);
+
+/*
  * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.
  */
-extern void _set_bit_le(int nr, volatile unsigned long * p);
-extern void _clear_bit_le(int nr, volatile unsigned long * p);
-extern void _change_bit_le(int nr, volatile unsigned long * p);
-extern int _test_and_set_bit_le(int nr, volatile unsigned long * p);
-extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p);
-extern int _test_and_change_bit_le(int nr, volatile unsigned long * p);
 extern int _find_first_zero_bit_le(const void * p, unsigned size);