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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-03 17:31:24 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-03 17:31:24 -0400
commitbe82ae0238b0453afcf4a76f0512b7dde34ba500 (patch)
treeaaa3f5f11fd51fd73365ee1a2164aad9a03de060 /arch/arm/mach-ux500/include/mach
parent4b4fd27c0b5ec638a1f06ced9226fd95229dbbf0 (diff)
parent7b70c4275f28702b76b273c8534c38f8313812e9 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits) ARM: AMBA: Add pclk support to AMBA bus infrastructure ARM: 6278/2: fix regression in RealView after the introduction of pclk ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128 ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY ARM: 6246/1: mmci: support larger MMCIDATALENGTH register ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants ARM: 6244/1: mmci: add variant data and default MCICLOCK support ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback ARM: 6274/1: add global control registers definition header file for nuc900 mx2_camera: fix type of dma buffer virtual address pointer mx2_camera: Add soc_camera support for i.MX25/i.MX27 arm/imx/gpio: add spinlock protection ARM: Add support for the LPC32XX arch ARM: LPC32XX: Arch config menu supoport and makefiles ARM: LPC32XX: Phytec 3250 platform support ARM: LPC32XX: Misc support functions ARM: LPC32XX: Serial support code ARM: LPC32XX: System suspend support ARM: LPC32XX: GPIO, timer, and IRQ drivers ARM: LPC32XX: Clock driver ...
Diffstat (limited to 'arch/arm/mach-ux500/include/mach')
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h23
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h85
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db8500.h96
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h22
4 files changed, 220 insertions, 6 deletions
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
new file mode 100644
index 000000000000..cca4f705601e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_BOARD_MOP500_H
9#define __MACH_IRQS_BOARD_MOP500_H
10
11#define AB8500_NR_IRQS 104
12
13#define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START
14#define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \
15 + AB8500_NR_IRQS)
16#define MOP500_IRQ_END MOP500_AB8500_IRQ_END
17
18#if MOP500_IRQ_END > IRQ_BOARD_END
19#undef IRQ_BOARD_END
20#define IRQ_BOARD_END MOP500_IRQ_END
21#endif
22
23#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644
index 000000000000..6fbfe5e2065a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB5500_H
9#define __MACH_IRQS_DB5500_H
10
11#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
14#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
23#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
36#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
37#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
38#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
39#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
40#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
41#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
42#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
43#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
44#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
45#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
46#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
50#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
55#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
56#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
57#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
58#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
59#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
60#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
65#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
66#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
67#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
68#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
69#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
70#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
71#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
72#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
73#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
74#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
75#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
76#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
77#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
78#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
79#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
80#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
81#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
82#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
83#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
84
85#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
new file mode 100644
index 000000000000..8b5d9f0a1633
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB8500_H
9#define __MACH_IRQS_DB8500_H
10
11#define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB8500_PMU (IRQ_SHPI_START + 7)
14#define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB8500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB8500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16)
23#define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB8500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB8500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29)
36#define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31)
37#define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
38#define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
39#define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
40#define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
41#define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36)
42#define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37)
43#define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38)
44#define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39)
45#define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40)
46#define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB8500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB8500_SVA (IRQ_SHPI_START + 44)
50#define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB8500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49)
55#define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50)
56#define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51)
57#define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52)
58#define IRQ_DB8500_SKE (IRQ_SHPI_START + 53)
59#define IRQ_DB8500_KB (IRQ_SHPI_START + 54)
60#define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55)
61#define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56)
62#define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57)
63#define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59)
64#define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60)
65#define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61)
66#define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62)
67#define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63)
68#define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96)
69#define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97)
70#define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98)
71#define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99)
72#define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100)
73#define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104)
74#define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105)
75#define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106)
76#define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107)
77#define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108)
78#define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109)
79#define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110)
80#define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112)
81#define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113)
82#define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114)
83#define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115)
84#define IRQ_DB8500_MALI (IRQ_SHPI_START + 116)
85#define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118)
86#define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119)
87#define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120)
88#define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121)
89#define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122)
90#define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123)
91#define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124)
92#define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125)
93#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
94#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
95
96#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7970684b1d09..10385bdc2b77 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,7 +10,8 @@
10#ifndef ASM_ARCH_IRQS_H 10#ifndef ASM_ARCH_IRQS_H
11#define ASM_ARCH_IRQS_H 11#define ASM_ARCH_IRQS_H
12 12
13#include <mach/hardware.h> 13#include <mach/irqs-db5500.h>
14#include <mach/irqs-db8500.h>
14 15
15#define IRQ_LOCALTIMER 29 16#define IRQ_LOCALTIMER 29
16#define IRQ_LOCALWDOG 30 17#define IRQ_LOCALWDOG 30
@@ -67,12 +68,21 @@
67/* There are 128 shared peripheral interrupts assigned to 68/* There are 128 shared peripheral interrupts assigned to
68 * INTID[160:32]. The first 32 interrupts are reserved. 69 * INTID[160:32]. The first 32 interrupts are reserved.
69 */ 70 */
70#define U8500_SOC_NR_IRQS 161 71#define DBX500_NR_INTERNAL_IRQS 161
71 72
72/* After chip-specific IRQ numbers we have the GPIO ones */ 73/* After chip-specific IRQ numbers we have the GPIO ones */
73#define NOMADIK_NR_GPIO 288 74#define NOMADIK_NR_GPIO 288
74#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS) 75#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS)
75#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS) 76#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS)
76#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) 77#define IRQ_BOARD_START NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
77 78
78#endif /*ASM_ARCH_IRQS_H*/ 79/* This will be overridden by board-specific irq headers */
80#define IRQ_BOARD_END IRQ_BOARD_START
81
82#ifdef CONFIG_MACH_U8500_MOP
83#include <mach/irqs-board-mop500.h>
84#endif
85
86#define NR_IRQS IRQ_BOARD_END
87
88#endif /* ASM_ARCH_IRQS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 21:08:08 -0500