diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-02 11:56:55 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-02 11:56:55 -0400 |
commit | 4d26aa305414dbb33b3c32fb205b68004cda8ffc (patch) | |
tree | 78da855745406afc870ea3454e584907f7cccb73 /arch/arm/mach-tegra | |
parent | 600fe9751aeb6f6b72de84076a05c5b8c04152c0 (diff) | |
parent | e74fc973b6e531fef1fce8b101ffff05ecfb774c (diff) |
Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC non-critical fixes from Olof Johansson:
"Here is a collection of fixes (and some intermixed cleanups) that were
considered less important and thus not included in the later parts of
the 3.9-rc cycle.
It's a bit all over the map, contents wise. A series of ux500 fixes
and cleanups, a bunch of various fixes for OMAP and tegra, and some
for Freescale i.MX and even Qualcomm MSM.
Note that there's also a patch on this branch to globally turn off
-Wmaybe-uninitialized when building with -Os. It's been posted
several times by Arnd and no dissent was raised, but nobody seemed
interested to pick it up. So here it is, as the topmost patch."
* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
Turn off -Wmaybe-uninitialized when building with -Os
ARM: orion5x: include linux/cpu.h
ARM: tegra: call cpu_do_idle from C code
ARM: u300: fix ages old copy/paste bug
ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled
ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
ARM: tegra: fix build error when THUMB2_KERNEL enabled
ARM: msm: Fix uncompess.h tx underrun check
ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms
ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: mach-imx: mach-imx6q: Fix sparse warnings
ARM: mach-imx: src: Include "common.h
ARM: mach-imx: gpc: Include "common.h"
ARM: mach-imx: avic: Staticize *avic_base
ARM: mach-imx: tzic: Staticize *tzic_base
ARM: mach-imx: clk: Include "clk.h"
ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
...
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r-- | arch/arm/mach-tegra/board-harmony-pcie.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-tegra/cpuidle-tegra30.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 3 | ||||
-rw-r--r-- | arch/arm/mach-tegra/platsmp.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pm.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-tegra/powergate.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 49 | ||||
-rw-r--r-- | arch/arm/mach-tegra/sleep-tegra20.S | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/sleep-tegra30.S | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/sleep.h | 2 |
10 files changed, 63 insertions, 41 deletions
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 3cdc1bb8254c..d195db09ea32 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c | |||
@@ -62,7 +62,11 @@ int __init harmony_pcie_init(void) | |||
62 | goto err_reg; | 62 | goto err_reg; |
63 | } | 63 | } |
64 | 64 | ||
65 | regulator_enable(regulator); | 65 | err = regulator_enable(regulator); |
66 | if (err) { | ||
67 | pr_err("%s: regulator_enable failed: %d\n", __func__, err); | ||
68 | goto err_en; | ||
69 | } | ||
66 | 70 | ||
67 | err = tegra_pcie_init(true, true); | 71 | err = tegra_pcie_init(true, true); |
68 | if (err) { | 72 | if (err) { |
@@ -74,6 +78,7 @@ int __init harmony_pcie_init(void) | |||
74 | 78 | ||
75 | err_pcie: | 79 | err_pcie: |
76 | regulator_disable(regulator); | 80 | regulator_disable(regulator); |
81 | err_en: | ||
77 | regulator_put(regulator); | 82 | regulator_put(regulator); |
78 | err_reg: | 83 | err_reg: |
79 | gpio_free(en_vdd_1v05); | 84 | gpio_free(en_vdd_1v05); |
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index 36dc2befa9d8..9387daeeadc8 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c | |||
@@ -99,12 +99,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, | |||
99 | 99 | ||
100 | smp_wmb(); | 100 | smp_wmb(); |
101 | 101 | ||
102 | save_cpu_arch_register(); | ||
103 | |||
104 | cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); | 102 | cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); |
105 | 103 | ||
106 | restore_cpu_arch_register(); | ||
107 | |||
108 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); | 104 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); |
109 | 105 | ||
110 | return true; | 106 | return true; |
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index fd473f2b4c3d..045c16f2dd51 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S | |||
@@ -7,8 +7,5 @@ | |||
7 | 7 | ||
8 | ENTRY(tegra_secondary_startup) | 8 | ENTRY(tegra_secondary_startup) |
9 | bl v7_invalidate_l1 | 9 | bl v7_invalidate_l1 |
10 | /* Enable coresight */ | ||
11 | mov32 r0, 0xC5ACCE55 | ||
12 | mcr p14, 0, r0, c7, c12, 6 | ||
13 | b secondary_startup | 10 | b secondary_startup |
14 | ENDPROC(tegra_secondary_startup) | 11 | ENDPROC(tegra_secondary_startup) |
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 2c6b3d55213b..e78d52d83acd 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
@@ -91,7 +91,7 @@ static int tegra30_power_up_cpu(unsigned int cpu) | |||
91 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { | 91 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { |
92 | timeout = jiffies + msecs_to_jiffies(50); | 92 | timeout = jiffies + msecs_to_jiffies(50); |
93 | do { | 93 | do { |
94 | if (!tegra_powergate_is_powered(pwrgateid)) | 94 | if (tegra_powergate_is_powered(pwrgateid)) |
95 | goto remove_clamps; | 95 | goto remove_clamps; |
96 | udelay(10); | 96 | udelay(10); |
97 | } while (time_before(jiffies, timeout)); | 97 | } while (time_before(jiffies, timeout)); |
@@ -124,6 +124,9 @@ remove_clamps: | |||
124 | 124 | ||
125 | /* Remove I/O clamps. */ | 125 | /* Remove I/O clamps. */ |
126 | ret = tegra_powergate_remove_clamping(pwrgateid); | 126 | ret = tegra_powergate_remove_clamping(pwrgateid); |
127 | if (ret) | ||
128 | return ret; | ||
129 | |||
127 | udelay(10); | 130 | udelay(10); |
128 | 131 | ||
129 | /* Clear flow controller CSR. */ | 132 | /* Clear flow controller CSR. */ |
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 523604de666f..04a8e06f59a9 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
@@ -46,26 +46,11 @@ | |||
46 | #define PMC_CPUPWROFF_TIMER 0xcc | 46 | #define PMC_CPUPWROFF_TIMER 0xcc |
47 | 47 | ||
48 | #ifdef CONFIG_PM_SLEEP | 48 | #ifdef CONFIG_PM_SLEEP |
49 | static unsigned int g_diag_reg; | ||
50 | static DEFINE_SPINLOCK(tegra_lp2_lock); | 49 | static DEFINE_SPINLOCK(tegra_lp2_lock); |
51 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | 50 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); |
52 | static struct clk *tegra_pclk; | 51 | static struct clk *tegra_pclk; |
53 | void (*tegra_tear_down_cpu)(void); | 52 | void (*tegra_tear_down_cpu)(void); |
54 | 53 | ||
55 | void save_cpu_arch_register(void) | ||
56 | { | ||
57 | /* read diagnostic register */ | ||
58 | asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); | ||
59 | return; | ||
60 | } | ||
61 | |||
62 | void restore_cpu_arch_register(void) | ||
63 | { | ||
64 | /* write diagnostic register */ | ||
65 | asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); | ||
66 | return; | ||
67 | } | ||
68 | |||
69 | static void set_power_timers(unsigned long us_on, unsigned long us_off) | 54 | static void set_power_timers(unsigned long us_on, unsigned long us_off) |
70 | { | 55 | { |
71 | unsigned long long ticks; | 56 | unsigned long long ticks; |
@@ -119,8 +104,6 @@ static void restore_cpu_complex(void) | |||
119 | tegra_cpu_clock_resume(); | 104 | tegra_cpu_clock_resume(); |
120 | 105 | ||
121 | flowctrl_cpu_suspend_exit(cpu); | 106 | flowctrl_cpu_suspend_exit(cpu); |
122 | |||
123 | restore_cpu_arch_register(); | ||
124 | } | 107 | } |
125 | 108 | ||
126 | /* | 109 | /* |
@@ -145,8 +128,6 @@ static void suspend_cpu_complex(void) | |||
145 | tegra_cpu_clock_suspend(); | 128 | tegra_cpu_clock_suspend(); |
146 | 129 | ||
147 | flowctrl_cpu_suspend_enter(cpu); | 130 | flowctrl_cpu_suspend_enter(cpu); |
148 | |||
149 | save_cpu_arch_register(); | ||
150 | } | 131 | } |
151 | 132 | ||
152 | void tegra_clear_cpu_in_lp2(int phy_cpu_id) | 133 | void tegra_clear_cpu_in_lp2(int phy_cpu_id) |
@@ -181,6 +162,11 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id) | |||
181 | return last_cpu; | 162 | return last_cpu; |
182 | } | 163 | } |
183 | 164 | ||
165 | int tegra_cpu_do_idle(void) | ||
166 | { | ||
167 | return cpu_do_idle(); | ||
168 | } | ||
169 | |||
184 | static int tegra_sleep_cpu(unsigned long v2p) | 170 | static int tegra_sleep_cpu(unsigned long v2p) |
185 | { | 171 | { |
186 | /* Switch to the identity mapping. */ | 172 | /* Switch to the identity mapping. */ |
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index c6bc8f85759c..af9067e2867c 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/debugfs.h> | 22 | #include <linux/debugfs.h> |
23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
24 | #include <linux/err.h> | 24 | #include <linux/err.h> |
25 | #include <linux/export.h> | ||
25 | #include <linux/init.h> | 26 | #include <linux/init.h> |
26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
27 | #include <linux/seq_file.h> | 28 | #include <linux/seq_file.h> |
@@ -75,7 +76,7 @@ static int tegra_powergate_set(int id, bool new_state) | |||
75 | 76 | ||
76 | if (status == new_state) { | 77 | if (status == new_state) { |
77 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); | 78 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); |
78 | return -EINVAL; | 79 | return 0; |
79 | } | 80 | } |
80 | 81 | ||
81 | pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); | 82 | pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); |
@@ -168,6 +169,7 @@ err_clk: | |||
168 | err_power: | 169 | err_power: |
169 | return ret; | 170 | return ret; |
170 | } | 171 | } |
172 | EXPORT_SYMBOL(tegra_powergate_sequence_power_up); | ||
171 | 173 | ||
172 | int tegra_cpu_powergate_id(int cpuid) | 174 | int tegra_cpu_powergate_id(int cpuid) |
173 | { | 175 | { |
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 54382ceade4a..e6de88a2ea06 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S | |||
@@ -41,12 +41,10 @@ | |||
41 | */ | 41 | */ |
42 | ENTRY(tegra_resume) | 42 | ENTRY(tegra_resume) |
43 | bl v7_invalidate_l1 | 43 | bl v7_invalidate_l1 |
44 | /* Enable coresight */ | ||
45 | mov32 r0, 0xC5ACCE55 | ||
46 | mcr p14, 0, r0, c7, c12, 6 | ||
47 | 44 | ||
48 | cpu_id r0 | 45 | cpu_id r0 |
49 | cmp r0, #0 @ CPU0? | 46 | cmp r0, #0 @ CPU0? |
47 | THUMB( it ne ) | ||
50 | bne cpu_resume @ no | 48 | bne cpu_resume @ no |
51 | 49 | ||
52 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | 50 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
@@ -99,6 +97,8 @@ ENTRY(__tegra_cpu_reset_handler_start) | |||
99 | * | 97 | * |
100 | * Register usage within the reset handler: | 98 | * Register usage within the reset handler: |
101 | * | 99 | * |
100 | * Others: scratch | ||
101 | * R6 = SoC ID << 8 | ||
102 | * R7 = CPU present (to the OS) mask | 102 | * R7 = CPU present (to the OS) mask |
103 | * R8 = CPU in LP1 state mask | 103 | * R8 = CPU in LP1 state mask |
104 | * R9 = CPU in LP2 state mask | 104 | * R9 = CPU in LP2 state mask |
@@ -114,6 +114,40 @@ ENTRY(__tegra_cpu_reset_handler_start) | |||
114 | ENTRY(__tegra_cpu_reset_handler) | 114 | ENTRY(__tegra_cpu_reset_handler) |
115 | 115 | ||
116 | cpsid aif, 0x13 @ SVC mode, interrupts disabled | 116 | cpsid aif, 0x13 @ SVC mode, interrupts disabled |
117 | |||
118 | mov32 r6, TEGRA_APB_MISC_BASE | ||
119 | ldr r6, [r6, #APB_MISC_GP_HIDREV] | ||
120 | and r6, r6, #0xff00 | ||
121 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
122 | t20_check: | ||
123 | cmp r6, #(0x20 << 8) | ||
124 | bne after_t20_check | ||
125 | t20_errata: | ||
126 | # Tegra20 is a Cortex-A9 r1p1 | ||
127 | mrc p15, 0, r0, c1, c0, 0 @ read system control register | ||
128 | orr r0, r0, #1 << 14 @ erratum 716044 | ||
129 | mcr p15, 0, r0, c1, c0, 0 @ write system control register | ||
130 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register | ||
131 | orr r0, r0, #1 << 4 @ erratum 742230 | ||
132 | orr r0, r0, #1 << 11 @ erratum 751472 | ||
133 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register | ||
134 | b after_errata | ||
135 | after_t20_check: | ||
136 | #endif | ||
137 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | ||
138 | t30_check: | ||
139 | cmp r6, #(0x30 << 8) | ||
140 | bne after_t30_check | ||
141 | t30_errata: | ||
142 | # Tegra30 is a Cortex-A9 r2p9 | ||
143 | mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register | ||
144 | orr r0, r0, #1 << 6 @ erratum 743622 | ||
145 | orr r0, r0, #1 << 11 @ erratum 751472 | ||
146 | mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register | ||
147 | b after_errata | ||
148 | after_t30_check: | ||
149 | #endif | ||
150 | after_errata: | ||
117 | mrc p15, 0, r10, c0, c0, 5 @ MPIDR | 151 | mrc p15, 0, r10, c0, c0, 5 @ MPIDR |
118 | and r10, r10, #0x3 @ R10 = CPU number | 152 | and r10, r10, #0x3 @ R10 = CPU number |
119 | mov r11, #1 | 153 | mov r11, #1 |
@@ -129,16 +163,13 @@ ENTRY(__tegra_cpu_reset_handler) | |||
129 | 163 | ||
130 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 164 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
131 | /* Are we on Tegra20? */ | 165 | /* Are we on Tegra20? */ |
132 | mov32 r6, TEGRA_APB_MISC_BASE | 166 | cmp r6, #(0x20 << 8) |
133 | ldr r0, [r6, #APB_MISC_GP_HIDREV] | ||
134 | and r0, r0, #0xff00 | ||
135 | cmp r0, #(0x20 << 8) | ||
136 | bne 1f | 167 | bne 1f |
137 | /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ | 168 | /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ |
138 | mov32 r6, TEGRA_PMC_BASE | 169 | mov32 r5, TEGRA_PMC_BASE |
139 | mov r0, #0 | 170 | mov r0, #0 |
140 | cmp r10, #0 | 171 | cmp r10, #0 |
141 | strne r0, [r6, #PMC_SCRATCH41] | 172 | strne r0, [r5, #PMC_SCRATCH41] |
142 | 1: | 173 | 1: |
143 | #endif | 174 | #endif |
144 | 175 | ||
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 9f6bfafdd512..e3f2417c420e 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S | |||
@@ -197,7 +197,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish) | |||
197 | mov r3, #CPU_RESETTABLE | 197 | mov r3, #CPU_RESETTABLE |
198 | str r3, [r0] | 198 | str r3, [r0] |
199 | 199 | ||
200 | bl cpu_do_idle | 200 | bl tegra_cpu_do_idle |
201 | 201 | ||
202 | /* | 202 | /* |
203 | * cpu may be reset while in wfi, which will return through | 203 | * cpu may be reset while in wfi, which will return through |
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 63a15bd9b653..d29dfcce948d 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S | |||
@@ -66,7 +66,9 @@ ENTRY(tegra30_cpu_shutdown) | |||
66 | FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ | 66 | FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ |
67 | FLOW_CTRL_CSR_ENABLE | 67 | FLOW_CTRL_CSR_ENABLE |
68 | mov r4, #(1 << 4) | 68 | mov r4, #(1 << 4) |
69 | orr r12, r12, r4, lsl r3 | 69 | ARM( orr r12, r12, r4, lsl r3 ) |
70 | THUMB( lsl r4, r4, r3 ) | ||
71 | THUMB( orr r12, r12, r4 ) | ||
70 | str r12, [r1] | 72 | str r12, [r1] |
71 | 73 | ||
72 | /* Halt this CPU. */ | 74 | /* Halt this CPU. */ |
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 4ffae541726e..bb308eab9079 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h | |||
@@ -92,7 +92,7 @@ | |||
92 | 92 | ||
93 | #ifdef CONFIG_CACHE_L2X0 | 93 | #ifdef CONFIG_CACHE_L2X0 |
94 | .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs | 94 | .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs |
95 | adr \tmp1, \phys_l2x0_saved_regs | 95 | W(adr) \tmp1, \phys_l2x0_saved_regs |
96 | ldr \tmp1, [\tmp1] | 96 | ldr \tmp1, [\tmp1] |
97 | ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] | 97 | ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] |
98 | ldr \tmp3, [\tmp2, #L2X0_CTRL] | 98 | ldr \tmp3, [\tmp2, #L2X0_CTRL] |