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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 11:56:55 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 11:56:55 -0400
commit4d26aa305414dbb33b3c32fb205b68004cda8ffc (patch)
tree78da855745406afc870ea3454e584907f7cccb73 /arch/arm
parent600fe9751aeb6f6b72de84076a05c5b8c04152c0 (diff)
parente74fc973b6e531fef1fce8b101ffff05ecfb774c (diff)
Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC non-critical fixes from Olof Johansson: "Here is a collection of fixes (and some intermixed cleanups) that were considered less important and thus not included in the later parts of the 3.9-rc cycle. It's a bit all over the map, contents wise. A series of ux500 fixes and cleanups, a bunch of various fixes for OMAP and tegra, and some for Freescale i.MX and even Qualcomm MSM. Note that there's also a patch on this branch to globally turn off -Wmaybe-uninitialized when building with -Os. It's been posted several times by Arnd and no dissent was raised, but nobody seemed interested to pick it up. So here it is, as the topmost patch." * tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits) Turn off -Wmaybe-uninitialized when building with -Os ARM: orion5x: include linux/cpu.h ARM: tegra: call cpu_do_idle from C code ARM: u300: fix ages old copy/paste bug ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7 ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled ARM: tegra: fix build error when THUMB2_KERNEL enabled ARM: msm: Fix uncompess.h tx underrun check ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" ARM: mach-imx: mach-imx6q: Fix sparse warnings ARM: mach-imx: src: Include "common.h ARM: mach-imx: gpc: Include "common.h" ARM: mach-imx: avic: Staticize *avic_base ARM: mach-imx: tzic: Staticize *tzic_base ARM: mach-imx: clk: Include "clk.h" ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi7
-rw-r--r--arch/arm/boot/dts/href.dtsi1
-rw-r--r--arch/arm/boot/dts/hrefprev60.dts10
-rw-r--r--arch/arm/boot/dts/snowball.dts4
-rw-r--r--arch/arm/boot/dts/stuib.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts1
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts2
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi2
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts2
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts2
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts2
-rw-r--r--arch/arm/mach-cns3xxx/core.c10
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h27
-rw-r--r--arch/arm/mach-imx/avic.c2
-rw-r--r--arch/arm/mach-imx/clk-busy.c2
-rw-r--r--arch/arm/mach-imx/clk-gate2.c1
-rw-r--r--arch/arm/mach-imx/clk-pllv1.c2
-rw-r--r--arch/arm/mach-imx/clk-pllv2.c2
-rw-r--r--arch/arm/mach-imx/clk.c1
-rw-r--r--arch/arm/mach-imx/cpu-imx5.c1
-rw-r--r--arch/arm/mach-imx/cpu.c1
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c4
-rw-r--r--arch/arm/mach-imx/gpc.c1
-rw-r--r--arch/arm/mach-imx/iomux-imx31.c2
-rw-r--r--arch/arm/mach-imx/irq-common.c19
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c4
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c4
-rw-r--r--arch/arm/mach-imx/mm-imx3.c2
-rw-r--r--arch/arm/mach-imx/src.c1
-rw-r--r--arch/arm/mach-imx/tzic.c2
-rw-r--r--arch/arm/mach-msm/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-omap1/Kconfig6
-rw-r--r--arch/arm/mach-omap2/Kconfig7
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c8
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c30
-rw-r--r--arch/arm/mach-omap2/dsp.c4
-rw-r--r--arch/arm/mach-omap2/id.c12
-rw-r--r--arch/arm/mach-omap2/io.c9
-rw-r--r--arch/arm/mach-omap2/omap4-common.c10
-rw-r--r--arch/arm/mach-omap2/omap4-sar-layout.h14
-rw-r--r--arch/arm/mach-omap2/omap54xx.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c15
-rw-r--r--arch/arm/mach-omap2/powerdomain.c18
-rw-r--r--arch/arm/mach-omap2/prm44xx.c6
-rw-r--r--arch/arm/mach-omap2/soc.h2
-rw-r--r--arch/arm/mach-omap2/timer.c5
-rw-r--r--arch/arm/mach-orion5x/common.c1
-rw-r--r--arch/arm/mach-tegra/board-harmony-pcie.c7
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra30.c4
-rw-r--r--arch/arm/mach-tegra/headsmp.S3
-rw-r--r--arch/arm/mach-tegra/platsmp.c5
-rw-r--r--arch/arm/mach-tegra/pm.c24
-rw-r--r--arch/arm/mach-tegra/powergate.c4
-rw-r--r--arch/arm/mach-tegra/reset-handler.S49
-rw-r--r--arch/arm/mach-tegra/sleep-tegra20.S2
-rw-r--r--arch/arm/mach-tegra/sleep-tegra30.S4
-rw-r--r--arch/arm/mach-tegra/sleep.h2
-rw-r--r--arch/arm/mach-u300/include/mach/u300-regs.h2
-rw-r--r--arch/arm/mach-ux500/board-mop500-regulators.c14
-rw-r--r--arch/arm/mach-ux500/board-mop500-regulators.h1
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c51
-rw-r--r--arch/arm/mach-ux500/board-mop500.c45
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c1
74 files changed, 279 insertions, 242 deletions
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index aaa63d0a8096..b6bc4ff17f26 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -191,7 +191,7 @@
191 191
192 prcmu: prcmu@80157000 { 192 prcmu: prcmu@80157000 {
193 compatible = "stericsson,db8500-prcmu"; 193 compatible = "stericsson,db8500-prcmu";
194 reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; 194 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
195 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; 195 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
196 interrupts = <0 47 0x4>; 196 interrupts = <0 47 0x4>;
197 #address-cells = <1>; 197 #address-cells = <1>;
@@ -674,10 +674,13 @@
674 compatible = "regulator-gpio"; 674 compatible = "regulator-gpio";
675 675
676 regulator-min-microvolt = <1800000>; 676 regulator-min-microvolt = <1800000>;
677 regulator-max-microvolt = <2600000>; 677 regulator-max-microvolt = <2900000>;
678 regulator-name = "mmci-reg"; 678 regulator-name = "mmci-reg";
679 regulator-type = "voltage"; 679 regulator-type = "voltage";
680 680
681 startup-delay-us = <100>;
682 enable-active-high;
683
681 states = <1800000 0x1 684 states = <1800000 0x1
682 2900000 0x0>; 685 2900000 0x0>;
683 686
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index 379128eb9d98..c0bc426952ea 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -87,6 +87,7 @@
87 mmc-cap-sd-highspeed; 87 mmc-cap-sd-highspeed;
88 mmc-cap-mmc-highspeed; 88 mmc-cap-mmc-highspeed;
89 vmmc-supply = <&ab8500_ldo_aux3_reg>; 89 vmmc-supply = <&ab8500_ldo_aux3_reg>;
90 vqmmc-supply = <&vmmci>;
90 91
91 cd-gpios = <&tc3589x_gpio 3 0x4>; 92 cd-gpios = <&tc3589x_gpio 3 0x4>;
92 93
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
index eec29c4a86dc..c2d274815923 100644
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -25,6 +25,14 @@
25 }; 25 };
26 26
27 soc-u9500 { 27 soc-u9500 {
28 prcmu@80157000 {
29 ab8500@5 {
30 ab8500-gpio {
31 compatible = "stericsson,ab8500-gpio";
32 };
33 };
34 };
35
28 i2c@80004000 { 36 i2c@80004000 {
29 tps61052@33 { 37 tps61052@33 {
30 compatible = "tps61052"; 38 compatible = "tps61052";
@@ -40,7 +48,7 @@
40 48
41 vmmci: regulator-gpio { 49 vmmci: regulator-gpio {
42 gpios = <&tc3589x_gpio 18 0x4>; 50 gpios = <&tc3589x_gpio 18 0x4>;
43 gpio-enable = <&tc3589x_gpio 17 0x4>; 51 enable-gpio = <&tc3589x_gpio 17 0x4>;
44 52
45 status = "okay"; 53 status = "okay";
46 }; 54 };
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index d3ec32f6b790..db5db24fd544 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -299,6 +299,10 @@
299 }; 299 };
300 300
301 ab8500 { 301 ab8500 {
302 ab8500-gpio {
303 compatible = "stericsson,ab8500-gpio";
304 };
305
302 ab8500-regulators { 306 ab8500-regulators {
303 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 307 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
304 regulator-name = "V-DISPLAY"; 308 regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 39446a247e79..615392a75676 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -15,7 +15,7 @@
15 stmpe1601: stmpe1601@40 { 15 stmpe1601: stmpe1601@40 {
16 compatible = "st,stmpe1601"; 16 compatible = "st,stmpe1601";
17 reg = <0x40>; 17 reg = <0x40>;
18 interrupts = <26 0x1>; 18 interrupts = <26 0x2>;
19 interrupt-parent = <&gpio6>; 19 interrupt-parent = <&gpio6>;
20 interrupt-controller; 20 interrupt-controller;
21 21
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 444162090042..cb73e62d61a9 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -444,7 +444,7 @@
444 }; 444 };
445 445
446 sdhci@c8000600 { 446 sdhci@c8000600 {
447 cd-gpios = <&gpio 23 0>; /* gpio PC7 */ 447 cd-gpios = <&gpio 23 1>; /* gpio PC7 */
448 }; 448 };
449 449
450 sound { 450 sound {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d027f03617..1f79c0debb05 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -437,7 +437,7 @@
437 437
438 sdhci@c8000200 { 438 sdhci@c8000200 {
439 status = "okay"; 439 status = "okay";
440 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 440 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
441 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 441 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
442 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 442 power-gpios = <&gpio 155 0>; /* gpio PT3 */
443 bus-width = <4>; 443 bus-width = <4>;
@@ -445,7 +445,7 @@
445 445
446 sdhci@c8000600 { 446 sdhci@c8000600 {
447 status = "okay"; 447 status = "okay";
448 cd-gpios = <&gpio 58 0>; /* gpio PH2 */ 448 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
449 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 449 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
450 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 450 power-gpios = <&gpio 70 0>; /* gpio PI6 */
451 bus-width = <8>; 451 bus-width = <8>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54d6fce00a59..9db36da8e023 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -436,7 +436,7 @@
436 436
437 sdhci@c8000000 { 437 sdhci@c8000000 {
438 status = "okay"; 438 status = "okay";
439 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 439 cd-gpios = <&gpio 173 1>; /* gpio PV5 */
440 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 440 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
441 power-gpios = <&gpio 169 0>; /* gpio PV1 */ 441 power-gpios = <&gpio 169 0>; /* gpio PV1 */
442 bus-width = <4>; 442 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 37b3a57ec0f1..715a8b8dd9cd 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -584,7 +584,7 @@
584 584
585 sdhci@c8000400 { 585 sdhci@c8000400 {
586 status = "okay"; 586 status = "okay";
587 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 587 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
588 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 588 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
589 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 589 power-gpios = <&gpio 70 0>; /* gpio PI6 */
590 bus-width = <4>; 590 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4766abae7a72..6e9d91fc6195 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -465,7 +465,7 @@
465 }; 465 };
466 466
467 sdhci@c8000600 { 467 sdhci@c8000600 {
468 cd-gpios = <&gpio 58 0>; /* gpio PH2 */ 468 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
469 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 469 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
470 bus-width = <4>; 470 bus-width = <4>;
471 status = "okay"; 471 status = "okay";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 5d79e4fc49a6..98f3e44f2a51 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -325,7 +325,7 @@
325 325
326 sdhci@c8000600 { 326 sdhci@c8000600 {
327 status = "okay"; 327 status = "okay";
328 cd-gpios = <&gpio 121 0>; /* gpio PP1 */ 328 cd-gpios = <&gpio 121 1>; /* gpio PP1 */
329 wp-gpios = <&gpio 122 0>; /* gpio PP2 */ 329 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
330 bus-width = <4>; 330 bus-width = <4>;
331 }; 331 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 425c89000c20..4aef56f2d96a 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -520,7 +520,7 @@
520 520
521 sdhci@c8000400 { 521 sdhci@c8000400 {
522 status = "okay"; 522 status = "okay";
523 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 523 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
524 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 524 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
525 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 525 power-gpios = <&gpio 70 0>; /* gpio PI6 */
526 bus-width = <4>; 526 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index ea57c0f6dcce..5762188c60ad 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -510,6 +510,7 @@
510 510
511 sdhci@c8000400 { 511 sdhci@c8000400 {
512 status = "okay"; 512 status = "okay";
513 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
513 wp-gpios = <&gpio 173 0>; /* gpio PV5 */ 514 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
514 bus-width = <8>; 515 bus-width = <8>;
515 }; 516 };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 8ff2ff20e4a3..0a2cd24df853 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -257,7 +257,7 @@
257 257
258 sdhci@78000000 { 258 sdhci@78000000 {
259 status = "okay"; 259 status = "okay";
260 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 260 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
261 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 261 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
262 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 262 power-gpios = <&gpio 31 0>; /* gpio PD7 */
263 bus-width = <4>; 263 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 17499272a4ef..3e2d21018a5b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -311,7 +311,7 @@
311 311
312 sdhci@78000000 { 312 sdhci@78000000 {
313 status = "okay"; 313 status = "okay";
314 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 314 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
315 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 315 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
316 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 316 power-gpios = <&gpio 31 0>; /* gpio PD7 */
317 bus-width = <4>; 317 bus-width = <4>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 73187173117c..9420053acc14 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -117,7 +117,7 @@
117 }; 117 };
118 118
119 pmu { 119 pmu {
120 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 120 compatible = "arm,cortex-a15-pmu";
121 interrupts = <0 68 4>, 121 interrupts = <0 68 4>,
122 <0 69 4>; 122 <0 69 4>;
123 }; 123 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index dfe371ec2749..d2803be4e1a8 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -134,7 +134,7 @@
134 }; 134 };
135 135
136 pmu { 136 pmu {
137 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 137 compatible = "arm,cortex-a15-pmu";
138 interrupts = <0 68 4>, 138 interrupts = <0 68 4>,
139 <0 69 4>; 139 <0 69 4>;
140 }; 140 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 6328cbc71d30..c544a5504591 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -111,7 +111,7 @@
111 }; 111 };
112 112
113 pmu { 113 pmu {
114 compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; 114 compatible = "arm,cortex-a5-pmu";
115 interrupts = <0 68 4>, 115 interrupts = <0 68 4>,
116 <0 69 4>; 116 <0 69 4>;
117 }; 117 };
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 52e4bb5cf12d..126f74f6087c 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -32,16 +32,6 @@ static struct map_desc cns3xxx_io_desc[] __initdata = {
32 .length = SZ_4K, 32 .length = SZ_4K,
33 .type = MT_DEVICE, 33 .type = MT_DEVICE,
34 }, { 34 }, {
35 .virtual = CNS3XXX_GPIOA_BASE_VIRT,
36 .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
37 .length = SZ_4K,
38 .type = MT_DEVICE,
39 }, {
40 .virtual = CNS3XXX_GPIOB_BASE_VIRT,
41 .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
42 .length = SZ_4K,
43 .type = MT_DEVICE,
44 }, {
45 .virtual = CNS3XXX_MISC_BASE_VIRT, 35 .virtual = CNS3XXX_MISC_BASE_VIRT,
46 .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), 36 .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
47 .length = SZ_4K, 37 .length = SZ_4K,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index b1021aafa481..9b145b1e48ea 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -20,22 +20,16 @@
20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ 20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
21 21
22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ 22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
23#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
24 23
25#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ 24#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
26#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
27 25
28#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ 26#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
29#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
30 27
31#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ 28#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
32#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
33 29
34#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ 30#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
35#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
36 31
37#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ 32#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
38#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
39 33
40#define SMC_MEMC_STATUS_OFFSET 0x000 34#define SMC_MEMC_STATUS_OFFSET 0x000
41#define SMC_MEMIF_CFG_OFFSET 0x004 35#define SMC_MEMIF_CFG_OFFSET 0x004
@@ -74,13 +68,10 @@
74#define SMC_PCELL_ID_3_OFFSET 0xFFC 68#define SMC_PCELL_ID_3_OFFSET 0xFFC
75 69
76#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ 70#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
77#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
78 71
79#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ 72#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
80#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
81 73
82#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ 74#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
83#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
84 75
85#define RTC_SEC_OFFSET 0x00 76#define RTC_SEC_OFFSET 0x00
86#define RTC_MIN_OFFSET 0x04 77#define RTC_MIN_OFFSET 0x04
@@ -112,22 +103,16 @@
112#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 103#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
113 104
114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ 105#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
116 106
117#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ 107#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
118#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
119 108
120#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ 109#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
121#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
122 110
123#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ 111#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
124#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
125 112
126#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ 113#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
127#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
128 114
129#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ 115#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
131 116
132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ 117#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 118#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
@@ -150,42 +135,31 @@
150#define TIMER_FREERUN_CONTROL_OFFSET 0x44 135#define TIMER_FREERUN_CONTROL_OFFSET 0x44
151 136
152#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ 137#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
153#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
154 138
155#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ 139#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
156#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
157 140
158#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ 141#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
159#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
160 142
161#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ 143#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
162#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
163 144
164#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ 145#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
165#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
166 146
167#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ 147#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
168 148
169#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ 149#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
170#define CNS3XXX_SATA2_SIZE SZ_16M 150#define CNS3XXX_SATA2_SIZE SZ_16M
171#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
172 151
173#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ 152#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
174#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
175 153
176#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ 154#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
177#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
178 155
179#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ 156#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
180#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
181 157
182#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ 158#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
183#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
184 159
185#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ 160#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
186 161
187#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ 162#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
188#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
189 163
190#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ 164#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
191#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 165#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
@@ -239,7 +213,6 @@
239#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) 213#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
240 214
241#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ 215#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
242#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
243 216
244/* 217/*
245 * Misc block 218 * Misc block
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 0eff23ed92b9..9c3e014705b1 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -51,7 +51,7 @@
51 51
52#define AVIC_NUM_IRQS 64 52#define AVIC_NUM_IRQS 64
53 53
54void __iomem *avic_base; 54static void __iomem *avic_base;
55static struct irq_domain *domain; 55static struct irq_domain *domain;
56 56
57static u32 avic_saved_mask_reg[2]; 57static u32 avic_saved_mask_reg[2];
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
index 85b728cc27ab..4bb1bc419b79 100644
--- a/arch/arm/mach-imx/clk-busy.c
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -147,7 +147,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
147 return ret; 147 return ret;
148} 148}
149 149
150struct clk_ops clk_busy_mux_ops = { 150static struct clk_ops clk_busy_mux_ops = {
151 .get_parent = clk_busy_mux_get_parent, 151 .get_parent = clk_busy_mux_get_parent,
152 .set_parent = clk_busy_mux_set_parent, 152 .set_parent = clk_busy_mux_set_parent,
153}; 153};
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index cc49c7ae186e..a63e415609a8 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -15,6 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/string.h> 17#include <linux/string.h>
18#include "clk.h"
18 19
19/** 20/**
20 * DOC: basic gatable clock which can gate and ungate it's ouput 21 * DOC: basic gatable clock which can gate and ungate it's ouput
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index abff350ba24c..c1eaee346954 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -78,7 +78,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
78 return ll; 78 return ll;
79} 79}
80 80
81struct clk_ops clk_pllv1_ops = { 81static struct clk_ops clk_pllv1_ops = {
82 .recalc_rate = clk_pllv1_recalc_rate, 82 .recalc_rate = clk_pllv1_recalc_rate,
83}; 83};
84 84
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
index 0440379e3628..20889d59b44d 100644
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -229,7 +229,7 @@ static void clk_pllv2_unprepare(struct clk_hw *hw)
229 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); 229 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
230} 230}
231 231
232struct clk_ops clk_pllv2_ops = { 232static struct clk_ops clk_pllv2_ops = {
233 .prepare = clk_pllv2_prepare, 233 .prepare = clk_pllv2_prepare,
234 .unprepare = clk_pllv2_unprepare, 234 .unprepare = clk_pllv2_unprepare,
235 .recalc_rate = clk_pllv2_recalc_rate, 235 .recalc_rate = clk_pllv2_recalc_rate,
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index f5e8be8e7f11..37e884ed1cd4 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,3 +1,4 @@
1#include <linux/spinlock.h> 1#include <linux/spinlock.h>
2#include "clk.h"
2 3
3DEFINE_SPINLOCK(imx_ccm_lock); 4DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index d7ce72252a4e..c1c99a72c6a1 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -18,6 +18,7 @@
18#include <linux/io.h> 18#include <linux/io.h>
19 19
20#include "hardware.h" 20#include "hardware.h"
21#include "common.h"
21 22
22static int mx5_cpu_rev = -1; 23static int mx5_cpu_rev = -1;
23 24
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 03fcbd082593..e70e3acbf9bd 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -3,6 +3,7 @@
3#include <linux/io.h> 3#include <linux/io.h>
4 4
5#include "hardware.h" 5#include "hardware.h"
6#include "common.h"
6 7
7unsigned int __mxc_cpu_type; 8unsigned int __mxc_cpu_type;
8EXPORT_SYMBOL(__mxc_cpu_type); 9EXPORT_SYMBOL(__mxc_cpu_type);
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index b4c70028d359..b2f08bfbbdd3 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -46,7 +46,7 @@ static const int eukrea_mbimx27_pins[] __initconst = {
46 PE10_PF_UART3_CTS, 46 PE10_PF_UART3_CTS,
47 PE11_PF_UART3_RTS, 47 PE11_PF_UART3_RTS,
48 /* UART4 */ 48 /* UART4 */
49#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) 49#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
50 PB26_AF_UART4_RTS, 50 PB26_AF_UART4_RTS,
51 PB28_AF_UART4_TXD, 51 PB28_AF_UART4_TXD,
52 PB29_AF_UART4_CTS, 52 PB29_AF_UART4_CTS,
@@ -306,7 +306,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
306 306
307 imx27_add_imx_uart1(&uart_pdata); 307 imx27_add_imx_uart1(&uart_pdata);
308 imx27_add_imx_uart2(&uart_pdata); 308 imx27_add_imx_uart2(&uart_pdata);
309#if !defined(MACH_EUKREA_CPUIMX27_USEUART4) 309#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
310 imx27_add_imx_uart3(&uart_pdata); 310 imx27_add_imx_uart3(&uart_pdata);
311#endif 311#endif
312 312
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index a96ccc7f5012..02b61cdf39b9 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -16,6 +16,7 @@
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/of_irq.h> 17#include <linux/of_irq.h>
18#include <linux/irqchip/arm-gic.h> 18#include <linux/irqchip/arm-gic.h>
19#include "common.h"
19 20
20#define GPC_IMR1 0x008 21#define GPC_IMR1 0x008
21#define GPC_PGC_CPU_PDN 0x2a0 22#define GPC_PGC_CPU_PDN 0x2a0
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index cabefbc5e7c1..7c66805d2cc0 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -40,7 +40,7 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
40 40
41#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) 41#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
42 42
43unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; 43static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
44/* 44/*
45 * set the mode for a IOMUX pin. 45 * set the mode for a IOMUX pin.
46 */ 46 */
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index b6e11458e5ae..4b34f52dc46b 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -21,25 +21,6 @@
21 21
22#include "irq-common.h" 22#include "irq-common.h"
23 23
24int imx_irq_set_priority(unsigned char irq, unsigned char prio)
25{
26 struct irq_chip_generic *gc;
27 struct mxc_extra_irq *exirq;
28 int ret;
29
30 ret = -ENOSYS;
31
32 gc = irq_get_chip_data(irq);
33 if (gc && gc->private) {
34 exirq = gc->private;
35 if (exirq->set_priority)
36 ret = exirq->set_priority(irq, prio);
37 }
38
39 return ret;
40}
41EXPORT_SYMBOL(imx_irq_set_priority);
42
43int mxc_set_irq_fiq(unsigned int irq, unsigned int type) 24int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
44{ 25{
45 struct irq_chip_generic *gc; 26 struct irq_chip_generic *gc;
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 146559311bd2..ea50870bda80 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -48,7 +48,7 @@ static const int eukrea_cpuimx27_pins[] __initconst = {
48 PE14_PF_UART1_CTS, 48 PE14_PF_UART1_CTS,
49 PE15_PF_UART1_RTS, 49 PE15_PF_UART1_RTS,
50 /* UART4 */ 50 /* UART4 */
51#if defined(MACH_EUKREA_CPUIMX27_USEUART4) 51#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
52 PB26_AF_UART4_RTS, 52 PB26_AF_UART4_RTS,
53 PB28_AF_UART4_TXD, 53 PB28_AF_UART4_TXD,
54 PB29_AF_UART4_CTS, 54 PB29_AF_UART4_CTS,
@@ -272,7 +272,7 @@ static void __init eukrea_cpuimx27_init(void)
272 /* SDHC2 can be used for Wifi */ 272 /* SDHC2 can be used for Wifi */
273 imx27_add_mxc_mmc(1, NULL); 273 imx27_add_mxc_mmc(1, NULL);
274#endif 274#endif
275#if defined(MACH_EUKREA_CPUIMX27_USEUART4) 275#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
276 /* in which case UART4 is also used for Bluetooth */ 276 /* in which case UART4 is also used for Bluetooth */
277 imx27_add_imx_uart3(&uart_pdata); 277 imx27_add_imx_uart3(&uart_pdata);
278#endif 278#endif
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103b27e4..fe1b7aafabdc 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -73,7 +73,7 @@ static int imx6q_revision(void)
73 } 73 }
74} 74}
75 75
76void imx6q_restart(char mode, const char *cmd) 76static void imx6q_restart(char mode, const char *cmd)
77{ 77{
78 struct device_node *np; 78 struct device_node *np;
79 void __iomem *wdog_base; 79 void __iomem *wdog_base;
@@ -256,7 +256,7 @@ put_node:
256 of_node_put(np); 256 of_node_put(np);
257} 257}
258 258
259struct platform_device imx6q_cpufreq_pdev = { 259static struct platform_device imx6q_cpufreq_pdev = {
260 .name = "imx6q-cpufreq", 260 .name = "imx6q-cpufreq",
261}; 261};
262 262
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index cefa047c4053..e0e69a682174 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -82,7 +82,7 @@ static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
82 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 82 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
83} 83}
84 84
85void __init imx3_init_l2x0(void) 85static void __init imx3_init_l2x0(void)
86{ 86{
87#ifdef CONFIG_CACHE_L2X0 87#ifdef CONFIG_CACHE_L2X0
88 void __iomem *l2x0_base; 88 void __iomem *l2x0_base;
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 09a742f8c7ab..324731c2a441 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -16,6 +16,7 @@
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <asm/smp_plat.h> 18#include <asm/smp_plat.h>
19#include "common.h"
19 20
20#define SRC_SCR 0x000 21#define SRC_SCR 0x000
21#define SRC_GPR1 0x020 22#define SRC_GPR1 0x020
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 9721161f208f..8183178d5aa3 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -49,7 +49,7 @@
49#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ 49#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
50#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ 50#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
51 51
52void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ 52static void __iomem *tzic_base;
53static struct irq_domain *domain; 53static struct irq_domain *domain;
54 54
55#define TZIC_NUM_IRQS 128 55#define TZIC_NUM_IRQS 128
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index fa97a10d8695..94324870fb04 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -37,7 +37,7 @@ static void putc(int c)
37 * Wait for TX_READY to be set; but skip it if we have a 37 * Wait for TX_READY to be set; but skip it if we have a
38 * TX underrun. 38 * TX underrun.
39 */ 39 */
40 if (UART_DM_SR & 0x08) 40 if (!(UART_DM_SR & 0x08))
41 while (!(UART_DM_ISR & 0x80)) 41 while (!(UART_DM_ISR & 0x80))
42 cpu_relax(); 42 cpu_relax();
43 43
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 903da8eb886c..cdd05f2e67ee 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -55,12 +55,6 @@ config MACH_OMAP_H3
55 TI OMAP 1710 H3 board support. Say Y here if you have such 55 TI OMAP 1710 H3 board support. Say Y here if you have such
56 a board. 56 a board.
57 57
58config MACH_OMAP_HTCWIZARD
59 bool "HTC Wizard"
60 depends on ARCH_OMAP850
61 help
62 HTC Wizard smartphone support (AKA QTEK 9100, ...)
63
64config MACH_HERALD 58config MACH_HERALD
65 bool "HTC Herald" 59 bool "HTC Herald"
66 depends on ARCH_OMAP850 60 depends on ARCH_OMAP850
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8111cd9ff3e5..4dc34ae6a857 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -55,6 +55,7 @@ config SOC_HAS_REALTIME_COUNTER
55config ARCH_OMAP2 55config ARCH_OMAP2
56 bool "TI OMAP2" 56 bool "TI OMAP2"
57 depends on ARCH_OMAP2PLUS 57 depends on ARCH_OMAP2PLUS
58 depends on ARCH_MULTI_V6
58 default y 59 default y
59 select CPU_V6 60 select CPU_V6
60 select MULTI_IRQ_HANDLER 61 select MULTI_IRQ_HANDLER
@@ -64,6 +65,7 @@ config ARCH_OMAP2
64config ARCH_OMAP3 65config ARCH_OMAP3
65 bool "TI OMAP3" 66 bool "TI OMAP3"
66 depends on ARCH_OMAP2PLUS 67 depends on ARCH_OMAP2PLUS
68 depends on ARCH_MULTI_V7
67 default y 69 default y
68 select ARCH_HAS_OPP 70 select ARCH_HAS_OPP
69 select ARM_CPU_SUSPEND if PM 71 select ARM_CPU_SUSPEND if PM
@@ -80,6 +82,7 @@ config ARCH_OMAP4
80 bool "TI OMAP4" 82 bool "TI OMAP4"
81 default y 83 default y
82 depends on ARCH_OMAP2PLUS 84 depends on ARCH_OMAP2PLUS
85 depends on ARCH_MULTI_V7
83 select ARCH_HAS_OPP 86 select ARCH_HAS_OPP
84 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 87 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
85 select ARM_CPU_SUSPEND if PM 88 select ARM_CPU_SUSPEND if PM
@@ -99,6 +102,7 @@ config ARCH_OMAP4
99 102
100config SOC_OMAP5 103config SOC_OMAP5
101 bool "TI OMAP5" 104 bool "TI OMAP5"
105 depends on ARCH_MULTI_V7
102 select ARM_CPU_SUSPEND if PM 106 select ARM_CPU_SUSPEND if PM
103 select ARM_GIC 107 select ARM_GIC
104 select CPU_V7 108 select CPU_V7
@@ -135,6 +139,7 @@ config SOC_TI81XX
135 139
136config SOC_AM33XX 140config SOC_AM33XX
137 bool "AM33XX support" 141 bool "AM33XX support"
142 depends on ARCH_MULTI_V7
138 default y 143 default y
139 select ARM_CPU_SUSPEND if PM 144 select ARM_CPU_SUSPEND if PM
140 select CPU_V7 145 select CPU_V7
@@ -408,7 +413,7 @@ config OMAP3_SDRC_AC_TIMING
408 413
409config OMAP4_ERRATA_I688 414config OMAP4_ERRATA_I688
410 bool "OMAP4 errata: Async Bridge Corruption" 415 bool "OMAP4 errata: Async Bridge Corruption"
411 depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM 416 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
412 select ARCH_HAS_BARRIERS 417 select ARCH_HAS_BARRIERS
413 help 418 help
414 If a data is stalled inside asynchronous bridge because of back 419 If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a3e0aaa4886b..cb0596b631cf 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void)
166 omap_display_init(&sdp2430_dss_data); 166 omap_display_init(&sdp2430_dss_data);
167} 167}
168 168
169#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) 169#if IS_ENABLED(CONFIG_SMC91X)
170 170
171static struct omap_smc91x_platform_data board_smc91x_data = { 171static struct omap_smc91x_platform_data board_smc91x_data = {
172 .cs = 5, 172 .cs = 5,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 812c829fa46f..5b4ec51c385f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void)
246 return 0; 246 return 0;
247} 247}
248 248
249#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) 249#if IS_ENABLED(CONFIG_SMC91X)
250 250
251static struct omap_smc91x_platform_data board_smc91x_data = { 251static struct omap_smc91x_platform_data board_smc91x_data = {
252 .cs = 1, 252 .cs = 1,
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..7f091c85384e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -958,6 +958,14 @@ int __init am33xx_clk_init(void)
958 958
959 clk_set_parent(&timer3_fck, &sys_clkin_ck); 959 clk_set_parent(&timer3_fck, &sys_clkin_ck);
960 clk_set_parent(&timer6_fck, &sys_clkin_ck); 960 clk_set_parent(&timer6_fck, &sys_clkin_ck);
961 /*
962 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
963 * the design/spec, so as a result, for example, timer which supposed
964 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
965 * not expected by any use-case, so change WDT1 clock source to PRCM
966 * 32KHz clock.
967 */
968 clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
961 969
962 return 0; 970 return 0;
963} 971}
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3aed4b0b9563..3a0296cfcace 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
307 _omap3_noncore_dpll_bypass(clk); 307 _omap3_noncore_dpll_bypass(clk);
308 308
309 /* 309 /*
310 * Set jitter correction. No jitter correction for OMAP4 and 3630 310 * Set jitter correction. Jitter correction applicable for OMAP343X
311 * since freqsel field is no longer present 311 * only since freqsel field is no longer present on other devices.
312 */ 312 */
313 if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { 313 if (cpu_is_omap343x()) {
314 v = __raw_readl(dd->control_reg); 314 v = __raw_readl(dd->control_reg);
315 v &= ~dd->freqsel_mask; 315 v &= ~dd->freqsel_mask;
316 v |= freqsel << __ffs(dd->freqsel_mask); 316 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -480,29 +480,30 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
480 if (!dd) 480 if (!dd)
481 return -EINVAL; 481 return -EINVAL;
482 482
483 __clk_prepare(dd->clk_bypass);
484 clk_enable(dd->clk_bypass);
485 __clk_prepare(dd->clk_ref);
486 clk_enable(dd->clk_ref);
487
488 if (__clk_get_rate(dd->clk_bypass) == rate && 483 if (__clk_get_rate(dd->clk_bypass) == rate &&
489 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 484 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
490 pr_debug("%s: %s: set rate: entering bypass.\n", 485 pr_debug("%s: %s: set rate: entering bypass.\n",
491 __func__, __clk_get_name(hw->clk)); 486 __func__, __clk_get_name(hw->clk));
492 487
488 __clk_prepare(dd->clk_bypass);
489 clk_enable(dd->clk_bypass);
493 ret = _omap3_noncore_dpll_bypass(clk); 490 ret = _omap3_noncore_dpll_bypass(clk);
494 if (!ret) 491 if (!ret)
495 new_parent = dd->clk_bypass; 492 new_parent = dd->clk_bypass;
493 clk_disable(dd->clk_bypass);
494 __clk_unprepare(dd->clk_bypass);
496 } else { 495 } else {
496 __clk_prepare(dd->clk_ref);
497 clk_enable(dd->clk_ref);
498
497 if (dd->last_rounded_rate != rate) 499 if (dd->last_rounded_rate != rate)
498 rate = __clk_round_rate(hw->clk, rate); 500 rate = __clk_round_rate(hw->clk, rate);
499 501
500 if (dd->last_rounded_rate == 0) 502 if (dd->last_rounded_rate == 0)
501 return -EINVAL; 503 return -EINVAL;
502 504
503 /* No freqsel on AM335x, OMAP4 and OMAP3630 */ 505 /* Freqsel is available only on OMAP343X devices */
504 if (!soc_is_am33xx() && !cpu_is_omap44xx() && 506 if (cpu_is_omap343x()) {
505 !cpu_is_omap3630()) {
506 freqsel = _omap3_dpll_compute_freqsel(clk, 507 freqsel = _omap3_dpll_compute_freqsel(clk,
507 dd->last_rounded_n); 508 dd->last_rounded_n);
508 WARN_ON(!freqsel); 509 WARN_ON(!freqsel);
@@ -514,6 +515,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
514 ret = omap3_noncore_dpll_program(clk, freqsel); 515 ret = omap3_noncore_dpll_program(clk, freqsel);
515 if (!ret) 516 if (!ret)
516 new_parent = dd->clk_ref; 517 new_parent = dd->clk_ref;
518 clk_disable(dd->clk_ref);
519 __clk_unprepare(dd->clk_ref);
517 } 520 }
518 /* 521 /*
519 * FIXME - this is all wrong. common code handles reparenting and 522 * FIXME - this is all wrong. common code handles reparenting and
@@ -525,11 +528,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
525 if (!ret) 528 if (!ret)
526 __clk_reparent(hw->clk, new_parent); 529 __clk_reparent(hw->clk, new_parent);
527 530
528 clk_disable(dd->clk_ref);
529 __clk_unprepare(dd->clk_ref);
530 clk_disable(dd->clk_bypass);
531 __clk_unprepare(dd->clk_bypass);
532
533 return 0; 531 return 0;
534} 532}
535 533
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index b155500e84a8..b8208b4b1bd9 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -26,7 +26,7 @@
26#include "control.h" 26#include "control.h"
27#include "cm2xxx_3xxx.h" 27#include "cm2xxx_3xxx.h"
28#include "prm2xxx_3xxx.h" 28#include "prm2xxx_3xxx.h"
29#ifdef CONFIG_BRIDGE_DVFS 29#ifdef CONFIG_TIDSPBRIDGE_DVFS
30#include "omap-pm.h" 30#include "omap-pm.h"
31#endif 31#endif
32 32
@@ -35,7 +35,7 @@
35static struct platform_device *omap_dsp_pdev; 35static struct platform_device *omap_dsp_pdev;
36 36
37static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { 37static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
38#ifdef CONFIG_BRIDGE_DVFS 38#ifdef CONFIG_TIDSPBRIDGE_DVFS
39 .dsp_set_min_opp = omap_pm_dsp_set_min_opp, 39 .dsp_set_min_opp = omap_pm_dsp_set_min_opp,
40 .dsp_get_opp = omap_pm_dsp_get_opp, 40 .dsp_get_opp = omap_pm_dsp_get_opp,
41 .cpu_set_freq = omap_pm_cpu_set_freq, 41 .cpu_set_freq = omap_pm_cpu_set_freq,
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8a68f1ec66b9..ff0bc9e51aa7 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -529,22 +529,28 @@ void __init omap5xxx_check_revision(void)
529 case 0xb942: 529 case 0xb942:
530 switch (rev) { 530 switch (rev) {
531 case 0: 531 case 0:
532 default:
533 omap_revision = OMAP5430_REV_ES1_0; 532 omap_revision = OMAP5430_REV_ES1_0;
533 break;
534 case 1:
535 default:
536 omap_revision = OMAP5430_REV_ES2_0;
534 } 537 }
535 break; 538 break;
536 539
537 case 0xb998: 540 case 0xb998:
538 switch (rev) { 541 switch (rev) {
539 case 0: 542 case 0:
540 default:
541 omap_revision = OMAP5432_REV_ES1_0; 543 omap_revision = OMAP5432_REV_ES1_0;
544 break;
545 case 1:
546 default:
547 omap_revision = OMAP5432_REV_ES2_0;
542 } 548 }
543 break; 549 break;
544 550
545 default: 551 default:
546 /* Unknown default to latest silicon rev as default*/ 552 /* Unknown default to latest silicon rev as default*/
547 omap_revision = OMAP5430_REV_ES1_0; 553 omap_revision = OMAP5430_REV_ES2_0;
548 } 554 }
549 555
550 pr_info("OMAP%04x ES%d.0\n", 556 pr_info("OMAP%04x ES%d.0\n",
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5c445ca1e271..e210fa830f8d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -277,6 +277,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
277 .length = L4_PER_54XX_SIZE, 277 .length = L4_PER_54XX_SIZE,
278 .type = MT_DEVICE, 278 .type = MT_DEVICE,
279 }, 279 },
280#ifdef CONFIG_OMAP4_ERRATA_I688
281 {
282 .virtual = OMAP4_SRAM_VA,
283 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
284 .length = PAGE_SIZE,
285 .type = MT_MEMORY_SO,
286 },
287#endif
280}; 288};
281#endif 289#endif
282 290
@@ -329,6 +337,7 @@ void __init omap4_map_io(void)
329void __init omap5_map_io(void) 337void __init omap5_map_io(void)
330{ 338{
331 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
340 omap_barriers_init();
332} 341}
333#endif 342#endif
334/* 343/*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 708bb115a27f..2aeb928efdfd 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -240,15 +240,21 @@ void __iomem *omap4_get_sar_ram_base(void)
240 */ 240 */
241static int __init omap4_sar_ram_init(void) 241static int __init omap4_sar_ram_init(void)
242{ 242{
243 unsigned long sar_base;
244
243 /* 245 /*
244 * To avoid code running on other OMAPs in 246 * To avoid code running on other OMAPs in
245 * multi-omap builds 247 * multi-omap builds
246 */ 248 */
247 if (!cpu_is_omap44xx()) 249 if (cpu_is_omap44xx())
250 sar_base = OMAP44XX_SAR_RAM_BASE;
251 else if (soc_is_omap54xx())
252 sar_base = OMAP54XX_SAR_RAM_BASE;
253 else
248 return -ENOMEM; 254 return -ENOMEM;
249 255
250 /* Static mapping, never released */ 256 /* Static mapping, never released */
251 sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); 257 sar_ram_base = ioremap(sar_base, SZ_16K);
252 if (WARN_ON(!sar_ram_base)) 258 if (WARN_ON(!sar_ram_base))
253 return -ENOMEM; 259 return -ENOMEM;
254 260
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index e170fe803b04..937417523b8e 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -48,13 +48,13 @@
48#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 48#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
49 49
50/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ 50/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
51#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) 51#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc)
52#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) 52#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0)
53#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) 53#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04)
54#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) 54#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18)
55#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) 55#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c)
56#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) 56#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930)
57#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) 57#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34)
58#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) 58#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
59 59
60#endif 60#endif
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a2582bb3cab3..a086ba15868b 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -28,5 +28,6 @@
28#define OMAP54XX_PRCM_MPU_BASE 0x48243000 28#define OMAP54XX_PRCM_MPU_BASE 0x48243000
29#define OMAP54XX_SCM_BASE 0x4a002000 29#define OMAP54XX_SCM_BASE 0x4a002000
30#define OMAP54XX_CTRL_BASE 0x4a002800 30#define OMAP54XX_CTRL_BASE 0x4a002800
31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
31 32
32#endif /* __ASM_SOC_OMAP555554XX_H */ 33#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index e512253601c8..9553c9907d40 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -611,8 +611,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
611 611
612 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 612 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
613 613
614 oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
615
616 return 0; 614 return 0;
617} 615}
618 616
@@ -646,8 +644,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
646 644
647 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 645 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
648 646
649 oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
650
651 return 0; 647 return 0;
652} 648}
653 649
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d5dc935f6060..fe5962921f07 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -482,15 +482,13 @@ struct omap_hwmod_omap4_prcm {
482 * These are for internal use only and are managed by the omap_hwmod code. 482 * These are for internal use only and are managed by the omap_hwmod code.
483 * 483 *
484 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module 484 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
485 * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
486 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached 485 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
487 * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - 486 * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
488 * causes the first call to _enable() to only update the pinmux 487 * causes the first call to _enable() to only update the pinmux
489 */ 488 */
490#define _HWMOD_NO_MPU_PORT (1 << 0) 489#define _HWMOD_NO_MPU_PORT (1 << 0)
491#define _HWMOD_WAKEUP_ENABLED (1 << 1) 490#define _HWMOD_SYSCONFIG_LOADED (1 << 1)
492#define _HWMOD_SYSCONFIG_LOADED (1 << 2) 491#define _HWMOD_SKIP_ENABLE (1 << 2)
493#define _HWMOD_SKIP_ENABLE (1 << 3)
494 492
495/* 493/*
496 * omap_hwmod._state definitions 494 * omap_hwmod._state definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 26eee4a556ad..31bea1ce3de1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -28,6 +28,7 @@
28#include "prm-regbits-33xx.h" 28#include "prm-regbits-33xx.h"
29#include "i2c.h" 29#include "i2c.h"
30#include "mmc.h" 30#include "mmc.h"
31#include "wd_timer.h"
31 32
32/* 33/*
33 * IP blocks 34 * IP blocks
@@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
2087}; 2088};
2088 2089
2089/* 'wd_timer' class */ 2090/* 'wd_timer' class */
2091static struct omap_hwmod_class_sysconfig wdt_sysc = {
2092 .rev_offs = 0x0,
2093 .sysc_offs = 0x10,
2094 .syss_offs = 0x14,
2095 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2096 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2097 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2098 SIDLE_SMART_WKUP),
2099 .sysc_fields = &omap_hwmod_sysc_type1,
2100};
2101
2090static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { 2102static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2091 .name = "wd_timer", 2103 .name = "wd_timer",
2104 .sysc = &wdt_sysc,
2105 .pre_shutdown = &omap2_wd_timer_disable,
2092}; 2106};
2093 2107
2094/* 2108/*
@@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2099 .name = "wd_timer2", 2113 .name = "wd_timer2",
2100 .class = &am33xx_wd_timer_hwmod_class, 2114 .class = &am33xx_wd_timer_hwmod_class,
2101 .clkdm_name = "l4_wkup_clkdm", 2115 .clkdm_name = "l4_wkup_clkdm",
2116 .flags = HWMOD_SWSUP_SIDLE,
2102 .main_clk = "wdt1_fck", 2117 .main_clk = "wdt1_fck",
2103 .prcm = { 2118 .prcm = {
2104 .omap4 = { 2119 .omap4 = {
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 8e61d80bf6b3..89cad4a605dd 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -52,7 +52,6 @@ enum {
52#define ALREADYACTIVE_SWITCH 0 52#define ALREADYACTIVE_SWITCH 0
53#define FORCEWAKEUP_SWITCH 1 53#define FORCEWAKEUP_SWITCH 1
54#define LOWPOWERSTATE_SWITCH 2 54#define LOWPOWERSTATE_SWITCH 2
55#define ERROR_SWITCH 3
56 55
57/* pwrdm_list contains all registered struct powerdomains */ 56/* pwrdm_list contains all registered struct powerdomains */
58static LIST_HEAD(pwrdm_list); 57static LIST_HEAD(pwrdm_list);
@@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
233{ 232{
234 u8 sleep_switch; 233 u8 sleep_switch;
235 234
236 if (curr_pwrst < 0) { 235 if (curr_pwrst < PWRDM_POWER_ON) {
237 WARN_ON(1);
238 sleep_switch = ERROR_SWITCH;
239 } else if (curr_pwrst < PWRDM_POWER_ON) {
240 if (curr_pwrst > pwrst && 236 if (curr_pwrst > pwrst &&
241 pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && 237 pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
242 arch_pwrdm->pwrdm_set_lowpwrstchange) { 238 arch_pwrdm->pwrdm_set_lowpwrstchange) {
@@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
1091 */ 1087 */
1092int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) 1088int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
1093{ 1089{
1094 u8 curr_pwrst, next_pwrst, sleep_switch; 1090 u8 next_pwrst, sleep_switch;
1091 int curr_pwrst;
1095 int ret = 0; 1092 int ret = 0;
1096 bool hwsup = false; 1093 bool hwsup = false;
1097 1094
@@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
1107 pwrdm_lock(pwrdm); 1104 pwrdm_lock(pwrdm);
1108 1105
1109 curr_pwrst = pwrdm_read_pwrst(pwrdm); 1106 curr_pwrst = pwrdm_read_pwrst(pwrdm);
1107 if (curr_pwrst < 0) {
1108 ret = -EINVAL;
1109 goto osps_out;
1110 }
1111
1110 next_pwrst = pwrdm_read_next_pwrst(pwrdm); 1112 next_pwrst = pwrdm_read_next_pwrst(pwrdm);
1111 if (curr_pwrst == pwrst && next_pwrst == pwrst) 1113 if (curr_pwrst == pwrst && next_pwrst == pwrst)
1112 goto osps_out; 1114 goto osps_out;
1113 1115
1114 sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, 1116 sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
1115 pwrst, &hwsup); 1117 pwrst, &hwsup);
1116 if (sleep_switch == ERROR_SWITCH) {
1117 ret = -EINVAL;
1118 goto osps_out;
1119 }
1120 1118
1121 ret = pwrdm_set_next_pwrst(pwrdm, pwrst); 1119 ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
1122 if (ret) 1120 if (ret)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d35f98aabf7a..415c7e0c9393 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
81/* Read a register in a CM/PRM instance in the PRM module */ 81/* Read a register in a CM/PRM instance in the PRM module */
82u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) 82u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
83{ 83{
84 return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); 84 return __raw_readl(prm_base + inst + reg);
85} 85}
86 86
87/* Write into a register in a CM/PRM instance in the PRM module */ 87/* Write into a register in a CM/PRM instance in the PRM module */
88void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) 88void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
89{ 89{
90 __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); 90 __raw_writel(val, prm_base + inst + reg);
91} 91}
92 92
93/* Read-modify-write a register in a PRM module. Caller must lock */ 93/* Read-modify-write a register in a PRM module. Caller must lock */
@@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
650 650
651int __init omap44xx_prm_init(void) 651int __init omap44xx_prm_init(void)
652{ 652{
653 if (!cpu_is_omap44xx()) 653 if (!cpu_is_omap44xx() && !soc_is_omap54xx())
654 return 0; 654 return 0;
655 655
656 return prm_register(&omap44xx_prm_ll_data); 656 return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index c62116bbc760..18fdeeb3a44a 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430)
413 413
414#define OMAP54XX_CLASS 0x54000054 414#define OMAP54XX_CLASS 0x54000054
415#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) 415#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
416#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
416#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) 417#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
418#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
417 419
418void omap2xxx_check_revision(void); 420void omap2xxx_check_revision(void);
419void omap3xxx_check_revision(void); 421void omap3xxx_check_revision(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f62b509ed08d..d00d89c93f1c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -62,6 +62,7 @@
62#define OMAP2_MPU_SOURCE "sys_ck" 62#define OMAP2_MPU_SOURCE "sys_ck"
63#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 63#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
64#define OMAP4_MPU_SOURCE "sys_clkin_ck" 64#define OMAP4_MPU_SOURCE "sys_clkin_ck"
65#define OMAP5_MPU_SOURCE "sys_clkin"
65#define OMAP2_32K_SOURCE "func_32k_ck" 66#define OMAP2_32K_SOURCE "func_32k_ck"
66#define OMAP3_32K_SOURCE "omap_32k_fck" 67#define OMAP3_32K_SOURCE "omap_32k_fck"
67#define OMAP4_32K_SOURCE "sys_32k_ck" 68#define OMAP4_32K_SOURCE "sys_32k_ck"
@@ -487,7 +488,7 @@ static void __init realtime_counter_init(void)
487 pr_err("%s: ioremap failed\n", __func__); 488 pr_err("%s: ioremap failed\n", __func__);
488 return; 489 return;
489 } 490 }
490 sys_clk = clk_get(NULL, "sys_clkin_ck"); 491 sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
491 if (IS_ERR(sys_clk)) { 492 if (IS_ERR(sys_clk)) {
492 pr_err("%s: failed to get system clock handle\n", __func__); 493 pr_err("%s: failed to get system clock handle\n", __func__);
493 iounmap(base); 494 iounmap(base);
@@ -620,7 +621,7 @@ void __init omap4_local_timer_init(void)
620 621
621#ifdef CONFIG_SOC_OMAP5 622#ifdef CONFIG_SOC_OMAP5
622OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", 623OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
623 2, OMAP4_MPU_SOURCE); 624 2, OMAP5_MPU_SOURCE);
624void __init omap5_realtime_timer_init(void) 625void __init omap5_realtime_timer_init(void)
625{ 626{
626 int err; 627 int err;
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index ad71c8a03ffd..2075bf8e3d90 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -19,6 +19,7 @@
19#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/clk-provider.h> 21#include <linux/clk-provider.h>
22#include <linux/cpu.h>
22#include <net/dsa.h> 23#include <net/dsa.h>
23#include <asm/page.h> 24#include <asm/page.h>
24#include <asm/setup.h> 25#include <asm/setup.h>
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 3cdc1bb8254c..d195db09ea32 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -62,7 +62,11 @@ int __init harmony_pcie_init(void)
62 goto err_reg; 62 goto err_reg;
63 } 63 }
64 64
65 regulator_enable(regulator); 65 err = regulator_enable(regulator);
66 if (err) {
67 pr_err("%s: regulator_enable failed: %d\n", __func__, err);
68 goto err_en;
69 }
66 70
67 err = tegra_pcie_init(true, true); 71 err = tegra_pcie_init(true, true);
68 if (err) { 72 if (err) {
@@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
74 78
75err_pcie: 79err_pcie:
76 regulator_disable(regulator); 80 regulator_disable(regulator);
81err_en:
77 regulator_put(regulator); 82 regulator_put(regulator);
78err_reg: 83err_reg:
79 gpio_free(en_vdd_1v05); 84 gpio_free(en_vdd_1v05);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 36dc2befa9d8..9387daeeadc8 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -99,12 +99,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
99 99
100 smp_wmb(); 100 smp_wmb();
101 101
102 save_cpu_arch_register();
103
104 cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); 102 cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
105 103
106 restore_cpu_arch_register();
107
108 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); 104 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
109 105
110 return true; 106 return true;
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2b4c3d..045c16f2dd51 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
7 7
8ENTRY(tegra_secondary_startup) 8ENTRY(tegra_secondary_startup)
9 bl v7_invalidate_l1 9 bl v7_invalidate_l1
10 /* Enable coresight */
11 mov32 r0, 0xC5ACCE55
12 mcr p14, 0, r0, c7, c12, 6
13 b secondary_startup 10 b secondary_startup
14ENDPROC(tegra_secondary_startup) 11ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2c6b3d55213b..e78d52d83acd 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -91,7 +91,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
91 if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { 91 if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
92 timeout = jiffies + msecs_to_jiffies(50); 92 timeout = jiffies + msecs_to_jiffies(50);
93 do { 93 do {
94 if (!tegra_powergate_is_powered(pwrgateid)) 94 if (tegra_powergate_is_powered(pwrgateid))
95 goto remove_clamps; 95 goto remove_clamps;
96 udelay(10); 96 udelay(10);
97 } while (time_before(jiffies, timeout)); 97 } while (time_before(jiffies, timeout));
@@ -124,6 +124,9 @@ remove_clamps:
124 124
125 /* Remove I/O clamps. */ 125 /* Remove I/O clamps. */
126 ret = tegra_powergate_remove_clamping(pwrgateid); 126 ret = tegra_powergate_remove_clamping(pwrgateid);
127 if (ret)
128 return ret;
129
127 udelay(10); 130 udelay(10);
128 131
129 /* Clear flow controller CSR. */ 132 /* Clear flow controller CSR. */
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 523604de666f..04a8e06f59a9 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -46,26 +46,11 @@
46#define PMC_CPUPWROFF_TIMER 0xcc 46#define PMC_CPUPWROFF_TIMER 0xcc
47 47
48#ifdef CONFIG_PM_SLEEP 48#ifdef CONFIG_PM_SLEEP
49static unsigned int g_diag_reg;
50static DEFINE_SPINLOCK(tegra_lp2_lock); 49static DEFINE_SPINLOCK(tegra_lp2_lock);
51static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 50static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
52static struct clk *tegra_pclk; 51static struct clk *tegra_pclk;
53void (*tegra_tear_down_cpu)(void); 52void (*tegra_tear_down_cpu)(void);
54 53
55void save_cpu_arch_register(void)
56{
57 /* read diagnostic register */
58 asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
59 return;
60}
61
62void restore_cpu_arch_register(void)
63{
64 /* write diagnostic register */
65 asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
66 return;
67}
68
69static void set_power_timers(unsigned long us_on, unsigned long us_off) 54static void set_power_timers(unsigned long us_on, unsigned long us_off)
70{ 55{
71 unsigned long long ticks; 56 unsigned long long ticks;
@@ -119,8 +104,6 @@ static void restore_cpu_complex(void)
119 tegra_cpu_clock_resume(); 104 tegra_cpu_clock_resume();
120 105
121 flowctrl_cpu_suspend_exit(cpu); 106 flowctrl_cpu_suspend_exit(cpu);
122
123 restore_cpu_arch_register();
124} 107}
125 108
126/* 109/*
@@ -145,8 +128,6 @@ static void suspend_cpu_complex(void)
145 tegra_cpu_clock_suspend(); 128 tegra_cpu_clock_suspend();
146 129
147 flowctrl_cpu_suspend_enter(cpu); 130 flowctrl_cpu_suspend_enter(cpu);
148
149 save_cpu_arch_register();
150} 131}
151 132
152void tegra_clear_cpu_in_lp2(int phy_cpu_id) 133void tegra_clear_cpu_in_lp2(int phy_cpu_id)
@@ -181,6 +162,11 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id)
181 return last_cpu; 162 return last_cpu;
182} 163}
183 164
165int tegra_cpu_do_idle(void)
166{
167 return cpu_do_idle();
168}
169
184static int tegra_sleep_cpu(unsigned long v2p) 170static int tegra_sleep_cpu(unsigned long v2p)
185{ 171{
186 /* Switch to the identity mapping. */ 172 /* Switch to the identity mapping. */
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index c6bc8f85759c..af9067e2867c 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -22,6 +22,7 @@
22#include <linux/debugfs.h> 22#include <linux/debugfs.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/export.h>
25#include <linux/init.h> 26#include <linux/init.h>
26#include <linux/io.h> 27#include <linux/io.h>
27#include <linux/seq_file.h> 28#include <linux/seq_file.h>
@@ -75,7 +76,7 @@ static int tegra_powergate_set(int id, bool new_state)
75 76
76 if (status == new_state) { 77 if (status == new_state) {
77 spin_unlock_irqrestore(&tegra_powergate_lock, flags); 78 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
78 return -EINVAL; 79 return 0;
79 } 80 }
80 81
81 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 82 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
@@ -168,6 +169,7 @@ err_clk:
168err_power: 169err_power:
169 return ret; 170 return ret;
170} 171}
172EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
171 173
172int tegra_cpu_powergate_id(int cpuid) 174int tegra_cpu_powergate_id(int cpuid)
173{ 175{
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 54382ceade4a..e6de88a2ea06 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,12 +41,10 @@
41 */ 41 */
42ENTRY(tegra_resume) 42ENTRY(tegra_resume)
43 bl v7_invalidate_l1 43 bl v7_invalidate_l1
44 /* Enable coresight */
45 mov32 r0, 0xC5ACCE55
46 mcr p14, 0, r0, c7, c12, 6
47 44
48 cpu_id r0 45 cpu_id r0
49 cmp r0, #0 @ CPU0? 46 cmp r0, #0 @ CPU0?
47 THUMB( it ne )
50 bne cpu_resume @ no 48 bne cpu_resume @ no
51 49
52#ifdef CONFIG_ARCH_TEGRA_3x_SOC 50#ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -99,6 +97,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
99 * 97 *
100 * Register usage within the reset handler: 98 * Register usage within the reset handler:
101 * 99 *
100 * Others: scratch
101 * R6 = SoC ID << 8
102 * R7 = CPU present (to the OS) mask 102 * R7 = CPU present (to the OS) mask
103 * R8 = CPU in LP1 state mask 103 * R8 = CPU in LP1 state mask
104 * R9 = CPU in LP2 state mask 104 * R9 = CPU in LP2 state mask
@@ -114,6 +114,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
114ENTRY(__tegra_cpu_reset_handler) 114ENTRY(__tegra_cpu_reset_handler)
115 115
116 cpsid aif, 0x13 @ SVC mode, interrupts disabled 116 cpsid aif, 0x13 @ SVC mode, interrupts disabled
117
118 mov32 r6, TEGRA_APB_MISC_BASE
119 ldr r6, [r6, #APB_MISC_GP_HIDREV]
120 and r6, r6, #0xff00
121#ifdef CONFIG_ARCH_TEGRA_2x_SOC
122t20_check:
123 cmp r6, #(0x20 << 8)
124 bne after_t20_check
125t20_errata:
126 # Tegra20 is a Cortex-A9 r1p1
127 mrc p15, 0, r0, c1, c0, 0 @ read system control register
128 orr r0, r0, #1 << 14 @ erratum 716044
129 mcr p15, 0, r0, c1, c0, 0 @ write system control register
130 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
131 orr r0, r0, #1 << 4 @ erratum 742230
132 orr r0, r0, #1 << 11 @ erratum 751472
133 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
134 b after_errata
135after_t20_check:
136#endif
137#ifdef CONFIG_ARCH_TEGRA_3x_SOC
138t30_check:
139 cmp r6, #(0x30 << 8)
140 bne after_t30_check
141t30_errata:
142 # Tegra30 is a Cortex-A9 r2p9
143 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
144 orr r0, r0, #1 << 6 @ erratum 743622
145 orr r0, r0, #1 << 11 @ erratum 751472
146 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
147 b after_errata
148after_t30_check:
149#endif
150after_errata:
117 mrc p15, 0, r10, c0, c0, 5 @ MPIDR 151 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
118 and r10, r10, #0x3 @ R10 = CPU number 152 and r10, r10, #0x3 @ R10 = CPU number
119 mov r11, #1 153 mov r11, #1
@@ -129,16 +163,13 @@ ENTRY(__tegra_cpu_reset_handler)
129 163
130#ifdef CONFIG_ARCH_TEGRA_2x_SOC 164#ifdef CONFIG_ARCH_TEGRA_2x_SOC
131 /* Are we on Tegra20? */ 165 /* Are we on Tegra20? */
132 mov32 r6, TEGRA_APB_MISC_BASE 166 cmp r6, #(0x20 << 8)
133 ldr r0, [r6, #APB_MISC_GP_HIDREV]
134 and r0, r0, #0xff00
135 cmp r0, #(0x20 << 8)
136 bne 1f 167 bne 1f
137 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ 168 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
138 mov32 r6, TEGRA_PMC_BASE 169 mov32 r5, TEGRA_PMC_BASE
139 mov r0, #0 170 mov r0, #0
140 cmp r10, #0 171 cmp r10, #0
141 strne r0, [r6, #PMC_SCRATCH41] 172 strne r0, [r5, #PMC_SCRATCH41]
1421: 1731:
143#endif 174#endif
144 175
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 9f6bfafdd512..e3f2417c420e 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -197,7 +197,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
197 mov r3, #CPU_RESETTABLE 197 mov r3, #CPU_RESETTABLE
198 str r3, [r0] 198 str r3, [r0]
199 199
200 bl cpu_do_idle 200 bl tegra_cpu_do_idle
201 201
202 /* 202 /*
203 * cpu may be reset while in wfi, which will return through 203 * cpu may be reset while in wfi, which will return through
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 63a15bd9b653..d29dfcce948d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -66,7 +66,9 @@ ENTRY(tegra30_cpu_shutdown)
66 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ 66 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
67 FLOW_CTRL_CSR_ENABLE 67 FLOW_CTRL_CSR_ENABLE
68 mov r4, #(1 << 4) 68 mov r4, #(1 << 4)
69 orr r12, r12, r4, lsl r3 69 ARM( orr r12, r12, r4, lsl r3 )
70 THUMB( lsl r4, r4, r3 )
71 THUMB( orr r12, r12, r4 )
70 str r12, [r1] 72 str r12, [r1]
71 73
72 /* Halt this CPU. */ 74 /* Halt this CPU. */
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4ffae541726e..bb308eab9079 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -92,7 +92,7 @@
92 92
93#ifdef CONFIG_CACHE_L2X0 93#ifdef CONFIG_CACHE_L2X0
94.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 94.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
95 adr \tmp1, \phys_l2x0_saved_regs 95 W(adr) \tmp1, \phys_l2x0_saved_regs
96 ldr \tmp1, [\tmp1] 96 ldr \tmp1, [\tmp1]
97 ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] 97 ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
98 ldr \tmp3, [\tmp2, #L2X0_CTRL] 98 ldr \tmp3, [\tmp2, #L2X0_CTRL]
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 1e49d901f2c9..0320495efc4d 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -95,7 +95,7 @@
95#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) 95#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
96 96
97/* Fast UART1 on U335 only */ 97/* Fast UART1 on U335 only */
98#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) 98#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
99 99
100/* 100/*
101 * SLOW peripherals 101 * SLOW peripherals
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index ff3c9f016591..33c353bc1c4a 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -30,6 +30,20 @@ struct regulator_init_data gpio_en_3v3_regulator = {
30 .consumer_supplies = gpio_en_3v3_consumers, 30 .consumer_supplies = gpio_en_3v3_consumers,
31}; 31};
32 32
33static struct regulator_consumer_supply sdi0_reg_consumers[] = {
34 REGULATOR_SUPPLY("vqmmc", "sdi0"),
35};
36
37struct regulator_init_data sdi0_reg_init_data = {
38 .constraints = {
39 .min_uV = 1800000,
40 .max_uV = 2900000,
41 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS,
42 },
43 .num_consumer_supplies = ARRAY_SIZE(sdi0_reg_consumers),
44 .consumer_supplies = sdi0_reg_consumers,
45};
46
33/* 47/*
34 * TPS61052 regulator 48 * TPS61052 regulator
35 */ 49 */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 9bece38fe933..039f5132c370 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -18,6 +18,7 @@ extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
18extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data; 18extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
19extern struct regulator_init_data tps61052_regulator; 19extern struct regulator_init_data tps61052_regulator;
20extern struct regulator_init_data gpio_en_3v3_regulator; 20extern struct regulator_init_data gpio_en_3v3_regulator;
21extern struct regulator_init_data sdi0_reg_init_data;
21 22
22void mop500_regulator_init(void); 23void mop500_regulator_init(void);
23 24
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 7f2cb6c5e2c1..6db0740128de 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -31,35 +31,6 @@
31 * SDI 0 (MicroSD slot) 31 * SDI 0 (MicroSD slot)
32 */ 32 */
33 33
34/* GPIO pins used by the sdi0 level shifter */
35static int sdi0_en = -1;
36static int sdi0_vsel = -1;
37
38static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
39{
40 switch (ios->power_mode) {
41 case MMC_POWER_UP:
42 case MMC_POWER_ON:
43 /*
44 * Level shifter voltage should depend on vdd to when deciding
45 * on either 1.8V or 2.9V. Once the decision has been made the
46 * level shifter must be disabled and re-enabled with a changed
47 * select signal in order to switch the voltage. Since there is
48 * no framework support yet for indicating 1.8V in vdd, use the
49 * default 2.9V.
50 */
51 gpio_direction_output(sdi0_vsel, 0);
52 gpio_direction_output(sdi0_en, 1);
53 break;
54 case MMC_POWER_OFF:
55 gpio_direction_output(sdi0_vsel, 0);
56 gpio_direction_output(sdi0_en, 0);
57 break;
58 }
59
60 return 0;
61}
62
63#ifdef CONFIG_STE_DMA40 34#ifdef CONFIG_STE_DMA40
64struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { 35struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
65 .mode = STEDMA40_MODE_LOGICAL, 36 .mode = STEDMA40_MODE_LOGICAL,
@@ -100,22 +71,6 @@ struct mmci_platform_data mop500_sdi0_data = {
100 71
101static void sdi0_configure(struct device *parent) 72static void sdi0_configure(struct device *parent)
102{ 73{
103 int ret;
104
105 ret = gpio_request(sdi0_en, "level shifter enable");
106 if (!ret)
107 ret = gpio_request(sdi0_vsel,
108 "level shifter 1v8-3v select");
109
110 if (ret) {
111 pr_warning("unable to config sdi0 gpios for level shifter.\n");
112 return;
113 }
114
115 /* Select the default 2.9V and enable level shifter */
116 gpio_direction_output(sdi0_vsel, 0);
117 gpio_direction_output(sdi0_en, 1);
118
119 /* Add the device, force v2 to subrevision 1 */ 74 /* Add the device, force v2 to subrevision 1 */
120 db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID); 75 db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
121} 76}
@@ -123,8 +78,6 @@ static void sdi0_configure(struct device *parent)
123void mop500_sdi_tc35892_init(struct device *parent) 78void mop500_sdi_tc35892_init(struct device *parent)
124{ 79{
125 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD; 80 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
126 sdi0_en = GPIO_SDMMC_EN;
127 sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
128 sdi0_configure(parent); 81 sdi0_configure(parent);
129} 82}
130 83
@@ -263,8 +216,6 @@ void __init snowball_sdi_init(struct device *parent)
263 /* External Micro SD slot */ 216 /* External Micro SD slot */
264 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; 217 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
265 mop500_sdi0_data.cd_invert = true; 218 mop500_sdi0_data.cd_invert = true;
266 sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
267 sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
268 sdi0_configure(parent); 219 sdi0_configure(parent);
269} 220}
270 221
@@ -276,8 +227,6 @@ void __init hrefv60_sdi_init(struct device *parent)
276 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID); 227 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
277 /* External Micro SD slot */ 228 /* External Micro SD slot */
278 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; 229 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
279 sdi0_en = HREFV60_SDMMC_EN_GPIO;
280 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
281 sdi0_configure(parent); 230 sdi0_configure(parent);
282 /* WLAN SDIO channel */ 231 /* WLAN SDIO channel */
283 db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID); 232 db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ce672378a830..574916b70b2e 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -25,6 +25,8 @@
25#include <linux/mfd/abx500/ab8500.h> 25#include <linux/mfd/abx500/ab8500.h>
26#include <linux/regulator/ab8500.h> 26#include <linux/regulator/ab8500.h>
27#include <linux/regulator/fixed.h> 27#include <linux/regulator/fixed.h>
28#include <linux/regulator/driver.h>
29#include <linux/regulator/gpio-regulator.h>
28#include <linux/mfd/tc3589x.h> 30#include <linux/mfd/tc3589x.h>
29#include <linux/mfd/tps6105x.h> 31#include <linux/mfd/tps6105x.h>
30#include <linux/mfd/abx500/ab8500-gpio.h> 32#include <linux/mfd/abx500/ab8500-gpio.h>
@@ -90,6 +92,37 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
90 }, 92 },
91}; 93};
92 94
95/* Dynamically populated. */
96static struct gpio sdi0_reg_gpios[] = {
97 { 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" },
98};
99
100static struct gpio_regulator_state sdi0_reg_states[] = {
101 { .value = 2900000, .gpios = (0 << 0) },
102 { .value = 1800000, .gpios = (1 << 0) },
103};
104
105static struct gpio_regulator_config sdi0_reg_info = {
106 .supply_name = "ext-mmc-level-shifter",
107 .gpios = sdi0_reg_gpios,
108 .nr_gpios = ARRAY_SIZE(sdi0_reg_gpios),
109 .states = sdi0_reg_states,
110 .nr_states = ARRAY_SIZE(sdi0_reg_states),
111 .type = REGULATOR_VOLTAGE,
112 .enable_high = 1,
113 .enabled_at_boot = 0,
114 .init_data = &sdi0_reg_init_data,
115 .startup_delay = 100,
116};
117
118static struct platform_device sdi0_regulator = {
119 .name = "gpio-regulator",
120 .id = -1,
121 .dev = {
122 .platform_data = &sdi0_reg_info,
123 },
124};
125
93static struct abx500_gpio_platform_data ab8500_gpio_pdata = { 126static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
94 .gpio_base = MOP500_AB8500_PIN_GPIO(1), 127 .gpio_base = MOP500_AB8500_PIN_GPIO(1),
95}; 128};
@@ -488,6 +521,7 @@ static struct hash_platform_data u8500_hash1_platform_data = {
488/* add any platform devices here - TODO */ 521/* add any platform devices here - TODO */
489static struct platform_device *mop500_platform_devs[] __initdata = { 522static struct platform_device *mop500_platform_devs[] __initdata = {
490 &mop500_gpio_keys_device, 523 &mop500_gpio_keys_device,
524 &sdi0_regulator,
491}; 525};
492 526
493#ifdef CONFIG_STE_DMA40 527#ifdef CONFIG_STE_DMA40
@@ -631,6 +665,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
631 &snowball_gpio_en_3v3_regulator_dev, 665 &snowball_gpio_en_3v3_regulator_dev,
632 &u8500_thsens_device, 666 &u8500_thsens_device,
633 &u8500_cpufreq_cooling_device, 667 &u8500_cpufreq_cooling_device,
668 &sdi0_regulator,
634}; 669};
635 670
636static void __init mop500_init_machine(void) 671static void __init mop500_init_machine(void)
@@ -642,6 +677,9 @@ static void __init mop500_init_machine(void)
642 platform_device_register(&db8500_prcmu_device); 677 platform_device_register(&db8500_prcmu_device);
643 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 678 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
644 679
680 sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN;
681 sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
682
645 mop500_pinmaps_init(); 683 mop500_pinmaps_init();
646 parent = u8500_init_devices(&ab8500_platdata); 684 parent = u8500_init_devices(&ab8500_platdata);
647 685
@@ -675,6 +713,10 @@ static void __init snowball_init_machine(void)
675 int i; 713 int i;
676 714
677 platform_device_register(&db8500_prcmu_device); 715 platform_device_register(&db8500_prcmu_device);
716
717 sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
718 sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
719
678 snowball_pinmaps_init(); 720 snowball_pinmaps_init();
679 parent = u8500_init_devices(&ab8500_platdata); 721 parent = u8500_init_devices(&ab8500_platdata);
680 722
@@ -710,6 +752,9 @@ static void __init hrefv60_init_machine(void)
710 */ 752 */
711 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 753 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
712 754
755 sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO;
756 sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
757
713 hrefv60_pinmaps_init(); 758 hrefv60_pinmaps_init();
714 parent = u8500_init_devices(&ab8500_platdata); 759 parent = u8500_init_devices(&ab8500_platdata);
715 760
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f1a581844372..5c6c2e633868 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -282,6 +282,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
282 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), 282 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
283 OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", 283 OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
284 &db8500_prcmu_pdata), 284 &db8500_prcmu_pdata),
285 OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
285 /* Requires device name bindings. */ 286 /* Requires device name bindings. */
286 OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE, 287 OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
287 "pinctrl-db8500", NULL), 288 "pinctrl-db8500", NULL),
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 12:37:16 -0500