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authorViresh Kumar <viresh.kumar@st.com>2012-04-09 23:32:35 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-12 15:44:12 -0400
commit5df33a62c4a028d6fc7f2dcc159827d09b7334b8 (patch)
treef4da61ce3bf14e9bf4a1dae3188109a6de34f708 /arch/arm/mach-spear3xx
parentf8abc080d33e69dfa2c3dd0f84c31832e2679091 (diff)
SPEAr: Switch to common clock framework
SPEAr SoCs used its own clock framework since now. From now on they will move to use common clock framework. This patch updates existing SPEAr machine support to adapt for common clock framework. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r--arch/arm/mach-spear3xx/Makefile2
-rw-r--r--arch/arm/mach-spear3xx/clock.c760
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h13
-rw-r--r--arch/arm/mach-spear3xx/spear320.c1
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c2
7 files changed, 19 insertions, 906 deletions
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..5b30d0d10892 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# common files 5# common files
6obj-y += spear3xx.o clock.o 6obj-y += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index 6c4841f55223..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <asm/mach-types.h>
18#include <plat/clock.h>
19#include <mach/misc_regs.h>
20
21/* root clks */
22/* 32 KHz oscillator clock */
23static struct clk osc_32k_clk = {
24 .flags = ALWAYS_ENABLED,
25 .rate = 32000,
26};
27
28/* 24 MHz oscillator clock */
29static struct clk osc_24m_clk = {
30 .flags = ALWAYS_ENABLED,
31 .rate = 24000000,
32};
33
34/* clock derived from 32 KHz osc clk */
35/* rtc clock */
36static struct clk rtc_clk = {
37 .pclk = &osc_32k_clk,
38 .en_reg = PERIP1_CLK_ENB,
39 .en_reg_bit = RTC_CLK_ENB,
40 .recalc = &follow_parent,
41};
42
43/* clock derived from 24 MHz osc clk */
44/* pll masks structure */
45static struct pll_clk_masks pll1_masks = {
46 .mode_mask = PLL_MODE_MASK,
47 .mode_shift = PLL_MODE_SHIFT,
48 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
49 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
50 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
51 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
52 .div_p_mask = PLL_DIV_P_MASK,
53 .div_p_shift = PLL_DIV_P_SHIFT,
54 .div_n_mask = PLL_DIV_N_MASK,
55 .div_n_shift = PLL_DIV_N_SHIFT,
56};
57
58/* pll1 configuration structure */
59static struct pll_clk_config pll1_config = {
60 .mode_reg = PLL1_CTR,
61 .cfg_reg = PLL1_FRQ,
62 .masks = &pll1_masks,
63};
64
65/* pll rate configuration table, in ascending order of rates */
66struct pll_rate_tbl pll_rtbl[] = {
67 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
68 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
69};
70
71/* PLL1 clock */
72static struct clk pll1_clk = {
73 .flags = ENABLED_ON_INIT,
74 .pclk = &osc_24m_clk,
75 .en_reg = PLL1_CTR,
76 .en_reg_bit = PLL_ENABLE,
77 .calc_rate = &pll_calc_rate,
78 .recalc = &pll_clk_recalc,
79 .set_rate = &pll_clk_set_rate,
80 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
81 .private_data = &pll1_config,
82};
83
84/* PLL3 48 MHz clock */
85static struct clk pll3_48m_clk = {
86 .flags = ALWAYS_ENABLED,
87 .pclk = &osc_24m_clk,
88 .rate = 48000000,
89};
90
91/* watch dog timer clock */
92static struct clk wdt_clk = {
93 .flags = ALWAYS_ENABLED,
94 .pclk = &osc_24m_clk,
95 .recalc = &follow_parent,
96};
97
98/* clock derived from pll1 clk */
99/* cpu clock */
100static struct clk cpu_clk = {
101 .flags = ALWAYS_ENABLED,
102 .pclk = &pll1_clk,
103 .recalc = &follow_parent,
104};
105
106/* ahb masks structure */
107static struct bus_clk_masks ahb_masks = {
108 .mask = PLL_HCLK_RATIO_MASK,
109 .shift = PLL_HCLK_RATIO_SHIFT,
110};
111
112/* ahb configuration structure */
113static struct bus_clk_config ahb_config = {
114 .reg = CORE_CLK_CFG,
115 .masks = &ahb_masks,
116};
117
118/* ahb rate configuration table, in ascending order of rates */
119struct bus_rate_tbl bus_rtbl[] = {
120 {.div = 3}, /* == parent divided by 4 */
121 {.div = 2}, /* == parent divided by 3 */
122 {.div = 1}, /* == parent divided by 2 */
123 {.div = 0}, /* == parent divided by 1 */
124};
125
126/* ahb clock */
127static struct clk ahb_clk = {
128 .flags = ALWAYS_ENABLED,
129 .pclk = &pll1_clk,
130 .calc_rate = &bus_calc_rate,
131 .recalc = &bus_clk_recalc,
132 .set_rate = &bus_clk_set_rate,
133 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
134 .private_data = &ahb_config,
135};
136
137/* auxiliary synthesizers masks */
138static struct aux_clk_masks aux_masks = {
139 .eq_sel_mask = AUX_EQ_SEL_MASK,
140 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
141 .eq1_mask = AUX_EQ1_SEL,
142 .eq2_mask = AUX_EQ2_SEL,
143 .xscale_sel_mask = AUX_XSCALE_MASK,
144 .xscale_sel_shift = AUX_XSCALE_SHIFT,
145 .yscale_sel_mask = AUX_YSCALE_MASK,
146 .yscale_sel_shift = AUX_YSCALE_SHIFT,
147};
148
149/* uart synth configurations */
150static struct aux_clk_config uart_synth_config = {
151 .synth_reg = UART_CLK_SYNT,
152 .masks = &aux_masks,
153};
154
155/* aux rate configuration table, in ascending order of rates */
156struct aux_rate_tbl aux_rtbl[] = {
157 /* For PLL1 = 332 MHz */
158 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
159 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
160 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
161};
162
163/* uart synth clock */
164static struct clk uart_synth_clk = {
165 .en_reg = UART_CLK_SYNT,
166 .en_reg_bit = AUX_SYNT_ENB,
167 .pclk = &pll1_clk,
168 .calc_rate = &aux_calc_rate,
169 .recalc = &aux_clk_recalc,
170 .set_rate = &aux_clk_set_rate,
171 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
172 .private_data = &uart_synth_config,
173};
174
175/* uart parents */
176static struct pclk_info uart_pclk_info[] = {
177 {
178 .pclk = &uart_synth_clk,
179 .pclk_val = AUX_CLK_PLL1_VAL,
180 }, {
181 .pclk = &pll3_48m_clk,
182 .pclk_val = AUX_CLK_PLL3_VAL,
183 },
184};
185
186/* uart parent select structure */
187static struct pclk_sel uart_pclk_sel = {
188 .pclk_info = uart_pclk_info,
189 .pclk_count = ARRAY_SIZE(uart_pclk_info),
190 .pclk_sel_reg = PERIP_CLK_CFG,
191 .pclk_sel_mask = UART_CLK_MASK,
192};
193
194/* uart clock */
195static struct clk uart_clk = {
196 .en_reg = PERIP1_CLK_ENB,
197 .en_reg_bit = UART_CLK_ENB,
198 .pclk_sel = &uart_pclk_sel,
199 .pclk_sel_shift = UART_CLK_SHIFT,
200 .recalc = &follow_parent,
201};
202
203/* firda configurations */
204static struct aux_clk_config firda_synth_config = {
205 .synth_reg = FIRDA_CLK_SYNT,
206 .masks = &aux_masks,
207};
208
209/* firda synth clock */
210static struct clk firda_synth_clk = {
211 .en_reg = FIRDA_CLK_SYNT,
212 .en_reg_bit = AUX_SYNT_ENB,
213 .pclk = &pll1_clk,
214 .calc_rate = &aux_calc_rate,
215 .recalc = &aux_clk_recalc,
216 .set_rate = &aux_clk_set_rate,
217 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
218 .private_data = &firda_synth_config,
219};
220
221/* firda parents */
222static struct pclk_info firda_pclk_info[] = {
223 {
224 .pclk = &firda_synth_clk,
225 .pclk_val = AUX_CLK_PLL1_VAL,
226 }, {
227 .pclk = &pll3_48m_clk,
228 .pclk_val = AUX_CLK_PLL3_VAL,
229 },
230};
231
232/* firda parent select structure */
233static struct pclk_sel firda_pclk_sel = {
234 .pclk_info = firda_pclk_info,
235 .pclk_count = ARRAY_SIZE(firda_pclk_info),
236 .pclk_sel_reg = PERIP_CLK_CFG,
237 .pclk_sel_mask = FIRDA_CLK_MASK,
238};
239
240/* firda clock */
241static struct clk firda_clk = {
242 .en_reg = PERIP1_CLK_ENB,
243 .en_reg_bit = FIRDA_CLK_ENB,
244 .pclk_sel = &firda_pclk_sel,
245 .pclk_sel_shift = FIRDA_CLK_SHIFT,
246 .recalc = &follow_parent,
247};
248
249/* gpt synthesizer masks */
250static struct gpt_clk_masks gpt_masks = {
251 .mscale_sel_mask = GPT_MSCALE_MASK,
252 .mscale_sel_shift = GPT_MSCALE_SHIFT,
253 .nscale_sel_mask = GPT_NSCALE_MASK,
254 .nscale_sel_shift = GPT_NSCALE_SHIFT,
255};
256
257/* gpt rate configuration table, in ascending order of rates */
258struct gpt_rate_tbl gpt_rtbl[] = {
259 /* For pll1 = 332 MHz */
260 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
261 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
262 {.mscale = 1, .nscale = 0}, /* 83 MHz */
263};
264
265/* gpt0 synth clk config*/
266static struct gpt_clk_config gpt0_synth_config = {
267 .synth_reg = PRSC1_CLK_CFG,
268 .masks = &gpt_masks,
269};
270
271/* gpt synth clock */
272static struct clk gpt0_synth_clk = {
273 .flags = ALWAYS_ENABLED,
274 .pclk = &pll1_clk,
275 .calc_rate = &gpt_calc_rate,
276 .recalc = &gpt_clk_recalc,
277 .set_rate = &gpt_clk_set_rate,
278 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
279 .private_data = &gpt0_synth_config,
280};
281
282/* gpt parents */
283static struct pclk_info gpt0_pclk_info[] = {
284 {
285 .pclk = &gpt0_synth_clk,
286 .pclk_val = AUX_CLK_PLL1_VAL,
287 }, {
288 .pclk = &pll3_48m_clk,
289 .pclk_val = AUX_CLK_PLL3_VAL,
290 },
291};
292
293/* gpt parent select structure */
294static struct pclk_sel gpt0_pclk_sel = {
295 .pclk_info = gpt0_pclk_info,
296 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
297 .pclk_sel_reg = PERIP_CLK_CFG,
298 .pclk_sel_mask = GPT_CLK_MASK,
299};
300
301/* gpt0 timer clock */
302static struct clk gpt0_clk = {
303 .flags = ALWAYS_ENABLED,
304 .pclk_sel = &gpt0_pclk_sel,
305 .pclk_sel_shift = GPT0_CLK_SHIFT,
306 .recalc = &follow_parent,
307};
308
309/* gpt1 synth clk configurations */
310static struct gpt_clk_config gpt1_synth_config = {
311 .synth_reg = PRSC2_CLK_CFG,
312 .masks = &gpt_masks,
313};
314
315/* gpt1 synth clock */
316static struct clk gpt1_synth_clk = {
317 .flags = ALWAYS_ENABLED,
318 .pclk = &pll1_clk,
319 .calc_rate = &gpt_calc_rate,
320 .recalc = &gpt_clk_recalc,
321 .set_rate = &gpt_clk_set_rate,
322 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
323 .private_data = &gpt1_synth_config,
324};
325
326static struct pclk_info gpt1_pclk_info[] = {
327 {
328 .pclk = &gpt1_synth_clk,
329 .pclk_val = AUX_CLK_PLL1_VAL,
330 }, {
331 .pclk = &pll3_48m_clk,
332 .pclk_val = AUX_CLK_PLL3_VAL,
333 },
334};
335
336/* gpt parent select structure */
337static struct pclk_sel gpt1_pclk_sel = {
338 .pclk_info = gpt1_pclk_info,
339 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
340 .pclk_sel_reg = PERIP_CLK_CFG,
341 .pclk_sel_mask = GPT_CLK_MASK,
342};
343
344/* gpt1 timer clock */
345static struct clk gpt1_clk = {
346 .en_reg = PERIP1_CLK_ENB,
347 .en_reg_bit = GPT1_CLK_ENB,
348 .pclk_sel = &gpt1_pclk_sel,
349 .pclk_sel_shift = GPT1_CLK_SHIFT,
350 .recalc = &follow_parent,
351};
352
353/* gpt2 synth clk configurations */
354static struct gpt_clk_config gpt2_synth_config = {
355 .synth_reg = PRSC3_CLK_CFG,
356 .masks = &gpt_masks,
357};
358
359/* gpt1 synth clock */
360static struct clk gpt2_synth_clk = {
361 .flags = ALWAYS_ENABLED,
362 .pclk = &pll1_clk,
363 .calc_rate = &gpt_calc_rate,
364 .recalc = &gpt_clk_recalc,
365 .set_rate = &gpt_clk_set_rate,
366 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
367 .private_data = &gpt2_synth_config,
368};
369
370static struct pclk_info gpt2_pclk_info[] = {
371 {
372 .pclk = &gpt2_synth_clk,
373 .pclk_val = AUX_CLK_PLL1_VAL,
374 }, {
375 .pclk = &pll3_48m_clk,
376 .pclk_val = AUX_CLK_PLL3_VAL,
377 },
378};
379
380/* gpt parent select structure */
381static struct pclk_sel gpt2_pclk_sel = {
382 .pclk_info = gpt2_pclk_info,
383 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
384 .pclk_sel_reg = PERIP_CLK_CFG,
385 .pclk_sel_mask = GPT_CLK_MASK,
386};
387
388/* gpt2 timer clock */
389static struct clk gpt2_clk = {
390 .en_reg = PERIP1_CLK_ENB,
391 .en_reg_bit = GPT2_CLK_ENB,
392 .pclk_sel = &gpt2_pclk_sel,
393 .pclk_sel_shift = GPT2_CLK_SHIFT,
394 .recalc = &follow_parent,
395};
396
397/* clock derived from pll3 clk */
398/* usbh clock */
399static struct clk usbh_clk = {
400 .pclk = &pll3_48m_clk,
401 .en_reg = PERIP1_CLK_ENB,
402 .en_reg_bit = USBH_CLK_ENB,
403 .recalc = &follow_parent,
404};
405
406/* usbd clock */
407static struct clk usbd_clk = {
408 .pclk = &pll3_48m_clk,
409 .en_reg = PERIP1_CLK_ENB,
410 .en_reg_bit = USBD_CLK_ENB,
411 .recalc = &follow_parent,
412};
413
414/* clock derived from ahb clk */
415/* apb masks structure */
416static struct bus_clk_masks apb_masks = {
417 .mask = HCLK_PCLK_RATIO_MASK,
418 .shift = HCLK_PCLK_RATIO_SHIFT,
419};
420
421/* apb configuration structure */
422static struct bus_clk_config apb_config = {
423 .reg = CORE_CLK_CFG,
424 .masks = &apb_masks,
425};
426
427/* apb clock */
428static struct clk apb_clk = {
429 .flags = ALWAYS_ENABLED,
430 .pclk = &ahb_clk,
431 .calc_rate = &bus_calc_rate,
432 .recalc = &bus_clk_recalc,
433 .set_rate = &bus_clk_set_rate,
434 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
435 .private_data = &apb_config,
436};
437
438/* i2c clock */
439static struct clk i2c_clk = {
440 .pclk = &ahb_clk,
441 .en_reg = PERIP1_CLK_ENB,
442 .en_reg_bit = I2C_CLK_ENB,
443 .recalc = &follow_parent,
444};
445
446/* dma clock */
447static struct clk dma_clk = {
448 .pclk = &ahb_clk,
449 .en_reg = PERIP1_CLK_ENB,
450 .en_reg_bit = DMA_CLK_ENB,
451 .recalc = &follow_parent,
452};
453
454/* jpeg clock */
455static struct clk jpeg_clk = {
456 .pclk = &ahb_clk,
457 .en_reg = PERIP1_CLK_ENB,
458 .en_reg_bit = JPEG_CLK_ENB,
459 .recalc = &follow_parent,
460};
461
462/* gmac clock */
463static struct clk gmac_clk = {
464 .pclk = &ahb_clk,
465 .en_reg = PERIP1_CLK_ENB,
466 .en_reg_bit = GMAC_CLK_ENB,
467 .recalc = &follow_parent,
468};
469
470/* smi clock */
471static struct clk smi_clk = {
472 .pclk = &ahb_clk,
473 .en_reg = PERIP1_CLK_ENB,
474 .en_reg_bit = SMI_CLK_ENB,
475 .recalc = &follow_parent,
476};
477
478/* c3 clock */
479static struct clk c3_clk = {
480 .pclk = &ahb_clk,
481 .en_reg = PERIP1_CLK_ENB,
482 .en_reg_bit = C3_CLK_ENB,
483 .recalc = &follow_parent,
484};
485
486/* clock derived from apb clk */
487/* adc clock */
488static struct clk adc_clk = {
489 .pclk = &apb_clk,
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = ADC_CLK_ENB,
492 .recalc = &follow_parent,
493};
494
495#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
496/* emi clock */
497static struct clk emi_clk = {
498 .flags = ALWAYS_ENABLED,
499 .pclk = &ahb_clk,
500 .recalc = &follow_parent,
501};
502#endif
503
504/* ssp clock */
505static struct clk ssp0_clk = {
506 .pclk = &apb_clk,
507 .en_reg = PERIP1_CLK_ENB,
508 .en_reg_bit = SSP_CLK_ENB,
509 .recalc = &follow_parent,
510};
511
512/* gpio clock */
513static struct clk gpio_clk = {
514 .pclk = &apb_clk,
515 .en_reg = PERIP1_CLK_ENB,
516 .en_reg_bit = GPIO_CLK_ENB,
517 .recalc = &follow_parent,
518};
519
520static struct clk dummy_apb_pclk;
521
522#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
523 defined(CONFIG_MACH_SPEAR320)
524/* fsmc clock */
525static struct clk fsmc_clk = {
526 .flags = ALWAYS_ENABLED,
527 .pclk = &ahb_clk,
528 .recalc = &follow_parent,
529};
530#endif
531
532/* common clocks to spear310 and spear320 */
533#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
534/* uart1 clock */
535static struct clk uart1_clk = {
536 .flags = ALWAYS_ENABLED,
537 .pclk = &apb_clk,
538 .recalc = &follow_parent,
539};
540
541/* uart2 clock */
542static struct clk uart2_clk = {
543 .flags = ALWAYS_ENABLED,
544 .pclk = &apb_clk,
545 .recalc = &follow_parent,
546};
547#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
548
549/* common clocks to spear300 and spear320 */
550#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
551/* clcd clock */
552static struct clk clcd_clk = {
553 .flags = ALWAYS_ENABLED,
554 .pclk = &pll3_48m_clk,
555 .recalc = &follow_parent,
556};
557
558/* sdhci clock */
559static struct clk sdhci_clk = {
560 .flags = ALWAYS_ENABLED,
561 .pclk = &ahb_clk,
562 .recalc = &follow_parent,
563};
564#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
565
566/* spear300 machine specific clock structures */
567#ifdef CONFIG_MACH_SPEAR300
568/* gpio1 clock */
569static struct clk gpio1_clk = {
570 .flags = ALWAYS_ENABLED,
571 .pclk = &apb_clk,
572 .recalc = &follow_parent,
573};
574
575/* keyboard clock */
576static struct clk kbd_clk = {
577 .flags = ALWAYS_ENABLED,
578 .pclk = &apb_clk,
579 .recalc = &follow_parent,
580};
581
582#endif
583
584/* spear310 machine specific clock structures */
585#ifdef CONFIG_MACH_SPEAR310
586/* uart3 clock */
587static struct clk uart3_clk = {
588 .flags = ALWAYS_ENABLED,
589 .pclk = &apb_clk,
590 .recalc = &follow_parent,
591};
592
593/* uart4 clock */
594static struct clk uart4_clk = {
595 .flags = ALWAYS_ENABLED,
596 .pclk = &apb_clk,
597 .recalc = &follow_parent,
598};
599
600/* uart5 clock */
601static struct clk uart5_clk = {
602 .flags = ALWAYS_ENABLED,
603 .pclk = &apb_clk,
604 .recalc = &follow_parent,
605};
606#endif
607
608/* spear320 machine specific clock structures */
609#ifdef CONFIG_MACH_SPEAR320
610/* can0 clock */
611static struct clk can0_clk = {
612 .flags = ALWAYS_ENABLED,
613 .pclk = &apb_clk,
614 .recalc = &follow_parent,
615};
616
617/* can1 clock */
618static struct clk can1_clk = {
619 .flags = ALWAYS_ENABLED,
620 .pclk = &apb_clk,
621 .recalc = &follow_parent,
622};
623
624/* i2c1 clock */
625static struct clk i2c1_clk = {
626 .flags = ALWAYS_ENABLED,
627 .pclk = &ahb_clk,
628 .recalc = &follow_parent,
629};
630
631/* ssp1 clock */
632static struct clk ssp1_clk = {
633 .flags = ALWAYS_ENABLED,
634 .pclk = &apb_clk,
635 .recalc = &follow_parent,
636};
637
638/* ssp2 clock */
639static struct clk ssp2_clk = {
640 .flags = ALWAYS_ENABLED,
641 .pclk = &apb_clk,
642 .recalc = &follow_parent,
643};
644
645/* pwm clock */
646static struct clk pwm_clk = {
647 .flags = ALWAYS_ENABLED,
648 .pclk = &apb_clk,
649 .recalc = &follow_parent,
650};
651#endif
652
653/* array of all spear 3xx clock lookups */
654static struct clk_lookup spear_clk_lookups[] = {
655 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
656 /* root clks */
657 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
658 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
659 /* clock derived from 32 KHz osc clk */
660 { .dev_id = "rtc-spear", .clk = &rtc_clk},
661 /* clock derived from 24 MHz osc clk */
662 { .con_id = "pll1_clk", .clk = &pll1_clk},
663 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
664 { .dev_id = "wdt", .clk = &wdt_clk},
665 /* clock derived from pll1 clk */
666 { .con_id = "cpu_clk", .clk = &cpu_clk},
667 { .con_id = "ahb_clk", .clk = &ahb_clk},
668 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
669 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
670 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
671 { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
672 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
673 { .dev_id = "uart", .clk = &uart_clk},
674 { .dev_id = "firda", .clk = &firda_clk},
675 { .dev_id = "gpt0", .clk = &gpt0_clk},
676 { .dev_id = "gpt1", .clk = &gpt1_clk},
677 { .dev_id = "gpt2", .clk = &gpt2_clk},
678 /* clock derived from pll3 clk */
679 { .dev_id = "designware_udc", .clk = &usbd_clk},
680 { .con_id = "usbh_clk", .clk = &usbh_clk},
681 /* clock derived from ahb clk */
682 { .con_id = "apb_clk", .clk = &apb_clk},
683 { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
684 { .dev_id = "dma", .clk = &dma_clk},
685 { .dev_id = "jpeg", .clk = &jpeg_clk},
686 { .dev_id = "gmac", .clk = &gmac_clk},
687 { .dev_id = "smi", .clk = &smi_clk},
688 { .dev_id = "c3", .clk = &c3_clk},
689 /* clock derived from apb clk */
690 { .dev_id = "adc", .clk = &adc_clk},
691 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
692 { .dev_id = "gpio", .clk = &gpio_clk},
693};
694
695/* array of all spear 300 clock lookups */
696#ifdef CONFIG_MACH_SPEAR300
697static struct clk_lookup spear300_clk_lookups[] = {
698 { .dev_id = "clcd", .clk = &clcd_clk},
699 { .con_id = "fsmc", .clk = &fsmc_clk},
700 { .dev_id = "gpio1", .clk = &gpio1_clk},
701 { .dev_id = "keyboard", .clk = &kbd_clk},
702 { .dev_id = "sdhci", .clk = &sdhci_clk},
703};
704#endif
705
706/* array of all spear 310 clock lookups */
707#ifdef CONFIG_MACH_SPEAR310
708static struct clk_lookup spear310_clk_lookups[] = {
709 { .con_id = "fsmc", .clk = &fsmc_clk},
710 { .con_id = "emi", .clk = &emi_clk},
711 { .dev_id = "uart1", .clk = &uart1_clk},
712 { .dev_id = "uart2", .clk = &uart2_clk},
713 { .dev_id = "uart3", .clk = &uart3_clk},
714 { .dev_id = "uart4", .clk = &uart4_clk},
715 { .dev_id = "uart5", .clk = &uart5_clk},
716};
717#endif
718
719/* array of all spear 320 clock lookups */
720#ifdef CONFIG_MACH_SPEAR320
721static struct clk_lookup spear320_clk_lookups[] = {
722 { .dev_id = "clcd", .clk = &clcd_clk},
723 { .con_id = "fsmc", .clk = &fsmc_clk},
724 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
725 { .con_id = "emi", .clk = &emi_clk},
726 { .dev_id = "pwm", .clk = &pwm_clk},
727 { .dev_id = "sdhci", .clk = &sdhci_clk},
728 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
729 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
730 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
731 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
732 { .dev_id = "uart1", .clk = &uart1_clk},
733 { .dev_id = "uart2", .clk = &uart2_clk},
734};
735#endif
736
737void __init spear3xx_clk_init(void)
738{
739 int i, cnt;
740 struct clk_lookup *lookups;
741
742 if (machine_is_spear300()) {
743 cnt = ARRAY_SIZE(spear300_clk_lookups);
744 lookups = spear300_clk_lookups;
745 } else if (machine_is_spear310()) {
746 cnt = ARRAY_SIZE(spear310_clk_lookups);
747 lookups = spear310_clk_lookups;
748 } else {
749 cnt = ARRAY_SIZE(spear320_clk_lookups);
750 lookups = spear320_clk_lookups;
751 }
752
753 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
754 clk_register(&spear_clk_lookups[i]);
755
756 for (i = 0; i < cnt; i++)
757 clk_register(&lookups[i]);
758
759 clk_init();
760}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..15c107aad202 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -36,8 +36,8 @@ extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 36extern struct sys_timer spear3xx_timer;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init spear3xx_clk_init(void);
40void __init spear_setup_timer(void); 39void __init spear_setup_timer(void);
40void __init spear3xx_clk_init(void);
41void __init spear3xx_map_io(void); 41void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 42void __init spear3xx_init_irq(void);
43void __init spear3xx_init(void); 43void __init spear3xx_init(void);
@@ -156,7 +156,6 @@ extern struct pmx_dev spear310_pmx_tdm0;
156/* Add spear310 machine function declarations here */ 156/* Add spear310 machine function declarations here */
157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 157void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
158 u8 pmx_dev_count); 158 u8 pmx_dev_count);
159
160#endif /* CONFIG_MACH_SPEAR310 */ 159#endif /* CONFIG_MACH_SPEAR310 */
161 160
162/* spear320 declarations */ 161/* spear320 declarations */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..50cfe0d1a7c4 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -15,150 +15,8 @@
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/spear.h>
18 19
19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 20#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20 21
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 11
64#define GPT2_CLK_SHIFT 12
65#define GPT_CLK_MASK 0x1
66#define AUX_CLK_PLL3_VAL 0
67#define AUX_CLK_PLL1_VAL 1
68
69#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5
73#define I2C_CLK_ENB 7
74#define JPEG_CLK_ENB 8
75#define FIRDA_CLK_ENB 10
76#define GPT1_CLK_ENB 11
77#define GPT2_CLK_ENB 12
78#define ADC_CLK_ENB 15
79#define RTC_CLK_ENB 17
80#define GPIO_CLK_ENB 18
81#define DMA_CLK_ENB 19
82#define SMI_CLK_ENB 21
83#define GMAC_CLK_ENB 23
84#define USBD_CLK_ENB 24
85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31
87
88#define SOC_CORE_ID (MISC_BASE + 0x030)
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90#define PERIP1_SOF_RST (MISC_BASE + 0x038)
91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8
93
94#define SOC_USER_ID (MISC_BASE + 0x03C)
95#define RAS_SOF_RST (MISC_BASE + 0x040)
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
127#define ICM2_ARB_CFG (MISC_BASE + 0x080)
128#define ICM3_ARB_CFG (MISC_BASE + 0x084)
129#define ICM4_ARB_CFG (MISC_BASE + 0x088)
130#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
131#define ICM6_ARB_CFG (MISC_BASE + 0x090)
132#define ICM7_ARB_CFG (MISC_BASE + 0x094)
133#define ICM8_ARB_CFG (MISC_BASE + 0x098)
134#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
135#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
136#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
137#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
138#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
139#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
140#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
141#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
142#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
143#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
144#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
145#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
146#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
147#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
148#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
149#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
150#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
151#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
152#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
153#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
154#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
155#define BIST4_CFG_CTR (MISC_BASE + 0x100)
156#define BIST5_CFG_CTR (MISC_BASE + 0x104)
157#define BIST1_STS_RES (MISC_BASE + 0x108)
158#define BIST2_STS_RES (MISC_BASE + 0x10C)
159#define BIST3_STS_RES (MISC_BASE + 0x110)
160#define BIST4_STS_RES (MISC_BASE + 0x114)
161#define BIST5_STS_RES (MISC_BASE + 0x118)
162#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
163
164#endif /* __MACH_MISC_REGS_H */ 22#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..881109522060 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -78,4 +78,17 @@
78#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE 78#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
79#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE 79#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
80 80
81/* SPEAr320 Macros */
82#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
83#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
84#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
85#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
86 #define SPEAR320_UARTX_PCLK_MASK 0x1
87 #define SPEAR320_UART2_PCLK_SHIFT 8
88 #define SPEAR320_UART3_PCLK_SHIFT 9
89 #define SPEAR320_UART4_PCLK_SHIFT 10
90 #define SPEAR320_UART5_PCLK_SHIFT 11
91 #define SPEAR320_UART6_PCLK_SHIFT 12
92 #define SPEAR320_RS485_PCLK_SHIFT 13
93
81#endif /* __MACH_SPEAR3XX_H */ 94#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..bfdad554319c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -16,6 +16,7 @@
16#include <plat/shirq.h> 16#include <plat/shirq.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19#include <mach/spear.h>
19 20
20/* pad multiplexing support */ 21/* pad multiplexing support */
21/* muxing registers */ 22/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..2625ab9a6c8b 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -511,6 +511,8 @@ static void __init spear3xx_timer_init(void)
511 char pclk_name[] = "pll3_48m_clk"; 511 char pclk_name[] = "pll3_48m_clk";
512 struct clk *gpt_clk, *pclk; 512 struct clk *gpt_clk, *pclk;
513 513
514 spear3xx_clk_init();
515
514 /* get the system timer clock */ 516 /* get the system timer clock */
515 gpt_clk = clk_get_sys("gpt0", NULL); 517 gpt_clk = clk_get_sys("gpt0", NULL);
516 if (IS_ERR(gpt_clk)) { 518 if (IS_ERR(gpt_clk)) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 09:50:43 -0500