SPEAr: Switch to common clock framework

SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.

This patch updates existing SPEAr machine support to adapt for common clock
framework.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>

19 files changed, 983 insertions, 3004 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 164e9a1df0f6..cb5425e3cd42 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6336,9 +6336,7 @@ L:	spear-devel@list.st.com
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.st.com/spear
 S:      Maintained
-F:      arch/arm/mach-spear*/clock.c
-F:      arch/arm/plat-spear/clock.c
-F:      arch/arm/plat-spear/include/plat/clock.h
+F:      drivers/clk/spear/
 
 SPEAR PAD MULTIPLEXING SUPPORT
 M:      Viresh Kumar <viresh.kumar@st.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d40342c..ce030c242644 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -980,6 +980,7 @@ config PLAT_SPEAR
         select ARM_AMBA
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..5b30d0d10892 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,7 +3,7 @@
 #
 
 # common files
-obj-y   += spear3xx.o clock.o
+obj-y   += spear3xx.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index 6c4841f55223..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/clock.c
- *
- * SPEAr3xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <asm/mach-types.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 32000,
-};
-
-/* 24 MHz oscillator clock */
-static struct clk osc_24m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .rate = 24000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-        .pclk = &osc_32k_clk,
-        .en_reg = PERIP1_CLK_ENB,
-        .en_reg_bit = RTC_CLK_ENB,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from 24 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-        .mode_mask = PLL_MODE_MASK,
-        .mode_shift = PLL_MODE_SHIFT,
-        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-        .div_p_mask = PLL_DIV_P_MASK,
-        .div_p_shift = PLL_DIV_P_SHIFT,
-        .div_n_mask = PLL_DIV_N_MASK,
-        .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-        .mode_reg = PLL1_CTR,
-        .cfg_reg = PLL1_FRQ,
-        .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-        .flags = ENABLED_ON_INIT,
-        .pclk = &osc_24m_clk,
-        .en_reg = PLL1_CTR,
-        .en_reg_bit = PLL_ENABLE,
-        .calc_rate = &pll_calc_rate,
-        .recalc = &pll_clk_recalc,
-        .set_rate = &pll_clk_set_rate,
-        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-        .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_24m_clk,
-        .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &osc_24m_clk,
-        .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,
-        .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-        .mask = PLL_HCLK_RATIO_MASK,
-        .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-        .reg = CORE_CLK_CFG,
-        .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-        {.div = 3}, /* == parent divided by 4 */
-        {.div = 2}, /* == parent divided by 3 */
-        {.div = 1}, /* == parent divided by 2 */
-        {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll1_clk,