Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

30 files changed, 716 insertions, 323 deletions

diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index fd4c52b7ccb6..42625e4d949a 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -90,8 +90,8 @@ config SA1100_JORNADA720
         # FIXME: select CPU_FREQ_SA11x0
         help
           Say Y here if you want to build a kernel for the HP Jornada 720
-          handheld computer.  See <http://www.hp.com/jornada/products/720>
-          for details.
+          handheld computer.  See 
+          <http://h10025.www1.hp.com/ewfrf/wc/product?product=61677&cc=us&lc=en&dlc=en&product=61677#> 
 
 config SA1100_JORNADA720_SSP
         bool "HP Jornada 720 Extended SSP driver"
@@ -118,6 +118,16 @@ config SA1100_LART
           (also known as the LART).  See <http://www.lartmaker.nl/> for
           information on the LART.
 
+config SA1100_NANOENGINE
+        bool "nanoEngine"
+        select CPU_FREQ_SA1110
+        select PCI
+        select PCI_NANOENGINE
+        help
+          Say Y here if you are using the Bright Star Engineering nanoEngine.
+          See <http://www.brightstareng.com/arm/nanoeng.htm> for information
+          on the BSE nanoEngine.
+
 config SA1100_PLEB
         bool "PLEB"
         select CPU_FREQ_SA1100
@@ -145,7 +155,7 @@ config SA1100_SIMPAD
           FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a
           PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same
           like CL4 in additional it has a PCMCIA-Slot. For more information
-          visit <http://www.my-siemens.com/> or <http://www.siemens.ch/>.
+          visit <http://www.usa.siemens.com/> or <http://www.siemens.ch/>.
 
 config SA1100_SSP
         tristate "Generic PIO SSP"
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 89349c1dd7a6..41252d22e659 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_SA1100_JORNADA720_SSP)	+= jornada720_ssp.o
 obj-$(CONFIG_SA1100_LART)               += lart.o
 led-$(CONFIG_SA1100_LART)               += leds-lart.o
 
+obj-$(CONFIG_SA1100_NANOENGINE)         += nanoengine.o
+obj-$(CONFIG_PCI_NANOENGINE)            += pci-nanoengine.o
+
 obj-$(CONFIG_SA1100_PLEB)               += pleb.o
 
 obj-$(CONFIG_SA1100_SHANNON)            += shannon.o
@@ -47,7 +50,7 @@ led-$(CONFIG_SA1100_SIMPAD)		+= leds-simpad.o
 # LEDs support
 obj-$(CONFIG_LEDS) += $(led-y)
 
-# Miscelaneous functions
+# Miscellaneous functions
 obj-$(CONFIG_PM)                        += pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)                += ssp.o
 
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 169e5b87dbff..5778274a8260 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -447,8 +447,6 @@ static void __init assabet_map_io(void)
 
 
 MACHINE_START(ASSABET, "Intel-Assabet")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .fixup          = fixup_assabet,
         .map_io         = assabet_map_io,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index 259cb2c15fff..4f19ff868b00 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -302,8 +302,6 @@ static void __init badge4_map_io(void)
 }
 
 MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = badge4_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index bc950ef418af..7f3da4b11ec9 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = {
 static void __init cerf_init_irq(void)
 {
         sa1100_init_irq();
-        set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
 }
 
 static struct map_desc cerf_io_desc[] __initdata = {
@@ -135,8 +135,6 @@ static void __init cerf_init(void)
 
 MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
         /* Maintainer: support@intrinsyc.com */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .map_io         = cerf_map_io,
         .init_irq       = cerf_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 16e682d5dbb7..bd3e1bfdd6aa 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -241,6 +241,9 @@ static struct locomo_platform_data locomo_info = {
 struct platform_device collie_locomo_device = {
         .name           = "locomo",
         .id             = 0,
+        .dev            = {
+                .platform_data  = &locomo_info,
+        },
         .num_resources  = ARRAY_SIZE(locomo_resources),
         .resource       = locomo_resources,
 };
@@ -379,8 +382,6 @@ static void __init collie_map_io(void)
 }
 
 MACHINE_START(COLLIE, "Sharp-Collie")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .map_io         = collie_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index ef817876a5d6..aaa8acf76b7b 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -13,7 +13,7 @@
  * This software has been developed while working on the LART
  * computing board (http://www.lartmaker.nl/), which is
  * sponsored by the Mobile Multi-media Communications
- * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications
+ * (http://www.mobimedia.org/) and Ubiquitous Communications
  * (http://www.ubicom.tudelft.nl/) projects.
  *
  * The authors can be reached at:
@@ -68,7 +68,7 @@
  * clock change in ROM and jump to that code from the kernel. The main
  * disadvantage is that the ROM has to be modified, which is not
  * possible on all SA-1100 platforms. Another disadvantage is that
- * jumping to ROM makes clock switching unecessary complicated.
+ * jumping to ROM makes clock switching unnecessary complicated.
  *
  * The idea behind this driver is that the memory configuration can be
  * changed while running from DRAM (even with interrupts turned on!)
@@ -94,48 +94,47 @@
 
 #include "generic.h"
 
-typedef struct {
+struct sa1100_dram_regs {
         int speed;
         u32 mdcnfg;
         u32 mdcas0;
         u32 mdcas1;
         u32 mdcas2;
-} sa1100_dram_regs_t;
+};
 
 
 static struct cpufreq_driver sa1100_driver;
 
-static sa1100_dram_regs_t sa1100_dram_settings[] =
-{
-        /* speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2  clock frequency */
-        {  59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  59.0 MHz */
-        {  73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  73.7 MHz */
-        {  88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  88.5 MHz */
-        { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */
-        { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */
-        { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */
-        { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */
-        { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */
-        { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */
-        { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */
-        { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */
-        { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */
-        { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */
-        { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */
-        { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */
-        { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */
+static struct sa1100_dram_regs sa1100_dram_settings[] = {
+        /*speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2,   clock freq */
+        { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  59.0 MHz */
+        { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  73.7 MHz */
+        { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  88.5 MHz */
+        {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
+        {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
+        {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
+        {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
+        {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
+        {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
+        {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
+        {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
+        {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
+        {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
+        {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
+        {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
+        {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
         { 0, 0, 0, 0, 0 } /* last entry */
 };
 
 static void sa1100_update_dram_timings(int current_speed, int new_speed)
 {
-        sa1100_dram_regs_t *settings = sa1100_dram_settings;
+        struct sa1100_dram_regs *settings = sa1100_dram_settings;
 
         /* find speed */
         while (settings->speed != 0) {
-                if(new_speed == settings->speed)
+                if (new_speed == settings->speed)
                         break;
-                
+
                 settings++;
         }
 
@@ -149,7 +148,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed)
                 /* We're going FASTER, so first relax the memory
                  * timings before changing the core frequency
                  */
-                
+
                 /* Half the memory access clock */
                 MDCNFG |= MDCNFG_CDB2;
 
@@ -184,16 +183,15 @@ static int sa1100_target(struct cpufreq_policy *policy,
 {
         unsigned int cur = sa11x0_getspeed(0);
         unsigned int new_ppcr;
-
         struct cpufreq_freqs freqs;
-        switch(relation){
+
+        new_ppcr = sa11x0_freq_to_ppcr(target_freq);
+        switch (relation) {
         case CPUFREQ_RELATION_L:
-                new_ppcr = sa11x0_freq_to_ppcr(target_freq);
                 if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
                         new_ppcr--;
                 break;
         case CPUFREQ_RELATION_H:
-                new_ppcr = sa11x0_freq_to_ppcr(target_freq);
                 if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
                     (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
                         new_ppcr--;
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 7252874d328b..675bf8ef97e8 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -16,28 +16,24 @@
  *
  * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
  */
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
 
-#include <mach/hardware.h>
 #include <asm/cputype.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
+
+#include <mach/hardware.h>
 
 #include "generic.h"
 
 #undef DEBUG
 
-static struct cpufreq_driver sa1110_driver;
-
 struct sdram_params {
-        const char name[16];
+        const char name[20];
         u_char  rows;           /* bits                          */
         u_char  cas_latency;    /* cycles                        */
         u_char  tck;            /* clock cycle time (ns)         */
@@ -107,6 +103,15 @@ static struct sdram_params sdram_tbl[] __initdata = {
                 .twr            = 8,
                 .refresh        = 64000,
                 .cas_latency    = 3,
+        }, {    /* Micron MT48LC8M16A2TG-75 */
+                .name           = "MT48LC8M16A2TG-75",
+                .rows           = 12,
+                .tck            = 8,
+                .trcd           = 20,
+                .trp            = 20,
+                .twr            = 8,
+                .refresh        = 64000,
+                .cas_latency    = 3,
         },
 };
 
@@ -180,11 +185,13 @@ sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
                 sd->mdrefr |= MDREFR_K1DB2;
 
         /* initial number of '1's in MDCAS + 1 */
-        set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
+        set_mdcas(sd->mdcas, sd_khz >= 62000,
+                ns_to_cycles(sdram->trcd, mem_khz));
 
 #ifdef DEBUG
-        printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
-                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
+        printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
+                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
+                sd->mdcas[2]);
 #endif
 }
 
@@ -213,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
 
 #ifdef DEBUG
         mdelay(250);
-        printk("new dri value = %d\n", dri);
+        printk(KERN_DEBUG "new dri value = %d\n", dri);
 #endif
 
         sdram_set_refresh(dri);
@@ -232,7 +239,7 @@ static int sa1110_target(struct cpufreq_policy *policy,
         unsigned long flags;
         unsigned int ppcr, unused;
 
-        switch(relation){
+        switch (relation) {
         case CPUFREQ_RELATION_L:
                 ppcr = sa11x0_freq_to_ppcr(target_freq);
                 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
@@ -280,11 +287,10 @@ static int sa1110_target(struct cpufreq_policy *policy,
          * We wait 20ms to be safe.
          */
         sdram_set_refresh(2);
-        if (!irqs_disabled()) {
+        if (!irqs_disabled())
                 msleep(20);
-        } else {
+        else
                 mdelay(20);
-        }
 
         /*
          * Reprogram the DRAM timings with interrupts disabled, and
@@ -295,7 +301,7 @@ static int sa1110_target(struct cpufreq_policy *policy,
         local_irq_save(flags);
         asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
         udelay(10);
-        __asm__ __volatile__("                                  \n\
+        __asm__ __volatile__("\n\
                 b       2f                                      \n\
                 .align  5                                       \n\
 1:              str     %3, [%1, #0]            @ MDCNFG        \n\
@@ -336,7 +342,9 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
         return 0;
 }
 
-static struct cpufreq_driver sa1110_driver = {
+/* sa1110_driver needs __refdata because it must remain after init registers
+ * it with cpufreq_register_driver() */
+static struct cpufreq_driver sa1110_driver __refdata = {
         .flags          = CPUFREQ_STICKY,
         .verify         = sa11x0_verify_speed,
         .target         = sa1110_target,
@@ -349,7 +357,8 @@ static struct sdram_params *sa1110_find_sdram(const char *name)
 {
         struct sdram_params *sdram;
 
-        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
+        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
+             sdram++)
                 if (strcmp(name, sdram->name) == 0)
                         return sdram;
 
@@ -369,14 +378,14 @@ static int __init sa1110_clk_init(void)
         if (!name[0]) {
                 if (machine_is_assabet())
                         name = "TC59SM716-CL3";
-
                 if (machine_is_pt_system3())
                         name = "K4S641632D";
-
                 if (machine_is_h3100())
                         name = "KM416S4030CT";
                 if (machine_is_jornada720())
-                        name = "K4S281632B-1H";
+                        name = "K4S281632B-1H";
+                if (machine_is_nanoengine())
+                        name = "MT48LC8M16A2TG-75";
         }
 
         sdram = sa1110_find_sdram(name);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 3c1fcd696714..e21f3470eece 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -16,14 +16,11 @@
 #include <linux/pm.h>
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
-#include <linux/sched.h>        /* just for sched_clock() - funny that */
 #include <linux/platform_device.h>
-#include <linux/cnt32_to_63.h>
 
 #include <asm/div64.h>
 #include <mach/hardware.h>
 #include <asm/system.h>
-#include <asm/pgtable.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/irq.h>
@@ -110,27 +107,6 @@ unsigned int sa11x0_getspeed(unsigned int cpu)
 }
 
 /*
- * This is the SA11x0 sched_clock implementation.  This has
- * a resolution of 271ns, and a maximum value of 32025597s (370 days).
- *
- * The return value is guaranteed to be monotonic in that range as
- * long as there is always less than 582 seconds between successive
- * calls to this function.
- *
- *  ( * 1E9 / 3686400 => * 78125 / 288)
- */
-unsigned long long sched_clock(void)
-{
-        unsigned long long v = cnt32_to_63(OSCR);
-
-        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
-        v *= 78125<<1;
-        do_div(v, 288<<1);
-
-        return v;
-}
-
-/*
  * Default power-off for SA1100
  */
 static void sa1100_power_off(void)
@@ -163,10 +139,15 @@ static void sa11x0_register_device(struct platform_device *dev, void *data)
 
 static struct resource sa11x0udc_resources[] = {
         [0] = {
-                .start  = 0x80000000,
-                .end    = 0x8000ffff,
+                .start  = __PREG(Ser0UDCCR),
+                .end    = __PREG(Ser0UDCCR) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser0UDC,
+                .end    = IRQ_Ser0UDC,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
@@ -184,10 +165,15 @@ static struct platform_device sa11x0udc_device = {
 
 static struct resource sa11x0uart1_resources[] = {
         [0] = {
-                .start  = 0x80010000,
-                .end    = 0x8001ffff,
+                .start  = __PREG(Ser1UTCR0),
+                .end    = __PREG(Ser1UTCR0) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser1UART,
+                .end    = IRQ_Ser1UART,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device sa11x0uart1_device = {
@@ -199,10 +185,15 @@ static struct platform_device sa11x0uart1_device = {
 
 static struct resource sa11x0uart3_resources[] = {
         [0] = {
-                .start  = 0x80050000,
-                .end    = 0x8005ffff,
+                .start  = __PREG(Ser3UTCR0),
+                .end    = __PREG(Ser3UTCR0) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser3UART,
+                .end    = IRQ_Ser3UART,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device sa11x0uart3_device = {
@@ -214,10 +205,15 @@ static struct platform_device sa11x0uart3_device = {
 
 static struct resource sa11x0mcp_resources[] = {
         [0] = {
-                .start  = 0x80060000,
-                .end    = 0x8006ffff,
+                .start  = __PREG(Ser4MCCR0),
+                .end    = __PREG(Ser4MCCR0) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser4MCP,
+                .end    = IRQ_Ser4MCP,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
@@ -244,6 +240,11 @@ static struct resource sa11x0ssp_resources[] = {
                 .end    = 0x8007ffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser4SSP,
+                .end    = IRQ_Ser4SSP,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 0c7cea0dc013..03d7376cf8a0 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -84,8 +84,6 @@ static void __init h3100_mach_init(void)
 }
 
 MACHINE_START(H3100, "Compaq iPAQ H3100")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = h3100_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index af3b71459f8d..965f64a836f8 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -125,8 +125,6 @@ static void __init h3600_mach_init(void)
 }
 
 MACHINE_START(H3600, "Compaq iPAQ H3600")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = h3600_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 51568dfc8e97..db5e434a17db 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -195,8 +195,6 @@ static void __init hackkit_init(void)
  */
 
 MACHINE_START(HACKKIT, "HackKit Cpu Board")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = hackkit_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 4f7ea012e1e5..bae8296f5dbf 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1794,7 +1794,7 @@
                         (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
                          DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
 
-#define DCSR_RUN        0x00000001      /* DMA RUNing                      */
+#define DCSR_RUN        0x00000001      /* DMA running                     */
 #define DCSR_IE         0x00000002      /* DMA Interrupt Enable            */
 #define DCSR_ERROR      0x00000004      /* DMA ERROR                       */
 #define DCSR_DONEA      0x00000008      /* DONE DMA transfer buffer A      */
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 336adccea542..0cd0fc9635b6 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,33 +12,37 @@
 */
 #include <mach/hardware.h>
 
-                .macro  addruart, rx, tmp
-                mrc     p15, 0, \rx, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000        @ physical base address
-                movne   \rx, #0xf8000000        @ virtual address
+                .macro  addruart, rp, rv
+                mrc     p15, 0, \rp, c1, c0
+                tst     \rp, #1                 @ MMU enabled?
+                moveq   \rp, #0x80000000        @ physical base address
+                movne   \rp, #0xf8000000        @ virtual address
 
                 @ We probe for the active serial port here, coherently with
                 @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
                 @ We assume r1 can be clobbered.
 
                 @ see if Ser3 is active
-                add     \rx, \rx, #0x00050000
-                ldr     r1, [\rx, #UTCR3]
-                tst     r1, #UTCR3_TXE
+                add     \rp, \rp, #0x00050000
+                ldr     \rv, [\rp, #UTCR3]
+                tst     \rv, #UTCR3_TXE
 
                 @ if Ser3 is inactive, then try Ser1
-                addeq   \rx, \rx, #(0x00010000 - 0x00050000)
-                ldreq   r1, [\rx, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
+                addeq   \rp, \rp, #(0x00010000 - 0x00050000)
+                ldreq   \rv, [\rp, #UTCR3]
+                tsteq   \rv, #UTCR3_TXE
 
                 @ if Ser1 is inactive, then try Ser2
-                addeq   \rx, \rx, #(0x00030000 - 0x00010000)
-                ldreq   r1, [\rx, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
+                addeq   \rp, \rp, #(0x00030000 - 0x00010000)
+                ldreq   \rv, [\rp, #UTCR3]
+                tsteq   \rv, #UTCR3_TXE
+
+                @ clear top bits, and generate both phys and virt addresses
+                lsl     \rp, \rp, #8
+                lsr     \rp, \rp, #8
+                orr     \rv, \rp, #0xf8000000   @ virtual
+                orr     \rp, \rp, #0x80000000   @ physical
 
-                @ if all ports are inactive, then there is nothing we can do
-                moveq   pc, lr
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de4..967ae7684390 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void)
 #include "SA-1101.h"
 #endif
 
+#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO          0
+#define PCIBIOS_MIN_MEM         0
+#define pcibios_assign_all_busses()     1
+#define HAVE_ARCH_PCI_SET_DMA_MASK      1
+#endif
+
+
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index 128a1dfa96b9..cff31ee246b7 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -12,20 +12,10 @@
 /*
  * Physical DRAM offset is 0xc0000000 on the SA1100
  */
-#define PHYS_OFFSET     UL(0xc0000000)
-
-#ifndef __ASSEMBLY__
+#define PLAT_PHYS_OFFSET        UL(0xc0000000)
 
 #ifdef CONFIG_SA1111
-void sa1111_adjust_zones(unsigned long *size, unsigned long *holes);
-
-#define arch_adjust_zones(size, holes) \
-        sa1111_adjust_zones(size, holes)
-
-#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
-#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_1M)
-
-#endif
+#define ARM_DMA_ZONE_SIZE       SZ_1M
 #endif
 
 /*
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
new file mode 100644
index 000000000000..14f8382d0665
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/nanoengine.h
+ *
+ * This file contains the hardware specific definitions for nanoEngine.
+ * Only include this file from SA1100-specific files.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_ARCH_NANOENGINE_H
+#define __ASM_ARCH_NANOENGINE_H
+
+#include <mach/irqs.h>
+
+#define GPIO_PC_READY0  GPIO_GPIO(11) /* ready for socket 0 (active high)*/
+#define GPIO_PC_READY1  GPIO_GPIO(12) /* ready for socket 1 (active high) */
+#define GPIO_PC_CD0     GPIO_GPIO(13) /* detect for socket 0 (active low) */
+#define GPIO_PC_CD1     GPIO_GPIO(14) /* detect for socket 1 (active low) */
+#define GPIO_PC_RESET0  GPIO_GPIO(15) /* reset socket 0 */
+#define GPIO_PC_RESET1  GPIO_GPIO(16) /* reset socket 1 */
+
+#define NANOENGINE_IRQ_GPIO_PCI         IRQ_GPIO0
+#define NANOENGINE_IRQ_GPIO_PC_READY0   IRQ_GPIO11
+#define NANOENGINE_IRQ_GPIO_PC_READY1   IRQ_GPIO12
+#define NANOENGINE_IRQ_GPIO_PC_CD0      IRQ_GPIO13
+#define NANOENGINE_IRQ_GPIO_PC_CD1      IRQ_GPIO14
+
+/*
+ * nanoEngine Memory Map:
+ *
+ * 0000.0000 - 003F.0000 -   4 MB Flash
+ * C000.0000 - C1FF.FFFF -  32 MB SDRAM
+ * 1860.0000 - 186F.FFFF -   1 MB Internal PCI Memory Read/Write
+ * 18A1.0000 - 18A1.FFFF -  64 KB Internal PCI Config Space
+ * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
+ * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
+ *
+ */
+
+#define NANO_PCI_MEM_RW_PHYS            0x18600000
+#define NANO_PCI_MEM_RW_VIRT            0xf1000000
+#define NANO_PCI_MEM_RW_SIZE            SZ_1M
+#define NANO_PCI_CONFIG_SPACE_PHYS      0x18A10000
+#define NANO_PCI_CONFIG_SPACE_VIRT      0xf2000000
+#define NANO_PCI_CONFIG_SPACE_SIZE      SZ_64K
+
+#endif
+
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3093d46a9c6f..dfbf824a69fa 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -14,7 +14,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/syscore_ops.h>
 
 #include <mach/hardware.h>
 #include <asm/mach/irq.h>
@@ -37,14 +37,14 @@ static int GPIO_IRQ_mask = (1 << 11) - 1;
 #define GPIO_11_27_IRQ(i)       ((i) - 21)
 #define GPIO11_27_MASK(irq)     (1 << GPIO_11_27_IRQ(irq))
 
-static int sa1100_gpio_type(unsigned int irq, unsigned int type)
+static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
 {
         unsigned int mask;
 
-        if (irq <= 10)
-                mask = 1 << irq;
+        if (d->irq <= 10)
+                mask = 1 << d->irq;
         else
-                mask = GPIO11_27_MASK(irq);
+                mask = GPIO11_27_MASK(d->irq);
 
         if (type == IRQ_TYPE_PROBE) {
                 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
@@ -70,37 +70,37 @@ static int sa1100_gpio_type(unsigned int irq, unsigned int type)
 /*
  * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
  */
-static void sa1100_low_gpio_ack(unsigned int irq)
+static void sa1100_low_gpio_ack(struct irq_data *d)
 {
-        GEDR = (1 << irq);
+        GEDR = (1 << d->irq);
 }
 
-static void sa1100_low_gpio_mask(unsigned int irq)
+static void sa1100_low_gpio_mask(struct irq_data *d)
 {
-        ICMR &= ~(1 << irq);
+        ICMR &= ~(1 << d->irq);
 }
 
-static void sa1100_low_gpio_unmask(unsigned int irq)
+static void sa1100_low_gpio_unmask(struct irq_data *d)
 {
-        ICMR |= 1 << irq;
+        ICMR |= 1 << d->irq;
 }
 
-static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
+static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
 {
         if (on)
-                PWER |= 1 << irq;
+                PWER |= 1 << d->irq;
         else
-                PWER &= ~(1 << irq);
+                PWER &= ~(1 << d->irq);
         return 0;
 }
 
 static struct irq_chip sa1100_low_gpio_chip = {
         .name           = "GPIO-l",
-        .ack            = sa1100_low_gpio_ack,
-        .mask           = sa1100_low_gpio_mask,
-        .unmask         = sa1100_low_gpio_unmask,
-        .set_type       = sa1100_gpio_type,
-        .set_wake       = sa1100_low_gpio_wake,
+        .irq_ack        = sa1100_low_gpio_ack,
+        .irq_mask       = sa1100_low_gpio_mask,
+        .irq_unmask     = sa1100_low_gpio_unmask,
+        .irq_set_type   = sa1100_gpio_type,
+        .irq_set_wake   = sa1100_low_gpio_wake,
 };
 
 /*
@@ -139,16 +139,16 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
  * In addition, the IRQs are all collected up into one bit in the
  * interrupt controller registers.
  */
-static void sa1100_high_gpio_ack(unsigned int irq)
+static void sa1100_high_gpio_ack(struct irq_data *d)
 {
-        unsigned int mask = GPIO11_27_MASK(irq);
+        unsigned int mask = GPIO11_27_MASK(d->irq);
 
         GEDR = mask;
 }
 
-static void sa1100_high_gpio_mask(unsigned int irq)
+static void sa1100_high_gpio_mask(struct irq_data *d)
 {
-        unsigned int mask = GPIO11_27_MASK(irq);
+        unsigned int mask = GPIO11_27_MASK(d->irq);
 
         GPIO_IRQ_mask &= ~mask;
 
@@ -156,9 +156,9 @@ static void sa1100_high_gpio_mask(unsigned int irq)
         GFER &= ~mask;
 }
 
-static void sa1100_high_gpio_unmask(unsigned int irq)
+static void sa1100_high_gpio_unmask(struct irq_data *d)
 {
-        unsigned int mask = GPIO11_27_MASK(irq);
+        unsigned int mask = GPIO11_27_MASK(d->irq);
 
         GPIO_IRQ_mask |= mask;
 
@@ -166,44 +166,44 @@ static void sa1100_high_gpio_unmask(unsigned int irq)
         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 }
 
-static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
+static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
 {
         if (on)
-                PWER |= GPIO11_27_MASK(irq);
+                PWER |= GPIO11_27_MASK(d->irq);
         else
-                PWER &= ~GPIO11_27_MASK(irq);
+                PWER &= ~GPIO11_27_MASK(d->irq);
         return 0;
 }
 
 static struct irq_chip sa1100_high_gpio_chip = {
         .name           = "GPIO-h",
-        .ack            = sa1100_high_gpio_ack,
-        .mask           = sa1100_high_gpio_mask,
-        .unmask         = sa1100_high_gpio_unmask,
-        .set_type       = sa1100_gpio_type,
-        .set_wake       = sa1100_high_gpio_wake,
+        .irq_ack        = sa1100_high_gpio_ack,
+        .irq_mask       = sa1100_high_gpio_mask,
+        .irq_unmask     = sa1100_high_gpio_unmask,
+        .irq_set_type   = sa1100_gpio_type,
+        .irq_set_wake   = sa1100_high_gpio_wake,
 };
 
 /*
  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
  * this is for internal IRQs i.e. from 11 to 31.
  */
-static void sa1100_mask_irq(unsigned int irq)
+static void sa1100_mask_irq(struct irq_data *d)
 {
-        ICMR &= ~(1 << irq);
+        ICMR &= ~(1 << d->irq);
 }
 
-static void sa1100_unmask_irq(unsigned int irq)
+static void sa1100_unmask_irq(struct irq_data *d)
 {
-        ICMR |= (1 << irq);
+        ICMR |= (1 << d->irq);
 }
 
 /*
  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
  */
-static int sa1100_set_wake(unsigned int irq, unsigned int on)
+static int sa1100_set_wake(struct irq_data *d, unsigned int on)
 {
-        if (irq == IRQ_RTCAlrm) {
+        if (d->irq == IRQ_RTCAlrm) {
                 if (on)
                         PWER |= PWER_RTC;
                 else
@@ -215,10 +215,10 @@ static int sa1100_set_wake(unsigned int irq, unsigned int on)
 
 static struct irq_chip sa1100_normal_chip = {
         .name           = "SC",
-        .ack            = sa1100_mask_irq,
-        .mask           = sa1100_mask_irq,
-        .unmask         = sa1100_unmask_irq,
-        .set_wake       = sa1100_set_wake,
+        .irq_ack        = sa1100_mask_irq,
+        .irq_mask       = sa1100_mask_irq,
+        .irq_unmask     = sa1100_unmask_irq,
+        .irq_set_wake   = sa1100_set_wake,
 };
 
 static struct resource irq_resource = {
@@ -234,7 +234,7 @@ static struct sa1100irq_state {
         unsigned int    iccr;
 } sa1100irq_state;
 
-static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
+static int sa1100irq_suspend(void)
 {
         struct sa1100irq_state *st = &sa1100irq_state;
 
@@ -264,7 +264,7 @@ static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
         return 0;
 }
 
-static int sa1100irq_resume(struct sys_device *dev)
+static void sa1100irq_resume(void)
 {
         struct sa1100irq_state *st = &sa1100irq_state;
 
@@ -277,24 +277,17 @@ static int sa1100irq_resume(struct sys_device *dev)
 
                 ICMR = st->icmr;
         }
-        return 0;
 }
 
-static struct sysdev_class sa1100irq_sysclass = {
-        .name           = "sa11x0-irq",
+static struct syscore_ops sa1100irq_syscore_ops = {
         .suspend        = sa1100irq_suspend,
         .resume         = sa1100irq_resume,
 };
 
-static struct sys_device sa1100irq_device = {
-        .id             = 0,
-        .cls            = &sa1100irq_sysclass,
-};
-
 static int __init sa1100irq_init_devicefs(void)
 {
-        sysdev_class_register(&sa1100irq_sysclass);
-        return sysdev_register(&sa1100irq_device);
+        register_syscore_ops(&sa1100irq_syscore_ops);
+        return 0;
 }
 
 device_initcall(sa1100irq_init_devicefs);
@@ -323,28 +316,28 @@ void __init sa1100_init_irq(void)
         ICCR = 1;
 
         for (irq = 0; irq <= 10; irq++) {
-                set_irq_chip(irq, &sa1100_low_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         for (irq = 12; irq <= 31; irq++) {
-                set_irq_chip(irq, &sa1100_normal_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &sa1100_normal_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
         for (irq = 32; irq <= 48; irq++) {
-                set_irq_chip(irq, &sa1100_high_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         /*
          * Install handler for GPIO 11-27 edge detect interrupts
          */
-        set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
-        set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
+        irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
+        irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 
         sa1100_init_gpio();
 }
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index d3ec620618f1..491ac9f20fb4 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -364,8 +364,6 @@ static void __init jornada720_mach_init(void)
 
 MACHINE_START(JORNADA720, "HP Jornada 720")
         /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = jornada720_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index 9d490c66891c..f50b00bd18a0 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -29,7 +29,7 @@ static unsigned long jornada_ssp_flags;
 /**
  * jornada_ssp_reverse - reverses input byte
  *
- * we need to reverse all data we recieve from the mcu due to its physical location
+ * we need to reverse all data we receive from the mcu due to its physical location
  * returns : 01110111 -> 11101110
  */
 u8 inline jornada_ssp_reverse(u8 byte)
@@ -179,7 +179,7 @@ static int __devinit jornada_ssp_probe(struct platform_device *dev)
 
 static int jornada_ssp_remove(struct platform_device *dev)
 {
-        /* Note that this doesnt actually remove the driver, since theres nothing to remove
+        /* Note that this doesn't actually remove the driver, since theres nothing to remove
          * It just makes sure everything is turned off */
         GPSR = GPIO_GPIO25;
         ssp_exit();
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 68069d6dc07a..7b9556b59057 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -61,8 +61,6 @@ static void __init lart_map_io(void)
 }
 
 MACHINE_START(LART, "LART")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = lart_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
new file mode 100644
index 000000000000..72087f0658b7
--- /dev/null
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -0,0 +1,119 @@
+/*
+ * linux/arch/arm/mach-sa1100/nanoengine.c
+ *
+ * Bright Star Engineering's nanoEngine board init code.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/root_dev.h>
+
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include <mach/hardware.h>
+#include <mach/nanoengine.h>
+
+#include "generic.h"
+
+/* Flash bank 0 */
+static struct mtd_partition nanoengine_partitions[] = {
+        {
+                .name   = "nanoEngine boot firmware and parameter table",
+                .size           = 0x00010000,  /* 32K */
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel/initrd reserved",
+                .size           = 0x002f0000,
+                .offset         = 0x00010000,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "experimental filesystem allocation",
+                .size           = 0x00100000,
+                .offset         = 0x00300000,
+                .mask_flags     = MTD_WRITEABLE,
+        }
+};
+
+static struct flash_platform_data nanoengine_flash_data = {
+        .map_name       = "jedec_probe",
+        .parts          = nanoengine_partitions,
+        .nr_parts       = ARRAY_SIZE(nanoengine_partitions),
+};
+
+static struct resource nanoengine_flash_resources[] = {
+        {
+                .start  = SA1100_CS0_PHYS,
+                .end    = SA1100_CS0_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = SA1100_CS1_PHYS,
+                .end    = SA1100_CS1_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct map_desc nanoengine_io_desc[] __initdata = {
+        {
+                /* System Registers */
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0x10000000),
+                .length         = 0x00100000,
+                .type           = MT_DEVICE
+        }, {
+                /* Internal PCI Memory Read/Write */
+                .virtual        = NANO_PCI_MEM_RW_VIRT,
+                .pfn            = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
+                .length         = NANO_PCI_MEM_RW_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                /* Internal PCI Config Space */
+                .virtual        = NANO_PCI_CONFIG_SPACE_VIRT,
+                .pfn            = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
+                .length         = NANO_PCI_CONFIG_SPACE_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+
+static void __init nanoengine_map_io(void)
+{
+        sa1100_map_io();
+        iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
+
+        sa1100_register_uart(0, 1);
+        sa1100_register_uart(1, 2);
+        sa1100_register_uart(2, 3);
+        Ser1SDCR0 |= SDCR0_UART;
+        /* disable IRDA -- UART2 is used as a normal serial port */
+        Ser2UTCR4 = 0;
+        Ser2HSCR0 = 0;
+}
+
+static void __init nanoengine_init(void)
+{
+        sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
+                ARRAY_SIZE(nanoengine_flash_resources));
+}
+
+MACHINE_START(NANOENGINE, "BSE nanoEngine")
+        .boot_params    = 0xc0000000,
+        .map_io         = nanoengine_map_io,
+        .init_irq       = sa1100_init_irq,
+        .timer          = &sa1100_timer,
+        .init_machine   = nanoengine_init,
+MACHINE_END
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index c601a75a333d..b4fa53a1427e 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -35,7 +35,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                 /*
                  * Acknowledge the parent IRQ.
                  */
-                desc->chip->ack(irq);
+                desc->irq_data.chip->irq_ack(&desc->irq_data);
 
                 /*
                  * Read the interrupt reason register.  Let's have all
@@ -53,7 +53,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                  * recheck the register for any pending IRQs.
                  */
                 if (irr & (IRR_ETHERNET | IRR_USAR)) {
-                        desc->chip->mask(irq);
+                        desc->irq_data.chip->irq_mask(&desc->irq_data);
 
                         /*
                          * Ack the interrupt now to prevent re-entering
@@ -61,7 +61,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                          * since we'll check the IRR register prior to
                          * leaving.
                          */
-                        desc->chip->ack(irq);
+                        desc->irq_data.chip->irq_ack(&desc->irq_data);
 
                         if (irr & IRR_ETHERNET) {
                                 generic_handle_irq(IRQ_NEPONSET_SMC9196);
@@ -71,7 +71,7 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                                 generic_handle_irq(IRQ_NEPONSET_USAR);
                         }
 
-                        desc->chip->unmask(irq);
+                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
                 }
 
                 if (irr & IRR_SA1111) {
@@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev)
         /*
          * Install handler for GPIO25.
          */
-        set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
-        set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler);
+        irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
+        irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler);
 
         /*
          * We would set IRQ_GPIO25 to be a wake-up IRQ, but
@@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev)
          * Setup other Neponset IRQs.  SA1111 will be done by the
          * generic SA1111 code.
          */
-        set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
+        irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
         set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
-        set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
+        irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
         set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
 
         /*
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
new file mode 100644
index 000000000000..fba7a913f12b
--- /dev/null
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -0,0 +1,284 @@
+/*
+ * linux/arch/arm/mach-sa1100/pci-nanoengine.c
+ *
+ * PCI functions for BSE nanoEngine PCI
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+#include <mach/nanoengine.h>
+
+static DEFINE_SPINLOCK(nano_lock);
+
+static int nanoengine_get_pci_address(struct pci_bus *bus,
+        unsigned int devfn, int where, unsigned long *address)
+{
+        int ret = PCIBIOS_DEVICE_NOT_FOUND;
+        unsigned int busnr = bus->number;
+
+        *address = NANO_PCI_CONFIG_SPACE_VIRT +
+                ((bus->number << 16) | (devfn << 8) | (where & ~3));
+
+        ret = (busnr > 255 || devfn > 255 || where > 255) ?
+                PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+
+        return ret;
+}
+
+static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+        int size, u32 *val)
+{
+        int ret;
+        unsigned long address;
+        unsigned long flags;
+        u32 v;
+
+        /* nanoEngine PCI bridge does not return -1 for a non-existing
+         * device. We must fake the answer. We know that the only valid
+         * device is device zero at bus 0, which is the network chip. */
+        if (bus->number != 0 || (devfn >> 3) != 0) {
+                v = -1;
+                nanoengine_get_pci_address(bus, devfn, where, &address);
+                goto exit_function;
+        }
+
+        spin_lock_irqsave(&nano_lock, flags);
+
+        ret = nanoengine_get_pci_address(bus, devfn, where, &address);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        v = __raw_readl(address);
+
+        spin_unlock_irqrestore(&nano_lock, flags);
+
+        v >>= ((where & 3) * 8);
+        v &= (unsigned long)(-1) >> ((4 - size) * 8);
+
+exit_function:
+        *val = v;
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+        int size, u32 val)
+{
+        int ret;
+        unsigned long address;
+        unsigned long flags;
+        unsigned shift;
+        u32 v;
+
+        shift = (where & 3) * 8;
+
+        spin_lock_irqsave(&nano_lock, flags);
+
+        ret = nanoengine_get_pci_address(bus, devfn, where, &address);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        v = __raw_readl(address);
+        switch (size) {
+        case 1:
+                v &= ~(0xFF << shift);
+                v |= val << shift;
+                break;
+        case 2:
+                v &= ~(0xFFFF << shift);
+                v |= val << shift;
+                break;
+        case 4:
+                v = val;
+                break;
+        }
+        __raw_writel(v, address);
+
+        spin_unlock_irqrestore(&nano_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops pci_nano_ops = {
+        .read   = nanoengine_read_config,
+        .write  = nanoengine_write_config,
+};
+
+static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return NANOENGINE_IRQ_GPIO_PCI;
+}
+
+struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
+}
+
+static struct resource pci_io_ports = {
+        .name   = "PCI IO",
+        .start  = 0x400,
+        .end    = 0x7FF,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource pci_non_prefetchable_memory = {
+        .name   = "PCI non-prefetchable",
+        .start  = NANO_PCI_MEM_RW_PHYS,
+        /* nanoEngine documentation says there is a 1 Megabyte window here,
+         * but PCI reports just 128 + 8 kbytes. */
+        .end    = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
+/*      .end    = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
+        .flags  = IORESOURCE_MEM,
+};
+
+/*
+ * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
+ * overlaps with previously defined memory.
+ *
+ * Here is what happens:
+ *
+# dmesg
+...
+pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
+pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
+pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
+pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
+pci 0000:00:00.0: supports D1 D2
+pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
+pci 0000:00:00.0: PME# disabled
+PCI: bus0: Fast back to back transfers enabled
+pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
+pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
+pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
+pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
+pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
+pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
+pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
+ *
+ * On the other hand, if we do not request the prefetchable memory resource,
+ * linux will alloc it first and the two non-prefetchable memory areas that
+ * are our real interest will not be mapped. So we choose to map it to an
+ * unused area. It gets recognized as expansion ROM, but becomes disabled.
+ *
+ * Here is what happens then:
+ *
+# dmesg
+...
+pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
+pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
+pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
+pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
+pci 0000:00:00.0: supports D1 D2
+pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
+pci 0000:00:00.0: PME# disabled
+PCI: bus0: Fast back to back transfers enabled
+pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
+pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
+pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
+pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
+pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
+pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
+pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
+
+# lspci -vv -s 0000:00:00.0
+00:00.0 Class 0200: Device 8086:1209 (rev 09)
+        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
+        Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
+        Interrupt: pin A routed to IRQ 0
+        Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
+        Region 1: I/O ports at 0400 [size=64]
+        Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
+        [virtual] Expansion ROM at 78000000 [disabled] [size=1M]
+        Capabilities: [dc] Power Management version 2
+                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
+                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
+        Kernel driver in use: e100
+        Kernel modules: e100
+ *
+ */
+static struct resource pci_prefetchable_memory = {
+        .name   = "PCI prefetchable",
+        .start  = 0x78000000,
+        .end    = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
+        .flags  = IORESOURCE_MEM  | IORESOURCE_PREFETCH,
+};
+
+static int __init pci_nanoengine_setup_resources(struct resource **resource)
+{
+        if (request_resource(&ioport_resource, &pci_io_ports)) {
+                printk(KERN_ERR "PCI: unable to allocate io port region\n");
+                return -EBUSY;
+        }
+        if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
+                release_resource(&pci_io_ports);
+                printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
+                return -EBUSY;
+        }
+        if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
+                release_resource(&pci_io_ports);
+                release_resource(&pci_non_prefetchable_memory);
+                printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
+                return -EBUSY;
+        }
+        resource[0] = &pci_io_ports;
+        resource[1] = &pci_non_prefetchable_memory;
+        resource[2] = &pci_prefetchable_memory;
+
+        return 1;
+}
+
+int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
+{
+        int ret = 0;
+
+        if (nr == 0) {
+                sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
+                sys->io_offset = 0x400;
+                ret = pci_nanoengine_setup_resources(sys->resource);
+                /* Enable alternate memory bus master mode, see
+                 * "Intel StrongARM SA1110 Developer's Manual",
+                 * section 10.8, "Alternate Memory Bus Master Mode". */
+                GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
+                GAFR |= GPIO_MBGNT | GPIO_MBREQ;
+                TUCR |= TUCR_MBGPIO;
+        }
+
+        return ret;
+}
+
+static struct hw_pci nanoengine_pci __initdata = {
+        .map_irq                = pci_nanoengine_map_irq,
+        .nr_controllers         = 1,
+        .scan                   = pci_nanoengine_scan_bus,
+        .setup                  = pci_nanoengine_setup,
+};
+
+static int __init nanoengine_pci_init(void)
+{
+        if (machine_is_nanoengine())
+                pci_common_init(&nanoengine_pci);
+        return 0;
+}
+
+subsys_initcall(nanoengine_pci_init);
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 1ccd6018d3a3..65161f2bea29 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -142,12 +142,10 @@ static void __init pleb_map_io(void)
 
         GPDR &= ~GPIO_ETH0_IRQ;
 
-        set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
 }
 
 MACHINE_START(PLEB, "PLEB")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .map_io         = pleb_map_io,
         .init_irq       = sa1100_init_irq,
         .timer          = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index c83fdc80edfd..c4661aab22fb 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -32,8 +32,7 @@
 #include <asm/system.h>
 #include <asm/mach/time.h>
 
-extern void sa1100_cpu_suspend(void);
-extern void sa1100_cpu_resume(void);
+extern void sa1100_cpu_suspend(long);
 
 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
@@ -73,10 +72,10 @@ static int sa11x0_pm_enter(suspend_state_t state)
         RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
 
         /* set resume return address */
-        PSPR = virt_to_phys(sa1100_cpu_resume);
+        PSPR = virt_to_phys(cpu_resume);
 
         /* go zzz */
-        sa1100_cpu_suspend();
+        sa1100_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
 
         cpu_init();
 
@@ -115,12 +114,7 @@ static int sa11x0_pm_enter(suspend_state_t state)
         return 0;
 }
 
-unsigned long sleep_phys_sp(void *sp)
-{
-        return virt_to_phys(sp);
-}
-
-static struct platform_suspend_ops sa11x0_pm_ops = {
+static const struct platform_suspend_ops sa11x0_pm_ops = {
         .enter          = sa11x0_pm_enter,
         .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 85e82bb73d7e..7917b2405579 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -82,8 +82,6 @@ static void __init shannon_map_io(void)
 }
 
 MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = shannon_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 49cfd64663ac..cfb76077bd25 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -166,9 +166,6 @@ static void __init simpad_map_io(void)
         PCFR = 0;
         PSDR = 0;
 
-        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
-                              ARRAY_SIZE(simpad_flash_resources));
-        sa11x0_register_mcp(&simpad_mcp_data);
 }
 
 static void simpad_power_off(void)
@@ -216,6 +213,10 @@ static int __init simpad_init(void)
 
         pm_power_off = simpad_power_off;
 
+        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
+                              ARRAY_SIZE(simpad_flash_resources));
+        sa11x0_register_mcp(&simpad_mcp_data);
+
         ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         if(ret)
                 printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device");
@@ -228,8 +229,6 @@ arch_initcall(simpad_init);
 
 MACHINE_START(SIMPAD, "Simpad")
         /* Maintainer: Holger Freyther */
-        .phys_io        = 0x80000000,
-        .io_pg_offst    = ((0xf8000000) >> 18) & 0xfffc,
         .boot_params    = 0xc0000100,
         .map_io         = simpad_map_io,
         .init_irq       = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 80f31bad707c..04f2a618d4ef 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -20,12 +20,7 @@
 #include <asm/assembler.h>
 #include <mach/hardware.h>
 
-
-
                 .text
-
-
-
 /*
  * sa1100_cpu_suspend()
  *
@@ -34,27 +29,10 @@
  */
 
 ENTRY(sa1100_cpu_suspend)
-
         stmfd   sp!, {r4 - r12, lr}             @ save registers on stack
-
-        @ get coprocessor registers
-        mrc     p15, 0, r4, c3, c0, 0           @ domain ID
-        mrc     p15, 0, r5, c2, c0, 0           @ translation table base addr
-        mrc     p15, 0, r6, c13, c0, 0          @ PID
-        mrc     p15, 0, r7, c1, c0, 0           @ control reg
-
-        @ store them plus current virtual stack ptr on stack
-        mov     r8, sp
-        stmfd   sp!, {r4 - r8}
-
-        @ preserve phys address of stack
-        mov     r0, sp
-        bl      sleep_phys_sp
-        ldr     r1, =sleep_save_sp
-        str     r0, [r1]
-
-        @ clean data cache and invalidate WB
-        bl      v4wb_flush_kern_cache_all
+        mov     r1, r0
+        ldr     r3, =sa1100_cpu_resume          @ return function
+        bl      cpu_suspend
 
         @ disable clock switching
         mcr     p15, 0, r1, c15, c2, 2
@@ -166,50 +144,8 @@ sa1110_sdram_controller_fix:
  * cpu_sa1100_resume()
  *
  * entry point from bootloader into kernel during resume
- *
- * Note: Yes, part of the following code is located into the .data section.
- *       This is to allow sleep_save_sp to be accessed with a relative load
- *       while we can't rely on any MMU translation.  We could have put
- *       sleep_save_sp in the .text section as well, but some setups might
- *       insist on it to be truly read-only.
  */
-
-        .data
-        .align 5
-ENTRY(sa1100_cpu_resume)
-        mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-        msr     cpsr_c, r0                      @ set SVC, irqs off
-
-        ldr     r0, sleep_save_sp               @ stack phys addr
-        ldr     r2, =resume_after_mmu           @ its absolute virtual address
-        ldmfd   r0, {r4 - r7, sp}               @ CP regs + virt stack ptr
-
-        mov     r1, #0
-        mcr     p15, 0, r1, c8, c7, 0           @ flush I+D TLBs
-        mcr     p15, 0, r1, c7, c7, 0           @ flush I&D cache
-        mcr     p15, 0, r1, c9, c0, 0           @ invalidate RB
-        mcr     p15, 0, r1, c9, c0, 5           @ allow user space to use RB
-
-        mcr     p15, 0, r4, c3, c0, 0           @ domain ID
-        mcr     p15, 0, r5, c2, c0, 0           @ translation table base addr
-        mcr     p15, 0, r6, c13, c0, 0          @ PID
-        b       resume_turn_on_mmu              @ cache align execution
-
         .align 5
-resume_turn_on_mmu:
-        mcr     p15, 0, r7, c1, c0, 0           @ turn on MMU, caches, etc.
-        nop
-        mov     pc, r2                          @ jump to virtual addr
-        nop
-        nop
-        nop
-
-sleep_save_sp:
-        .word   0                               @ preserve stack phys ptr here
-
-        .text
-resume_after_mmu:
+sa1100_cpu_resume:
         mcr     p15, 0, r1, c15, c1, 2          @ enable clock switching
         ldmfd   sp!, {r4 - r12, pc}             @ return to caller
-
-
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 74b6e0e570b6..fa6602491d54 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -12,12 +12,39 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/sched.h>        /* just for sched_clock() - funny that */
 #include <linux/timex.h>
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <mach/hardware.h>
 
+/*
+ * This is the SA11x0 sched_clock implementation.
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+/*
+ * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz,
+ * NSEC_PER_SEC, 60).
+ * This gives a resolution of about 271ns and a wrap period of about 19min.
+ */
+#define SC_MULT         2275555556u
+#define SC_SHIFT        23
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = OSCR;
+        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+
+static void notrace sa1100_update_sched_clock(void)
+{
+        u32 cyc = OSCR;
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
 #define MIN_OSCR_DELTA 2
 
 static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
@@ -65,26 +92,11 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
 static struct clock_event_device ckevt_sa1100_osmr0 = {
         .name           = "osmr0",
         .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
         .rating         = 200,
         .set_next_event = sa1100_osmr0_set_next_event,
         .set_mode       = sa1100_osmr0_set_mode,
 };
 
-static cycle_t sa1100_read_oscr(struct clocksource *s)
-{
-        return OSCR;
-}
-
-static struct clocksource cksrc_sa1100_oscr = {
-        .name           = "oscr",
-        .rating         = 200,
-        .read           = sa1100_read_oscr,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
 static struct irqaction sa1100_timer_irq = {
         .name           = "ost0",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
@@ -94,23 +106,23 @@ static struct irqaction sa1100_timer_irq = {
 
 static void __init sa1100_timer_init(void)
 {
-        OIER = 0;               /* disable any timer interrupts */
-        OSSR = 0xf;             /* clear status on all timers */
+        OIER = 0;
+        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
-        ckevt_sa1100_osmr0.mult =
-                div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
+        init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
+                               3686400, SC_MULT, SC_SHIFT);
+
+        clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
         ckevt_sa1100_osmr0.max_delta_ns =
                 clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
         ckevt_sa1100_osmr0.min_delta_ns =
                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
         ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
 
-        cksrc_sa1100_oscr.mult =
-                clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
-
         setup_irq(IRQ_OST0, &sa1100_timer_irq);
 
-        clocksource_register(&cksrc_sa1100_oscr);
+        clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
+                clocksource_mmio_readl_up);
         clockevents_register_device(&ckevt_sa1100_osmr0);
 }