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authorKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:34:55 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:34:55 -0400
commitf2b7e3c54a304677a1142829fb5913595885379f (patch)
tree1eb941524c7325672f947dab525d96228b362e20 /arch/arm/mach-s5pv210
parent6b8eda04ffdc24b68d379a32358f4f09a425a380 (diff)
parent0fdb480e7fb1ecdd4076ddf8b6ab16b0d77406c1 (diff)
Merge branch 'next-s5p' into for-next
Conflicts: arch/arm/mach-s5pv210/mach-aquila.c arch/arm/mach-s5pv210/mach-goni.c
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/system.h7
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c30
6 files changed, 63 insertions, 66 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index e1d3c453db81..e1c020e5a49b 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -36,7 +36,7 @@
36 36
37/* VIC1: ARM, Power, Memory, Connectivity, Storage */ 37/* VIC1: ARM, Power, Memory, Connectivity, Storage */
38 38
39#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) 39#define IRQ_PMU S5P_IRQ_VIC1(0)
40#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) 40#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
41#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) 41#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
42#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) 42#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
index 1ca04d5025b3..af8a200b2135 100644
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ b/arch/arm/mach-s5pv210/include/mach/system.h
@@ -13,12 +13,9 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16static void arch_idle(void) 16#include <plat/system-reset.h>
17{
18 /* nothing here yet */
19}
20 17
21static void arch_reset(char mode, const char *cmd) 18static void arch_idle(void)
22{ 19{
23 /* nothing here yet */ 20 /* nothing here yet */
24} 21}
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0c894010e278..a6b4ed364840 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,52 +38,52 @@
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39 39
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 40/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 41#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 42 S3C2410_UCON_RXILEVEL | \
43 S3C2410_UCON_TXIRQMODE | \ 43 S3C2410_UCON_TXIRQMODE | \
44 S3C2410_UCON_RXIRQMODE | \ 44 S3C2410_UCON_RXIRQMODE | \
45 S3C2410_UCON_RXFIFO_TOI | \ 45 S3C2410_UCON_RXFIFO_TOI | \
46 S3C2443_UCON_RXERR_IRQEN) 46 S3C2443_UCON_RXERR_IRQEN)
47 47
48#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 48#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
49 49
50#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE 50#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
51 51
52static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = { 52static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
53 [0] = { 53 [0] = {
54 .hwport = 0, 54 .hwport = 0,
55 .flags = 0, 55 .flags = 0,
56 .ucon = S5PV210_UCON_DEFAULT, 56 .ucon = AQUILA_UCON_DEFAULT,
57 .ulcon = S5PV210_ULCON_DEFAULT, 57 .ulcon = AQUILA_ULCON_DEFAULT,
58 /* 58 /*
59 * Actually UART0 can support 256 bytes fifo, but aquila board 59 * Actually UART0 can support 256 bytes fifo, but aquila board
60 * supports 128 bytes fifo because of initial chip bug 60 * supports 128 bytes fifo because of initial chip bug
61 */ 61 */
62 .ufcon = S5PV210_UFCON_DEFAULT | 62 .ufcon = AQUILA_UFCON_DEFAULT |
63 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128, 63 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
64 }, 64 },
65 [1] = { 65 [1] = {
66 .hwport = 1, 66 .hwport = 1,
67 .flags = 0, 67 .flags = 0,
68 .ucon = S5PV210_UCON_DEFAULT, 68 .ucon = AQUILA_UCON_DEFAULT,
69 .ulcon = S5PV210_ULCON_DEFAULT, 69 .ulcon = AQUILA_ULCON_DEFAULT,
70 .ufcon = S5PV210_UFCON_DEFAULT | 70 .ufcon = AQUILA_UFCON_DEFAULT |
71 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, 71 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
72 }, 72 },
73 [2] = { 73 [2] = {
74 .hwport = 2, 74 .hwport = 2,
75 .flags = 0, 75 .flags = 0,
76 .ucon = S5PV210_UCON_DEFAULT, 76 .ucon = AQUILA_UCON_DEFAULT,
77 .ulcon = S5PV210_ULCON_DEFAULT, 77 .ulcon = AQUILA_ULCON_DEFAULT,
78 .ufcon = S5PV210_UFCON_DEFAULT | 78 .ufcon = AQUILA_UFCON_DEFAULT |
79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
80 }, 80 },
81 [3] = { 81 [3] = {
82 .hwport = 3, 82 .hwport = 3,
83 .flags = 0, 83 .flags = 0,
84 .ucon = S5PV210_UCON_DEFAULT, 84 .ucon = AQUILA_UCON_DEFAULT,
85 .ulcon = S5PV210_ULCON_DEFAULT, 85 .ulcon = AQUILA_ULCON_DEFAULT,
86 .ufcon = S5PV210_UFCON_DEFAULT | 86 .ufcon = AQUILA_UFCON_DEFAULT |
87 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 87 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
88 }, 88 },
89}; 89};
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index a094b44a43e8..0be739e5bfe6 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -38,48 +38,48 @@
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39 39
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 40/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 41#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 42 S3C2410_UCON_RXILEVEL | \
43 S3C2410_UCON_TXIRQMODE | \ 43 S3C2410_UCON_TXIRQMODE | \
44 S3C2410_UCON_RXIRQMODE | \ 44 S3C2410_UCON_RXIRQMODE | \
45 S3C2410_UCON_RXFIFO_TOI | \ 45 S3C2410_UCON_RXFIFO_TOI | \
46 S3C2443_UCON_RXERR_IRQEN) 46 S3C2443_UCON_RXERR_IRQEN)
47 47
48#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 48#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
49 49
50#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE 50#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
51 51
52static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { 52static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
53 [0] = { 53 [0] = {
54 .hwport = 0, 54 .hwport = 0,
55 .flags = 0, 55 .flags = 0,
56 .ucon = S5PV210_UCON_DEFAULT, 56 .ucon = GONI_UCON_DEFAULT,
57 .ulcon = S5PV210_ULCON_DEFAULT, 57 .ulcon = GONI_ULCON_DEFAULT,
58 .ufcon = S5PV210_UFCON_DEFAULT | 58 .ufcon = GONI_UFCON_DEFAULT |
59 S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, 59 S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
60 }, 60 },
61 [1] = { 61 [1] = {
62 .hwport = 1, 62 .hwport = 1,
63 .flags = 0, 63 .flags = 0,
64 .ucon = S5PV210_UCON_DEFAULT, 64 .ucon = GONI_UCON_DEFAULT,
65 .ulcon = S5PV210_ULCON_DEFAULT, 65 .ulcon = GONI_ULCON_DEFAULT,
66 .ufcon = S5PV210_UFCON_DEFAULT | 66 .ufcon = GONI_UFCON_DEFAULT |
67 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, 67 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
68 }, 68 },
69 [2] = { 69 [2] = {
70 .hwport = 2, 70 .hwport = 2,
71 .flags = 0, 71 .flags = 0,
72 .ucon = S5PV210_UCON_DEFAULT, 72 .ucon = GONI_UCON_DEFAULT,
73 .ulcon = S5PV210_ULCON_DEFAULT, 73 .ulcon = GONI_ULCON_DEFAULT,
74 .ufcon = S5PV210_UFCON_DEFAULT | 74 .ufcon = GONI_UFCON_DEFAULT |
75 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 75 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
76 }, 76 },
77 [3] = { 77 [3] = {
78 .hwport = 3, 78 .hwport = 3,
79 .flags = 0, 79 .flags = 0,
80 .ucon = S5PV210_UCON_DEFAULT, 80 .ucon = GONI_UCON_DEFAULT,
81 .ulcon = S5PV210_ULCON_DEFAULT, 81 .ulcon = GONI_ULCON_DEFAULT,
82 .ufcon = S5PV210_UFCON_DEFAULT | 82 .ufcon = GONI_UFCON_DEFAULT |
83 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 83 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
84 }, 84 },
85}; 85};
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 9f4f0bdd2cc3..8211bb87c54b 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -30,16 +30,16 @@
30#include <plat/iic.h> 30#include <plat/iic.h>
31 31
32/* Following are default values for UCON, ULCON and UFCON UART registers */ 32/* Following are default values for UCON, ULCON and UFCON UART registers */
33#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 33#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
34 S3C2410_UCON_RXILEVEL | \ 34 S3C2410_UCON_RXILEVEL | \
35 S3C2410_UCON_TXIRQMODE | \ 35 S3C2410_UCON_TXIRQMODE | \
36 S3C2410_UCON_RXIRQMODE | \ 36 S3C2410_UCON_RXIRQMODE | \
37 S3C2410_UCON_RXFIFO_TOI | \ 37 S3C2410_UCON_RXFIFO_TOI | \
38 S3C2443_UCON_RXERR_IRQEN) 38 S3C2443_UCON_RXERR_IRQEN)
39 39
40#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 40#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
41 41
42#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 42#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
43 S5PV210_UFCON_TXTRIG4 | \ 43 S5PV210_UFCON_TXTRIG4 | \
44 S5PV210_UFCON_RXTRIG4) 44 S5PV210_UFCON_RXTRIG4)
45 45
@@ -47,30 +47,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
47 [0] = { 47 [0] = {
48 .hwport = 0, 48 .hwport = 0,
49 .flags = 0, 49 .flags = 0,
50 .ucon = S5PV210_UCON_DEFAULT, 50 .ucon = SMDKC110_UCON_DEFAULT,
51 .ulcon = S5PV210_ULCON_DEFAULT, 51 .ulcon = SMDKC110_ULCON_DEFAULT,
52 .ufcon = S5PV210_UFCON_DEFAULT, 52 .ufcon = SMDKC110_UFCON_DEFAULT,
53 }, 53 },
54 [1] = { 54 [1] = {
55 .hwport = 1, 55 .hwport = 1,
56 .flags = 0, 56 .flags = 0,
57 .ucon = S5PV210_UCON_DEFAULT, 57 .ucon = SMDKC110_UCON_DEFAULT,
58 .ulcon = S5PV210_ULCON_DEFAULT, 58 .ulcon = SMDKC110_ULCON_DEFAULT,
59 .ufcon = S5PV210_UFCON_DEFAULT, 59 .ufcon = SMDKC110_UFCON_DEFAULT,
60 }, 60 },
61 [2] = { 61 [2] = {
62 .hwport = 2, 62 .hwport = 2,
63 .flags = 0, 63 .flags = 0,
64 .ucon = S5PV210_UCON_DEFAULT, 64 .ucon = SMDKC110_UCON_DEFAULT,
65 .ulcon = S5PV210_ULCON_DEFAULT, 65 .ulcon = SMDKC110_ULCON_DEFAULT,
66 .ufcon = S5PV210_UFCON_DEFAULT, 66 .ufcon = SMDKC110_UFCON_DEFAULT,
67 }, 67 },
68 [3] = { 68 [3] = {
69 .hwport = 3, 69 .hwport = 3,
70 .flags = 0, 70 .flags = 0,
71 .ucon = S5PV210_UCON_DEFAULT, 71 .ucon = SMDKC110_UCON_DEFAULT,
72 .ulcon = S5PV210_ULCON_DEFAULT, 72 .ulcon = SMDKC110_ULCON_DEFAULT,
73 .ufcon = S5PV210_UFCON_DEFAULT, 73 .ufcon = SMDKC110_UFCON_DEFAULT,
74 }, 74 },
75}; 75};
76 76
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 1e4ed147dbc7..fbbc0a3c3738 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -33,16 +33,16 @@
33#include <plat/keypad.h> 33#include <plat/keypad.h>
34 34
35/* Following are default values for UCON, ULCON and UFCON UART registers */ 35/* Following are default values for UCON, ULCON and UFCON UART registers */
36#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 36#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
37 S3C2410_UCON_RXILEVEL | \ 37 S3C2410_UCON_RXILEVEL | \
38 S3C2410_UCON_TXIRQMODE | \ 38 S3C2410_UCON_TXIRQMODE | \
39 S3C2410_UCON_RXIRQMODE | \ 39 S3C2410_UCON_RXIRQMODE | \
40 S3C2410_UCON_RXFIFO_TOI | \ 40 S3C2410_UCON_RXFIFO_TOI | \
41 S3C2443_UCON_RXERR_IRQEN) 41 S3C2443_UCON_RXERR_IRQEN)
42 42
43#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 43#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
44 44
45#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 45#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
46 S5PV210_UFCON_TXTRIG4 | \ 46 S5PV210_UFCON_TXTRIG4 | \
47 S5PV210_UFCON_RXTRIG4) 47 S5PV210_UFCON_RXTRIG4)
48 48
@@ -50,30 +50,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
50 [0] = { 50 [0] = {
51 .hwport = 0, 51 .hwport = 0,
52 .flags = 0, 52 .flags = 0,
53 .ucon = S5PV210_UCON_DEFAULT, 53 .ucon = SMDKV210_UCON_DEFAULT,
54 .ulcon = S5PV210_ULCON_DEFAULT, 54 .ulcon = SMDKV210_ULCON_DEFAULT,
55 .ufcon = S5PV210_UFCON_DEFAULT, 55 .ufcon = SMDKV210_UFCON_DEFAULT,
56 }, 56 },
57 [1] = { 57 [1] = {
58 .hwport = 1, 58 .hwport = 1,
59 .flags = 0, 59 .flags = 0,
60 .ucon = S5PV210_UCON_DEFAULT, 60 .ucon = SMDKV210_UCON_DEFAULT,
61 .ulcon = S5PV210_ULCON_DEFAULT, 61 .ulcon = SMDKV210_ULCON_DEFAULT,
62 .ufcon = S5PV210_UFCON_DEFAULT, 62 .ufcon = SMDKV210_UFCON_DEFAULT,
63 }, 63 },
64 [2] = { 64 [2] = {
65 .hwport = 2, 65 .hwport = 2,
66 .flags = 0, 66 .flags = 0,
67 .ucon = S5PV210_UCON_DEFAULT, 67 .ucon = SMDKV210_UCON_DEFAULT,
68 .ulcon = S5PV210_ULCON_DEFAULT, 68 .ulcon = SMDKV210_ULCON_DEFAULT,
69 .ufcon = S5PV210_UFCON_DEFAULT, 69 .ufcon = SMDKV210_UFCON_DEFAULT,
70 }, 70 },
71 [3] = { 71 [3] = {
72 .hwport = 3, 72 .hwport = 3,
73 .flags = 0, 73 .flags = 0,
74 .ucon = S5PV210_UCON_DEFAULT, 74 .ucon = SMDKV210_UCON_DEFAULT,
75 .ulcon = S5PV210_ULCON_DEFAULT, 75 .ulcon = SMDKV210_ULCON_DEFAULT,
76 .ufcon = S5PV210_UFCON_DEFAULT, 76 .ufcon = SMDKV210_UFCON_DEFAULT,
77 }, 77 },
78}; 78};
79 79
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