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authorKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:34:55 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-08-06 08:34:55 -0400
commitf2b7e3c54a304677a1142829fb5913595885379f (patch)
tree1eb941524c7325672f947dab525d96228b362e20
parent6b8eda04ffdc24b68d379a32358f4f09a425a380 (diff)
parent0fdb480e7fb1ecdd4076ddf8b6ab16b0d77406c1 (diff)
Merge branch 'next-s5p' into for-next
Conflicts: arch/arm/mach-s5pv210/mach-aquila.c arch/arm/mach-s5pv210/mach-goni.c
Diffstat
-rw-r--r--arch/arm/mach-s5p6440/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5p6440/include/mach/system.h7
-rw-r--r--arch/arm/mach-s5p6440/mach-smdk6440.c30
-rw-r--r--arch/arm/mach-s5p6442/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5p6442/include/mach/system.h7
-rw-r--r--arch/arm/mach-s5p6442/mach-smdk6442.c24
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pc100/include/mach/system.h9
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c30
-rw-r--r--arch/arm/mach-s5pv210/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/system.h7
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c30
-rw-r--r--arch/arm/plat-s5p/Makefile1
-rw-r--r--arch/arm/plat-s5p/cpu.c5
-rw-r--r--arch/arm/plat-s5p/dev-pmu.c36
-rw-r--r--arch/arm/plat-s5p/include/plat/reset.h16
-rw-r--r--arch/arm/plat-s5p/include/plat/system-reset.h31
20 files changed, 202 insertions, 129 deletions
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h
index 911854d9ad42..16a761270de1 100644
--- a/arch/arm/mach-s5p6440/include/mach/irqs.h
+++ b/arch/arm/mach-s5p6440/include/mach/irqs.h
@@ -51,7 +51,7 @@
51#define IRQ_DISPCON3 S5P_IRQ_VIC1(19) 51#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
52#define IRQ_FIMGVG S5P_IRQ_VIC1(20) 52#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
53#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) 53#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
54#define IRQ_PMUIRQ S5P_IRQ_VIC1(23) 54#define IRQ_PMU S5P_IRQ_VIC1(23)
55#define IRQ_HSMMC0 S5P_IRQ_VIC1(24) 55#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
56#define IRQ_HSMMC1 S5P_IRQ_VIC1(25) 56#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
57#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ 57#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h
index d2dd817da66a..a359ee3fa510 100644
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ b/arch/arm/mach-s5p6440/include/mach/system.h
@@ -13,12 +13,9 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16static void arch_idle(void) 16#include <plat/system-reset.h>
17{
18 /* nothing here yet */
19}
20 17
21static void arch_reset(char mode, const char *cmd) 18static void arch_idle(void)
22{ 19{
23 /* nothing here yet */ 20 /* nothing here yet */
24} 21}
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c
index 8c83d8fb0162..9202aaac3b56 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p6440/mach-smdk6440.c
@@ -43,16 +43,16 @@
43#include <plat/adc.h> 43#include <plat/adc.h>
44#include <plat/ts.h> 44#include <plat/ts.h>
45 45
46#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 46#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
47 S3C2410_UCON_RXILEVEL | \ 47 S3C2410_UCON_RXILEVEL | \
48 S3C2410_UCON_TXIRQMODE | \ 48 S3C2410_UCON_TXIRQMODE | \
49 S3C2410_UCON_RXIRQMODE | \ 49 S3C2410_UCON_RXIRQMODE | \
50 S3C2410_UCON_RXFIFO_TOI | \ 50 S3C2410_UCON_RXFIFO_TOI | \
51 S3C2443_UCON_RXERR_IRQEN) 51 S3C2443_UCON_RXERR_IRQEN)
52 52
53#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 53#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8
54 54
55#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 55#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
56 S3C2440_UFCON_TXTRIG16 | \ 56 S3C2440_UFCON_TXTRIG16 | \
57 S3C2410_UFCON_RXTRIG8) 57 S3C2410_UFCON_RXTRIG8)
58 58
@@ -60,30 +60,30 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
60 [0] = { 60 [0] = {
61 .hwport = 0, 61 .hwport = 0,
62 .flags = 0, 62 .flags = 0,
63 .ucon = S5P6440_UCON_DEFAULT, 63 .ucon = SMDK6440_UCON_DEFAULT,
64 .ulcon = S5P6440_ULCON_DEFAULT, 64 .ulcon = SMDK6440_ULCON_DEFAULT,
65 .ufcon = S5P6440_UFCON_DEFAULT, 65 .ufcon = SMDK6440_UFCON_DEFAULT,
66 }, 66 },
67 [1] = { 67 [1] = {
68 .hwport = 1, 68 .hwport = 1,
69 .flags = 0, 69 .flags = 0,
70 .ucon = S5P6440_UCON_DEFAULT, 70 .ucon = SMDK6440_UCON_DEFAULT,
71 .ulcon = S5P6440_ULCON_DEFAULT, 71 .ulcon = SMDK6440_ULCON_DEFAULT,
72 .ufcon = S5P6440_UFCON_DEFAULT, 72 .ufcon = SMDK6440_UFCON_DEFAULT,
73 }, 73 },
74 [2] = { 74 [2] = {
75 .hwport = 2, 75 .hwport = 2,
76 .flags = 0, 76 .flags = 0,
77 .ucon = S5P6440_UCON_DEFAULT, 77 .ucon = SMDK6440_UCON_DEFAULT,
78 .ulcon = S5P6440_ULCON_DEFAULT, 78 .ulcon = SMDK6440_ULCON_DEFAULT,
79 .ufcon = S5P6440_UFCON_DEFAULT, 79 .ufcon = SMDK6440_UFCON_DEFAULT,
80 }, 80 },
81 [3] = { 81 [3] = {
82 .hwport = 3, 82 .hwport = 3,
83 .flags = 0, 83 .flags = 0,
84 .ucon = S5P6440_UCON_DEFAULT, 84 .ucon = SMDK6440_UCON_DEFAULT,
85 .ulcon = S5P6440_ULCON_DEFAULT, 85 .ulcon = SMDK6440_ULCON_DEFAULT,
86 .ufcon = S5P6440_UFCON_DEFAULT, 86 .ufcon = SMDK6440_UFCON_DEFAULT,
87 }, 87 },
88}; 88};
89 89
diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h
index 02c23749c023..3fbc6c3ad2da 100644
--- a/arch/arm/mach-s5p6442/include/mach/irqs.h
+++ b/arch/arm/mach-s5p6442/include/mach/irqs.h
@@ -32,7 +32,7 @@
32#define IRQ_GPIOINT S5P_IRQ_VIC0(30) 32#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
33 33
34/* VIC1 */ 34/* VIC1 */
35#define IRQ_nPMUIRQ S5P_IRQ_VIC1(0) 35#define IRQ_PMU S5P_IRQ_VIC1(0)
36#define IRQ_ONENAND S5P_IRQ_VIC1(7) 36#define IRQ_ONENAND S5P_IRQ_VIC1(7)
37#define IRQ_UART0 S5P_IRQ_VIC1(10) 37#define IRQ_UART0 S5P_IRQ_VIC1(10)
38#define IRQ_UART1 S5P_IRQ_VIC1(11) 38#define IRQ_UART1 S5P_IRQ_VIC1(11)
diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h
index 8bcd8ed0c3c3..c30c1cc1b97e 100644
--- a/arch/arm/mach-s5p6442/include/mach/system.h
+++ b/arch/arm/mach-s5p6442/include/mach/system.h
@@ -13,12 +13,9 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16static void arch_idle(void) 16#include <plat/system-reset.h>
17{
18 /* nothing here yet */
19}
20 17
21static void arch_reset(char mode, const char *cmd) 18static void arch_idle(void)
22{ 19{
23 /* nothing here yet */ 20 /* nothing here yet */
24} 21}
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index 6e061bec6b74..8d8d04272f85 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -27,16 +27,16 @@
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28 28
29/* Following are default values for UCON, ULCON and UFCON UART registers */ 29/* Following are default values for UCON, ULCON and UFCON UART registers */
30#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 30#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
31 S3C2410_UCON_RXILEVEL | \ 31 S3C2410_UCON_RXILEVEL | \
32 S3C2410_UCON_TXIRQMODE | \ 32 S3C2410_UCON_TXIRQMODE | \
33 S3C2410_UCON_RXIRQMODE | \ 33 S3C2410_UCON_RXIRQMODE | \
34 S3C2410_UCON_RXFIFO_TOI | \ 34 S3C2410_UCON_RXFIFO_TOI | \
35 S3C2443_UCON_RXERR_IRQEN) 35 S3C2443_UCON_RXERR_IRQEN)
36 36
37#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8 37#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
38 38
39#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 39#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
40 S5PV210_UFCON_TXTRIG4 | \ 40 S5PV210_UFCON_TXTRIG4 | \
41 S5PV210_UFCON_RXTRIG4) 41 S5PV210_UFCON_RXTRIG4)
42 42
@@ -44,23 +44,23 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
44 [0] = { 44 [0] = {
45 .hwport = 0, 45 .hwport = 0,
46 .flags = 0, 46 .flags = 0,
47 .ucon = S5P6442_UCON_DEFAULT, 47 .ucon = SMDK6442_UCON_DEFAULT,
48 .ulcon = S5P6442_ULCON_DEFAULT, 48 .ulcon = SMDK6442_ULCON_DEFAULT,
49 .ufcon = S5P6442_UFCON_DEFAULT, 49 .ufcon = SMDK6442_UFCON_DEFAULT,
50 }, 50 },
51 [1] = { 51 [1] = {
52 .hwport = 1, 52 .hwport = 1,
53 .flags = 0, 53 .flags = 0,
54 .ucon = S5P6442_UCON_DEFAULT, 54 .ucon = SMDK6442_UCON_DEFAULT,
55 .ulcon = S5P6442_ULCON_DEFAULT, 55 .ulcon = SMDK6442_ULCON_DEFAULT,
56 .ufcon = S5P6442_UFCON_DEFAULT, 56 .ufcon = SMDK6442_UFCON_DEFAULT,
57 }, 57 },
58 [2] = { 58 [2] = {
59 .hwport = 2, 59 .hwport = 2,
60 .flags = 0, 60 .flags = 0,
61 .ucon = S5P6442_UCON_DEFAULT, 61 .ucon = SMDK6442_UCON_DEFAULT,
62 .ulcon = S5P6442_ULCON_DEFAULT, 62 .ulcon = SMDK6442_ULCON_DEFAULT,
63 .ufcon = S5P6442_UFCON_DEFAULT, 63 .ufcon = SMDK6442_UFCON_DEFAULT,
64 }, 64 },
65}; 65};
66 66
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index bfcc0b9d7ad7..06513e647242 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -29,7 +29,7 @@
29#define IRQ_GPIOINT S5P_IRQ_VIC0(30) 29#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
30 30
31/* VIC1: ARM, power, memory, connectivity */ 31/* VIC1: ARM, power, memory, connectivity */
32#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) 32#define IRQ_PMU S5P_IRQ_VIC1(0)
33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) 33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) 34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) 35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index 681f626a9ae1..a9ea57c06600 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,18 +11,11 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__ 12#define __ASM_ARCH_SYSTEM_H __FILE__
13 13
14#include <linux/io.h> 14#include <plat/system-reset.h>
15#include <mach/map.h>
16#include <mach/regs-clock.h>
17 15
18static void arch_idle(void) 16static void arch_idle(void)
19{ 17{
20 /* nothing here yet */ 18 /* nothing here yet */
21} 19}
22 20
23static void arch_reset(char mode, const char *cmd)
24{
25 __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
26 return;
27}
28#endif /* __ASM_ARCH_IRQ_H */ 21#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 83a5d648a980..a63c8a46571d 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -49,16 +49,16 @@
49#include <plat/ts.h> 49#include <plat/ts.h>
50 50
51/* Following are default values for UCON, ULCON and UFCON UART registers */ 51/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 52#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
53 S3C2410_UCON_RXILEVEL | \ 53 S3C2410_UCON_RXILEVEL | \
54 S3C2410_UCON_TXIRQMODE | \ 54 S3C2410_UCON_TXIRQMODE | \
55 S3C2410_UCON_RXIRQMODE | \ 55 S3C2410_UCON_RXIRQMODE | \
56 S3C2410_UCON_RXFIFO_TOI | \ 56 S3C2410_UCON_RXFIFO_TOI | \
57 S3C2443_UCON_RXERR_IRQEN) 57 S3C2443_UCON_RXERR_IRQEN)
58 58
59#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 59#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8
60 60
61#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 61#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
62 S3C2440_UFCON_RXTRIG8 | \ 62 S3C2440_UFCON_RXTRIG8 | \
63 S3C2440_UFCON_TXTRIG16) 63 S3C2440_UFCON_TXTRIG16)
64 64
@@ -66,30 +66,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
66 [0] = { 66 [0] = {
67 .hwport = 0, 67 .hwport = 0,
68 .flags = 0, 68 .flags = 0,
69 .ucon = S5PC100_UCON_DEFAULT, 69 .ucon = SMDKC100_UCON_DEFAULT,
70 .ulcon = S5PC100_ULCON_DEFAULT, 70 .ulcon = SMDKC100_ULCON_DEFAULT,
71 .ufcon = S5PC100_UFCON_DEFAULT, 71 .ufcon = SMDKC100_UFCON_DEFAULT,
72 }, 72 },
73 [1] = { 73 [1] = {
74 .hwport = 1, 74 .hwport = 1,
75 .flags = 0, 75 .flags = 0,
76 .ucon = S5PC100_UCON_DEFAULT, 76 .ucon = SMDKC100_UCON_DEFAULT,
77 .ulcon = S5PC100_ULCON_DEFAULT, 77 .ulcon = SMDKC100_ULCON_DEFAULT,
78 .ufcon = S5PC100_UFCON_DEFAULT, 78 .ufcon = SMDKC100_UFCON_DEFAULT,
79 }, 79 },
80 [2] = { 80 [2] = {
81 .hwport = 2, 81 .hwport = 2,
82 .flags = 0, 82 .flags = 0,
83 .ucon = S5PC100_UCON_DEFAULT, 83 .ucon = SMDKC100_UCON_DEFAULT,
84 .ulcon = S5PC100_ULCON_DEFAULT, 84 .ulcon = SMDKC100_ULCON_DEFAULT,
85 .ufcon = S5PC100_UFCON_DEFAULT, 85 .ufcon = SMDKC100_UFCON_DEFAULT,
86 }, 86 },
87 [3] = { 87 [3] = {
88 .hwport = 3, 88 .hwport = 3,
89 .flags = 0, 89 .flags = 0,
90 .ucon = S5PC100_UCON_DEFAULT, 90 .ucon = SMDKC100_UCON_DEFAULT,
91 .ulcon = S5PC100_ULCON_DEFAULT, 91 .ulcon = SMDKC100_ULCON_DEFAULT,
92 .ufcon = S5PC100_UFCON_DEFAULT, 92 .ufcon = SMDKC100_UFCON_DEFAULT,
93 }, 93 },
94}; 94};
95 95
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index e1d3c453db81..e1c020e5a49b 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -36,7 +36,7 @@
36 36
37/* VIC1: ARM, Power, Memory, Connectivity, Storage */ 37/* VIC1: ARM, Power, Memory, Connectivity, Storage */
38 38
39#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) 39#define IRQ_PMU S5P_IRQ_VIC1(0)
40#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) 40#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
41#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) 41#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
42#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) 42#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
index 1ca04d5025b3..af8a200b2135 100644
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ b/arch/arm/mach-s5pv210/include/mach/system.h
@@ -13,12 +13,9 @@
13#ifndef __ASM_ARCH_SYSTEM_H 13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__ 14#define __ASM_ARCH_SYSTEM_H __FILE__
15 15
16static void arch_idle(void) 16#include <plat/system-reset.h>
17{
18 /* nothing here yet */
19}
20 17
21static void arch_reset(char mode, const char *cmd) 18static void arch_idle(void)
22{ 19{
23 /* nothing here yet */ 20 /* nothing here yet */
24} 21}
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0c894010e278..a6b4ed364840 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,52 +38,52 @@
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39 39
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 40/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 41#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 42 S3C2410_UCON_RXILEVEL | \
43 S3C2410_UCON_TXIRQMODE | \ 43 S3C2410_UCON_TXIRQMODE | \
44 S3C2410_UCON_RXIRQMODE | \ 44 S3C2410_UCON_RXIRQMODE | \
45 S3C2410_UCON_RXFIFO_TOI | \ 45 S3C2410_UCON_RXFIFO_TOI | \
46 S3C2443_UCON_RXERR_IRQEN) 46 S3C2443_UCON_RXERR_IRQEN)
47 47
48#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 48#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
49 49
50#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE 50#define AQUILA_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
51 51
52static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = { 52static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
53 [0] = { 53 [0] = {
54 .hwport = 0, 54 .hwport = 0,
55 .flags = 0, 55 .flags = 0,
56 .ucon = S5PV210_UCON_DEFAULT, 56 .ucon = AQUILA_UCON_DEFAULT,
57 .ulcon = S5PV210_ULCON_DEFAULT, 57 .ulcon = AQUILA_ULCON_DEFAULT,
58 /* 58 /*
59 * Actually UART0 can support 256 bytes fifo, but aquila board 59 * Actually UART0 can support 256 bytes fifo, but aquila board
60 * supports 128 bytes fifo because of initial chip bug 60 * supports 128 bytes fifo because of initial chip bug
61 */ 61 */
62 .ufcon = S5PV210_UFCON_DEFAULT | 62 .ufcon = AQUILA_UFCON_DEFAULT |
63 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128, 63 S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
64 }, 64 },
65 [1] = { 65 [1] = {
66 .hwport = 1, 66 .hwport = 1,
67 .flags = 0, 67 .flags = 0,
68 .ucon = S5PV210_UCON_DEFAULT, 68 .ucon = AQUILA_UCON_DEFAULT,
69 .ulcon = S5PV210_ULCON_DEFAULT, 69 .ulcon = AQUILA_ULCON_DEFAULT,
70 .ufcon = S5PV210_UFCON_DEFAULT | 70 .ufcon = AQUILA_UFCON_DEFAULT |
71 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, 71 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
72 }, 72 },
73 [2] = { 73 [2] = {
74 .hwport = 2, 74 .hwport = 2,
75 .flags = 0, 75 .flags = 0,
76 .ucon = S5PV210_UCON_DEFAULT, 76 .ucon = AQUILA_UCON_DEFAULT,
77 .ulcon = S5PV210_ULCON_DEFAULT, 77 .ulcon = AQUILA_ULCON_DEFAULT,
78 .ufcon = S5PV210_UFCON_DEFAULT | 78 .ufcon = AQUILA_UFCON_DEFAULT |
79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 79 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
80 }, 80 },
81 [3] = { 81 [3] = {
82 .hwport = 3, 82 .hwport = 3,
83 .flags = 0, 83 .flags = 0,
84 .ucon = S5PV210_UCON_DEFAULT, 84 .ucon = AQUILA_UCON_DEFAULT,
85 .ulcon = S5PV210_ULCON_DEFAULT, 85 .ulcon = AQUILA_ULCON_DEFAULT,
86 .ufcon = S5PV210_UFCON_DEFAULT | 86 .ufcon = AQUILA_UFCON_DEFAULT |
87 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 87 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
88 }, 88 },
89}; 89};
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index a094b44a43e8..0be739e5bfe6 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -38,48 +38,48 @@
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39 39
40/* Following are default values for UCON, ULCON and UFCON UART registers */ 40/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 41#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \ 42 S3C2410_UCON_RXILEVEL | \
43 S3C2410_UCON_TXIRQMODE | \ 43 S3C2410_UCON_TXIRQMODE | \
44 S3C2410_UCON_RXIRQMODE | \ 44 S3C2410_UCON_RXIRQMODE | \
45 S3C2410_UCON_RXFIFO_TOI | \ 45 S3C2410_UCON_RXFIFO_TOI | \
46 S3C2443_UCON_RXERR_IRQEN) 46 S3C2443_UCON_RXERR_IRQEN)
47 47
48#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 48#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
49 49
50#define S5PV210_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE 50#define GONI_UFCON_DEFAULT S3C2410_UFCON_FIFOMODE
51 51
52static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { 52static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
53 [0] = { 53 [0] = {
54 .hwport = 0, 54 .hwport = 0,
55 .flags = 0, 55 .flags = 0,
56 .ucon = S5PV210_UCON_DEFAULT, 56 .ucon = GONI_UCON_DEFAULT,
57 .ulcon = S5PV210_ULCON_DEFAULT, 57 .ulcon = GONI_ULCON_DEFAULT,
58 .ufcon = S5PV210_UFCON_DEFAULT | 58 .ufcon = GONI_UFCON_DEFAULT |
59 S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256, 59 S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
60 }, 60 },
61 [1] = { 61 [1] = {
62 .hwport = 1, 62 .hwport = 1,
63 .flags = 0, 63 .flags = 0,
64 .ucon = S5PV210_UCON_DEFAULT, 64 .ucon = GONI_UCON_DEFAULT,
65 .ulcon = S5PV210_ULCON_DEFAULT, 65 .ulcon = GONI_ULCON_DEFAULT,
66 .ufcon = S5PV210_UFCON_DEFAULT | 66 .ufcon = GONI_UFCON_DEFAULT |
67 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64, 67 S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
68 }, 68 },
69 [2] = { 69 [2] = {
70 .hwport = 2, 70 .hwport = 2,
71 .flags = 0, 71 .flags = 0,
72 .ucon = S5PV210_UCON_DEFAULT, 72 .ucon = GONI_UCON_DEFAULT,
73 .ulcon = S5PV210_ULCON_DEFAULT, 73 .ulcon = GONI_ULCON_DEFAULT,
74 .ufcon = S5PV210_UFCON_DEFAULT | 74 .ufcon = GONI_UFCON_DEFAULT |
75 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 75 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
76 }, 76 },
77 [3] = { 77 [3] = {
78 .hwport = 3, 78 .hwport = 3,
79 .flags = 0, 79 .flags = 0,
80 .ucon = S5PV210_UCON_DEFAULT, 80 .ucon = GONI_UCON_DEFAULT,
81 .ulcon = S5PV210_ULCON_DEFAULT, 81 .ulcon = GONI_ULCON_DEFAULT,
82 .ufcon = S5PV210_UFCON_DEFAULT | 82 .ufcon = GONI_UFCON_DEFAULT |
83 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16, 83 S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
84 }, 84 },
85}; 85};
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 9f4f0bdd2cc3..8211bb87c54b 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -30,16 +30,16 @@
30#include <plat/iic.h> 30#include <plat/iic.h>
31 31
32/* Following are default values for UCON, ULCON and UFCON UART registers */ 32/* Following are default values for UCON, ULCON and UFCON UART registers */
33#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 33#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
34 S3C2410_UCON_RXILEVEL | \ 34 S3C2410_UCON_RXILEVEL | \
35 S3C2410_UCON_TXIRQMODE | \ 35 S3C2410_UCON_TXIRQMODE | \
36 S3C2410_UCON_RXIRQMODE | \ 36 S3C2410_UCON_RXIRQMODE | \
37 S3C2410_UCON_RXFIFO_TOI | \ 37 S3C2410_UCON_RXFIFO_TOI | \
38 S3C2443_UCON_RXERR_IRQEN) 38 S3C2443_UCON_RXERR_IRQEN)
39 39
40#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 40#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
41 41
42#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 42#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
43 S5PV210_UFCON_TXTRIG4 | \ 43 S5PV210_UFCON_TXTRIG4 | \
44 S5PV210_UFCON_RXTRIG4) 44 S5PV210_UFCON_RXTRIG4)
45 45
@@ -47,30 +47,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
47 [0] = { 47 [0] = {
48 .hwport = 0, 48 .hwport = 0,
49 .flags = 0, 49 .flags = 0,
50 .ucon = S5PV210_UCON_DEFAULT, 50 .ucon = SMDKC110_UCON_DEFAULT,
51 .ulcon = S5PV210_ULCON_DEFAULT, 51 .ulcon = SMDKC110_ULCON_DEFAULT,
52 .ufcon = S5PV210_UFCON_DEFAULT, 52 .ufcon = SMDKC110_UFCON_DEFAULT,
53 }, 53 },
54 [1] = { 54 [1] = {
55 .hwport = 1, 55 .hwport = 1,
56 .flags = 0, 56 .flags = 0,
57 .ucon = S5PV210_UCON_DEFAULT, 57 .ucon = SMDKC110_UCON_DEFAULT,
58 .ulcon = S5PV210_ULCON_DEFAULT, 58 .ulcon = SMDKC110_ULCON_DEFAULT,
59 .ufcon = S5PV210_UFCON_DEFAULT, 59 .ufcon = SMDKC110_UFCON_DEFAULT,
60 }, 60 },
61 [2] = { 61 [2] = {
62 .hwport = 2, 62 .hwport = 2,
63 .flags = 0, 63 .flags = 0,
64 .ucon = S5PV210_UCON_DEFAULT, 64 .ucon = SMDKC110_UCON_DEFAULT,
65 .ulcon = S5PV210_ULCON_DEFAULT, 65 .ulcon = SMDKC110_ULCON_DEFAULT,
66 .ufcon = S5PV210_UFCON_DEFAULT, 66 .ufcon = SMDKC110_UFCON_DEFAULT,
67 }, 67 },
68 [3] = { 68 [3] = {
69 .hwport = 3, 69 .hwport = 3,
70 .flags = 0, 70 .flags = 0,
71 .ucon = S5PV210_UCON_DEFAULT, 71 .ucon = SMDKC110_UCON_DEFAULT,
72 .ulcon = S5PV210_ULCON_DEFAULT, 72 .ulcon = SMDKC110_ULCON_DEFAULT,
73 .ufcon = S5PV210_UFCON_DEFAULT, 73 .ufcon = SMDKC110_UFCON_DEFAULT,
74 }, 74 },
75}; 75};
76 76
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 1e4ed147dbc7..fbbc0a3c3738 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -33,16 +33,16 @@
33#include <plat/keypad.h> 33#include <plat/keypad.h>
34 34
35/* Following are default values for UCON, ULCON and UFCON UART registers */ 35/* Following are default values for UCON, ULCON and UFCON UART registers */
36#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 36#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
37 S3C2410_UCON_RXILEVEL | \ 37 S3C2410_UCON_RXILEVEL | \
38 S3C2410_UCON_TXIRQMODE | \ 38 S3C2410_UCON_TXIRQMODE | \
39 S3C2410_UCON_RXIRQMODE | \ 39 S3C2410_UCON_RXIRQMODE | \
40 S3C2410_UCON_RXFIFO_TOI | \ 40 S3C2410_UCON_RXFIFO_TOI | \
41 S3C2443_UCON_RXERR_IRQEN) 41 S3C2443_UCON_RXERR_IRQEN)
42 42
43#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 43#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
44 44
45#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 45#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
46 S5PV210_UFCON_TXTRIG4 | \ 46 S5PV210_UFCON_TXTRIG4 | \
47 S5PV210_UFCON_RXTRIG4) 47 S5PV210_UFCON_RXTRIG4)
48 48
@@ -50,30 +50,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
50 [0] = { 50 [0] = {
51 .hwport = 0, 51 .hwport = 0,
52 .flags = 0, 52 .flags = 0,
53 .ucon = S5PV210_UCON_DEFAULT, 53 .ucon = SMDKV210_UCON_DEFAULT,
54 .ulcon = S5PV210_ULCON_DEFAULT, 54 .ulcon = SMDKV210_ULCON_DEFAULT,
55 .ufcon = S5PV210_UFCON_DEFAULT, 55 .ufcon = SMDKV210_UFCON_DEFAULT,
56 }, 56 },
57 [1] = { 57 [1] = {
58 .hwport = 1, 58 .hwport = 1,
59 .flags = 0, 59 .flags = 0,
60 .ucon = S5PV210_UCON_DEFAULT, 60 .ucon = SMDKV210_UCON_DEFAULT,
61 .ulcon = S5PV210_ULCON_DEFAULT, 61 .ulcon = SMDKV210_ULCON_DEFAULT,
62 .ufcon = S5PV210_UFCON_DEFAULT, 62 .ufcon = SMDKV210_UFCON_DEFAULT,
63 }, 63 },
64 [2] = { 64 [2] = {
65 .hwport = 2, 65 .hwport = 2,
66 .flags = 0, 66 .flags = 0,
67 .ucon = S5PV210_UCON_DEFAULT, 67 .ucon = SMDKV210_UCON_DEFAULT,
68 .ulcon = S5PV210_ULCON_DEFAULT, 68 .ulcon = SMDKV210_ULCON_DEFAULT,
69 .ufcon = S5PV210_UFCON_DEFAULT, 69 .ufcon = SMDKV210_UFCON_DEFAULT,
70 }, 70 },
71 [3] = { 71 [3] = {
72 .hwport = 3, 72 .hwport = 3,
73 .flags = 0, 73 .flags = 0,
74 .ucon = S5PV210_UCON_DEFAULT, 74 .ucon = SMDKV210_UCON_DEFAULT,
75 .ulcon = S5PV210_ULCON_DEFAULT, 75 .ulcon = SMDKV210_ULCON_DEFAULT,
76 .ufcon = S5PV210_UFCON_DEFAULT, 76 .ufcon = SMDKV210_UFCON_DEFAULT,
77 }, 77 },
78}; 78};
79 79
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 39c242bb9d58..7e34194b0aaf 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,6 +12,7 @@ obj- :=
12 12
13# Core files 13# Core files
14 14
15obj-y += dev-pmu.o
15obj-y += dev-uart.o 16obj-y += dev-uart.o
16obj-y += cpu.o 17obj-y += cpu.o
17obj-y += clock.o 18obj-y += clock.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 9261a27d7fe5..b07a078fd284 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -115,6 +115,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
115 .pfn = __phys_to_pfn(S5P_PA_GPIO), 115 .pfn = __phys_to_pfn(S5P_PA_GPIO),
116 .length = SZ_4K, 116 .length = SZ_4K,
117 .type = MT_DEVICE, 117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_WATCHDOG,
120 .pfn = __phys_to_pfn(S3C_PA_WDT),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
118 }, 123 },
119}; 124};
120 125
diff --git a/arch/arm/plat-s5p/dev-pmu.c b/arch/arm/plat-s5p/dev-pmu.c
new file mode 100644
index 000000000000..a08576da72b0
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-pmu.c
@@ -0,0 +1,36 @@
1/*
2 * linux/arch/arm/plat-s5p/dev-pmu.c
3 *
4 * Copyright (C) 2010 Samsung Electronics Co.Ltd
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/platform_device.h>
15#include <asm/pmu.h>
16#include <mach/irqs.h>
17
18static struct resource s5p_pmu_resource = {
19 .start = IRQ_PMU,
20 .end = IRQ_PMU,
21 .flags = IORESOURCE_IRQ,
22};
23
24struct platform_device s5p_device_pmu = {
25 .name = "arm-pmu",
26 .id = ARM_PMU_DEVICE_CPU,
27 .num_resources = 1,
28 .resource = &s5p_pmu_resource,
29};
30
31static int __init s5p_pmu_init(void)
32{
33 platform_device_register(&s5p_device_pmu);
34 return 0;
35}
36arch_initcall(s5p_pmu_init);
diff --git a/arch/arm/plat-s5p/include/plat/reset.h b/arch/arm/plat-s5p/include/plat/reset.h
new file mode 100644
index 000000000000..335e97812eed
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/reset.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/plat-s5p/include/plat/reset.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_PLAT_S5P_RESET_H
12#define __ASM_PLAT_S5P_RESET_H __FILE__
13
14extern void (*s5p_reset_hook)(void);
15
16#endif /* __ASM_PLAT_S5P_RESET_H */
diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h
new file mode 100644
index 000000000000..f307f34e6422
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/system-reset.h
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-s5p/include/plat/system-reset.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
7 *
8 * S5P - System define for arch_reset()
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/watchdog-reset.h>
16
17void (*s5p_reset_hook)(void);
18
19static void arch_reset(char mode, const char *cmd)
20{
21 /* SWRESET support in s5p_reset_hook() */
22
23 if (s5p_reset_hook)
24 s5p_reset_hook();
25
26 /* Perform reset using Watchdog reset
27 * if there is no s5p_reset_hook()
28 */
29
30 arch_wdt_reset();
31}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 13:29:56 -0400