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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
commit4f2d658b2f09c41677871a4285a09cf35f954dad (patch)
treeec0a626a598530203871bbc37a340224e5ac87ad /arch/arm/mach-s5pv210
parente66d637134b7045ea6f14bdd416cd3695f73ed42 (diff)
parent1fc5f7d5c680ac36bd41e13a3d77cbe2eaa312e0 (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree description updates from Arnd Bergmann: "This branch contains two kinds of updates: Some platforms in the process of getting converted to device tree based booting, and the platform specific patches necessary for that are included here. Other platforms are already converted, so we just need to update the actual device tree source files and the binding documents to add support for new board and new drivers. In the future we will probably separate those into two branches, and in the long run, the plan is to move the device tree source files out of the kernel repository, but that has to wait until we have completed a much larger portion of the binding documents." Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly added clkdev registers next to a few removed unnecessary ones. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: LPC32xx: Add PWM to base dts file ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 ARM: EXYNOS: Add spi clock support for EXYNOS5 ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock ARM: ux500: Remove PMU platform registration when booting with DT ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure ARM: ux500: Ensure vendor specific properties have the vendor's identifier pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree ARM: ux500: Apply ab8500-debug node do the db8500 DT structure ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT ...
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/clock.c14
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c21
2 files changed, 9 insertions, 26 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d50961d..fcdf52dbcc49 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
445 .ctrlbit = (1 << 11), 445 .ctrlbit = (1 << 11),
446 }, { 446 }, {
447 .name = "spi", 447 .name = "spi",
448 .devname = "s3c64xx-spi.0", 448 .devname = "s5pv210-spi.0",
449 .parent = &clk_pclk_psys.clk, 449 .parent = &clk_pclk_psys.clk,
450 .enable = s5pv210_clk_ip3_ctrl, 450 .enable = s5pv210_clk_ip3_ctrl,
451 .ctrlbit = (1<<12), 451 .ctrlbit = (1<<12),
452 }, { 452 }, {
453 .name = "spi", 453 .name = "spi",
454 .devname = "s3c64xx-spi.1", 454 .devname = "s5pv210-spi.1",
455 .parent = &clk_pclk_psys.clk, 455 .parent = &clk_pclk_psys.clk,
456 .enable = s5pv210_clk_ip3_ctrl, 456 .enable = s5pv210_clk_ip3_ctrl,
457 .ctrlbit = (1<<13), 457 .ctrlbit = (1<<13),
458 }, { 458 }, {
459 .name = "spi", 459 .name = "spi",
460 .devname = "s3c64xx-spi.2", 460 .devname = "s5pv210-spi.2",
461 .parent = &clk_pclk_psys.clk, 461 .parent = &clk_pclk_psys.clk,
462 .enable = s5pv210_clk_ip3_ctrl, 462 .enable = s5pv210_clk_ip3_ctrl,
463 .ctrlbit = (1<<14), 463 .ctrlbit = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
1035static struct clksrc_clk clk_sclk_spi0 = { 1035static struct clksrc_clk clk_sclk_spi0 = {
1036 .clk = { 1036 .clk = {
1037 .name = "sclk_spi", 1037 .name = "sclk_spi",
1038 .devname = "s3c64xx-spi.0", 1038 .devname = "s5pv210-spi.0",
1039 .enable = s5pv210_clk_mask0_ctrl, 1039 .enable = s5pv210_clk_mask0_ctrl,
1040 .ctrlbit = (1 << 16), 1040 .ctrlbit = (1 << 16),
1041 }, 1041 },
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
1047static struct clksrc_clk clk_sclk_spi1 = { 1047static struct clksrc_clk clk_sclk_spi1 = {
1048 .clk = { 1048 .clk = {
1049 .name = "sclk_spi", 1049 .name = "sclk_spi",
1050 .devname = "s3c64xx-spi.1", 1050 .devname = "s5pv210-spi.1",
1051 .enable = s5pv210_clk_mask0_ctrl, 1051 .enable = s5pv210_clk_mask0_ctrl,
1052 .ctrlbit = (1 << 17), 1052 .ctrlbit = (1 << 17),
1053 }, 1053 },
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1331 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1331 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1332 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), 1332 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1333 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 1333 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1334 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 1334 CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1335 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 1335 CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1336}; 1336};
1337 1337
1338void __init s5pv210_register_clocks(void) 1338void __init s5pv210_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index f43c5048a37d..81aecc162f82 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -9,20 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 13
17#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata = { 15int s3c64xx_spi0_cfg_gpio(void)
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .tx_st_done = 25,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{ 16{
27 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); 17 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
28 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); 18 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
@@ -33,14 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
33#endif 23#endif
34 24
35#ifdef CONFIG_S3C64XX_DEV_SPI1 25#ifdef CONFIG_S3C64XX_DEV_SPI1
36struct s3c64xx_spi_info s3c64xx_spi1_pdata = { 26int s3c64xx_spi1_cfg_gpio(void)
37 .fifo_lvl_mask = 0x7f,
38 .rx_lvl_offset = 15,
39 .high_speed = 1,
40 .tx_st_done = 25,
41};
42
43int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
44{ 27{
45 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); 28 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);