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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
commit4f2d658b2f09c41677871a4285a09cf35f954dad (patch)
treeec0a626a598530203871bbc37a340224e5ac87ad /arch/arm
parente66d637134b7045ea6f14bdd416cd3695f73ed42 (diff)
parent1fc5f7d5c680ac36bd41e13a3d77cbe2eaa312e0 (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree description updates from Arnd Bergmann: "This branch contains two kinds of updates: Some platforms in the process of getting converted to device tree based booting, and the platform specific patches necessary for that are included here. Other platforms are already converted, so we just need to update the actual device tree source files and the binding documents to add support for new board and new drivers. In the future we will probably separate those into two branches, and in the long run, the plan is to move the device tree source files out of the kernel repository, but that has to wait until we have completed a much larger portion of the binding documents." Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly added clkdev registers next to a few removed unnecessary ones. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: LPC32xx: Add PWM to base dts file ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 ARM: EXYNOS: Add spi clock support for EXYNOS5 ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock ARM: ux500: Remove PMU platform registration when booting with DT ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure ARM: ux500: Ensure vendor specific properties have the vendor's identifier pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree ARM: ux500: Apply ab8500-debug node do the db8500 DT structure ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/aks-cdu.dts113
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts20
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts20
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi158
-rw-r--r--arch/arm/boot/dts/am3517-evm.dts32
-rw-r--r--arch/arm/boot/dts/db8500.dtsi77
-rw-r--r--arch/arm/boot/dts/ea3250.dts17
-rw-r--r--arch/arm/boot/dts/evk-pro3.dts41
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts12
-rw-r--r--arch/arm/boot/dts/exynos4210-smdkv310.dts38
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi47
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts38
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi36
-rw-r--r--arch/arm/boot/dts/ge863-pro3.dtsi52
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts66
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts44
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts78
-rw-r--r--arch/arm/boot/dts/imx23.dtsi169
-rw-r--r--arch/arm/boot/dts/imx27-3ds.dts41
-rw-r--r--arch/arm/boot/dts/imx27.dtsi12
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts198
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts52
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts164
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts210
-rw-r--r--arch/arm/boot/dts/imx28-tx28.dts97
-rw-r--r--arch/arm/boot/dts/imx28.dtsi353
-rw-r--r--arch/arm/boot/dts/imx31-bug.dts31
-rw-r--r--arch/arm/boot/dts/imx31.dtsi88
-rw-r--r--arch/arm/boot/dts/imx51.dtsi8
-rw-r--r--arch/arm/boot/dts/imx53.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts6
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts33
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi99
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi5
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts20
-rw-r--r--arch/arm/boot/dts/omap3-evm.dts28
-rw-r--r--arch/arm/boot/dts/omap3.dtsi5
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts37
-rw-r--r--arch/arm/boot/dts/omap4-pandaES.dts24
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts68
-rw-r--r--arch/arm/boot/dts/omap4-var_som.dts96
-rw-r--r--arch/arm/boot/dts/omap4.dtsi23
-rw-r--r--arch/arm/boot/dts/snowball.dts21
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts85
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts301
-rw-r--r--arch/arm/mach-at91/Makefile.boot2
-rw-r--r--arch/arm/mach-davinci/cp_intc.c16
-rw-r--r--arch/arm/mach-davinci/include/mach/cp_intc.h1
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c67
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c95
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c6
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c6
-rw-r--r--arch/arm/mach-exynos/setup-spi.c33
-rw-r--r--arch/arm/mach-imx/Kconfig13
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/clk-imx31.c19
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c22
-rw-r--r--arch/arm/mach-imx/imx31-dt.c63
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c41
-rw-r--r--arch/arm/mach-mxs/Kconfig1
-rw-r--r--arch/arm/mach-mxs/Makefile.boot9
-rw-r--r--arch/arm/mach-mxs/devices-mx23.h2
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h2
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxsfb.c2
-rw-r--r--arch/arm/mach-mxs/include/mach/mxsfb.h49
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c215
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2416.c3
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2443.c2
-rw-r--r--arch/arm/mach-s3c24xx/common-s3c2443.c4
-rw-r--r--arch/arm/mach-s3c24xx/setup-spi.c10
-rw-r--r--arch/arm/mach-s3c64xx/clock.c20
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/dma.h1
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c19
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c12
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c12
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c21
-rw-r--r--arch/arm/mach-s5pc100/clock.c30
-rw-r--r--arch/arm/mach-s5pc100/setup-spi.c30
-rw-r--r--arch/arm/mach-s5pv210/clock.c14
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c21
-rw-r--r--arch/arm/mach-tegra/Makefile.boot1
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c4
-rw-r--r--arch/arm/mach-ux500/board-mop500.c63
-rw-r--r--arch/arm/mach-ux500/board-mop500.h3
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c4
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h1
-rw-r--r--arch/arm/plat-samsung/devs.c60
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h39
93 files changed, 3755 insertions, 473 deletions
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
new file mode 100644
index 000000000000..29b9f15e7599
--- /dev/null
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -0,0 +1,113 @@
1/*
2 * aks-cdu.dts - Device Tree file for AK signal CDU
3 *
4 * Copyright (C) 2012 AK signal Brno a.s.
5 * 2012 Jiri Prchal <jiri.prchal@aksignal.cz>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/dts-v1/;
11
12/include/ "ge863-pro3.dtsi"
13
14/ {
15 chosen {
16 bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs";
17 };
18
19 ahb {
20 apb {
21 usart0: serial@fffb0000 {
22 status = "okay";
23 };
24
25 usart1: serial@fffb4000 {
26 status = "okay";
27 linux,rs485-enabled-at-boot-time;
28 rs485-rts-delay = <0 0>;
29 };
30
31 usart2: serial@fffb8000 {
32 status = "okay";
33 linux,rs485-enabled-at-boot-time;
34 rs485-rts-delay = <0 0>;
35 };
36
37 usart3: serial@fffd0000 {
38 status = "okay";
39 linux,rs485-enabled-at-boot-time;
40 rs485-rts-delay = <0 0>;
41 };
42
43 macb0: ethernet@fffc4000 {
44 phy-mode = "rmii";
45 status = "okay";
46 };
47
48 usb1: gadget@fffa4000 {
49 atmel,vbus-gpio = <&pioC 15 0>;
50 status = "okay";
51 };
52 };
53
54 usb0: ohci@00500000 {
55 num-ports = <2>;
56 status = "okay";
57 };
58
59 nand0: nand@40000000 {
60 nand-bus-width = <8>;
61 nand-ecc-mode = "soft";
62 nand-on-flash-bbt;
63 status = "okay";
64
65 bootstrap@0 {
66 label = "bootstrap";
67 reg = <0x0 0x40000>;
68 };
69
70 uboot@40000 {
71 label = "uboot";
72 reg = <0x40000 0x80000>;
73 };
74 ubootenv@c0000 {
75 label = "ubootenv";
76 reg = <0xc0000 0x40000>;
77 };
78 kernel@100000 {
79 label = "kernel";
80 reg = <0x100000 0x400000>;
81 };
82 rootfs@500000 {
83 label = "rootfs";
84 reg = <0x500000 0x7b00000>;
85 };
86 };
87 };
88
89 leds {
90 compatible = "gpio-leds";
91
92 red {
93 gpios = <&pioC 10 0>;
94 linux,default-trigger = "none";
95 };
96
97 green {
98 gpios = <&pioA 5 1>;
99 linux,default-trigger = "none";
100 default-state = "on";
101 };
102
103 yellow {
104 gpios = <&pioB 20 1>;
105 linux,default-trigger = "none";
106 };
107
108 blue {
109 gpios = <&pioB 21 1>;
110 linux,default-trigger = "none";
111 };
112 };
113};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
new file mode 100644
index 000000000000..a9af4db7234c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "am33xx.dtsi"
11
12/ {
13 model = "TI AM335x BeagleBone";
14 compatible = "ti,am335x-bone", "ti,am33xx";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
new file mode 100644
index 000000000000..d6a97d9eff72
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "am33xx.dtsi"
11
12/ {
13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
new file mode 100644
index 000000000000..59509c48d7e5
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -0,0 +1,158 @@
1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
15
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 serial5 = &uart6;
23 };
24
25 cpus {
26 cpu@0 {
27 compatible = "arm,cortex-a8";
28 };
29 };
30
31 /*
32 * The soc node represents the soc top level view. It is uses for IPs
33 * that are not memory mapped in the MPU view or for the MPU itself.
34 */
35 soc {
36 compatible = "ti,omap-infra";
37 mpu {
38 compatible = "ti,omap3-mpu";
39 ti,hwmods = "mpu";
40 };
41 };
42
43 /*
44 * XXX: Use a flat representation of the AM33XX interconnect.
45 * The real AM33XX interconnect network is quite complex.Since
46 * that will not bring real advantage to represent that in DT
47 * for the moment, just use a fake OCP bus entry to represent
48 * the whole bus hierarchy.
49 */
50 ocp {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55 ti,hwmods = "l3_main";
56
57 intc: interrupt-controller@48200000 {
58 compatible = "ti,omap2-intc";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 ti,intc-size = <128>;
62 reg = <0x48200000 0x1000>;
63 };
64
65 gpio1: gpio@44e07000 {
66 compatible = "ti,omap4-gpio";
67 ti,hwmods = "gpio1";
68 gpio-controller;
69 #gpio-cells = <2>;
70 interrupt-controller;
71 #interrupt-cells = <1>;
72 };
73
74 gpio2: gpio@4804C000 {
75 compatible = "ti,omap4-gpio";
76 ti,hwmods = "gpio2";
77 gpio-controller;
78 #gpio-cells = <2>;
79 interrupt-controller;
80 #interrupt-cells = <1>;
81 };
82
83 gpio3: gpio@481AC000 {
84 compatible = "ti,omap4-gpio";
85 ti,hwmods = "gpio3";
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupt-controller;
89 #interrupt-cells = <1>;
90 };
91
92 gpio4: gpio@481AE000 {
93 compatible = "ti,omap4-gpio";
94 ti,hwmods = "gpio4";
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <1>;
99 };
100
101 uart1: serial@44E09000 {
102 compatible = "ti,omap3-uart";
103 ti,hwmods = "uart1";
104 clock-frequency = <48000000>;
105 };
106
107 uart2: serial@48022000 {
108 compatible = "ti,omap3-uart";
109 ti,hwmods = "uart2";
110 clock-frequency = <48000000>;
111 };
112
113 uart3: serial@48024000 {
114 compatible = "ti,omap3-uart";
115 ti,hwmods = "uart3";
116 clock-frequency = <48000000>;
117 };
118
119 uart4: serial@481A6000 {
120 compatible = "ti,omap3-uart";
121 ti,hwmods = "uart4";
122 clock-frequency = <48000000>;
123 };
124
125 uart5: serial@481A8000 {
126 compatible = "ti,omap3-uart";
127 ti,hwmods = "uart5";
128 clock-frequency = <48000000>;
129 };
130
131 uart6: serial@481AA000 {
132 compatible = "ti,omap3-uart";
133 ti,hwmods = "uart6";
134 clock-frequency = <48000000>;
135 };
136
137 i2c1: i2c@44E0B000 {
138 compatible = "ti,omap4-i2c";
139 #address-cells = <1>;
140 #size-cells = <0>;
141 ti,hwmods = "i2c1";
142 };
143
144 i2c2: i2c@4802A000 {
145 compatible = "ti,omap4-i2c";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 ti,hwmods = "i2c2";
149 };
150
151 i2c3: i2c@4819C000 {
152 compatible = "ti,omap4-i2c";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 ti,hwmods = "i2c3";
156 };
157 };
158};
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
new file mode 100644
index 000000000000..474f760ecadf
--- /dev/null
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI AM3517 EVM (AM3517/05)";
14 compatible = "ti,am3517-evm", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20};
21
22&i2c1 {
23 clock-frequency = <400000>;
24};
25
26&i2c2 {
27 clock-frequency = <400000>;
28};
29
30&i2c3 {
31 clock-frequency = <400000>;
32};
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index ec2be92b270d..3180a9c588b9 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -48,7 +48,7 @@
48 }; 48 };
49 49
50 rtc@80154000 { 50 rtc@80154000 {
51 compatible = "stericsson,db8500-rtc"; 51 compatible = "arm,rtc-pl031", "arm,primecell";
52 reg = <0x80154000 0x1000>; 52 reg = <0x80154000 0x1000>;
53 interrupts = <0 18 0x4>; 53 interrupts = <0 18 0x4>;
54 }; 54 };
@@ -60,7 +60,7 @@
60 interrupts = <0 119 0x4>; 60 interrupts = <0 119 0x4>;
61 interrupt-controller; 61 interrupt-controller;
62 #interrupt-cells = <2>; 62 #interrupt-cells = <2>;
63 supports-sleepmode; 63 st,supports-sleepmode;
64 gpio-controller; 64 gpio-controller;
65 #gpio-cells = <2>; 65 #gpio-cells = <2>;
66 gpio-bank = <0>; 66 gpio-bank = <0>;
@@ -73,7 +73,7 @@
73 interrupts = <0 120 0x4>; 73 interrupts = <0 120 0x4>;
74 interrupt-controller; 74 interrupt-controller;
75 #interrupt-cells = <2>; 75 #interrupt-cells = <2>;
76 supports-sleepmode; 76 st,supports-sleepmode;
77 gpio-controller; 77 gpio-controller;
78 #gpio-cells = <2>; 78 #gpio-cells = <2>;
79 gpio-bank = <1>; 79 gpio-bank = <1>;
@@ -86,7 +86,7 @@
86 interrupts = <0 121 0x4>; 86 interrupts = <0 121 0x4>;
87 interrupt-controller; 87 interrupt-controller;
88 #interrupt-cells = <2>; 88 #interrupt-cells = <2>;
89 supports-sleepmode; 89 st,supports-sleepmode;
90 gpio-controller; 90 gpio-controller;
91 #gpio-cells = <2>; 91 #gpio-cells = <2>;
92 gpio-bank = <2>; 92 gpio-bank = <2>;
@@ -99,7 +99,7 @@
99 interrupts = <0 122 0x4>; 99 interrupts = <0 122 0x4>;
100 interrupt-controller; 100 interrupt-controller;
101 #interrupt-cells = <2>; 101 #interrupt-cells = <2>;
102 supports-sleepmode; 102 st,supports-sleepmode;
103 gpio-controller; 103 gpio-controller;
104 #gpio-cells = <2>; 104 #gpio-cells = <2>;
105 gpio-bank = <3>; 105 gpio-bank = <3>;
@@ -112,7 +112,7 @@
112 interrupts = <0 123 0x4>; 112 interrupts = <0 123 0x4>;
113 interrupt-controller; 113 interrupt-controller;
114 #interrupt-cells = <2>; 114 #interrupt-cells = <2>;
115 supports-sleepmode; 115 st,supports-sleepmode;
116 gpio-controller; 116 gpio-controller;
117 #gpio-cells = <2>; 117 #gpio-cells = <2>;
118 gpio-bank = <4>; 118 gpio-bank = <4>;
@@ -125,7 +125,7 @@
125 interrupts = <0 124 0x4>; 125 interrupts = <0 124 0x4>;
126 interrupt-controller; 126 interrupt-controller;
127 #interrupt-cells = <2>; 127 #interrupt-cells = <2>;
128 supports-sleepmode; 128 st,supports-sleepmode;
129 gpio-controller; 129 gpio-controller;
130 #gpio-cells = <2>; 130 #gpio-cells = <2>;
131 gpio-bank = <5>; 131 gpio-bank = <5>;
@@ -138,7 +138,7 @@
138 interrupts = <0 125 0x4>; 138 interrupts = <0 125 0x4>;
139 interrupt-controller; 139 interrupt-controller;
140 #interrupt-cells = <2>; 140 #interrupt-cells = <2>;
141 supports-sleepmode; 141 st,supports-sleepmode;
142 gpio-controller; 142 gpio-controller;
143 #gpio-cells = <2>; 143 #gpio-cells = <2>;
144 gpio-bank = <6>; 144 gpio-bank = <6>;
@@ -151,7 +151,7 @@
151 interrupts = <0 126 0x4>; 151 interrupts = <0 126 0x4>;
152 interrupt-controller; 152 interrupt-controller;
153 #interrupt-cells = <2>; 153 #interrupt-cells = <2>;
154 supports-sleepmode; 154 st,supports-sleepmode;
155 gpio-controller; 155 gpio-controller;
156 #gpio-cells = <2>; 156 #gpio-cells = <2>;
157 gpio-bank = <7>; 157 gpio-bank = <7>;
@@ -164,7 +164,7 @@
164 interrupts = <0 127 0x4>; 164 interrupts = <0 127 0x4>;
165 interrupt-controller; 165 interrupt-controller;
166 #interrupt-cells = <2>; 166 #interrupt-cells = <2>;
167 supports-sleepmode; 167 st,supports-sleepmode;
168 gpio-controller; 168 gpio-controller;
169 #gpio-cells = <2>; 169 #gpio-cells = <2>;
170 gpio-bank = <8>; 170 gpio-bank = <8>;
@@ -331,6 +331,63 @@
331 compatible = "stericsson,ab8500"; 331 compatible = "stericsson,ab8500";
332 reg = <5>; /* mailbox 5 is i2c */ 332 reg = <5>; /* mailbox 5 is i2c */
333 interrupts = <0 40 0x4>; 333 interrupts = <0 40 0x4>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336
337 ab8500-rtc {
338 compatible = "stericsson,ab8500-rtc";
339 interrupts = <17 0x4
340 18 0x4>;
341 interrupt-names = "60S", "ALARM";
342 };
343
344 ab8500-gpadc {
345 compatible = "stericsson,ab8500-gpadc";
346 interrupts = <32 0x4
347 39 0x4>;
348 interrupt-names = "HW_CONV_END", "SW_CONV_END";
349 vddadc-supply = <&ab8500_ldo_tvout_reg>;
350 };
351
352 ab8500-usb {
353 compatible = "stericsson,ab8500-usb";
354 interrupts = < 90 0x4
355 96 0x4
356 14 0x4
357 15 0x4
358 79 0x4
359 74 0x4
360 75 0x4>;
361 interrupt-names = "ID_WAKEUP_R",
362 "ID_WAKEUP_F",
363 "VBUS_DET_F",
364 "VBUS_DET_R",
365 "USB_LINK_STATUS",
366 "USB_ADP_PROBE_PLUG",
367 "USB_ADP_PROBE_UNPLUG";
368 vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
369 v-ape-supply = <&db8500_vape_reg>;
370 musb_1v8-supply = <&db8500_vsmps2_reg>;
371 };
372
373 ab8500-ponkey {
374 compatible = "stericsson,ab8500-ponkey";
375 interrupts = <6 0x4
376 7 0x4>;
377 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
378 };
379
380 ab8500-sysctrl {
381 compatible = "stericsson,ab8500-sysctrl";
382 };
383
384 ab8500-pwm {
385 compatible = "stericsson,ab8500-pwm";
386 };
387
388 ab8500-debugfs {
389 compatible = "stericsson,ab8500-debug";
390 };
334 391
335 ab8500-regulators { 392 ab8500-regulators {
336 compatible = "stericsson,ab8500-regulator"; 393 compatible = "stericsson,ab8500-regulator";
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
index c07ba8c2cc0d..d79b28d9c963 100644
--- a/arch/arm/boot/dts/ea3250.dts
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -152,6 +152,23 @@
152 uart1: serial@40014000 { 152 uart1: serial@40014000 {
153 status = "okay"; 153 status = "okay";
154 }; 154 };
155
156 /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
157 adc@40048000 {
158 status = "okay";
159 };
160 };
161 };
162
163 gpio_keys {
164 compatible = "gpio-keys";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 autorepeat;
168 button@21 {
169 label = "GPIO Key UP";
170 linux,code = <103>;
171 gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
155 }; 172 };
156 }; 173 };
157}; 174};
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
new file mode 100644
index 000000000000..b7354e6506de
--- /dev/null
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -0,0 +1,41 @@
1/*
2 * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3
3 *
4 * Copyright (C) 2012 Telit,
5 * 2012 Fabio Porcedda <fabio.porcedda@gmail.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/dts-v1/;
11
12/include/ "ge863-pro3.dtsi"
13
14/ {
15 model = "Telit EVK-PRO3 for Telit GE863-PRO3";
16 compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";
17
18 ahb {
19 apb {
20 macb0: ethernet@fffc4000 {
21 phy-mode = "rmii";
22 status = "okay";
23 };
24
25 usb1: gadget@fffa4000 {
26 atmel,vbus-gpio = <&pioC 5 0>;
27 status = "okay";
28 };
29 };
30
31 usb0: ohci@00500000 {
32 num-ports = <2>;
33 status = "okay";
34 };
35 };
36
37 i2c@0 {
38 status = "okay";
39 };
40
41}; \ No newline at end of file
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index b8c476384eef..0c49caa09978 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -134,4 +134,16 @@
134 i2c@138D0000 { 134 i2c@138D0000 {
135 status = "disabled"; 135 status = "disabled";
136 }; 136 };
137
138 spi_0: spi@13920000 {
139 status = "disabled";
140 };
141
142 spi_1: spi@13930000 {
143 status = "disabled";
144 };
145
146 spi_2: spi@13940000 {
147 status = "disabled";
148 };
137}; 149};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 27afc8e535ca..1beccc8f14ff 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -179,4 +179,42 @@
179 i2c@138D0000 { 179 i2c@138D0000 {
180 status = "disabled"; 180 status = "disabled";
181 }; 181 };
182
183 spi_0: spi@13920000 {
184 status = "disabled";
185 };
186
187 spi_1: spi@13930000 {
188 status = "disabled";
189 };
190
191 spi_2: spi@13940000 {
192 gpios = <&gpc1 1 5 3 0>,
193 <&gpc1 3 5 3 0>,
194 <&gpc1 4 5 3 0>;
195
196 w25x80@0 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 compatible = "w25x80";
200 reg = <0>;
201 spi-max-frequency = <1000000>;
202
203 controller-data {
204 cs-gpio = <&gpc1 2 1 0 3>;
205 samsung,spi-feedback-delay = <0>;
206 };
207
208 partition@0 {
209 label = "U-Boot";
210 reg = <0x0 0x40000>;
211 read-only;
212 };
213
214 partition@40000 {
215 label = "Kernel";
216 reg = <0x40000 0xc0000>;
217 };
218 };
219 };
182}; 220};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee83753..02891fe876e4 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -25,6 +25,12 @@
25 compatible = "samsung,exynos4210"; 25 compatible = "samsung,exynos4210";
26 interrupt-parent = <&gic>; 26 interrupt-parent = <&gic>;
27 27
28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
32 };
33
28 gic:interrupt-controller@10490000 { 34 gic:interrupt-controller@10490000 {
29 compatible = "arm,cortex-a9-gic"; 35 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>; 36 #interrupt-cells = <3>;
@@ -33,6 +39,17 @@
33 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 39 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
34 }; 40 };
35 41
42 combiner:interrupt-controller@10440000 {
43 compatible = "samsung,exynos4210-combiner";
44 #interrupt-cells = <2>;
45 interrupt-controller;
46 reg = <0x10440000 0x1000>;
47 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
48 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
49 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
50 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
51 };
52
36 watchdog@10060000 { 53 watchdog@10060000 {
37 compatible = "samsung,s3c2410-wdt"; 54 compatible = "samsung,s3c2410-wdt";
38 reg = <0x10060000 0x100>; 55 reg = <0x10060000 0x100>;
@@ -147,6 +164,36 @@
147 interrupts = <0 65 0>; 164 interrupts = <0 65 0>;
148 }; 165 };
149 166
167 spi_0: spi@13920000 {
168 compatible = "samsung,exynos4210-spi";
169 reg = <0x13920000 0x100>;
170 interrupts = <0 66 0>;
171 tx-dma-channel = <&pdma0 7>; /* preliminary */
172 rx-dma-channel = <&pdma0 6>; /* preliminary */
173 #address-cells = <1>;
174 #size-cells = <0>;
175 };
176
177 spi_1: spi@13930000 {
178 compatible = "samsung,exynos4210-spi";
179 reg = <0x13930000 0x100>;
180 interrupts = <0 67 0>;
181 tx-dma-channel = <&pdma1 7>; /* preliminary */
182 rx-dma-channel = <&pdma1 6>; /* preliminary */
183 #address-cells = <1>;
184 #size-cells = <0>;
185 };
186
187 spi_2: spi@13940000 {
188 compatible = "samsung,exynos4210-spi";
189 reg = <0x13940000 0x100>;
190 interrupts = <0 68 0>;
191 tx-dma-channel = <&pdma0 9>; /* preliminary */
192 rx-dma-channel = <&pdma0 8>; /* preliminary */
193 #address-cells = <1>;
194 #size-cells = <0>;
195 };
196
150 amba { 197 amba {
151 #address-cells = <1>; 198 #address-cells = <1>;
152 #size-cells = <1>; 199 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49945cc1bc7d..8a5e348793c7 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -71,4 +71,42 @@
71 i2c@12CD0000 { 71 i2c@12CD0000 {
72 status = "disabled"; 72 status = "disabled";
73 }; 73 };
74
75 spi_0: spi@12d20000 {
76 status = "disabled";
77 };
78
79 spi_1: spi@12d30000 {
80 gpios = <&gpa2 4 2 3 0>,
81 <&gpa2 6 2 3 0>,
82 <&gpa2 7 2 3 0>;
83
84 w25q80bw@0 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 compatible = "w25x80";
88 reg = <0>;
89 spi-max-frequency = <1000000>;
90
91 controller-data {
92 cs-gpio = <&gpa2 5 1 0 3>;
93 samsung,spi-feedback-delay = <0>;
94 };
95
96 partition@0 {
97 label = "U-Boot";
98 reg = <0x0 0x40000>;
99 read-only;
100 };
101
102 partition@40000 {
103 label = "Kernel";
104 reg = <0x40000 0xc0000>;
105 };
106 };
107 };
108
109 spi_2: spi@12d40000 {
110 status = "disabled";
111 };
74}; 112};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4272b2949228..004aaa8d123c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,6 +23,12 @@
23 compatible = "samsung,exynos5250"; 23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>; 24 interrupt-parent = <&gic>;
25 25
26 aliases {
27 spi0 = &spi_0;
28 spi1 = &spi_1;
29 spi2 = &spi_2;
30 };
31
26 gic:interrupt-controller@10481000 { 32 gic:interrupt-controller@10481000 {
27 compatible = "arm,cortex-a9-gic"; 33 compatible = "arm,cortex-a9-gic";
28 #interrupt-cells = <3>; 34 #interrupt-cells = <3>;
@@ -146,6 +152,36 @@
146 #size-cells = <0>; 152 #size-cells = <0>;
147 }; 153 };
148 154
155 spi_0: spi@12d20000 {
156 compatible = "samsung,exynos4210-spi";
157 reg = <0x12d20000 0x100>;
158 interrupts = <0 66 0>;
159 tx-dma-channel = <&pdma0 5>; /* preliminary */
160 rx-dma-channel = <&pdma0 4>; /* preliminary */
161 #address-cells = <1>;
162 #size-cells = <0>;
163 };
164
165 spi_1: spi@12d30000 {
166 compatible = "samsung,exynos4210-spi";
167 reg = <0x12d30000 0x100>;
168 interrupts = <0 67 0>;
169 tx-dma-channel = <&pdma1 5>; /* preliminary */
170 rx-dma-channel = <&pdma1 4>; /* preliminary */
171 #address-cells = <1>;
172 #size-cells = <0>;
173 };
174
175 spi_2: spi@12d40000 {
176 compatible = "samsung,exynos4210-spi";
177 reg = <0x12d40000 0x100>;
178 interrupts = <0 68 0>;
179 tx-dma-channel = <&pdma0 7>; /* preliminary */
180 rx-dma-channel = <&pdma0 6>; /* preliminary */
181 #address-cells = <1>;
182 #size-cells = <0>;
183 };
184
149 amba { 185 amba {
150 #address-cells = <1>; 186 #address-cells = <1>;
151 #size-cells = <1>; 187 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
new file mode 100644
index 000000000000..17136fc7a516
--- /dev/null
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -0,0 +1,52 @@
1/*
2 * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
3 *
4 * Copyright (C) 2012 Telit,
5 * 2012 Fabio Porcedda <fabio.porcedda@gmail.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "at91sam9260.dtsi"
11
12/ {
13 clocks {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 main_clock: clock@0 {
19 compatible = "atmel,osc", "fixed-clock";
20 clock-frequency = <6000000>;
21 };
22 };
23
24 ahb {
25 apb {
26 dbgu: serial@fffff200 {
27 status = "okay";
28 };
29 };
30
31 nand0: nand@40000000 {
32 nand-bus-width = <8>;
33 nand-ecc-mode = "soft";
34 nand-on-flash-bbt;
35 status = "okay";
36
37 boot@0 {
38 label = "boot";
39 reg = <0x0 0x7c0000>;
40 };
41
42 root@07c0000 {
43 label = "root";
44 reg = <0x7c0000 0x7840000>;
45 };
46 };
47 };
48
49 chosen {
50 bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs";
51 };
52};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 70bffa929b65..e3486f486b40 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -22,17 +22,60 @@
22 22
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
28 status = "okay";
29 };
30
25 ssp0: ssp@80010000 { 31 ssp0: ssp@80010000 {
26 compatible = "fsl,imx23-mmc"; 32 compatible = "fsl,imx23-mmc";
27 pinctrl-names = "default"; 33 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>; 34 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
29 bus-width = <8>; 35 bus-width = <4>;
30 wp-gpios = <&gpio1 30 0>; 36 wp-gpios = <&gpio1 30 0>;
37 vmmc-supply = <&reg_vddio_sd0>;
38 status = "okay";
39 };
40
41 pinctrl@80018000 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&hog_pins_a>;
44
45 hog_pins_a: hog-gpios@0 {
46 reg = <0>;
47 fsl,pinmux-ids = <
48 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
49 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
50 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
51 >;
52 fsl,drive-strength = <0>;
53 fsl,voltage = <1>;
54 fsl,pull-up = <0>;
55 };
56 };
57
58 lcdif@80030000 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&lcdif_24bit_pins_a>;
61 panel-enable-gpios = <&gpio1 18 0>;
31 status = "okay"; 62 status = "okay";
32 }; 63 };
33 }; 64 };
34 65
35 apbx@80040000 { 66 apbx@80040000 {
67 pwm: pwm@80064000 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pwm2_pins_a>;
70 status = "okay";
71 };
72
73 auart0: serial@8006c000 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&auart0_pins_a>;
76 status = "okay";
77 };
78
36 duart: serial@80070000 { 79 duart: serial@80070000 {
37 pinctrl-names = "default"; 80 pinctrl-names = "default";
38 pinctrl-0 = <&duart_pins_a>; 81 pinctrl-0 = <&duart_pins_a>;
@@ -40,4 +83,23 @@
40 }; 83 };
41 }; 84 };
42 }; 85 };
86
87 regulators {
88 compatible = "simple-bus";
89
90 reg_vddio_sd0: vddio-sd0 {
91 compatible = "regulator-fixed";
92 regulator-name = "vddio-sd0";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 gpio = <&gpio1 29 0>;
96 };
97 };
98
99 backlight {
100 compatible = "pwm-backlight";
101 pwms = <&pwm 2 5000000>;
102 brightness-levels = <0 4 8 16 32 64 128 255>;
103 default-brightness-level = <6>;
104 };
43}; 105};
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
new file mode 100644
index 000000000000..20912b1d8893
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "imx23.dtsi"
16
17/ {
18 model = "i.MX23 Olinuxino Low Cost Board";
19 compatible = "olimex,imx23-olinuxino", "fsl,imx23";
20
21 memory {
22 reg = <0x40000000 0x04000000>;
23 };
24
25 apb@80000000 {
26 apbh@80000000 {
27 ssp0: ssp@80010000 {
28 compatible = "fsl,imx23-mmc";
29 pinctrl-names = "default";
30 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
31 bus-width = <4>;
32 status = "okay";
33 };
34 };
35
36 apbx@80040000 {
37 duart: serial@80070000 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&duart_pins_a>;
40 status = "okay";
41 };
42 };
43 };
44};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
new file mode 100644
index 000000000000..757a327ff3e8
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx23.dtsi"
14
15/ {
16 model = "Freescale STMP378x Development Board";
17 compatible = "fsl,stmp378x-devb", "fsl,imx23";
18
19 memory {
20 reg = <0x40000000 0x04000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx23-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
29 bus-width = <4>;
30 wp-gpios = <&gpio1 30 0>;
31 vmmc-supply = <&reg_vddio_sd0>;
32 status = "okay";
33 };
34
35 pinctrl@80018000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&hog_pins_a>;
38
39 hog_pins_a: hog-gpios@0 {
40 reg = <0>;
41 fsl,pinmux-ids = <
42 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
43 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
44 >;
45 fsl,drive-strength = <0>;
46 fsl,voltage = <1>;
47 fsl,pull-up = <0>;
48 };
49 };
50 };
51
52 apbx@80040000 {
53 auart0: serial@8006c000 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&auart0_pins_a>;
56 status = "okay";
57 };
58
59 duart: serial@80070000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&duart_pins_a>;
62 status = "okay";
63 };
64 };
65 };
66
67 regulators {
68 compatible = "simple-bus";
69
70 reg_vddio_sd0: vddio-sd0 {
71 compatible = "regulator-fixed";
72 regulator-name = "vddio-sd0";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio1 29 0>;
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 8c5f9994f3fc..a874dbfb5ae6 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -18,6 +18,8 @@
18 gpio0 = &gpio0; 18 gpio0 = &gpio0;
19 gpio1 = &gpio1; 19 gpio1 = &gpio1;
20 gpio2 = &gpio2; 20 gpio2 = &gpio2;
21 serial0 = &auart0;
22 serial1 = &auart1;
21 }; 23 };
22 24
23 cpus { 25 cpus {
@@ -57,13 +59,15 @@
57 status = "disabled"; 59 status = "disabled";
58 }; 60 };
59 61
60 bch@8000a000 { 62 gpmi-nand@8000c000 {
61 reg = <0x8000a000 2000>; 63 compatible = "fsl,imx23-gpmi-nand";
62 status = "disabled"; 64 #address-cells = <1>;
63 }; 65 #size-cells = <1>;
64 66 reg = <0x8000c000 2000>, <0x8000a000 2000>;
65 gpmi@8000c000 { 67 reg-names = "gpmi-nand", "bch";
66 reg = <0x8000c000 2000>; 68 interrupts = <13>, <56>;
69 interrupt-names = "gpmi-dma", "bch";
70 fsl,gpmi-dma-channel = <4>;
67 status = "disabled"; 71 status = "disabled";
68 }; 72 };
69 73
@@ -114,24 +118,151 @@
114 118
115 duart_pins_a: duart@0 { 119 duart_pins_a: duart@0 {
116 reg = <0>; 120 reg = <0>;
117 fsl,pinmux-ids = <0x11a2 0x11b2>; 121 fsl,pinmux-ids = <
122 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
123 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
124 >;
125 fsl,drive-strength = <0>;
126 fsl,voltage = <1>;
127 fsl,pull-up = <0>;
128 };
129
130 auart0_pins_a: auart0@0 {
131 reg = <0>;
132 fsl,pinmux-ids = <
133 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
134 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
135 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
136 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
137 >;
118 fsl,drive-strength = <0>; 138 fsl,drive-strength = <0>;
119 fsl,voltage = <1>; 139 fsl,voltage = <1>;
120 fsl,pull-up = <0>; 140 fsl,pull-up = <0>;
121 }; 141 };
122 142
143 gpmi_pins_a: gpmi-nand@0 {
144 reg = <0>;
145 fsl,pinmux-ids = <
146 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
147 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
148 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
149 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
150 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
151 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
152 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
153 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
154 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
155 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
156 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
157 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
158 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
159 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
160 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
161 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
162 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
163 >;
164 fsl,drive-strength = <0>;
165 fsl,voltage = <1>;
166 fsl,pull-up = <0>;
167 };
168
169 gpmi_pins_fixup: gpmi-pins-fixup {
170 fsl,pinmux-ids = <
171 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
172 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
173 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
174 >;
175 fsl,drive-strength = <2>;
176 };
177
178 mmc0_4bit_pins_a: mmc0-4bit@0 {
179 reg = <0>;
180 fsl,pinmux-ids = <
181 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
182 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
183 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
184 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
185 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
186 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
187 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
188 >;
189 fsl,drive-strength = <1>;
190 fsl,voltage = <1>;
191 fsl,pull-up = <1>;
192 };
193
123 mmc0_8bit_pins_a: mmc0-8bit@0 { 194 mmc0_8bit_pins_a: mmc0-8bit@0 {
124 reg = <0>; 195 reg = <0>;
125 fsl,pinmux-ids = <0x2020 0x2030 0x2040 196 fsl,pinmux-ids = <
126 0x2050 0x0082 0x0092 0x00a2 197 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
127 0x00b2 0x2000 0x2010 0x2060>; 198 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
199 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
200 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
201 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
202 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
203 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
204 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
205 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
206 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
207 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
208 >;
128 fsl,drive-strength = <1>; 209 fsl,drive-strength = <1>;
129 fsl,voltage = <1>; 210 fsl,voltage = <1>;
130 fsl,pull-up = <1>; 211 fsl,pull-up = <1>;
131 }; 212 };
132 213
133 mmc0_pins_fixup: mmc0-pins-fixup { 214 mmc0_pins_fixup: mmc0-pins-fixup {
134 fsl,pinmux-ids = <0x2010 0x2060>; 215 fsl,pinmux-ids = <
216 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
217 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
218 >;
219 fsl,pull-up = <0>;
220 };
221
222 pwm2_pins_a: pwm2@0 {
223 reg = <0>;
224 fsl,pinmux-ids = <
225 0x11c0 /* MX23_PAD_PWM2__PWM2 */
226 >;
227 fsl,drive-strength = <0>;
228 fsl,voltage = <1>;
229 fsl,pull-up = <0>;
230 };
231
232 lcdif_24bit_pins_a: lcdif-24bit@0 {
233 reg = <0>;
234 fsl,pinmux-ids = <
235 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
236 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
237 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
238 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
239 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
240 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
241 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
242 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
243 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
244 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
245 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
246 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
247 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
248 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
249 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
250 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
251 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
252 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
253 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
254 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
255 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
256 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
257 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
258 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
259 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
260 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
261 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
262 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
263 >;
264 fsl,drive-strength = <0>;
265 fsl,voltage = <1>;
135 fsl,pull-up = <0>; 266 fsl,pull-up = <0>;
136 }; 267 };
137 }; 268 };
@@ -172,7 +303,9 @@
172 }; 303 };
173 304
174 lcdif@80030000 { 305 lcdif@80030000 {
306 compatible = "fsl,imx23-lcdif";
175 reg = <0x80030000 2000>; 307 reg = <0x80030000 2000>;
308 interrupts = <46 45>;
176 status = "disabled"; 309 status = "disabled";
177 }; 310 };
178 311
@@ -242,12 +375,16 @@
242 }; 375 };
243 376
244 rtc@8005c000 { 377 rtc@8005c000 {
378 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
245 reg = <0x8005c000 2000>; 379 reg = <0x8005c000 2000>;
246 status = "disabled"; 380 interrupts = <22>;
247 }; 381 };
248 382
249 pwm@80064000 { 383 pwm: pwm@80064000 {
384 compatible = "fsl,imx23-pwm";
250 reg = <0x80064000 2000>; 385 reg = <0x80064000 2000>;
386 #pwm-cells = <2>;
387 fsl,pwm-number = <5>;
251 status = "disabled"; 388 status = "disabled";
252 }; 389 };
253 390
@@ -257,12 +394,16 @@
257 }; 394 };
258 395
259 auart0: serial@8006c000 { 396 auart0: serial@8006c000 {
397 compatible = "fsl,imx23-auart";
260 reg = <0x8006c000 0x2000>; 398 reg = <0x8006c000 0x2000>;
399 interrupts = <24 25 23>;
261 status = "disabled"; 400 status = "disabled";
262 }; 401 };
263 402
264 auart1: serial@8006e000 { 403 auart1: serial@8006e000 {
404 compatible = "fsl,imx23-auart";
265 reg = <0x8006e000 0x2000>; 405 reg = <0x8006e000 0x2000>;
406 interrupts = <59 60 58>;
266 status = "disabled"; 407 status = "disabled";
267 }; 408 };
268 409
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
new file mode 100644
index 000000000000..d3f8296e19e0
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx27.dtsi"
14
15/ {
16 model = "mx27_3ds";
17 compatible = "freescale,imx27-3ds", "fsl,imx27";
18
19 memory {
20 reg = <0x0 0x0>;
21 };
22
23 soc {
24 aipi@10000000 { /* aipi */
25
26 wdog@10002000 {
27 status = "okay";
28 };
29
30 uart@1000a000 {
31 fsl,uart-has-rtscts;
32 status = "okay";
33 };
34
35 fec@1002b000 {
36 status = "okay";
37 };
38 };
39 };
40
41};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 386c769c38d1..00bae3aad5ab 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -121,7 +121,7 @@
121 gpio-controller; 121 gpio-controller;
122 #gpio-cells = <2>; 122 #gpio-cells = <2>;
123 interrupt-controller; 123 interrupt-controller;
124 #interrupt-cells = <1>; 124 #interrupt-cells = <2>;
125 }; 125 };
126 126
127 gpio2: gpio@10015100 { 127 gpio2: gpio@10015100 {
@@ -131,7 +131,7 @@
131 gpio-controller; 131 gpio-controller;
132 #gpio-cells = <2>; 132 #gpio-cells = <2>;
133 interrupt-controller; 133 interrupt-controller;
134 #interrupt-cells = <1>; 134 #interrupt-cells = <2>;
135 }; 135 };
136 136
137 gpio3: gpio@10015200 { 137 gpio3: gpio@10015200 {
@@ -141,7 +141,7 @@
141 gpio-controller; 141 gpio-controller;
142 #gpio-cells = <2>; 142 #gpio-cells = <2>;
143 interrupt-controller; 143 interrupt-controller;
144 #interrupt-cells = <1>; 144 #interrupt-cells = <2>;
145 }; 145 };
146 146
147 gpio4: gpio@10015300 { 147 gpio4: gpio@10015300 {
@@ -151,7 +151,7 @@
151 gpio-controller; 151 gpio-controller;
152 #gpio-cells = <2>; 152 #gpio-cells = <2>;
153 interrupt-controller; 153 interrupt-controller;
154 #interrupt-cells = <1>; 154 #interrupt-cells = <2>;
155 }; 155 };
156 156
157 gpio5: gpio@10015400 { 157 gpio5: gpio@10015400 {
@@ -161,7 +161,7 @@
161 gpio-controller; 161 gpio-controller;
162 #gpio-cells = <2>; 162 #gpio-cells = <2>;
163 interrupt-controller; 163 interrupt-controller;
164 #interrupt-cells = <1>; 164 #interrupt-cells = <2>;
165 }; 165 };
166 166
167 gpio6: gpio@10015500 { 167 gpio6: gpio@10015500 {
@@ -171,7 +171,7 @@
171 gpio-controller; 171 gpio-controller;
172 #gpio-cells = <2>; 172 #gpio-cells = <2>;
173 interrupt-controller; 173 interrupt-controller;
174 #interrupt-cells = <1>; 174 #interrupt-cells = <2>;
175 }; 175 };
176 176
177 cspi3: cspi@10017000 { 177 cspi3: cspi@10017000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
new file mode 100644
index 000000000000..b383417a558f
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -0,0 +1,198 @@
1/dts-v1/;
2/include/ "imx28.dtsi"
3
4/ {
5 model = "Bluegiga APX4 Development Kit";
6 compatible = "bluegiga,apx4devkit", "fsl,imx28";
7
8 memory {
9 reg = <0x40000000 0x04000000>;
10 };
11
12 apb@80000000 {
13 apbh@80000000 {
14 gpmi-nand@8000c000 {
15 pinctrl-names = "default";
16 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
17 status = "okay";
18 };
19
20 ssp0: ssp@80010000 {
21 compatible = "fsl,imx28-mmc";
22 pinctrl-names = "default";
23 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
24 bus-width = <4>;
25 status = "okay";
26 };
27
28 ssp2: ssp@80014000 {
29 compatible = "fsl,imx28-mmc";
30 pinctrl-names = "default";
31 pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
32 bus-width = <4>;
33 status = "okay";
34 };
35
36 pinctrl@80018000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&hog_pins_a>;
39
40 hog_pins_a: hog-gpios@0 {
41 reg = <0>;
42 fsl,pinmux-ids = <
43 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
44 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */
45 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */
46 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */
47 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
48 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
49 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */
50 >;
51 fsl,drive-strength = <0>;
52 fsl,voltage = <1>;
53 fsl,pull-up = <0>;
54 };
55
56 lcdif_pins_apx4: lcdif-apx4@0 {
57 reg = <0>;
58 fsl,pinmux-ids = <
59 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
60 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
61 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
62 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
63 >;
64 fsl,drive-strength = <0>;
65 fsl,voltage = <1>;
66 fsl,pull-up = <0>;
67 };
68
69 mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
70 reg = <0>;
71 fsl,pinmux-ids = <
72 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */
73 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */
74 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */
75 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
76 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */
77 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */
78 >;
79 fsl,drive-strength = <1>;
80 fsl,voltage = <1>;
81 fsl,pull-up = <1>;
82 };
83
84 mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
85 fsl,pinmux-ids = <
86 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
87 >;
88 fsl,drive-strength = <2>;
89 fsl,pull-up = <0>;
90 };
91 };
92
93 lcdif@80030000 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&lcdif_24bit_pins_a
96 &lcdif_pins_apx4>;
97 status = "okay";
98 };
99 };
100
101 apbx@80040000 {
102 saif0: saif@80042000 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&saif0_pins_a>;
105 status = "okay";
106 };
107
108 saif1: saif@80046000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&saif1_pins_a>;
111 fsl,saif-master = <&saif0>;
112 status = "okay";
113 };
114
115 i2c0: i2c@80058000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&i2c0_pins_a>;
118 status = "okay";
119
120 sgtl5000: codec@0a {
121 compatible = "fsl,sgtl5000";
122 reg = <0x0a>;
123 VDDA-supply = <&reg_3p3v>;
124 VDDIO-supply = <&reg_3p3v>;
125
126 };
127
128 pcf8563: rtc@51 {
129 compatible = "phg,pcf8563";
130 reg = <0x51>;
131 };
132 };
133
134 duart: serial@80074000 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&duart_pins_a>;
137 status = "okay";
138 };
139
140 auart0: serial@8006a000 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&auart0_pins_a>;
143 status = "okay";
144 };
145
146 auart1: serial@8006c000 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&auart1_2pins_a>;
149 status = "okay";
150 };
151
152 auart2: serial@8006e000 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&auart2_2pins_a>;
155 status = "okay";
156 };
157 };
158 };
159
160 ahb@80080000 {
161 mac0: ethernet@800f0000 {
162 phy-mode = "rmii";
163 pinctrl-names = "default";
164 pinctrl-0 = <&mac0_pins_a>;
165 status = "okay";
166 };
167 };
168
169 regulators {
170 compatible = "simple-bus";
171
172 reg_3p3v: 3p3v {
173 compatible = "regulator-fixed";
174 regulator-name = "3P3V";
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
177 regulator-always-on;
178 };
179 };
180
181 sound {
182 compatible = "bluegiga,apx4devkit-sgtl5000",
183 "fsl,mxs-audio-sgtl5000";
184 model = "apx4devkit-sgtl5000";
185 saif-controllers = <&saif0 &saif1>;
186 audio-codec = <&sgtl5000>;
187 };
188
189 leds {
190 compatible = "gpio-leds";
191
192 user {
193 label = "Heartbeat";
194 gpios = <&gpio3 28 0>;
195 linux,default-trigger = "heartbeat";
196 };
197 };
198};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
new file mode 100644
index 000000000000..c03a577beca3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2012 Free Electrons
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Crystalfontz CFA-10036 Board";
17 compatible = "crystalfontz,cfa10036", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_4bit_pins_a
29 &mmc0_cd_cfg &mmc0_sck_cfg>;
30 bus-width = <4>;
31 status = "okay";
32 };
33 };
34
35 apbx@80040000 {
36 duart: serial@80074000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&duart_pins_b>;
39 status = "okay";
40 };
41 };
42 };
43
44 leds {
45 compatible = "gpio-leds";
46
47 power {
48 gpios = <&gpio3 4 1>;
49 default-state = "on";
50 };
51 };
52};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ee520a529cb4..773c0e84d1fb 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -22,6 +22,13 @@
22 22
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
28 &gpmi_pins_evk>;
29 status = "okay";
30 };
31
25 ssp0: ssp@80010000 { 32 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc"; 33 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default"; 34 pinctrl-names = "default";
@@ -29,6 +36,7 @@
29 &mmc0_cd_cfg &mmc0_sck_cfg>; 36 &mmc0_cd_cfg &mmc0_sck_cfg>;
30 bus-width = <8>; 37 bus-width = <8>;
31 wp-gpios = <&gpio2 12 0>; 38 wp-gpios = <&gpio2 12 0>;
39 vmmc-supply = <&reg_vddio_sd0>;
32 status = "okay"; 40 status = "okay";
33 }; 41 };
34 42
@@ -36,6 +44,72 @@
36 compatible = "fsl,imx28-mmc"; 44 compatible = "fsl,imx28-mmc";
37 bus-width = <8>; 45 bus-width = <8>;
38 wp-gpios = <&gpio0 28 0>; 46 wp-gpios = <&gpio0 28 0>;
47 };
48
49 pinctrl@80018000 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&hog_pins_a>;
52
53 hog_pins_a: hog-gpios@0 {
54 reg = <0>;
55 fsl,pinmux-ids = <
56 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
57 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */
58 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */
59 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
60 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
61 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
62 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
63 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
64 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
65 >;
66 fsl,drive-strength = <0>;
67 fsl,voltage = <1>;
68 fsl,pull-up = <0>;
69 };
70
71 gpmi_pins_evk: gpmi-nand-evk@0 {
72 reg = <0>;
73 fsl,pinmux-ids = <
74 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */
75 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */
76 >;
77 fsl,drive-strength = <0>;
78 fsl,voltage = <1>;
79 fsl,pull-up = <0>;
80 };
81
82 lcdif_pins_evk: lcdif-evk@0 {
83 reg = <0>;
84 fsl,pinmux-ids = <
85 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
86 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
87 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
88 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
89 >;
90 fsl,drive-strength = <0>;
91 fsl,voltage = <1>;
92 fsl,pull-up = <0>;
93 };
94 };
95
96 lcdif@80030000 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&lcdif_24bit_pins_a
99 &lcdif_pins_evk>;
100 panel-enable-gpios = <&gpio3 30 0>;
101 status = "okay";
102 };
103
104 can0: can@80032000 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&can0_pins_a>;
107 status = "okay";
108 };
109
110 can1: can@80034000 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&can1_pins_a>;
39 status = "okay"; 113 status = "okay";
40 }; 114 };
41 }; 115 };
@@ -68,19 +142,58 @@
68 }; 142 };
69 }; 143 };
70 144
145 pwm: pwm@80064000 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pwm2_pins_a>;
148 status = "okay";
149 };
150
71 duart: serial@80074000 { 151 duart: serial@80074000 {
72 pinctrl-names = "default"; 152 pinctrl-names = "default";
73 pinctrl-0 = <&duart_pins_a>; 153 pinctrl-0 = <&duart_pins_a>;
74 status = "okay"; 154 status = "okay";
75 }; 155 };
156
157 auart0: serial@8006a000 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&auart0_pins_a>;
160 status = "okay";
161 };
162
163 auart3: serial@80070000 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&auart3_pins_a>;
166 status = "okay";
167 };
168
169 usbphy0: usbphy@8007c000 {
170 status = "okay";
171 };
172
173 usbphy1: usbphy@8007e000 {
174 status = "okay";
175 };
76 }; 176 };
77 }; 177 };
78 178
79 ahb@80080000 { 179 ahb@80080000 {
180 usb0: usb@80080000 {
181 vbus-supply = <&reg_usb0_vbus>;
182 status = "okay";
183 };
184
185 usb1: usb@80090000 {
186 vbus-supply = <&reg_usb1_vbus>;
187 status = "okay";
188 };
189
80 mac0: ethernet@800f0000 { 190 mac0: ethernet@800f0000 {
81 phy-mode = "rmii"; 191 phy-mode = "rmii";
82 pinctrl-names = "default"; 192 pinctrl-names = "default";
83 pinctrl-0 = <&mac0_pins_a>; 193 pinctrl-0 = <&mac0_pins_a>;
194 phy-supply = <&reg_fec_3v3>;
195 phy-reset-gpios = <&gpio4 13 0>;
196 phy-reset-duration = <100>;
84 status = "okay"; 197 status = "okay";
85 }; 198 };
86 199
@@ -102,6 +215,40 @@
102 regulator-max-microvolt = <3300000>; 215 regulator-max-microvolt = <3300000>;
103 regulator-always-on; 216 regulator-always-on;
104 }; 217 };
218
219 reg_vddio_sd0: vddio-sd0 {
220 compatible = "regulator-fixed";
221 regulator-name = "vddio-sd0";
222 regulator-min-microvolt = <3300000>;
223 regulator-max-microvolt = <3300000>;
224 gpio = <&gpio3 28 0>;
225 };
226
227 reg_fec_3v3: fec-3v3 {
228 compatible = "regulator-fixed";
229 regulator-name = "fec-3v3";
230 regulator-min-microvolt = <3300000>;
231 regulator-max-microvolt = <3300000>;
232 gpio = <&gpio2 15 0>;
233 };
234
235 reg_usb0_vbus: usb0_vbus {
236 compatible = "regulator-fixed";
237 regulator-name = "usb0_vbus";
238 regulator-min-microvolt = <5000000>;
239 regulator-max-microvolt = <5000000>;
240 gpio = <&gpio3 9 0>;
241 enable-active-high;
242 };
243
244 reg_usb1_vbus: usb1_vbus {
245 compatible = "regulator-fixed";
246 regulator-name = "usb1_vbus";
247 regulator-min-microvolt = <5000000>;
248 regulator-max-microvolt = <5000000>;
249 gpio = <&gpio3 8 0>;
250 enable-active-high;
251 };
105 }; 252 };
106 253
107 sound { 254 sound {
@@ -111,4 +258,21 @@
111 saif-controllers = <&saif0 &saif1>; 258 saif-controllers = <&saif0 &saif1>;
112 audio-codec = <&sgtl5000>; 259 audio-codec = <&sgtl5000>;
113 }; 260 };
261
262 leds {
263 compatible = "gpio-leds";
264
265 user {
266 label = "Heartbeat";
267 gpios = <&gpio3 5 0>;
268 linux,default-trigger = "heartbeat";
269 };
270 };
271
272 backlight {
273 compatible = "pwm-backlight";
274 pwms = <&pwm 2 5000000>;
275 brightness-levels = <0 4 8 16 32 64 128 255>;
276 default-brightness-level = <6>;
277 };
114}; 278};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
new file mode 100644
index 000000000000..183a3fd2d859
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -0,0 +1,210 @@
1/*
2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "DENX M28EVK";
17 compatible = "denx,m28evk", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28 status = "okay";
29
30 partition@0 {
31 label = "bootloader";
32 reg = <0x00000000 0x00300000>;
33 read-only;
34 };
35
36 partition@1 {
37 label = "environment";
38 reg = <0x00300000 0x00080000>;
39 };
40
41 partition@2 {
42 label = "redundant-environment";
43 reg = <0x00380000 0x00080000>;
44 };
45
46 partition@3 {
47 label = "kernel";
48 reg = <0x00400000 0x00400000>;
49 };
50
51 partition@4 {
52 label = "filesystem";
53 reg = <0x00800000 0x0f800000>;
54 };
55 };
56
57 ssp0: ssp@80010000 {
58 compatible = "fsl,imx28-mmc";
59 pinctrl-names = "default";
60 pinctrl-0 = <&mmc0_8bit_pins_a
61 &mmc0_cd_cfg
62 &mmc0_sck_cfg>;
63 bus-width = <8>;
64 wp-gpios = <&gpio3 10 1>;
65 status = "okay";
66 };
67
68 pinctrl@80018000 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&hog_pins_a>;
71
72 hog_pins_a: hog-gpios@0 {
73 reg = <0>;
74 fsl,pinmux-ids = <
75 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
76 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
77 >;
78 fsl,drive-strength = <0>;
79 fsl,voltage = <1>;
80 fsl,pull-up = <0>;
81 };
82
83 lcdif_pins_m28: lcdif-m28@0 {
84 reg = <0>;
85 fsl,pinmux-ids = <
86 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */
87 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */
88 >;
89 fsl,drive-strength = <0>;
90 fsl,voltage = <1>;
91 fsl,pull-up = <0>;
92 };
93 };
94
95 lcdif@80030000 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&lcdif_24bit_pins_a
98 &lcdif_pins_m28>;
99 status = "okay";
100 };
101
102 can0: can@80032000 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&can0_pins_a>;
105 status = "okay";
106 };
107
108 can1: can@80034000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&can1_pins_a>;
111 status = "okay";
112 };
113 };
114
115 apbx@80040000 {
116 saif0: saif@80042000 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&saif0_pins_a>;
119 status = "okay";
120 };
121
122 saif1: saif@80046000 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&saif1_pins_a>;
125 fsl,saif-master = <&saif0>;
126 status = "okay";
127 };
128
129 i2c0: i2c@80058000 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&i2c0_pins_a>;
132 status = "okay";
133
134 sgtl5000: codec@0a {
135 compatible = "fsl,sgtl5000";
136 reg = <0x0a>;
137 VDDA-supply = <&reg_3p3v>;
138 VDDIO-supply = <&reg_3p3v>;
139
140 };
141
142 eeprom: eeprom@51 {
143 compatible = "atmel,24c128";
144 reg = <0x51>;
145 pagesize = <32>;
146 };
147
148 rtc: rtc@68 {
149 compatible = "stm,mt41t62";
150 reg = <0x68>;
151 };
152 };
153
154 duart: serial@80074000 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&duart_pins_a>;
157 status = "okay";
158 };
159
160 auart0: serial@8006a000 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&auart0_2pins_a>;
163 status = "okay";
164 };
165
166 auart3: serial@80070000 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&auart3_pins_a>;
169 status = "okay";
170 };
171 };
172 };
173
174 ahb@80080000 {
175 mac0: ethernet@800f0000 {
176 phy-mode = "rmii";
177 pinctrl-names = "default";
178 pinctrl-0 = <&mac0_pins_a>;
179 phy-reset-gpios = <&gpio3 11 0>;
180 status = "okay";
181 };
182
183 mac1: ethernet@800f4000 {
184 phy-mode = "rmii";
185 pinctrl-names = "default";
186 pinctrl-0 = <&mac1_pins_a>;
187 status = "okay";
188 };
189 };
190
191 regulators {
192 compatible = "simple-bus";
193
194 reg_3p3v: 3p3v {
195 compatible = "regulator-fixed";
196 regulator-name = "3P3V";
197 regulator-min-microvolt = <3300000>;
198 regulator-max-microvolt = <3300000>;
199 regulator-always-on;
200 };
201 };
202
203 sound {
204 compatible = "denx,m28evk-sgtl5000",
205 "fsl,mxs-audio-sgtl5000";
206 model = "m28evk-sgtl5000";
207 saif-controllers = <&saif0 &saif1>;
208 audio-codec = <&sgtl5000>;
209 };
210};
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
new file mode 100644
index 000000000000..62bf767409a6
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -0,0 +1,97 @@
1/dts-v1/;
2/include/ "imx28.dtsi"
3
4/ {
5 model = "Ka-Ro electronics TX28 module";
6 compatible = "karo,tx28", "fsl,imx28";
7
8 memory {
9 reg = <0x40000000 0x08000000>;
10 };
11
12 apb@80000000 {
13 apbh@80000000 {
14 ssp0: ssp@80010000 {
15 compatible = "fsl,imx28-mmc";
16 pinctrl-names = "default";
17 pinctrl-0 = <&mmc0_4bit_pins_a
18 &mmc0_cd_cfg
19 &mmc0_sck_cfg>;
20 bus-width = <4>;
21 status = "okay";
22 };
23
24 pinctrl@80018000 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&hog_pins_a>;
27
28 hog_pins_a: hog-gpios@0 {
29 reg = <0>;
30 fsl,pinmux-ids = <
31 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
32 >;
33 fsl,drive-strength = <0>;
34 fsl,voltage = <1>;
35 fsl,pull-up = <0>;
36 };
37 };
38 };
39
40 apbx@80040000 {
41 i2c0: i2c@80058000 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&i2c0_pins_a>;
44 status = "okay";
45
46 ds1339: rtc@68 {
47 compatible = "mxim,ds1339";
48 reg = <0x68>;
49 };
50 };
51
52 pwm: pwm@80064000 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pwm0_pins_a>;
55 status = "okay";
56 };
57
58 duart: serial@80074000 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&duart_4pins_a>;
61 status = "okay";
62 };
63
64 auart1: serial@8006c000 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&auart1_pins_a>;
67 status = "okay";
68 };
69 };
70 };
71
72 ahb@80080000 {
73 mac0: ethernet@800f0000 {
74 phy-mode = "rmii";
75 pinctrl-names = "default";
76 pinctrl-0 = <&mac0_pins_a>;
77 status = "okay";
78 };
79 };
80
81 leds {
82 compatible = "gpio-leds";
83
84 user {
85 label = "Heartbeat";
86 gpios = <&gpio4 10 0>;
87 linux,default-trigger = "heartbeat";
88 };
89 };
90
91 backlight {
92 compatible = "pwm-backlight";
93 pwms = <&pwm 0 5000000>;
94 brightness-levels = <0 4 8 16 32 64 128 255>;
95 default-brightness-level = <6>;
96 };
97};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb861a59..915db89e3644 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -22,6 +22,11 @@
22 gpio4 = &gpio4; 22 gpio4 = &gpio4;
23 saif0 = &saif0; 23 saif0 = &saif0;
24 saif1 = &saif1; 24 saif1 = &saif1;
25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
25 }; 30 };
26 31
27 cpus { 32 cpus {
@@ -68,15 +73,15 @@
68 status = "disabled"; 73 status = "disabled";
69 }; 74 };
70 75
71 bch@8000a000 { 76 gpmi-nand@8000c000 {
72 reg = <0x8000a000 2000>; 77 compatible = "fsl,imx28-gpmi-nand";
73 interrupts = <41>; 78 #address-cells = <1>;
74 status = "disabled"; 79 #size-cells = <1>;
75 }; 80 reg = <0x8000c000 2000>, <0x8000a000 2000>;
76 81 reg-names = "gpmi-nand", "bch";
77 gpmi@8000c000 { 82 interrupts = <88>, <41>;
78 reg = <0x8000c000 2000>; 83 interrupt-names = "gpmi-dma", "bch";
79 interrupts = <42 88>; 84 fsl,gpmi-dma-channel = <4>;
80 status = "disabled"; 85 status = "disabled";
81 }; 86 };
82 87
@@ -161,7 +166,150 @@
161 166
162 duart_pins_a: duart@0 { 167 duart_pins_a: duart@0 {
163 reg = <0>; 168 reg = <0>;
164 fsl,pinmux-ids = <0x3102 0x3112>; 169 fsl,pinmux-ids = <
170 0x3102 /* MX28_PAD_PWM0__DUART_RX */
171 0x3112 /* MX28_PAD_PWM1__DUART_TX */
172 >;
173 fsl,drive-strength = <0>;
174 fsl,voltage = <1>;
175 fsl,pull-up = <0>;
176 };
177
178 duart_pins_b: duart@1 {
179 reg = <1>;
180 fsl,pinmux-ids = <
181 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
182 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
183 >;
184 fsl,drive-strength = <0>;
185 fsl,voltage = <1>;
186 fsl,pull-up = <0>;
187 };
188
189 duart_4pins_a: duart-4pins@0 {
190 reg = <0>;
191 fsl,pinmux-ids = <
192 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
193 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
194 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
195 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
196 >;
197 fsl,drive-strength = <0>;
198 fsl,voltage = <1>;
199 fsl,pull-up = <0>;
200 };
201
202 gpmi_pins_a: gpmi-nand@0 {
203 reg = <0>;
204 fsl,pinmux-ids = <
205 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
206 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
207 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
208 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
209 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
210 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
211 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
212 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
213 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
214 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
215 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
216 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
217 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
218 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
219 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
220 >;
221 fsl,drive-strength = <0>;
222 fsl,voltage = <1>;
223 fsl,pull-up = <0>;
224 };
225
226 gpmi_status_cfg: gpmi-status-cfg {
227 fsl,pinmux-ids = <
228 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
229 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
230 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
231 >;
232 fsl,drive-strength = <2>;
233 };
234
235 auart0_pins_a: auart0@0 {
236 reg = <0>;
237 fsl,pinmux-ids = <
238 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
239 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
240 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
241 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
242 >;
243 fsl,drive-strength = <0>;
244 fsl,voltage = <1>;
245 fsl,pull-up = <0>;
246 };
247
248 auart0_2pins_a: auart0-2pins@0 {
249 reg = <0>;
250 fsl,pinmux-ids = <
251 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
252 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
253 >;
254 fsl,drive-strength = <0>;
255 fsl,voltage = <1>;
256 fsl,pull-up = <0>;
257 };
258
259 auart1_pins_a: auart1@0 {
260 reg = <0>;
261 fsl,pinmux-ids = <
262 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
263 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
264 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
265 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
266 >;
267 fsl,drive-strength = <0>;
268 fsl,voltage = <1>;
269 fsl,pull-up = <0>;
270 };
271
272 auart1_2pins_a: auart1-2pins@0 {
273 reg = <0>;
274 fsl,pinmux-ids = <
275 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
276 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
277 >;
278 fsl,drive-strength = <0>;
279 fsl,voltage = <1>;
280 fsl,pull-up = <0>;
281 };
282
283 auart2_2pins_a: auart2-2pins@0 {
284 reg = <0>;
285 fsl,pinmux-ids = <
286 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
287 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
288 >;
289 fsl,drive-strength = <0>;
290 fsl,voltage = <1>;
291 fsl,pull-up = <0>;
292 };
293
294 auart3_pins_a: auart3@0 {
295 reg = <0>;
296 fsl,pinmux-ids = <
297 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
298 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
299 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
300 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
301 >;
302 fsl,drive-strength = <0>;
303 fsl,voltage = <1>;
304 fsl,pull-up = <0>;
305 };
306
307 auart3_2pins_a: auart3-2pins@0 {
308 reg = <0>;
309 fsl,pinmux-ids = <
310 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
311 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
312 >;
165 fsl,drive-strength = <0>; 313 fsl,drive-strength = <0>;
166 fsl,voltage = <1>; 314 fsl,voltage = <1>;
167 fsl,pull-up = <0>; 315 fsl,pull-up = <0>;
@@ -169,9 +317,17 @@
169 317
170 mac0_pins_a: mac0@0 { 318 mac0_pins_a: mac0@0 {
171 reg = <0>; 319 reg = <0>;
172 fsl,pinmux-ids = <0x4000 0x4010 0x4020 320 fsl,pinmux-ids = <
173 0x4030 0x4040 0x4060 0x4070 321 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
174 0x4080 0x4100>; 322 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
323 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
324 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
325 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
326 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
327 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
328 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
329 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
330 >;
175 fsl,drive-strength = <1>; 331 fsl,drive-strength = <1>;
176 fsl,voltage = <1>; 332 fsl,voltage = <1>;
177 fsl,pull-up = <1>; 333 fsl,pull-up = <1>;
@@ -179,8 +335,14 @@
179 335
180 mac1_pins_a: mac1@0 { 336 mac1_pins_a: mac1@0 {
181 reg = <0>; 337 reg = <0>;
182 fsl,pinmux-ids = <0x40f1 0x4091 0x40a1 338 fsl,pinmux-ids = <
183 0x40e1 0x40b1 0x40c1>; 339 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
340 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
341 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
342 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
343 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
344 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
345 >;
184 fsl,drive-strength = <1>; 346 fsl,drive-strength = <1>;
185 fsl,voltage = <1>; 347 fsl,voltage = <1>;
186 fsl,pull-up = <1>; 348 fsl,pull-up = <1>;
@@ -188,28 +350,61 @@
188 350
189 mmc0_8bit_pins_a: mmc0-8bit@0 { 351 mmc0_8bit_pins_a: mmc0-8bit@0 {
190 reg = <0>; 352 reg = <0>;
191 fsl,pinmux-ids = <0x2000 0x2010 0x2020 353 fsl,pinmux-ids = <
192 0x2030 0x2040 0x2050 0x2060 354 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
193 0x2070 0x2080 0x2090 0x20a0>; 355 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
356 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
357 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
358 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
359 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
360 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
361 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
362 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
363 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
364 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
365 >;
366 fsl,drive-strength = <1>;
367 fsl,voltage = <1>;
368 fsl,pull-up = <1>;
369 };
370
371 mmc0_4bit_pins_a: mmc0-4bit@0 {
372 reg = <0>;
373 fsl,pinmux-ids = <
374 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
375 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
376 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
377 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
378 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
379 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
380 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
381 >;
194 fsl,drive-strength = <1>; 382 fsl,drive-strength = <1>;
195 fsl,voltage = <1>; 383 fsl,voltage = <1>;
196 fsl,pull-up = <1>; 384 fsl,pull-up = <1>;
197 }; 385 };
198 386
199 mmc0_cd_cfg: mmc0-cd-cfg { 387 mmc0_cd_cfg: mmc0-cd-cfg {
200 fsl,pinmux-ids = <0x2090>; 388 fsl,pinmux-ids = <
389 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
390 >;
201 fsl,pull-up = <0>; 391 fsl,pull-up = <0>;
202 }; 392 };
203 393
204 mmc0_sck_cfg: mmc0-sck-cfg { 394 mmc0_sck_cfg: mmc0-sck-cfg {
205 fsl,pinmux-ids = <0x20a0>; 395 fsl,pinmux-ids = <
396 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
397 >;
206 fsl,drive-strength = <2>; 398 fsl,drive-strength = <2>;
207 fsl,pull-up = <0>; 399 fsl,pull-up = <0>;
208 }; 400 };
209 401
210 i2c0_pins_a: i2c0@0 { 402 i2c0_pins_a: i2c0@0 {
211 reg = <0>; 403 reg = <0>;
212 fsl,pinmux-ids = <0x3180 0x3190>; 404 fsl,pinmux-ids = <
405 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
406 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
407 >;
213 fsl,drive-strength = <1>; 408 fsl,drive-strength = <1>;
214 fsl,voltage = <1>; 409 fsl,voltage = <1>;
215 fsl,pull-up = <1>; 410 fsl,pull-up = <1>;
@@ -217,8 +412,12 @@
217 412
218 saif0_pins_a: saif0@0 { 413 saif0_pins_a: saif0@0 {
219 reg = <0>; 414 reg = <0>;
220 fsl,pinmux-ids = 415 fsl,pinmux-ids = <
221 <0x3140 0x3150 0x3160 0x3170>; 416 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
417 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
418 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
419 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
420 >;
222 fsl,drive-strength = <2>; 421 fsl,drive-strength = <2>;
223 fsl,voltage = <1>; 422 fsl,voltage = <1>;
224 fsl,pull-up = <1>; 423 fsl,pull-up = <1>;
@@ -226,11 +425,88 @@
226 425
227 saif1_pins_a: saif1@0 { 426 saif1_pins_a: saif1@0 {
228 reg = <0>; 427 reg = <0>;
229 fsl,pinmux-ids = <0x31a0>; 428 fsl,pinmux-ids = <
429 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
430 >;
230 fsl,drive-strength = <2>; 431 fsl,drive-strength = <2>;
231 fsl,voltage = <1>; 432 fsl,voltage = <1>;
232 fsl,pull-up = <1>; 433 fsl,pull-up = <1>;
233 }; 434 };
435
436 pwm0_pins_a: pwm0@0 {
437 reg = <0>;
438 fsl,pinmux-ids = <
439 0x3100 /* MX28_PAD_PWM0__PWM_0 */
440 >;
441 fsl,drive-strength = <0>;
442 fsl,voltage = <1>;
443 fsl,pull-up = <0>;
444 };
445
446 pwm2_pins_a: pwm2@0 {
447 reg = <0>;
448 fsl,pinmux-ids = <
449 0x3120 /* MX28_PAD_PWM2__PWM_2 */
450 >;
451 fsl,drive-strength = <0>;
452 fsl,voltage = <1>;
453 fsl,pull-up = <0>;
454 };
455
456 lcdif_24bit_pins_a: lcdif-24bit@0 {
457 reg = <0>;
458 fsl,pinmux-ids = <
459 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
460 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
461 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
462 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
463 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
464 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
465 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
466 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
467 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
468 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
469 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
470 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
471 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
472 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
473 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
474 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
475 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
476 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
477 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
478 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
479 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
480 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
481 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
482 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
483 >;
484 fsl,drive-strength = <0>;
485 fsl,voltage = <1>;
486 fsl,pull-up = <0>;
487 };
488
489 can0_pins_a: can0@0 {
490 reg = <0>;
491 fsl,pinmux-ids = <
492 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
493 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
494 >;
495 fsl,drive-strength = <0>;
496 fsl,voltage = <1>;
497 fsl,pull-up = <0>;
498 };
499
500 can1_pins_a: can1@0 {
501 reg = <0>;
502 fsl,pinmux-ids = <
503 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
504 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
505 >;
506 fsl,drive-strength = <0>;
507 fsl,voltage = <1>;
508 fsl,pull-up = <0>;
509 };
234 }; 510 };
235 511
236 digctl@8001c000 { 512 digctl@8001c000 {
@@ -272,18 +548,21 @@
272 }; 548 };
273 549
274 lcdif@80030000 { 550 lcdif@80030000 {
551 compatible = "fsl,imx28-lcdif";
275 reg = <0x80030000 2000>; 552 reg = <0x80030000 2000>;
276 interrupts = <38 86>; 553 interrupts = <38 86>;
277 status = "disabled"; 554 status = "disabled";
278 }; 555 };
279 556
280 can0: can@80032000 { 557 can0: can@80032000 {
558 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
281 reg = <0x80032000 2000>; 559 reg = <0x80032000 2000>;
282 interrupts = <8>; 560 interrupts = <8>;
283 status = "disabled"; 561 status = "disabled";
284 }; 562 };
285 563
286 can1: can@80034000 { 564 can1: can@80034000 {
565 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
287 reg = <0x80034000 2000>; 566 reg = <0x80034000 2000>;
288 interrupts = <9>; 567 interrupts = <9>;
289 status = "disabled"; 568 status = "disabled";
@@ -370,9 +649,9 @@
370 }; 649 };
371 650
372 rtc@80056000 { 651 rtc@80056000 {
652 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
373 reg = <0x80056000 2000>; 653 reg = <0x80056000 2000>;
374 interrupts = <28 29>; 654 interrupts = <29>;
375 status = "disabled";
376 }; 655 };
377 656
378 i2c0: i2c@80058000 { 657 i2c0: i2c@80058000 {
@@ -393,8 +672,11 @@
393 status = "disabled"; 672 status = "disabled";
394 }; 673 };
395 674
396 pwm@80064000 { 675 pwm: pwm@80064000 {
676 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
397 reg = <0x80064000 2000>; 677 reg = <0x80064000 2000>;
678 #pwm-cells = <2>;
679 fsl,pwm-number = <8>;
398 status = "disabled"; 680 status = "disabled";
399 }; 681 };
400 682
@@ -404,30 +686,35 @@
404 }; 686 };
405 687
406 auart0: serial@8006a000 { 688 auart0: serial@8006a000 {
689 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
407 reg = <0x8006a000 0x2000>; 690 reg = <0x8006a000 0x2000>;
408 interrupts = <112 70 71>; 691 interrupts = <112 70 71>;
409 status = "disabled"; 692 status = "disabled";
410 }; 693 };
411 694
412 auart1: serial@8006c000 { 695 auart1: serial@8006c000 {
696 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
413 reg = <0x8006c000 0x2000>; 697 reg = <0x8006c000 0x2000>;
414 interrupts = <113 72 73>; 698 interrupts = <113 72 73>;
415 status = "disabled"; 699 status = "disabled";
416 }; 700 };
417 701
418 auart2: serial@8006e000 { 702 auart2: serial@8006e000 {
703 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
419 reg = <0x8006e000 0x2000>; 704 reg = <0x8006e000 0x2000>;
420 interrupts = <114 74 75>; 705 interrupts = <114 74 75>;
421 status = "disabled"; 706 status = "disabled";
422 }; 707 };
423 708
424 auart3: serial@80070000 { 709 auart3: serial@80070000 {
710 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
425 reg = <0x80070000 0x2000>; 711 reg = <0x80070000 0x2000>;
426 interrupts = <115 76 77>; 712 interrupts = <115 76 77>;
427 status = "disabled"; 713 status = "disabled";
428 }; 714 };
429 715
430 auart4: serial@80072000 { 716 auart4: serial@80072000 {
717 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
431 reg = <0x80072000 0x2000>; 718 reg = <0x80072000 0x2000>;
432 interrupts = <116 78 79>; 719 interrupts = <116 78 79>;
433 status = "disabled"; 720 status = "disabled";
@@ -441,11 +728,13 @@
441 }; 728 };
442 729
443 usbphy0: usbphy@8007c000 { 730 usbphy0: usbphy@8007c000 {
731 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
444 reg = <0x8007c000 0x2000>; 732 reg = <0x8007c000 0x2000>;
445 status = "disabled"; 733 status = "disabled";
446 }; 734 };
447 735
448 usbphy1: usbphy@8007e000 { 736 usbphy1: usbphy@8007e000 {
737 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
449 reg = <0x8007e000 0x2000>; 738 reg = <0x8007e000 0x2000>;
450 status = "disabled"; 739 status = "disabled";
451 }; 740 };
@@ -459,13 +748,19 @@
459 reg = <0x80080000 0x80000>; 748 reg = <0x80080000 0x80000>;
460 ranges; 749 ranges;
461 750
462 usbctrl0: usbctrl@80080000 { 751 usb0: usb@80080000 {
752 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
463 reg = <0x80080000 0x10000>; 753 reg = <0x80080000 0x10000>;
754 interrupts = <93>;
755 fsl,usbphy = <&usbphy0>;
464 status = "disabled"; 756 status = "disabled";
465 }; 757 };
466 758
467 usbctrl1: usbctrl@80090000 { 759 usb1: usb@80090000 {
760 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
468 reg = <0x80090000 0x10000>; 761 reg = <0x80090000 0x10000>;
762 interrupts = <92>;
763 fsl,usbphy = <&usbphy1>;
469 status = "disabled"; 764 status = "disabled";
470 }; 765 };
471 766
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
new file mode 100644
index 000000000000..24731cb78e8e
--- /dev/null
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -0,0 +1,31 @@
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx31.dtsi"
14
15/ {
16 model = "Buglabs i.MX31 Bug 1.x";
17 compatible = "fsl,imx31-bug", "fsl,imx31";
18
19 memory {
20 reg = <0x80000000 0x8000000>; /* 128M */
21 };
22
23 soc {
24 aips@43f00000 { /* AIPS1 */
25 uart5: serial@43fb4000 {
26 fsl,uart-has-rtscts;
27 status = "okay";
28 };
29 };
30 };
31};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
new file mode 100644
index 000000000000..eef7099f3e3c
--- /dev/null
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -0,0 +1,88 @@
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 };
22
23 avic: avic-interrupt-controller@60000000 {
24 compatible = "fsl,imx31-avic", "fsl,avic";
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 reg = <0x60000000 0x100000>;
28 };
29
30 soc {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 interrupt-parent = <&avic>;
35 ranges;
36
37 aips@43f00000 { /* AIPS1 */
38 compatible = "fsl,aips-bus", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0x43f00000 0x100000>;
42 ranges;
43
44 uart1: serial@43f90000 {
45 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
46 reg = <0x43f90000 0x4000>;
47 interrupts = <45>;
48 status = "disabled";
49 };
50
51 uart2: serial@43f94000 {
52 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
53 reg = <0x43f94000 0x4000>;
54 interrupts = <32>;
55 status = "disabled";
56 };
57
58 uart4: serial@43fb0000 {
59 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
60 reg = <0x43fb0000 0x4000>;
61 interrupts = <46>;
62 status = "disabled";
63 };
64
65 uart5: serial@43fb4000 {
66 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
67 reg = <0x43fb4000 0x4000>;
68 interrupts = <47>;
69 status = "disabled";
70 };
71 };
72
73 spba@50000000 {
74 compatible = "fsl,spba-bus", "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 reg = <0x50000000 0x100000>;
78 ranges;
79
80 uart3: serial@5000c000 {
81 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
82 reg = <0x5000c000 0x4000>;
83 interrupts = <18>;
84 status = "disabled";
85 };
86 };
87 };
88};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bfa65abe8ef2..922adefdd291 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -133,7 +133,7 @@
133 gpio-controller; 133 gpio-controller;
134 #gpio-cells = <2>; 134 #gpio-cells = <2>;
135 interrupt-controller; 135 interrupt-controller;
136 #interrupt-cells = <1>; 136 #interrupt-cells = <2>;
137 }; 137 };
138 138
139 gpio2: gpio@73f88000 { 139 gpio2: gpio@73f88000 {
@@ -143,7 +143,7 @@
143 gpio-controller; 143 gpio-controller;
144 #gpio-cells = <2>; 144 #gpio-cells = <2>;
145 interrupt-controller; 145 interrupt-controller;
146 #interrupt-cells = <1>; 146 #interrupt-cells = <2>;
147 }; 147 };
148 148
149 gpio3: gpio@73f8c000 { 149 gpio3: gpio@73f8c000 {
@@ -153,7 +153,7 @@
153 gpio-controller; 153 gpio-controller;
154 #gpio-cells = <2>; 154 #gpio-cells = <2>;
155 interrupt-controller; 155 interrupt-controller;
156 #interrupt-cells = <1>; 156 #interrupt-cells = <2>;
157 }; 157 };
158 158
159 gpio4: gpio@73f90000 { 159 gpio4: gpio@73f90000 {
@@ -163,7 +163,7 @@
163 gpio-controller; 163 gpio-controller;
164 #gpio-cells = <2>; 164 #gpio-cells = <2>;
165 interrupt-controller; 165 interrupt-controller;
166 #interrupt-cells = <1>; 166 #interrupt-cells = <2>;
167 }; 167 };
168 168
169 wdog@73f98000 { /* WDOG1 */ 169 wdog@73f98000 { /* WDOG1 */
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e869470cd3..4e735edc78ed 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,7 +135,7 @@
135 gpio-controller; 135 gpio-controller;
136 #gpio-cells = <2>; 136 #gpio-cells = <2>;
137 interrupt-controller; 137 interrupt-controller;
138 #interrupt-cells = <1>; 138 #interrupt-cells = <2>;
139 }; 139 };
140 140
141 gpio2: gpio@53f88000 { 141 gpio2: gpio@53f88000 {
@@ -145,7 +145,7 @@
145 gpio-controller; 145 gpio-controller;
146 #gpio-cells = <2>; 146 #gpio-cells = <2>;
147 interrupt-controller; 147 interrupt-controller;
148 #interrupt-cells = <1>; 148 #interrupt-cells = <2>;
149 }; 149 };
150 150
151 gpio3: gpio@53f8c000 { 151 gpio3: gpio@53f8c000 {
@@ -155,7 +155,7 @@
155 gpio-controller; 155 gpio-controller;
156 #gpio-cells = <2>; 156 #gpio-cells = <2>;
157 interrupt-controller; 157 interrupt-controller;
158 #interrupt-cells = <1>; 158 #interrupt-cells = <2>;
159 }; 159 };
160 160
161 gpio4: gpio@53f90000 { 161 gpio4: gpio@53f90000 {
@@ -165,7 +165,7 @@
165 gpio-controller; 165 gpio-controller;
166 #gpio-cells = <2>; 166 #gpio-cells = <2>;
167 interrupt-controller; 167 interrupt-controller;
168 #interrupt-cells = <1>; 168 #interrupt-cells = <2>;
169 }; 169 };
170 170
171 wdog@53f98000 { /* WDOG1 */ 171 wdog@53f98000 { /* WDOG1 */
@@ -203,7 +203,7 @@
203 gpio-controller; 203 gpio-controller;
204 #gpio-cells = <2>; 204 #gpio-cells = <2>;
205 interrupt-controller; 205 interrupt-controller;
206 #interrupt-cells = <1>; 206 #interrupt-cells = <2>;
207 }; 207 };
208 208
209 gpio6: gpio@53fe0000 { 209 gpio6: gpio@53fe0000 {
@@ -213,7 +213,7 @@
213 gpio-controller; 213 gpio-controller;
214 #gpio-cells = <2>; 214 #gpio-cells = <2>;
215 interrupt-controller; 215 interrupt-controller;
216 #interrupt-cells = <1>; 216 #interrupt-cells = <2>;
217 }; 217 };
218 218
219 gpio7: gpio@53fe4000 { 219 gpio7: gpio@53fe4000 {
@@ -223,7 +223,7 @@
223 gpio-controller; 223 gpio-controller;
224 #gpio-cells = <2>; 224 #gpio-cells = <2>;
225 interrupt-controller; 225 interrupt-controller;
226 #interrupt-cells = <1>; 226 #interrupt-cells = <2>;
227 }; 227 };
228 228
229 i2c@53fec000 { /* I2C3 */ 229 i2c@53fec000 { /* I2C3 */
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index db4c6096c562..d792581672cc 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -22,6 +22,12 @@
22 }; 22 };
23 23
24 soc { 24 soc {
25 gpmi-nand@00112000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
28 status = "disabled"; /* gpmi nand conflicts with SD */
29 };
30
25 aips-bus@02100000 { /* AIPS2 */ 31 aips-bus@02100000 { /* AIPS2 */
26 ethernet@02188000 { 32 ethernet@02188000 {
27 phy-mode = "rgmii"; 33 phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index e0ec92973e7e..d42e851ceb97 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -27,6 +27,8 @@
27 ecspi@02008000 { /* eCSPI1 */ 27 ecspi@02008000 { /* eCSPI1 */
28 fsl,spi-num-chipselects = <1>; 28 fsl,spi-num-chipselects = <1>;
29 cs-gpios = <&gpio3 19 0>; 29 cs-gpios = <&gpio3 19 0>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_ecspi1_1>;
30 status = "okay"; 32 status = "okay";
31 33
32 flash: m25p80@0 { 34 flash: m25p80@0 {
@@ -42,9 +44,31 @@
42 }; 44 };
43 }; 45 };
44 46
47 iomuxc@020e0000 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpio_hog>;
50
51 gpios {
52 pinctrl_gpio_hog: gpiohog {
53 fsl,pins = <
54 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
55 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
56 >;
57 };
58 };
59 };
45 }; 60 };
46 61
47 aips-bus@02100000 { /* AIPS2 */ 62 aips-bus@02100000 { /* AIPS2 */
63 usb@02184000 { /* USB OTG */
64 vbus-supply = <&reg_usb_otg_vbus>;
65 status = "okay";
66 };
67
68 usb@02184200 { /* USB1 */
69 status = "okay";
70 };
71
48 ethernet@02188000 { 72 ethernet@02188000 {
49 phy-mode = "rgmii"; 73 phy-mode = "rgmii";
50 phy-reset-gpios = <&gpio3 23 0>; 74 phy-reset-gpios = <&gpio3 23 0>;
@@ -111,6 +135,15 @@
111 regulator-max-microvolt = <3300000>; 135 regulator-max-microvolt = <3300000>;
112 regulator-always-on; 136 regulator-always-on;
113 }; 137 };
138
139 reg_usb_otg_vbus: usb_otg_vbus {
140 compatible = "regulator-fixed";
141 regulator-name = "usb_otg_vbus";
142 regulator-min-microvolt = <5000000>;
143 regulator-max-microvolt = <5000000>;
144 gpio = <&gpio3 22 0>;
145 enable-active-high;
146 };
114 }; 147 };
115 148
116 sound { 149 sound {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8c90cbac945f..c25d49584814 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -87,6 +87,23 @@
87 interrupt-parent = <&intc>; 87 interrupt-parent = <&intc>;
88 ranges; 88 ranges;
89 89
90 dma-apbh@00110000 {
91 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
92 reg = <0x00110000 0x2000>;
93 };
94
95 gpmi-nand@00112000 {
96 compatible = "fsl,imx6q-gpmi-nand";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
100 reg-names = "gpmi-nand", "bch";
101 interrupts = <0 13 0x04>, <0 15 0x04>;
102 interrupt-names = "gpmi-dma", "bch";
103 fsl,gpmi-dma-channel = <0>;
104 status = "disabled";
105 };
106
90 timer@00a00600 { 107 timer@00a00600 {
91 compatible = "arm,cortex-a9-twd-timer"; 108 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x20>; 109 reg = <0x00a00600 0x20>;
@@ -266,7 +283,7 @@
266 gpio-controller; 283 gpio-controller;
267 #gpio-cells = <2>; 284 #gpio-cells = <2>;
268 interrupt-controller; 285 interrupt-controller;
269 #interrupt-cells = <1>; 286 #interrupt-cells = <2>;
270 }; 287 };
271 288
272 gpio2: gpio@020a0000 { 289 gpio2: gpio@020a0000 {
@@ -276,7 +293,7 @@
276 gpio-controller; 293 gpio-controller;
277 #gpio-cells = <2>; 294 #gpio-cells = <2>;
278 interrupt-controller; 295 interrupt-controller;
279 #interrupt-cells = <1>; 296 #interrupt-cells = <2>;
280 }; 297 };
281 298
282 gpio3: gpio@020a4000 { 299 gpio3: gpio@020a4000 {
@@ -286,7 +303,7 @@
286 gpio-controller; 303 gpio-controller;
287 #gpio-cells = <2>; 304 #gpio-cells = <2>;
288 interrupt-controller; 305 interrupt-controller;
289 #interrupt-cells = <1>; 306 #interrupt-cells = <2>;
290 }; 307 };
291 308
292 gpio4: gpio@020a8000 { 309 gpio4: gpio@020a8000 {
@@ -296,7 +313,7 @@
296 gpio-controller; 313 gpio-controller;
297 #gpio-cells = <2>; 314 #gpio-cells = <2>;
298 interrupt-controller; 315 interrupt-controller;
299 #interrupt-cells = <1>; 316 #interrupt-cells = <2>;
300 }; 317 };
301 318
302 gpio5: gpio@020ac000 { 319 gpio5: gpio@020ac000 {
@@ -306,7 +323,7 @@
306 gpio-controller; 323 gpio-controller;
307 #gpio-cells = <2>; 324 #gpio-cells = <2>;
308 interrupt-controller; 325 interrupt-controller;
309 #interrupt-cells = <1>; 326 #interrupt-cells = <2>;
310 }; 327 };
311 328
312 gpio6: gpio@020b0000 { 329 gpio6: gpio@020b0000 {
@@ -316,7 +333,7 @@
316 gpio-controller; 333 gpio-controller;
317 #gpio-cells = <2>; 334 #gpio-cells = <2>;
318 interrupt-controller; 335 interrupt-controller;
319 #interrupt-cells = <1>; 336 #interrupt-cells = <2>;
320 }; 337 };
321 338
322 gpio7: gpio@020b4000 { 339 gpio7: gpio@020b4000 {
@@ -326,7 +343,7 @@
326 gpio-controller; 343 gpio-controller;
327 #gpio-cells = <2>; 344 #gpio-cells = <2>;
328 interrupt-controller; 345 interrupt-controller;
329 #interrupt-cells = <1>; 346 #interrupt-cells = <2>;
330 }; 347 };
331 348
332 kpp@020b8000 { 349 kpp@020b8000 {
@@ -444,12 +461,14 @@
444 }; 461 };
445 }; 462 };
446 463
447 usbphy@020c9000 { /* USBPHY1 */ 464 usbphy1: usbphy@020c9000 {
465 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
448 reg = <0x020c9000 0x1000>; 466 reg = <0x020c9000 0x1000>;
449 interrupts = <0 44 0x04>; 467 interrupts = <0 44 0x04>;
450 }; 468 };
451 469
452 usbphy@020ca000 { /* USBPHY2 */ 470 usbphy2: usbphy@020ca000 {
471 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
453 reg = <0x020ca000 0x1000>; 472 reg = <0x020ca000 0x1000>;
454 interrupts = <0 45 0x04>; 473 interrupts = <0 45 0x04>;
455 }; 474 };
@@ -495,6 +514,30 @@
495 }; 514 };
496 }; 515 };
497 516
517 gpmi-nand {
518 pinctrl_gpmi_nand_1: gpmi-nand-1 {
519 fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
520 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
521 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
522 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
523 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
524 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
525 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
526 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
527 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
528 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
529 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
530 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
531 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
532 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
533 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
534 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
535 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
536 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
537 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
538 };
539 };
540
498 i2c1 { 541 i2c1 {
499 pinctrl_i2c1_1: i2c1grp-1 { 542 pinctrl_i2c1_1: i2c1grp-1 {
500 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ 543 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
@@ -538,6 +581,14 @@
538 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ 581 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
539 }; 582 };
540 }; 583 };
584
585 ecspi1 {
586 pinctrl_ecspi1_1: ecspi1grp-1 {
587 fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
588 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
589 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
590 };
591 };
541 }; 592 };
542 593
543 dcic@020e4000 { /* DCIC1 */ 594 dcic@020e4000 { /* DCIC1 */
@@ -573,6 +624,36 @@
573 reg = <0x0217c000 0x4000>; 624 reg = <0x0217c000 0x4000>;
574 }; 625 };
575 626
627 usb@02184000 { /* USB OTG */
628 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
629 reg = <0x02184000 0x200>;
630 interrupts = <0 43 0x04>;
631 fsl,usbphy = <&usbphy1>;
632 status = "disabled";
633 };
634
635 usb@02184200 { /* USB1 */
636 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
637 reg = <0x02184200 0x200>;
638 interrupts = <0 40 0x04>;
639 fsl,usbphy = <&usbphy2>;
640 status = "disabled";
641 };
642
643 usb@02184400 { /* USB2 */
644 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
645 reg = <0x02184400 0x200>;
646 interrupts = <0 41 0x04>;
647 status = "disabled";
648 };
649
650 usb@02184600 { /* USB3 */
651 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
652 reg = <0x02184600 0x200>;
653 interrupts = <0 42 0x04>;
654 status = "disabled";
655 };
656
576 ethernet@02188000 { 657 ethernet@02188000 {
577 compatible = "fsl,imx6q-fec"; 658 compatible = "fsl,imx6q-fec";
578 reg = <0x02188000 0x4000>; 659 reg = <0x02188000 0x4000>;
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index c5f37fbd33e6..e5ffe960dbf3 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -278,6 +278,11 @@
278 status = "disabled"; 278 status = "disabled";
279 }; 279 };
280 280
281 pwm: pwm@4005C000 {
282 compatible = "nxp,lpc3220-pwm";
283 reg = <0x4005C000 0x8>;
284 status = "disabled";
285 };
281 }; 286 };
282 }; 287 };
283}; 288};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
new file mode 100644
index 000000000000..25b50b759dec
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap2.dtsi"
11
12/ {
13 model = "TI OMAP2420 H4 board";
14 compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x84000000>; /* 64 MB */
19 };
20};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 2eee16ec59b4..f349ee9182ce 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -18,3 +18,31 @@
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 19 };
20}; 20};
21
22&i2c1 {
23 clock-frequency = <2600000>;
24
25 twl: twl@48 {
26 reg = <0x48>;
27 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
28 interrupt-parent = <&intc>;
29 };
30};
31
32/include/ "twl4030.dtsi"
33
34&i2c2 {
35 clock-frequency = <400000>;
36};
37
38&i2c3 {
39 clock-frequency = <400000>;
40
41 /*
42 * TVP5146 Video decoder-in for analog input support.
43 */
44 tvp5146@5c {
45 compatible = "ti,tvp5146m2";
46 reg = <0x5c>;
47 };
48};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99474fa5fac4..810947198208 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -215,5 +215,10 @@
215 compatible = "ti,omap3-hsmmc"; 215 compatible = "ti,omap3-hsmmc";
216 ti,hwmods = "mmc3"; 216 ti,hwmods = "mmc3";
217 }; 217 };
218
219 wdt2: wdt@48314000 {
220 compatible = "ti,omap3-wdt";
221 ti,hwmods = "wd_timer2";
222 };
218 }; 223 };
219}; 224};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9d8abf0938e0..9880c12877b3 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -32,6 +32,30 @@
32 linux,default-trigger = "mmc0"; 32 linux,default-trigger = "mmc0";
33 }; 33 };
34 }; 34 };
35
36 sound: sound {
37 compatible = "ti,abe-twl6040";
38 ti,model = "PandaBoard";
39
40 ti,mclk-freq = <38400000>;
41
42 ti,mcpdm = <&mcpdm>;
43
44 ti,twl6040 = <&twl6040>;
45
46 /* Audio routing */
47 ti,audio-routing =
48 "Headset Stereophone", "HSOL",
49 "Headset Stereophone", "HSOR",
50 "Ext Spk", "HFL",
51 "Ext Spk", "HFR",
52 "Line Out", "AUXL",
53 "Line Out", "AUXR",
54 "HSMIC", "Headset Mic",
55 "Headset Mic", "Headset Mic Bias",
56 "AFML", "Line In",
57 "AFMR", "Line In";
58 };
35}; 59};
36 60
37&i2c1 { 61&i2c1 {
@@ -43,6 +67,19 @@
43 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ 67 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
44 interrupt-parent = <&gic>; 68 interrupt-parent = <&gic>;
45 }; 69 };
70
71 twl6040: twl@4b {
72 compatible = "ti,twl6040";
73 reg = <0x4b>;
74 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
75 interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
76 interrupt-parent = <&gic>;
77 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
78
79 vio-supply = <&v1v8>;
80 v2v1-supply = <&v2v1>;
81 enable-active-high;
82 };
46}; 83};
47 84
48/include/ "twl6030.dtsi" 85/include/ "twl6030.dtsi"
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-pandaES.dts
new file mode 100644
index 000000000000..d4ba43a48d9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-pandaES.dts
@@ -0,0 +1,24 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-panda.dts"
9
10/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
11&sound {
12 ti,model = "PandaBoardES";
13
14 /* Audio routing */
15 ti,audio-routing =
16 "Headset Stereophone", "HSOL",
17 "Headset Stereophone", "HSOR",
18 "Ext Spk", "HFL",
19 "Ext Spk", "HFR",
20 "Line Out", "AUXL",
21 "Line Out", "AUXR",
22 "AFML", "Line In",
23 "AFMR", "Line In";
24};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 9b1c13a16c2c..72216e932fc0 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -28,6 +28,14 @@
28 regulator-boot-on; 28 regulator-boot-on;
29 }; 29 };
30 30
31 vbat: fixedregulator@2 {
32 compatible = "regulator-fixed";
33 regulator-name = "VBAT";
34 regulator-min-microvolt = <3750000>;
35 regulator-max-microvolt = <3750000>;
36 regulator-boot-on;
37 };
38
31 leds { 39 leds {
32 compatible = "gpio-leds"; 40 compatible = "gpio-leds";
33 debug0 { 41 debug0 {
@@ -70,6 +78,41 @@
70 gpios = <&gpio5 11 0>; /* 139 */ 78 gpios = <&gpio5 11 0>; /* 139 */
71 }; 79 };
72 }; 80 };
81
82 sound {
83 compatible = "ti,abe-twl6040";
84 ti,model = "SDP4430";
85
86 ti,jack-detection = <1>;
87 ti,mclk-freq = <38400000>;
88
89 ti,mcpdm = <&mcpdm>;
90 ti,dmic = <&dmic>;
91
92 ti,twl6040 = <&twl6040>;
93
94 /* Audio routing */
95 ti,audio-routing =
96 "Headset Stereophone", "HSOL",
97 "Headset Stereophone", "HSOR",
98 "Earphone Spk", "EP",
99 "Ext Spk", "HFL",
100 "Ext Spk", "HFR",
101 "Line Out", "AUXL",
102 "Line Out", "AUXR",
103 "Vibrator", "VIBRAL",
104 "Vibrator", "VIBRAR",
105 "HSMIC", "Headset Mic",
106 "Headset Mic", "Headset Mic Bias",
107 "MAINMIC", "Main Handset Mic",
108 "Main Handset Mic", "Main Mic Bias",
109 "SUBMIC", "Sub Handset Mic",
110 "Sub Handset Mic", "Main Mic Bias",
111 "AFML", "Line In",
112 "AFMR", "Line In",
113 "DMic", "Digital Mic",
114 "Digital Mic", "Digital Mic1 Bias";
115 };
73}; 116};
74 117
75&i2c1 { 118&i2c1 {
@@ -81,6 +124,31 @@
81 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ 124 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
82 interrupt-parent = <&gic>; 125 interrupt-parent = <&gic>;
83 }; 126 };
127
128 twl6040: twl@4b {
129 compatible = "ti,twl6040";
130 reg = <0x4b>;
131 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
132 interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
133 interrupt-parent = <&gic>;
134 ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
135
136 vio-supply = <&v1v8>;
137 v2v1-supply = <&v2v1>;
138 enable-active-high;
139
140 /* regulators for vibra motor */
141 vddvibl-supply = <&vbat>;
142 vddvibr-supply = <&vbat>;
143
144 vibra {
145 /* Vibra driver, motor resistance parameters */
146 ti,vibldrv-res = <8>;
147 ti,vibrdrv-res = <3>;
148 ti,viblmotor-res = <10>;
149 ti,vibrmotor-res = <10>;
150 };
151 };
84}; 152};
85 153
86/include/ "twl6030.dtsi" 154/include/ "twl6030.dtsi"
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts
new file mode 100644
index 000000000000..6601e6af6092
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var_som.dts
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap4.dtsi"
11
12/ {
13 model = "Variscite OMAP4 SOM";
14 compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 };
20
21 vdd_eth: fixedregulator@0 {
22 compatible = "regulator-fixed";
23 regulator-name = "VDD_ETH";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 enable-active-high;
27 regulator-boot-on;
28 };
29};
30
31&i2c1 {
32 clock-frequency = <400000>;
33
34 twl: twl@48 {
35 reg = <0x48>;
36 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
37 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
38 interrupt-parent = <&gic>;
39 };
40};
41
42/include/ "twl6030.dtsi"
43
44&i2c2 {
45 clock-frequency = <400000>;
46};
47
48&i2c3 {
49 clock-frequency = <400000>;
50
51 /*
52 * Temperature Sensor
53 * http://www.ti.com/lit/ds/symlink/tmp105.pdf
54 */
55 tmp105@49 {
56 compatible = "ti,tmp105";
57 reg = <0x49>;
58 };
59};
60
61&i2c4 {
62 clock-frequency = <400000>;
63};
64
65&mcspi1 {
66 eth@0 {
67 compatible = "ks8851";
68 spi-max-frequency = <24000000>;
69 reg = <0>;
70 interrupt-parent = <&gpio6>;
71 interrupts = <11>; /* gpio line 171 */
72 vdd-supply = <&vdd_eth>;
73 };
74};
75
76&mmc1 {
77 vmmc-supply = <&vmmc>;
78 ti,bus-width = <8>;
79 ti,non-removable;
80};
81
82&mmc2 {
83 status = "disabled";
84};
85
86&mmc3 {
87 status = "disabled";
88};
89
90&mmc4 {
91 status = "disabled";
92};
93
94&mmc5 {
95 ti,bus-width = <4>;
96};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 359c4979c8aa..04cbbcb6ff91 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -272,5 +272,28 @@
272 ti,hwmods = "mmc5"; 272 ti,hwmods = "mmc5";
273 ti,needs-special-reset; 273 ti,needs-special-reset;
274 }; 274 };
275
276 wdt2: wdt@4a314000 {
277 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
278 ti,hwmods = "wd_timer2";
279 };
280
281 mcpdm: mcpdm@40132000 {
282 compatible = "ti,omap4-mcpdm";
283 reg = <0x40132000 0x7f>, /* MPU private access */
284 <0x49032000 0x7f>; /* L3 Interconnect */
285 interrupts = <0 112 0x4>;
286 interrupt-parent = <&gic>;
287 ti,hwmods = "mcpdm";
288 };
289
290 dmic: dmic@4012e000 {
291 compatible = "ti,omap4-dmic";
292 reg = <0x4012e000 0x7f>, /* MPU private access */
293 <0x4902e000 0x7f>; /* L3 Interconnect */
294 interrupts = <0 114 0x4>;
295 interrupt-parent = <&gic>;
296 ti,hwmods = "dmic";
297 };
275 }; 298 };
276}; 299};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index ec3c33975110..7e334d4cae21 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -77,6 +77,8 @@
77 used-led { 77 used-led {
78 label = "user_led"; 78 label = "user_led";
79 gpios = <&gpio4 14 0x4>; 79 gpios = <&gpio4 14 0x4>;
80 default-state = "on";
81 linux,default-trigger = "heartbeat";
80 }; 82 };
81 }; 83 };
82 84
@@ -101,15 +103,30 @@
101 }; 103 };
102 }; 104 };
103 105
106 // External Micro SD slot
104 sdi@80126000 { 107 sdi@80126000 {
105 status = "enabled"; 108 arm,primecell-periphid = <0x10480180>;
109 max-frequency = <50000000>;
110 bus-width = <8>;
111 mmc-cap-mmc-highspeed;
106 vmmc-supply = <&ab8500_ldo_aux3_reg>; 112 vmmc-supply = <&ab8500_ldo_aux3_reg>;
113
114 #gpio-cells = <1>;
107 cd-gpios = <&gpio6 26 0x4>; // 218 115 cd-gpios = <&gpio6 26 0x4>; // 218
116 cd-inverted;
117
118 status = "okay";
108 }; 119 };
109 120
121 // On-board eMMC
110 sdi@80114000 { 122 sdi@80114000 {
111 status = "enabled"; 123 arm,primecell-periphid = <0x10480180>;
124 max-frequency = <50000000>;
125 bus-width = <8>;
126 mmc-cap-mmc-highspeed;
112 vmmc-supply = <&ab8500_ldo_aux2_reg>; 127 vmmc-supply = <&ab8500_ldo_aux2_reg>;
128
129 status = "okay";
113 }; 130 };
114 131
115 uart@80120000 { 132 uart@80120000 {
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index b797901d040d..85e621ab2968 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -64,11 +64,6 @@
64 nvidia,pins = "dap4"; 64 nvidia,pins = "dap4";
65 nvidia,function = "dap4"; 65 nvidia,function = "dap4";
66 }; 66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta { 67 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 68 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi"; 69 nvidia,function = "vi";
@@ -129,14 +124,14 @@
129 "lspi", "lvp1", "lvs"; 124 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya"; 125 nvidia,function = "displaya";
131 }; 126 };
127 owc {
128 nvidia,pins = "owc", "spdi", "spdo", "uac";
129 nvidia,function = "rsvd2";
130 };
132 pmc { 131 pmc {
133 nvidia,pins = "pmc"; 132 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on"; 133 nvidia,function = "pwr_on";
135 }; 134 };
136 pta {
137 nvidia,pins = "pta";
138 nvidia,function = "i2c2";
139 };
140 rm { 135 rm {
141 nvidia,pins = "rm"; 136 nvidia,pins = "rm";
142 nvidia,function = "i2c1"; 137 nvidia,function = "i2c1";
@@ -176,7 +171,7 @@
176 conf_ata { 171 conf_ata {
177 nvidia,pins = "ata", "atb", "atc", "atd", 172 nvidia,pins = "ata", "atb", "atc", "atd",
178 "cdev1", "cdev2", "dap1", "dap2", 173 "cdev1", "cdev2", "dap1", "dap2",
179 "dap4", "dtf", "gma", "gmc", "gmd", 174 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
180 "gme", "gpu", "gpu7", "i2cp", "irrx", 175 "gme", "gpu", "gpu7", "i2cp", "irrx",
181 "irtx", "pta", "rm", "sdc", "sdd", 176 "irtx", "pta", "rm", "sdc", "sdd",
182 "slxd", "slxk", "spdi", "spdo", "uac", 177 "slxd", "slxk", "spdi", "spdo", "uac",
@@ -185,7 +180,7 @@
185 nvidia,tristate = <0>; 180 nvidia,tristate = <0>;
186 }; 181 };
187 conf_ate { 182 conf_ate {
188 nvidia,pins = "ate", "csus", "dap3", "ddc", 183 nvidia,pins = "ate", "csus", "dap3",
189 "gpv", "owc", "slxc", "spib", "spid", 184 "gpv", "owc", "slxc", "spib", "spid",
190 "spie"; 185 "spie";
191 nvidia,pull = <0>; 186 nvidia,pull = <0>;
@@ -255,6 +250,39 @@
255 nvidia,slew-rate-falling = <3>; 250 nvidia,slew-rate-falling = <3>;
256 }; 251 };
257 }; 252 };
253
254 state_i2cmux_ddc: pinmux_i2cmux_ddc {
255 ddc {
256 nvidia,pins = "ddc";
257 nvidia,function = "i2c2";
258 };
259 pta {
260 nvidia,pins = "pta";
261 nvidia,function = "rsvd4";
262 };
263 };
264
265 state_i2cmux_pta: pinmux_i2cmux_pta {
266 ddc {
267 nvidia,pins = "ddc";
268 nvidia,function = "rsvd4";
269 };
270 pta {
271 nvidia,pins = "pta";
272 nvidia,function = "i2c2";
273 };
274 };
275
276 state_i2cmux_idle: pinmux_i2cmux_idle {
277 ddc {
278 nvidia,pins = "ddc";
279 nvidia,function = "rsvd4";
280 };
281 pta {
282 nvidia,pins = "pta";
283 nvidia,function = "rsvd4";
284 };
285 };
258 }; 286 };
259 287
260 i2s@70002800 { 288 i2s@70002800 {
@@ -303,12 +331,37 @@
303 i2c@7000c400 { 331 i2c@7000c400 {
304 status = "okay"; 332 status = "okay";
305 clock-frequency = <100000>; 333 clock-frequency = <100000>;
334 };
335
336 i2cmux {
337 compatible = "i2c-mux-pinctrl";
338 #address-cells = <1>;
339 #size-cells = <0>;
340
341 i2c-parent = <&{/i2c@7000c400}>;
306 342
307 smart-battery@b { 343 pinctrl-names = "ddc", "pta", "idle";
308 compatible = "ti,bq20z75", "smart-battery-1.1"; 344 pinctrl-0 = <&state_i2cmux_ddc>;
309 reg = <0xb>; 345 pinctrl-1 = <&state_i2cmux_pta>;
310 ti,i2c-retry-count = <2>; 346 pinctrl-2 = <&state_i2cmux_idle>;
311 ti,poll-retry-count = <10>; 347
348 i2c@0 {
349 reg = <0>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 };
353
354 i2c@1 {
355 reg = <1>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358
359 smart-battery@b {
360 compatible = "ti,bq20z75", "smart-battery-1.1";
361 reg = <0xb>;
362 ti,i2c-retry-count = <2>;
363 ti,poll-retry-count = <10>;
364 };
312 }; 365 };
313 }; 366 };
314 367
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
new file mode 100644
index 000000000000..6916310bf58f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -0,0 +1,301 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Whistler evaluation board";
7 compatible = "nvidia,whistler", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
20 "gmc", "gmd", "gpu";
21 nvidia,function = "gmi";
22 };
23 atc {
24 nvidia,pins = "atc", "atd";
25 nvidia,function = "sdio4";
26 };
27 cdev1 {
28 nvidia,pins = "cdev1";
29 nvidia,function = "plla_out";
30 };
31 cdev2 {
32 nvidia,pins = "cdev2";
33 nvidia,function = "osc";
34 };
35 crtp {
36 nvidia,pins = "crtp";
37 nvidia,function = "crt";
38 };
39 csus {
40 nvidia,pins = "csus";
41 nvidia,function = "vi_sensor_clk";
42 };
43 dap1 {
44 nvidia,pins = "dap1";
45 nvidia,function = "dap1";
46 };
47 dap2 {
48 nvidia,pins = "dap2";
49 nvidia,function = "dap2";
50 };
51 dap3 {
52 nvidia,pins = "dap3";
53 nvidia,function = "dap3";
54 };
55 dap4 {
56 nvidia,pins = "dap4";
57 nvidia,function = "dap4";
58 };
59 ddc {
60 nvidia,pins = "ddc";
61 nvidia,function = "i2c2";
62 };
63 dta {
64 nvidia,pins = "dta", "dtb", "dtc", "dtd";
65 nvidia,function = "vi";
66 };
67 dte {
68 nvidia,pins = "dte";
69 nvidia,function = "rsvd1";
70 };
71 dtf {
72 nvidia,pins = "dtf";
73 nvidia,function = "i2c3";
74 };
75 gme {
76 nvidia,pins = "gme";
77 nvidia,function = "dap5";
78 };
79 gpu7 {
80 nvidia,pins = "gpu7";
81 nvidia,function = "rtck";
82 };
83 gpv {
84 nvidia,pins = "gpv";
85 nvidia,function = "pcie";
86 };
87 hdint {
88 nvidia,pins = "hdint", "pta";
89 nvidia,function = "hdmi";
90 };
91 i2cp {
92 nvidia,pins = "i2cp";
93 nvidia,function = "i2cp";
94 };
95 irrx {
96 nvidia,pins = "irrx", "irtx";
97 nvidia,function = "uartb";
98 };
99 kbca {
100 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
101 nvidia,function = "kbc";
102 };
103 kbcb {
104 nvidia,pins = "kbcb", "kbcd";
105 nvidia,function = "sdio2";
106 };
107 lcsn {
108 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
109 "spia", "spib", "spic";
110 nvidia,function = "spi3";
111 };
112 ld0 {
113 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
114 "ld5", "ld6", "ld7", "ld8", "ld9",
115 "ld10", "ld11", "ld12", "ld13", "ld14",
116 "ld15", "ld16", "ld17", "ldc", "ldi",
117 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
118 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
119 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "owr";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
137 "slxc", "slxd", "slxk";
138 nvidia,function = "sdio3";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 spdi {
145 nvidia,pins = "spdi", "spdo";
146 nvidia,function = "rsvd2";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spig", "spih";
150 nvidia,function = "spi2_alt";
151 };
152 spif {
153 nvidia,pins = "spif";
154 nvidia,function = "spi2";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab";
158 nvidia,function = "uarta";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 uda {
169 nvidia,pins = "uda";
170 nvidia,function = "spi1";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
174 "gmb", "gmc", "gmd", "irrx", "irtx",
175 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
176 "kbcf", "sdc", "sdd", "spie", "spig",
177 "spih", "uaa", "uab", "uad", "uca",
178 "ucb";
179 nvidia,pull = <2>;
180 nvidia,tristate = <0>;
181 };
182 conf_atd {
183 nvidia,pins = "atd", "ate", "cdev1", "csus",
184 "dap1", "dap2", "dap3", "dap4", "dte",
185 "dtf", "gpu", "gpu7", "gpv", "i2cp",
186 "rm", "sdio1", "slxa", "slxc", "slxd",
187 "slxk", "spdi", "spdo", "uac", "uda";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_cdev2 {
192 nvidia,pins = "cdev2", "spia", "spib";
193 nvidia,pull = <1>;
194 nvidia,tristate = <1>;
195 };
196 conf_ck32 {
197 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
198 "pmcb", "pmcc", "pmcd", "xm2c",
199 "xm2d";
200 nvidia,pull = <0>;
201 };
202 conf_crtp {
203 nvidia,pins = "crtp";
204 nvidia,pull = <0>;
205 nvidia,tristate = <1>;
206 };
207 conf_dta {
208 nvidia,pins = "dta", "dtb", "dtc", "dtd",
209 "spid", "spif";
210 nvidia,pull = <1>;
211 nvidia,tristate = <0>;
212 };
213 conf_gme {
214 nvidia,pins = "gme", "owc", "pta", "spic";
215 nvidia,pull = <2>;
216 nvidia,tristate = <1>;
217 };
218 conf_ld17_0 {
219 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
220 "ld23_22";
221 nvidia,pull = <1>;
222 };
223 conf_ls {
224 nvidia,pins = "ls", "pmce";
225 nvidia,pull = <2>;
226 };
227 drive_dap1 {
228 nvidia,pins = "drive_dap1";
229 nvidia,high-speed-mode = <0>;
230 nvidia,schmitt = <1>;
231 nvidia,low-power-mode = <0>;
232 nvidia,pull-down-strength = <0>;
233 nvidia,pull-up-strength = <0>;
234 nvidia,slew-rate-rising = <0>;
235 nvidia,slew-rate-falling = <0>;
236 };
237 };
238 };
239
240 i2s@70002800 {
241 status = "okay";
242 };
243
244 serial@70006000 {
245 status = "okay";
246 clock-frequency = <216000000>;
247 };
248
249 i2c@7000d000 {
250 status = "okay";
251 clock-frequency = <100000>;
252
253 codec: codec@1a {
254 compatible = "wlf,wm8753";
255 reg = <0x1a>;
256 };
257
258 tca6416: gpio@20 {
259 compatible = "ti,tca6416";
260 reg = <0x20>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 };
264 };
265
266 usb@c5000000 {
267 status = "okay";
268 nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
269 };
270
271 usb@c5008000 {
272 status = "okay";
273 nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
274 };
275
276 sdhci@c8000400 {
277 status = "okay";
278 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
279 bus-width = <8>;
280 };
281
282 sdhci@c8000600 {
283 status = "okay";
284 bus-width = <8>;
285 };
286
287 sound {
288 compatible = "nvidia,tegra-audio-wm8753-whistler",
289 "nvidia,tegra-audio-wm8753";
290 nvidia,model = "NVIDIA Tegra Whistler";
291
292 nvidia,audio-routing =
293 "Headphone Jack", "LOUT1",
294 "Headphone Jack", "ROUT1",
295 "MIC2", "Mic Jack",
296 "MIC2N", "Mic Jack";
297
298 nvidia,i2s-controller = <&tegra_i2s1>;
299 nvidia,audio-codec = <&codec>;
300 };
301};
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 9e84fe4f2aaa..30bb7332e30b 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -15,7 +15,9 @@ endif
15 15
16# Keep dtb files sorted alphabetically for each SoC 16# Keep dtb files sorted alphabetically for each SoC
17# sam9260 17# sam9260
18dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb
18dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb 19dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
20dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb
19dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb 21dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
20dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb 22dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
21# sam9263 23# sam9263
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 45d52567ced7..006dae8dfe44 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -14,6 +14,9 @@
14#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/irqdomain.h> 15#include <linux/irqdomain.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
17 20
18#include <mach/common.h> 21#include <mach/common.h>
19#include <mach/cp_intc.h> 22#include <mach/cp_intc.h>
@@ -119,7 +122,7 @@ static const struct irq_domain_ops cp_intc_host_ops = {
119 .xlate = irq_domain_xlate_onetwocell, 122 .xlate = irq_domain_xlate_onetwocell,
120}; 123};
121 124
122int __init __cp_intc_init(struct device_node *node) 125int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
123{ 126{
124 u32 num_irq = davinci_soc_info.intc_irq_num; 127 u32 num_irq = davinci_soc_info.intc_irq_num;
125 u8 *irq_prio = davinci_soc_info.intc_irq_prios; 128 u8 *irq_prio = davinci_soc_info.intc_irq_prios;
@@ -128,7 +131,14 @@ int __init __cp_intc_init(struct device_node *node)
128 int i, irq_base; 131 int i, irq_base;
129 132
130 davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; 133 davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
131 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); 134 if (node) {
135 davinci_intc_base = of_iomap(node, 0);
136 if (of_property_read_u32(node, "ti,intc-size", &num_irq))
137 pr_warn("unable to get intc-size, default to %d\n",
138 num_irq);
139 } else {
140 davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
141 }
132 if (WARN_ON(!davinci_intc_base)) 142 if (WARN_ON(!davinci_intc_base))
133 return -EINVAL; 143 return -EINVAL;
134 144
@@ -208,5 +218,5 @@ int __init __cp_intc_init(struct device_node *node)
208 218
209void __init cp_intc_init(void) 219void __init cp_intc_init(void)
210{ 220{
211 __cp_intc_init(NULL); 221 cp_intc_of_init(NULL, NULL);
212} 222}
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index 4e8190eed673..d13d8dfa2b0d 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,5 +52,6 @@
52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) 52#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
53 53
54void __init cp_intc_init(void); 54void __init cp_intc_init(void);
55int __init cp_intc_of_init(struct device_node *, struct device_node *);
55 56
56#endif /* __ASM_HARDWARE_CP_INTC_H */ 57#endif /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bcb7db453145..26fe9de35ecb 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
586 .ctrlbit = (1 << 13), 586 .ctrlbit = (1 << 13),
587 }, { 587 }, {
588 .name = "spi", 588 .name = "spi",
589 .devname = "s3c64xx-spi.0", 589 .devname = "exynos4210-spi.0",
590 .enable = exynos4_clk_ip_peril_ctrl, 590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 16), 591 .ctrlbit = (1 << 16),
592 }, { 592 }, {
593 .name = "spi", 593 .name = "spi",
594 .devname = "s3c64xx-spi.1", 594 .devname = "exynos4210-spi.1",
595 .enable = exynos4_clk_ip_peril_ctrl, 595 .enable = exynos4_clk_ip_peril_ctrl,
596 .ctrlbit = (1 << 17), 596 .ctrlbit = (1 << 17),
597 }, { 597 }, {
598 .name = "spi", 598 .name = "spi",
599 .devname = "s3c64xx-spi.2", 599 .devname = "exynos4210-spi.2",
600 .enable = exynos4_clk_ip_peril_ctrl, 600 .enable = exynos4_clk_ip_peril_ctrl,
601 .ctrlbit = (1 << 18), 601 .ctrlbit = (1 << 18),
602 }, { 602 }, {
@@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1242 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1242 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1243}; 1243};
1244 1244
1245static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1246 .clk = {
1247 .name = "mdout_spi",
1248 .devname = "exynos4210-spi.0",
1249 },
1250 .sources = &exynos4_clkset_group,
1251 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1252 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1253};
1254
1255static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1256 .clk = {
1257 .name = "mdout_spi",
1258 .devname = "exynos4210-spi.1",
1259 },
1260 .sources = &exynos4_clkset_group,
1261 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1262 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1263};
1264
1265static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1266 .clk = {
1267 .name = "mdout_spi",
1268 .devname = "exynos4210-spi.2",
1269 },
1270 .sources = &exynos4_clkset_group,
1271 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1272 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1273};
1274
1245static struct clksrc_clk exynos4_clk_sclk_spi0 = { 1275static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1246 .clk = { 1276 .clk = {
1247 .name = "sclk_spi", 1277 .name = "sclk_spi",
1248 .devname = "s3c64xx-spi.0", 1278 .devname = "exynos4210-spi.0",
1279 .parent = &exynos4_clk_mdout_spi0.clk,
1249 .enable = exynos4_clksrc_mask_peril1_ctrl, 1280 .enable = exynos4_clksrc_mask_peril1_ctrl,
1250 .ctrlbit = (1 << 16), 1281 .ctrlbit = (1 << 16),
1251 }, 1282 },
1252 .sources = &exynos4_clkset_group, 1283 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1253 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1254 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1255}; 1284};
1256 1285
1257static struct clksrc_clk exynos4_clk_sclk_spi1 = { 1286static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1258 .clk = { 1287 .clk = {
1259 .name = "sclk_spi", 1288 .name = "sclk_spi",
1260 .devname = "s3c64xx-spi.1", 1289 .devname = "exynos4210-spi.1",
1290 .parent = &exynos4_clk_mdout_spi1.clk,
1261 .enable = exynos4_clksrc_mask_peril1_ctrl, 1291 .enable = exynos4_clksrc_mask_peril1_ctrl,
1262 .ctrlbit = (1 << 20), 1292 .ctrlbit = (1 << 20),
1263 }, 1293 },
1264 .sources = &exynos4_clkset_group, 1294 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1265 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1266 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1267}; 1295};
1268 1296
1269static struct clksrc_clk exynos4_clk_sclk_spi2 = { 1297static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1270 .clk = { 1298 .clk = {
1271 .name = "sclk_spi", 1299 .name = "sclk_spi",
1272 .devname = "s3c64xx-spi.2", 1300 .devname = "exynos4210-spi.2",
1301 .parent = &exynos4_clk_mdout_spi2.clk,
1273 .enable = exynos4_clksrc_mask_peril1_ctrl, 1302 .enable = exynos4_clksrc_mask_peril1_ctrl,
1274 .ctrlbit = (1 << 24), 1303 .ctrlbit = (1 << 24),
1275 }, 1304 },
1276 .sources = &exynos4_clkset_group, 1305 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1277 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1278 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1279}; 1306};
1280 1307
1281/* Clock initialization code */ 1308/* Clock initialization code */
@@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1331 &exynos4_clk_sclk_spi0, 1358 &exynos4_clk_sclk_spi0,
1332 &exynos4_clk_sclk_spi1, 1359 &exynos4_clk_sclk_spi1,
1333 &exynos4_clk_sclk_spi2, 1360 &exynos4_clk_sclk_spi2,
1334 1361 &exynos4_clk_mdout_spi0,
1362 &exynos4_clk_mdout_spi1,
1363 &exynos4_clk_mdout_spi2,
1335}; 1364};
1336 1365
1337static struct clk_lookup exynos4_clk_lookup[] = { 1366static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1347,9 +1376,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1347 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), 1376 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1348 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), 1377 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1349 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), 1378 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1350 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), 1379 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1351 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), 1380 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1352 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), 1381 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1353}; 1382};
1354 1383
1355static int xtal_rate; 1384static int xtal_rate;
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index fefa336be2b4..774533c67066 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); 131 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
132} 132}
133 133
134static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
135{
136 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
137}
138
134static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) 139static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
135{ 140{
136 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); 141 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
@@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = {
741 .enable = exynos5_clk_ip_peric_ctrl, 746 .enable = exynos5_clk_ip_peric_ctrl,
742 .ctrlbit = (1 << 14), 747 .ctrlbit = (1 << 14),
743 }, { 748 }, {
749 .name = "spi",
750 .devname = "exynos4210-spi.0",
751 .parent = &exynos5_clk_aclk_66.clk,
752 .enable = exynos5_clk_ip_peric_ctrl,
753 .ctrlbit = (1 << 16),
754 }, {
755 .name = "spi",
756 .devname = "exynos4210-spi.1",
757 .parent = &exynos5_clk_aclk_66.clk,
758 .enable = exynos5_clk_ip_peric_ctrl,
759 .ctrlbit = (1 << 17),
760 }, {
761 .name = "spi",
762 .devname = "exynos4210-spi.2",
763 .parent = &exynos5_clk_aclk_66.clk,
764 .enable = exynos5_clk_ip_peric_ctrl,
765 .ctrlbit = (1 << 18),
766 }, {
744 .name = SYSMMU_CLOCK_NAME, 767 .name = SYSMMU_CLOCK_NAME,
745 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), 768 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
746 .enable = &exynos5_clk_ip_mfc_ctrl, 769 .enable = &exynos5_clk_ip_mfc_ctrl,
@@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1034 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1057 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1035}; 1058};
1036 1059
1060static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1061 .clk = {
1062 .name = "mdout_spi",
1063 .devname = "exynos4210-spi.0",
1064 },
1065 .sources = &exynos5_clkset_group,
1066 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1067 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1068};
1069
1070static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1071 .clk = {
1072 .name = "mdout_spi",
1073 .devname = "exynos4210-spi.1",
1074 },
1075 .sources = &exynos5_clkset_group,
1076 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1077 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1078};
1079
1080static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1081 .clk = {
1082 .name = "mdout_spi",
1083 .devname = "exynos4210-spi.2",
1084 },
1085 .sources = &exynos5_clkset_group,
1086 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1087 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1088};
1089
1090static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1091 .clk = {
1092 .name = "sclk_spi",
1093 .devname = "exynos4210-spi.0",
1094 .parent = &exynos5_clk_mdout_spi0.clk,
1095 .enable = exynos5_clksrc_mask_peric1_ctrl,
1096 .ctrlbit = (1 << 16),
1097 },
1098 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1099};
1100
1101static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1102 .clk = {
1103 .name = "sclk_spi",
1104 .devname = "exynos4210-spi.1",
1105 .parent = &exynos5_clk_mdout_spi1.clk,
1106 .enable = exynos5_clksrc_mask_peric1_ctrl,
1107 .ctrlbit = (1 << 20),
1108 },
1109 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1110};
1111
1112static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1113 .clk = {
1114 .name = "sclk_spi",
1115 .devname = "exynos4210-spi.2",
1116 .parent = &exynos5_clk_mdout_spi2.clk,
1117 .enable = exynos5_clksrc_mask_peric1_ctrl,
1118 .ctrlbit = (1 << 24),
1119 },
1120 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1121};
1122
1037static struct clksrc_clk exynos5_clksrcs[] = { 1123static struct clksrc_clk exynos5_clksrcs[] = {
1038 { 1124 {
1039 .clk = { 1125 .clk = {
@@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
1148 &exynos5_clk_dout_mmc4, 1234 &exynos5_clk_dout_mmc4,
1149 &exynos5_clk_aclk_acp, 1235 &exynos5_clk_aclk_acp,
1150 &exynos5_clk_pclk_acp, 1236 &exynos5_clk_pclk_acp,
1237 &exynos5_clk_sclk_spi0,
1238 &exynos5_clk_sclk_spi1,
1239 &exynos5_clk_sclk_spi2,
1240 &exynos5_clk_mdout_spi0,
1241 &exynos5_clk_mdout_spi1,
1242 &exynos5_clk_mdout_spi2,
1151}; 1243};
1152 1244
1153static struct clk *exynos5_clk_cdev[] = { 1245static struct clk *exynos5_clk_cdev[] = {
@@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
1176 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), 1268 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1177 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), 1269 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1178 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), 1270 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1271 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1272 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1273 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1179 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), 1274 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1180 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), 1275 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1181 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), 1276 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 7a4b4789eb72..35bced6f9092 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -195,6 +195,10 @@
195#define IRQ_IIC6 EXYNOS4_IRQ_IIC6 195#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
196#define IRQ_IIC7 EXYNOS4_IRQ_IIC7 196#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
197 197
198#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
199#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
200#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
201
198#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST 202#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
199#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG 203#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
200 204
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ca4aa89aa46b..c72b675b3e4b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -154,6 +154,9 @@
154#define EXYNOS4_PA_SPI0 0x13920000 154#define EXYNOS4_PA_SPI0 0x13920000
155#define EXYNOS4_PA_SPI1 0x13930000 155#define EXYNOS4_PA_SPI1 0x13930000
156#define EXYNOS4_PA_SPI2 0x13940000 156#define EXYNOS4_PA_SPI2 0x13940000
157#define EXYNOS5_PA_SPI0 0x12D20000
158#define EXYNOS5_PA_SPI1 0x12D30000
159#define EXYNOS5_PA_SPI2 0x12D40000
157 160
158#define EXYNOS4_PA_GPIO1 0x11400000 161#define EXYNOS4_PA_GPIO1 0x11400000
159#define EXYNOS4_PA_GPIO2 0x11000000 162#define EXYNOS4_PA_GPIO2 0x11000000
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e7e9743543ac..b2b5d5faa748 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
55 "exynos4-sdhci.3", NULL), 55 "exynos4-sdhci.3", NULL),
56 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), 56 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
57 "s3c2440-i2c.0", NULL), 57 "s3c2440-i2c.0", NULL),
58 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
59 "exynos4210-spi.0", NULL),
60 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
61 "exynos4210-spi.1", NULL),
62 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
63 "exynos4210-spi.2", NULL),
58 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), 64 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
59 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), 65 OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
60 {}, 66 {},
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7b1e11a228cc..ef770bc2318f 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
47 "s3c2440-i2c.0", NULL), 47 "s3c2440-i2c.0", NULL),
48 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), 48 OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
49 "s3c2440-i2c.1", NULL), 49 "s3c2440-i2c.1", NULL),
50 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
51 "exynos4210-spi.0", NULL),
52 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
53 "exynos4210-spi.1", NULL),
54 OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
55 "exynos4210-spi.2", NULL),
50 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), 56 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
51 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), 57 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
52 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), 58 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index 833ff40ee0e8..4999829d1c6e 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -9,21 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 13
17#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { 15int s3c64xx_spi0_cfg_gpio(void)
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .clk_from_cmu = true,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{ 16{
28 s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); 17 s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); 18 s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
@@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
34#endif 23#endif
35 24
36#ifdef CONFIG_S3C64XX_DEV_SPI1 25#ifdef CONFIG_S3C64XX_DEV_SPI1
37struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { 26int s3c64xx_spi1_cfg_gpio(void)
38 .fifo_lvl_mask = 0x7f,
39 .rx_lvl_offset = 15,
40 .high_speed = 1,
41 .clk_from_cmu = true,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{ 27{
47 s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); 28 s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
@@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
53#endif 34#endif
54 35
55#ifdef CONFIG_S3C64XX_DEV_SPI2 36#ifdef CONFIG_S3C64XX_DEV_SPI2
56struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { 37int s3c64xx_spi2_cfg_gpio(void)
57 .fifo_lvl_mask = 0x7f,
58 .rx_lvl_offset = 15,
59 .high_speed = 1,
60 .clk_from_cmu = true,
61 .tx_st_done = 25,
62};
63
64int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
65{ 38{
66 s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); 39 s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
67 s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); 40 s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1bba37c6598b..7616101a35f0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -52,6 +52,7 @@ config SOC_IMX25
52 select ARCH_MX25 52 select ARCH_MX25
53 select COMMON_CLK 53 select COMMON_CLK
54 select CPU_ARM926T 54 select CPU_ARM926T
55 select HAVE_CAN_FLEXCAN if CAN
55 select ARCH_MXC_IOMUX_V3 56 select ARCH_MXC_IOMUX_V3
56 select MXC_AVIC 57 select MXC_AVIC
57 58
@@ -79,6 +80,7 @@ config SOC_IMX35
79 select HAVE_EPIT 80 select HAVE_EPIT
80 select MXC_AVIC 81 select MXC_AVIC
81 select SMP_ON_UP if SMP 82 select SMP_ON_UP if SMP
83 select HAVE_CAN_FLEXCAN if CAN
82 84
83config SOC_IMX5 85config SOC_IMX5
84 select CPU_V7 86 select CPU_V7
@@ -105,6 +107,7 @@ config SOC_IMX53
105 select SOC_IMX5 107 select SOC_IMX5
106 select ARCH_MX5 108 select ARCH_MX5
107 select ARCH_MX53 109 select ARCH_MX53
110 select HAVE_CAN_FLEXCAN if CAN
108 111
109if ARCH_IMX_V4_V5 112if ARCH_IMX_V4_V5
110 113
@@ -556,6 +559,14 @@ config MACH_BUG
556 Include support for BUGBase 1.3 platform. This includes specific 559 Include support for BUGBase 1.3 platform. This includes specific
557 configurations for the board and its peripherals. 560 configurations for the board and its peripherals.
558 561
562config MACH_IMX31_DT
563 bool "Support i.MX31 platforms from device tree"
564 select SOC_IMX31
565 select USE_OF
566 help
567 Include support for Freescale i.MX31 based platforms
568 using the device tree for discovery.
569
559comment "MX35 platforms:" 570comment "MX35 platforms:"
560 571
561config MACH_PCM043 572config MACH_PCM043
@@ -826,10 +837,12 @@ config SOC_IMX6Q
826 select COMMON_CLK 837 select COMMON_CLK
827 select CPU_V7 838 select CPU_V7
828 select HAVE_ARM_SCU 839 select HAVE_ARM_SCU
840 select HAVE_CAN_FLEXCAN if CAN
829 select HAVE_IMX_GPC 841 select HAVE_IMX_GPC
830 select HAVE_IMX_MMDC 842 select HAVE_IMX_MMDC
831 select HAVE_IMX_SRC 843 select HAVE_IMX_SRC
832 select HAVE_SMP 844 select HAVE_SMP
845 select MFD_ANATOP
833 select PINCTRL 846 select PINCTRL
834 select PINCTRL_IMX6Q 847 select PINCTRL_IMX6Q
835 select USE_OF 848 select USE_OF
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ff29421414f2..07f7c226e4cf 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o
57obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o 57obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
58obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o 58obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
59obj-$(CONFIG_MACH_BUG) += mach-bug.o 59obj-$(CONFIG_MACH_BUG) += mach-bug.o
60obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
60 61
61# i.MX35 based machines 62# i.MX35 based machines
62obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o 63obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index c9a06d800f8e..f87a48fc74e1 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -20,6 +20,7 @@
20#include <linux/clkdev.h> 20#include <linux/clkdev.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/of.h>
23 24
24#include <mach/hardware.h> 25#include <mach/hardware.h>
25#include <mach/mx31.h> 26#include <mach/mx31.h>
@@ -179,3 +180,21 @@ int __init mx31_clocks_init(unsigned long fref)
179 180
180 return 0; 181 return 0;
181} 182}
183
184#ifdef CONFIG_OF
185int __init mx31_clocks_init_dt(void)
186{
187 struct device_node *np;
188 u32 fref = 26000000; /* default */
189
190 for_each_compatible_node(np, NULL, "fixed-clock") {
191 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
192 continue;
193
194 if (!of_property_read_u32(np, "clock-frequency", &fref))
195 break;
196 }
197
198 return mx31_clocks_init(fref);
199}
200#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index abb42e7453a9..ea89520b6e22 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -147,12 +147,12 @@ enum mx6q_clks {
147 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, 147 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
148 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, 148 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
149 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, 149 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
150 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, 150 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
151 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, 151 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
152 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, 152 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
153 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 153 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
154 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, 154 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
155 ssi2_ipg, ssi3_ipg, rom, 155 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
156 clk_max 156 clk_max
157}; 157};
158 158
@@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void)
198 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); 198 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
199 clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); 199 clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
200 200
201 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
202 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
203
201 /* name parent_name reg idx */ 204 /* name parent_name reg idx */
202 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 205 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
203 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 206 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
@@ -318,7 +321,7 @@ int __init mx6q_clocks_init(void)
318 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); 321 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
319 322
320 /* name parent_name reg shift */ 323 /* name parent_name reg shift */
321 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4); 324 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
322 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); 325 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
323 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 326 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
324 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 327 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
@@ -357,6 +360,7 @@ int __init mx6q_clocks_init(void)
357 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 360 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
358 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); 361 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
359 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); 362 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
363 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
360 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); 364 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
361 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); 365 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
362 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); 366 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
@@ -391,6 +395,18 @@ int __init mx6q_clocks_init(void)
391 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 395 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
392 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 396 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
393 clk_register_clkdev(clk[twd], NULL, "smp_twd"); 397 clk_register_clkdev(clk[twd], NULL, "smp_twd");
398 clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
399 clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
400 clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
401 clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
402 clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
403 clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
404 clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
405 clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
406 clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
407 clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
408 clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
409 clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
394 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); 410 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
395 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); 411 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
396 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); 412 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
new file mode 100644
index 000000000000..a68ba207b2b7
--- /dev/null
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/irq.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/time.h>
17#include <mach/common.h>
18#include <mach/mx31.h>
19
20static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
21 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
22 "imx21-uart.0", NULL),
23 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
24 "imx21-uart.1", NULL),
25 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
26 "imx21-uart.2", NULL),
27 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
28 "imx21-uart.3", NULL),
29 OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
30 "imx21-uart.4", NULL),
31 { /* sentinel */ }
32};
33
34static void __init imx31_dt_init(void)
35{
36 of_platform_populate(NULL, of_default_bus_match_table,
37 imx31_auxdata_lookup, NULL);
38}
39
40static void __init imx31_timer_init(void)
41{
42 mx31_clocks_init_dt();
43}
44
45static struct sys_timer imx31_timer = {
46 .init = imx31_timer_init,
47};
48
49static const char *imx31_dt_board_compat[] __initdata = {
50 "fsl,imx31",
51 NULL
52};
53
54DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
55 .map_io = mx31_map_io,
56 .init_early = imx31_init_early,
57 .init_irq = mx31_init_irq,
58 .handle_irq = imx31_handle_irq,
59 .timer = &imx31_timer,
60 .init_machine = imx31_dt_init,
61 .dt_compat = imx31_dt_board_compat,
62 .restart = mxc_restart,
63MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b47e98b7d539..140f55010630 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,6 +24,7 @@
24#include <linux/pinctrl/machine.h> 24#include <linux/pinctrl/machine.h>
25#include <linux/phy.h> 25#include <linux/phy.h>
26#include <linux/micrel_phy.h> 26#include <linux/micrel_phy.h>
27#include <linux/mfd/anatop.h>
27#include <asm/smp_twd.h> 28#include <asm/smp_twd.h>
28#include <asm/hardware/cache-l2x0.h> 29#include <asm/hardware/cache-l2x0.h>
29#include <asm/hardware/gic.h> 30#include <asm/hardware/gic.h>
@@ -113,6 +114,45 @@ static void __init imx6q_sabrelite_init(void)
113 imx6q_sabrelite_cko1_setup(); 114 imx6q_sabrelite_cko1_setup();
114} 115}
115 116
117static void __init imx6q_usb_init(void)
118{
119 struct device_node *np;
120 struct platform_device *pdev = NULL;
121 struct anatop *adata = NULL;
122
123 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
124 if (np)
125 pdev = of_find_device_by_node(np);
126 if (pdev)
127 adata = platform_get_drvdata(pdev);
128 if (!adata) {
129 if (np)
130 of_node_put(np);
131 return;
132 }
133
134#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
135#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
136
137#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
138#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
139
140 /*
141 * The external charger detector needs to be disabled,
142 * or the signal at DP will be poor
143 */
144 anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
145 BM_ANADIG_USB_CHRG_DETECT_EN_B
146 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
147 ~0);
148 anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
149 BM_ANADIG_USB_CHRG_DETECT_EN_B |
150 BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
151 ~0);
152
153 of_node_put(np);
154}
155
116static void __init imx6q_init_machine(void) 156static void __init imx6q_init_machine(void)
117{ 157{
118 /* 158 /*
@@ -127,6 +167,7 @@ static void __init imx6q_init_machine(void)
127 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 167 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
128 168
129 imx6q_pm_init(); 169 imx6q_pm_init();
170 imx6q_usb_init();
130} 171}
131 172
132static void __init imx6q_map_io(void) 173static void __init imx6q_map_io(void)
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 91cf0625819c..ccdf83b17cf1 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -16,6 +16,7 @@ config SOC_IMX28
16 bool 16 bool
17 select ARM_AMBA 17 select ARM_AMBA
18 select CPU_ARM926T 18 select CPU_ARM926T
19 select HAVE_CAN_FLEXCAN if CAN
19 select HAVE_PWM 20 select HAVE_PWM
20 select PINCTRL_IMX28 21 select PINCTRL_IMX28
21 22
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 07b11fe6453f..4582999cf080 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -1 +1,10 @@
1zreladdr-y += 0x40008000 1zreladdr-y += 0x40008000
2
3dtb-y += imx23-evk.dtb \
4 imx23-olinuxino.dtb \
5 imx23-stmp378x_devb.dtb \
6 imx28-apx4devkit.dtb \
7 imx28-cfa10036.dtb \
8 imx28-evk.dtb \
9 imx28-m28evk.dtb \
10 imx28-tx28.dtb \
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 9acdd6387047..9ee5cede3d42 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <mach/mx23.h> 11#include <mach/mx23.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h> 13#include <linux/mxsfb.h>
14#include <linux/amba/bus.h> 14#include <linux/amba/bus.h>
15 15
16static inline int mx23_add_duart(void) 16static inline int mx23_add_duart(void)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 84b2960df117..fcab431060f4 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <mach/mx28.h> 11#include <mach/mx28.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h> 13#include <linux/mxsfb.h>
14#include <linux/amba/bus.h> 14#include <linux/amba/bus.h>
15 15
16static inline int mx28_add_duart(void) 16static inline int mx28_add_duart(void)
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
index 5a75b7180f74..76b53f73418e 100644
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -10,7 +10,7 @@
10#include <mach/mx23.h> 10#include <mach/mx23.h>
11#include <mach/mx28.h> 11#include <mach/mx28.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h> 13#include <linux/mxsfb.h>
14 14
15#ifdef CONFIG_SOC_IMX23 15#ifdef CONFIG_SOC_IMX23
16struct platform_device *__init mx23_add_mxsfb( 16struct platform_device *__init mx23_add_mxsfb(
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
deleted file mode 100644
index e4d79791515e..000000000000
--- a/arch/arm/mach-mxs/include/mach/mxsfb.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
14 * MA 02110-1301, USA.
15 */
16
17#ifndef __MACH_FB_H
18#define __MACH_FB_H
19
20#include <linux/fb.h>
21
22#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
23#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
24#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
25#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
26
27#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
28#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */
29
30struct mxsfb_platform_data {
31 struct fb_videomode *mode_list;
32 unsigned mode_count;
33
34 unsigned default_bpp;
35
36 unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */
37 unsigned ld_intf_width; /* refer STMLCDIF_* macros */
38
39 unsigned fb_size; /* Size of the video memory. If zero a
40 * default will be used
41 */
42 unsigned long fb_phys; /* physical address for the video memory. If
43 * zero the framebuffer memory will be dynamically
44 * allocated. If specified,fb_size must also be specified.
45 * fb_phys must be unused by Linux.
46 */
47};
48
49#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8cac94b33020..648bdd05d38b 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -16,12 +16,95 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/irqdomain.h> 18#include <linux/irqdomain.h>
19#include <linux/micrel_phy.h>
20#include <linux/mxsfb.h>
19#include <linux/of_irq.h> 21#include <linux/of_irq.h>
20#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <linux/phy.h>
21#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
22#include <asm/mach/time.h> 25#include <asm/mach/time.h>
23#include <mach/common.h> 26#include <mach/common.h>
24 27
28static struct fb_videomode mx23evk_video_modes[] = {
29 {
30 .name = "Samsung-LMS430HF02",
31 .refresh = 60,
32 .xres = 480,
33 .yres = 272,
34 .pixclock = 108096, /* picosecond (9.2 MHz) */
35 .left_margin = 15,
36 .right_margin = 8,
37 .upper_margin = 12,
38 .lower_margin = 4,
39 .hsync_len = 1,
40 .vsync_len = 1,
41 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
42 FB_SYNC_DOTCLK_FAILING_ACT,
43 },
44};
45
46static struct fb_videomode mx28evk_video_modes[] = {
47 {
48 .name = "Seiko-43WVF1G",
49 .refresh = 60,
50 .xres = 800,
51 .yres = 480,
52 .pixclock = 29851, /* picosecond (33.5 MHz) */
53 .left_margin = 89,
54 .right_margin = 164,
55 .upper_margin = 23,
56 .lower_margin = 10,
57 .hsync_len = 10,
58 .vsync_len = 10,
59 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
60 FB_SYNC_DOTCLK_FAILING_ACT,
61 },
62};
63
64static struct fb_videomode m28evk_video_modes[] = {
65 {
66 .name = "Ampire AM-800480R2TMQW-T01H",
67 .refresh = 60,
68 .xres = 800,
69 .yres = 480,
70 .pixclock = 30066, /* picosecond (33.26 MHz) */
71 .left_margin = 0,
72 .right_margin = 256,
73 .upper_margin = 0,
74 .lower_margin = 45,
75 .hsync_len = 1,
76 .vsync_len = 1,
77 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
78 },
79};
80
81static struct fb_videomode apx4devkit_video_modes[] = {
82 {
83 .name = "HannStar PJ70112A",
84 .refresh = 60,
85 .xres = 800,
86 .yres = 480,
87 .pixclock = 33333, /* picosecond (30.00 MHz) */
88 .left_margin = 88,
89 .right_margin = 40,
90 .upper_margin = 32,
91 .lower_margin = 13,
92 .hsync_len = 48,
93 .vsync_len = 3,
94 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
95 FB_SYNC_DATA_ENABLE_HIGH_ACT |
96 FB_SYNC_DOTCLK_FAILING_ACT,
97 },
98};
99
100static struct mxsfb_platform_data mxsfb_pdata __initdata;
101
102static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
103 OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
104 OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
105 { /* sentinel */ }
106};
107
25static int __init mxs_icoll_add_irq_domain(struct device_node *np, 108static int __init mxs_icoll_add_irq_domain(struct device_node *np,
26 struct device_node *interrupt_parent) 109 struct device_node *interrupt_parent)
27{ 110{
@@ -71,33 +154,155 @@ static struct sys_timer imx28_timer = {
71 .init = imx28_timer_init, 154 .init = imx28_timer_init,
72}; 155};
73 156
74static void __init imx28_evk_init(void) 157enum mac_oui {
158 OUI_FSL,
159 OUI_DENX,
160};
161
162static void __init update_fec_mac_prop(enum mac_oui oui)
163{
164 struct device_node *np, *from = NULL;
165 struct property *oldmac, *newmac;
166 const u32 *ocotp = mxs_get_ocotp();
167 u8 *macaddr;
168 u32 val;
169 int i;
170
171 for (i = 0; i < 2; i++) {
172 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
173 if (!np)
174 return;
175 from = np;
176
177 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
178 if (!newmac)
179 return;
180 newmac->value = newmac + 1;
181 newmac->length = 6;
182
183 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
184 if (!newmac->name) {
185 kfree(newmac);
186 return;
187 }
188
189 /*
190 * OCOTP only stores the last 4 octets for each mac address,
191 * so hard-code OUI here.
192 */
193 macaddr = newmac->value;
194 switch (oui) {
195 case OUI_FSL:
196 macaddr[0] = 0x00;
197 macaddr[1] = 0x04;
198 macaddr[2] = 0x9f;
199 break;
200 case OUI_DENX:
201 macaddr[0] = 0xc0;
202 macaddr[1] = 0xe5;
203 macaddr[2] = 0x4e;
204 break;
205 }
206 val = ocotp[i];
207 macaddr[3] = (val >> 16) & 0xff;
208 macaddr[4] = (val >> 8) & 0xff;
209 macaddr[5] = (val >> 0) & 0xff;
210
211 oldmac = of_find_property(np, newmac->name, NULL);
212 if (oldmac)
213 prom_update_property(np, newmac, oldmac);
214 else
215 prom_add_property(np, newmac);
216 }
217}
218
219static void __init imx23_evk_init(void)
220{
221 mxsfb_pdata.mode_list = mx23evk_video_modes;
222 mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
223 mxsfb_pdata.default_bpp = 32;
224 mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
225}
226
227static inline void enable_clk_enet_out(void)
75{ 228{
76 struct clk *clk; 229 struct clk *clk = clk_get_sys("enet_out", NULL);
77 230
78 /* Enable fec phy clock */
79 clk = clk_get_sys("enet_out", NULL);
80 if (!IS_ERR(clk)) 231 if (!IS_ERR(clk))
81 clk_prepare_enable(clk); 232 clk_prepare_enable(clk);
82} 233}
83 234
235static void __init imx28_evk_init(void)
236{
237 enable_clk_enet_out();
238 update_fec_mac_prop(OUI_FSL);
239
240 mxsfb_pdata.mode_list = mx28evk_video_modes;
241 mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
242 mxsfb_pdata.default_bpp = 32;
243 mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
244}
245
246static void __init m28evk_init(void)
247{
248 enable_clk_enet_out();
249 update_fec_mac_prop(OUI_DENX);
250
251 mxsfb_pdata.mode_list = m28evk_video_modes;
252 mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
253 mxsfb_pdata.default_bpp = 16;
254 mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
255}
256
257static int apx4devkit_phy_fixup(struct phy_device *phy)
258{
259 phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
260 return 0;
261}
262
263static void __init apx4devkit_init(void)
264{
265 enable_clk_enet_out();
266
267 if (IS_BUILTIN(CONFIG_PHYLIB))
268 phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
269 apx4devkit_phy_fixup);
270
271 mxsfb_pdata.mode_list = apx4devkit_video_modes;
272 mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
273 mxsfb_pdata.default_bpp = 32;
274 mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
275}
276
84static void __init mxs_machine_init(void) 277static void __init mxs_machine_init(void)
85{ 278{
86 if (of_machine_is_compatible("fsl,imx28-evk")) 279 if (of_machine_is_compatible("fsl,imx28-evk"))
87 imx28_evk_init(); 280 imx28_evk_init();
281 else if (of_machine_is_compatible("fsl,imx23-evk"))
282 imx23_evk_init();
283 else if (of_machine_is_compatible("denx,m28evk"))
284 m28evk_init();
285 else if (of_machine_is_compatible("bluegiga,apx4devkit"))
286 apx4devkit_init();
88 287
89 of_platform_populate(NULL, of_default_bus_match_table, 288 of_platform_populate(NULL, of_default_bus_match_table,
90 NULL, NULL); 289 mxs_auxdata_lookup, NULL);
91} 290}
92 291
93static const char *imx23_dt_compat[] __initdata = { 292static const char *imx23_dt_compat[] __initdata = {
94 "fsl,imx23-evk", 293 "fsl,imx23-evk",
294 "fsl,stmp378x_devb"
295 "olimex,imx23-olinuxino",
95 "fsl,imx23", 296 "fsl,imx23",
96 NULL, 297 NULL,
97}; 298};
98 299
99static const char *imx28_dt_compat[] __initdata = { 300static const char *imx28_dt_compat[] __initdata = {
301 "bluegiga,apx4devkit",
302 "crystalfontz,cfa10036",
303 "denx,m28evk",
100 "fsl,imx28-evk", 304 "fsl,imx28-evk",
305 "karo,tx28",
101 "fsl,imx28", 306 "fsl,imx28",
102 NULL, 307 NULL,
103}; 308};
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7b4b9327e543..527c0046064d 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -772,7 +772,7 @@ static int __init omap_init_wdt(void)
772 char *oh_name = "wd_timer2"; 772 char *oh_name = "wd_timer2";
773 char *dev_name = "omap_wdt"; 773 char *dev_name = "omap_wdt";
774 774
775 if (!cpu_class_is_omap2()) 775 if (!cpu_class_is_omap2() || of_have_populated_dt())
776 return 0; 776 return 0;
777 777
778 oh = omap_hwmod_lookup(oh_name); 778 oh = omap_hwmod_lookup(oh_name);
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 8702ecfaab30..14a81c2317a4 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), 144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
145 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), 145 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
146 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), 146 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
147 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk), 147 /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
148 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
148}; 149};
149 150
150void __init s3c2416_init_clocks(int xtal) 151void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index a4c5a520d994..7f689ce1be61 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
181 181
182static struct clk_lookup s3c2443_clk_lookup[] = { 182static struct clk_lookup s3c2443_clk_lookup[] = {
183 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), 183 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
184 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk), 184 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
185}; 185};
186 186
187void __init s3c2443_init_clocks(int xtal) 187void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeeb2be283fa..aeb4a24ff3ed 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
559 559
560static struct clk hsspi_clk = { 560static struct clk hsspi_clk = {
561 .name = "spi", 561 .name = "spi",
562 .devname = "s3c64xx-spi.0", 562 .devname = "s3c2443-spi.0",
563 .parent = &clk_p, 563 .parent = &clk_p,
564 .enable = s3c2443_clkcon_enable_p, 564 .enable = s3c2443_clkcon_enable_p,
565 .ctrlbit = S3C2443_PCLKCON_HSSPI, 565 .ctrlbit = S3C2443_PCLKCON_HSSPI,
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
633 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 633 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
634 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 634 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
635 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), 635 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
636 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk), 636 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
637}; 637};
638 638
639void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 639void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 5712c85f39b1..3d47e023ce94 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -13,20 +13,12 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14 14
15#include <plat/gpio-cfg.h> 15#include <plat/gpio-cfg.h>
16#include <plat/s3c64xx-spi.h>
17 16
18#include <mach/hardware.h> 17#include <mach/hardware.h>
19#include <mach/regs-gpio.h> 18#include <mach/regs-gpio.h>
20 19
21#ifdef CONFIG_S3C64XX_DEV_SPI0 20#ifdef CONFIG_S3C64XX_DEV_SPI0
22struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { 21int s3c64xx_spi0_cfg_gpio(void)
23 .fifo_lvl_mask = 0x7f,
24 .rx_lvl_offset = 13,
25 .tx_st_done = 21,
26 .high_speed = 1,
27};
28
29int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
30{ 22{
31 /* enable hsspi bit in misccr */ 23 /* enable hsspi bit in misccr */
32 s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); 24 s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a691cb..28041e83dc82 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
179 }, { 179 }, {
180 .name = "spi", 180 .name = "spi",
181 .devname = "s3c64xx-spi.0", 181 .devname = "s3c6410-spi.0",
182 .parent = &clk_p, 182 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 183 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 184 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
185 }, { 185 }, {
186 .name = "spi", 186 .name = "spi",
187 .devname = "s3c64xx-spi.1", 187 .devname = "s3c6410-spi.1",
188 .parent = &clk_p, 188 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 189 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 190 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
331 331
332static struct clk clk_48m_spi0 = { 332static struct clk clk_48m_spi0 = {
333 .name = "spi_48m", 333 .name = "spi_48m",
334 .devname = "s3c64xx-spi.0", 334 .devname = "s3c6410-spi.0",
335 .parent = &clk_48m, 335 .parent = &clk_48m,
336 .enable = s3c64xx_sclk_ctrl, 336 .enable = s3c64xx_sclk_ctrl,
337 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 337 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
339 339
340static struct clk clk_48m_spi1 = { 340static struct clk clk_48m_spi1 = {
341 .name = "spi_48m", 341 .name = "spi_48m",
342 .devname = "s3c64xx-spi.1", 342 .devname = "s3c6410-spi.1",
343 .parent = &clk_48m, 343 .parent = &clk_48m,
344 .enable = s3c64xx_sclk_ctrl, 344 .enable = s3c64xx_sclk_ctrl,
345 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 345 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
802static struct clksrc_clk clk_sclk_spi0 = { 802static struct clksrc_clk clk_sclk_spi0 = {
803 .clk = { 803 .clk = {
804 .name = "spi-bus", 804 .name = "spi-bus",
805 .devname = "s3c64xx-spi.0", 805 .devname = "s3c6410-spi.0",
806 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 806 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
807 .enable = s3c64xx_sclk_ctrl, 807 .enable = s3c64xx_sclk_ctrl,
808 }, 808 },
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
814static struct clksrc_clk clk_sclk_spi1 = { 814static struct clksrc_clk clk_sclk_spi1 = {
815 .clk = { 815 .clk = {
816 .name = "spi-bus", 816 .name = "spi-bus",
817 .devname = "s3c64xx-spi.1", 817 .devname = "s3c6410-spi.1",
818 .ctrlbit = S3C_CLKCON_SCLK_SPI1, 818 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
819 .enable = s3c64xx_sclk_ctrl, 819 .enable = s3c64xx_sclk_ctrl,
820 }, 820 },
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
860 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 860 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
861 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 861 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
862 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), 862 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
863 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 863 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
864 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), 864 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
865}; 865};
866 866
867#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 867#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98cf0e4c..57b1ff4b2d7c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,6 +21,7 @@
21 */ 21 */
22enum dma_ch { 22enum dma_ch {
23 /* DMA0/SDMA0 */ 23 /* DMA0/SDMA0 */
24 DMACH_DT_PROP = -1, /* not yet supported, do not use */
24 DMACH_UART0 = 0, 25 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2, 26 DMACH_UART0_SRC2,
26 DMACH_UART1, 27 DMACH_UART1,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d0c352d861f8..6dd4fae33a82 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -799,7 +799,7 @@ static void __init crag6410_machine_init(void)
799 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); 799 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
800 800
801 samsung_keypad_set_platdata(&crag6410_keypad_data); 801 samsung_keypad_set_platdata(&crag6410_keypad_data);
802 s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1); 802 s3c64xx_spi0_set_platdata(NULL, 0, 1);
803 803
804 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); 804 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
805 805
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad7a825..4dc53450d715 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -9,19 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 13
17#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { 15int s3c64xx_spi0_cfg_gpio(void)
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{ 16{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, 17 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 18 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -30,13 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
30#endif 21#endif
31 22
32#ifdef CONFIG_S3C64XX_DEV_SPI1 23#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { 24int s3c64xx_spi1_cfg_gpio(void)
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{ 25{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, 26 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index ee1e8e7f5631..000445596ec4 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
227 .ctrlbit = (1 << 17), 227 .ctrlbit = (1 << 17),
228 }, { 228 }, {
229 .name = "spi", 229 .name = "spi",
230 .devname = "s3c64xx-spi.0", 230 .devname = "s5p64x0-spi.0",
231 .parent = &clk_pclk_low.clk, 231 .parent = &clk_pclk_low.clk,
232 .enable = s5p64x0_pclk_ctrl, 232 .enable = s5p64x0_pclk_ctrl,
233 .ctrlbit = (1 << 21), 233 .ctrlbit = (1 << 21),
234 }, { 234 }, {
235 .name = "spi", 235 .name = "spi",
236 .devname = "s3c64xx-spi.1", 236 .devname = "s5p64x0-spi.1",
237 .parent = &clk_pclk_low.clk, 237 .parent = &clk_pclk_low.clk,
238 .enable = s5p64x0_pclk_ctrl, 238 .enable = s5p64x0_pclk_ctrl,
239 .ctrlbit = (1 << 22), 239 .ctrlbit = (1 << 22),
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
467static struct clksrc_clk clk_sclk_spi0 = { 467static struct clksrc_clk clk_sclk_spi0 = {
468 .clk = { 468 .clk = {
469 .name = "sclk_spi", 469 .name = "sclk_spi",
470 .devname = "s3c64xx-spi.0", 470 .devname = "s5p64x0-spi.0",
471 .ctrlbit = (1 << 20), 471 .ctrlbit = (1 << 20),
472 .enable = s5p64x0_sclk_ctrl, 472 .enable = s5p64x0_sclk_ctrl,
473 }, 473 },
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
479static struct clksrc_clk clk_sclk_spi1 = { 479static struct clksrc_clk clk_sclk_spi1 = {
480 .clk = { 480 .clk = {
481 .name = "sclk_spi", 481 .name = "sclk_spi",
482 .devname = "s3c64xx-spi.1", 482 .devname = "s5p64x0-spi.1",
483 .ctrlbit = (1 << 21), 483 .ctrlbit = (1 << 21),
484 .enable = s5p64x0_sclk_ctrl, 484 .enable = s5p64x0_sclk_ctrl,
485 }, 485 },
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
519 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 519 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
520 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 520 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
521 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 521 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
522 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 522 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
523 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 523 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
524 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), 524 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
525 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 525 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
526 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 526 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index dae6a13f43bb..f3e0ef3d27c9 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
236 .ctrlbit = (1 << 17), 236 .ctrlbit = (1 << 17),
237 }, { 237 }, {
238 .name = "spi", 238 .name = "spi",
239 .devname = "s3c64xx-spi.0", 239 .devname = "s5p64x0-spi.0",
240 .parent = &clk_pclk_low.clk, 240 .parent = &clk_pclk_low.clk,
241 .enable = s5p64x0_pclk_ctrl, 241 .enable = s5p64x0_pclk_ctrl,
242 .ctrlbit = (1 << 21), 242 .ctrlbit = (1 << 21),
243 }, { 243 }, {
244 .name = "spi", 244 .name = "spi",
245 .devname = "s3c64xx-spi.1", 245 .devname = "s5p64x0-spi.1",
246 .parent = &clk_pclk_low.clk, 246 .parent = &clk_pclk_low.clk,
247 .enable = s5p64x0_pclk_ctrl, 247 .enable = s5p64x0_pclk_ctrl,
248 .ctrlbit = (1 << 22), 248 .ctrlbit = (1 << 22),
@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
528static struct clksrc_clk clk_sclk_spi0 = { 528static struct clksrc_clk clk_sclk_spi0 = {
529 .clk = { 529 .clk = {
530 .name = "sclk_spi", 530 .name = "sclk_spi",
531 .devname = "s3c64xx-spi.0", 531 .devname = "s5p64x0-spi.0",
532 .ctrlbit = (1 << 20), 532 .ctrlbit = (1 << 20),
533 .enable = s5p64x0_sclk_ctrl, 533 .enable = s5p64x0_sclk_ctrl,
534 }, 534 },
@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
540static struct clksrc_clk clk_sclk_spi1 = { 540static struct clksrc_clk clk_sclk_spi1 = {
541 .clk = { 541 .clk = {
542 .name = "sclk_spi", 542 .name = "sclk_spi",
543 .devname = "s3c64xx-spi.1", 543 .devname = "s5p64x0-spi.1",
544 .ctrlbit = (1 << 21), 544 .ctrlbit = (1 << 21),
545 .enable = s5p64x0_sclk_ctrl, 545 .enable = s5p64x0_sclk_ctrl,
546 }, 546 },
@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
562 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 562 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
563 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 563 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
564 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 564 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
565 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 565 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
566 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 566 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
567 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), 567 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
568 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 568 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
569 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 569 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index e9b841240352..7664356720ca 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -9,21 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14
15#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
16#include <plat/cpu.h>
17#include <plat/s3c64xx-spi.h>
18 13
19#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
20struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { 15int s3c64xx_spi0_cfg_gpio(void)
21 .fifo_lvl_mask = 0x1ff,
22 .rx_lvl_offset = 15,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{ 16{
28 if (soc_is_s5p6450()) 17 if (soc_is_s5p6450())
29 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, 18 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
@@ -36,13 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
36#endif 25#endif
37 26
38#ifdef CONFIG_S3C64XX_DEV_SPI1 27#ifdef CONFIG_S3C64XX_DEV_SPI1
39struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { 28int s3c64xx_spi1_cfg_gpio(void)
40 .fifo_lvl_mask = 0x7f,
41 .rx_lvl_offset = 15,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{ 29{
47 if (soc_is_s5p6450()) 30 if (soc_is_s5p6450())
48 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, 31 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 16eca4ea2010..926219791f0d 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
564 .ctrlbit = (1 << 5), 564 .ctrlbit = (1 << 5),
565 }, { 565 }, {
566 .name = "spi", 566 .name = "spi",
567 .devname = "s3c64xx-spi.0", 567 .devname = "s5pc100-spi.0",
568 .parent = &clk_div_d1_bus.clk, 568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl, 569 .enable = s5pc100_d1_4_ctrl,
570 .ctrlbit = (1 << 6), 570 .ctrlbit = (1 << 6),
571 }, { 571 }, {
572 .name = "spi", 572 .name = "spi",
573 .devname = "s3c64xx-spi.1", 573 .devname = "s5pc100-spi.1",
574 .parent = &clk_div_d1_bus.clk, 574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl, 575 .enable = s5pc100_d1_4_ctrl,
576 .ctrlbit = (1 << 7), 576 .ctrlbit = (1 << 7),
577 }, { 577 }, {
578 .name = "spi", 578 .name = "spi",
579 .devname = "s3c64xx-spi.2", 579 .devname = "s5pc100-spi.2",
580 .parent = &clk_div_d1_bus.clk, 580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl, 581 .enable = s5pc100_d1_4_ctrl,
582 .ctrlbit = (1 << 8), 582 .ctrlbit = (1 << 8),
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
702 702
703static struct clk clk_48m_spi0 = { 703static struct clk clk_48m_spi0 = {
704 .name = "spi_48m", 704 .name = "spi_48m",
705 .devname = "s3c64xx-spi.0", 705 .devname = "s5pc100-spi.0",
706 .parent = &clk_mout_48m.clk, 706 .parent = &clk_mout_48m.clk,
707 .enable = s5pc100_sclk0_ctrl, 707 .enable = s5pc100_sclk0_ctrl,
708 .ctrlbit = (1 << 7), 708 .ctrlbit = (1 << 7),
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
710 710
711static struct clk clk_48m_spi1 = { 711static struct clk clk_48m_spi1 = {
712 .name = "spi_48m", 712 .name = "spi_48m",
713 .devname = "s3c64xx-spi.1", 713 .devname = "s5pc100-spi.1",
714 .parent = &clk_mout_48m.clk, 714 .parent = &clk_mout_48m.clk,
715 .enable = s5pc100_sclk0_ctrl, 715 .enable = s5pc100_sclk0_ctrl,
716 .ctrlbit = (1 << 8), 716 .ctrlbit = (1 << 8),
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
718 718
719static struct clk clk_48m_spi2 = { 719static struct clk clk_48m_spi2 = {
720 .name = "spi_48m", 720 .name = "spi_48m",
721 .devname = "s3c64xx-spi.2", 721 .devname = "s5pc100-spi.2",
722 .parent = &clk_mout_48m.clk, 722 .parent = &clk_mout_48m.clk,
723 .enable = s5pc100_sclk0_ctrl, 723 .enable = s5pc100_sclk0_ctrl,
724 .ctrlbit = (1 << 9), 724 .ctrlbit = (1 << 9),
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
1085static struct clksrc_clk clk_sclk_spi0 = { 1085static struct clksrc_clk clk_sclk_spi0 = {
1086 .clk = { 1086 .clk = {
1087 .name = "sclk_spi", 1087 .name = "sclk_spi",
1088 .devname = "s3c64xx-spi.0", 1088 .devname = "s5pc100-spi.0",
1089 .ctrlbit = (1 << 4), 1089 .ctrlbit = (1 << 4),
1090 .enable = s5pc100_sclk0_ctrl, 1090 .enable = s5pc100_sclk0_ctrl,
1091 }, 1091 },
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
1097static struct clksrc_clk clk_sclk_spi1 = { 1097static struct clksrc_clk clk_sclk_spi1 = {
1098 .clk = { 1098 .clk = {
1099 .name = "sclk_spi", 1099 .name = "sclk_spi",
1100 .devname = "s3c64xx-spi.1", 1100 .devname = "s5pc100-spi.1",
1101 .ctrlbit = (1 << 5), 1101 .ctrlbit = (1 << 5),
1102 .enable = s5pc100_sclk0_ctrl, 1102 .enable = s5pc100_sclk0_ctrl,
1103 }, 1103 },
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
1109static struct clksrc_clk clk_sclk_spi2 = { 1109static struct clksrc_clk clk_sclk_spi2 = {
1110 .clk = { 1110 .clk = {
1111 .name = "sclk_spi", 1111 .name = "sclk_spi",
1112 .devname = "s3c64xx-spi.2", 1112 .devname = "s5pc100-spi.2",
1113 .ctrlbit = (1 << 6), 1113 .ctrlbit = (1 << 6),
1114 .enable = s5pc100_sclk0_ctrl, 1114 .enable = s5pc100_sclk0_ctrl,
1115 }, 1115 },
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 1315 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1316 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 1317 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), 1318 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
1319 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), 1319 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), 1320 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
1321 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), 1321 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), 1322 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
1323 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), 1323 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1324}; 1324};
1325 1325
1326void __init s5pc100_register_clocks(void) 1326void __init s5pc100_register_clocks(void)
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 431a6f747caa..183567961de1 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -9,20 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 13
17#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { 15int s3c64xx_spi0_cfg_gpio(void)
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .high_speed = 1,
22 .tx_st_done = 21,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{ 16{
27 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, 17 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 18 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -31,14 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
31#endif 21#endif
32 22
33#ifdef CONFIG_S3C64XX_DEV_SPI1 23#ifdef CONFIG_S3C64XX_DEV_SPI1
34struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { 24int s3c64xx_spi1_cfg_gpio(void)
35 .fifo_lvl_mask = 0x7f,
36 .rx_lvl_offset = 13,
37 .high_speed = 1,
38 .tx_st_done = 21,
39};
40
41int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
42{ 25{
43 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, 26 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
44 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -47,14 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
47#endif 30#endif
48 31
49#ifdef CONFIG_S3C64XX_DEV_SPI2 32#ifdef CONFIG_S3C64XX_DEV_SPI2
50struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { 33int s3c64xx_spi2_cfg_gpio(void)
51 .fifo_lvl_mask = 0x7f,
52 .rx_lvl_offset = 13,
53 .high_speed = 1,
54 .tx_st_done = 21,
55};
56
57int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
58{ 34{
59 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); 35 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
60 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); 36 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d50961d..fcdf52dbcc49 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
445 .ctrlbit = (1 << 11), 445 .ctrlbit = (1 << 11),
446 }, { 446 }, {
447 .name = "spi", 447 .name = "spi",
448 .devname = "s3c64xx-spi.0", 448 .devname = "s5pv210-spi.0",
449 .parent = &clk_pclk_psys.clk, 449 .parent = &clk_pclk_psys.clk,
450 .enable = s5pv210_clk_ip3_ctrl, 450 .enable = s5pv210_clk_ip3_ctrl,
451 .ctrlbit = (1<<12), 451 .ctrlbit = (1<<12),
452 }, { 452 }, {
453 .name = "spi", 453 .name = "spi",
454 .devname = "s3c64xx-spi.1", 454 .devname = "s5pv210-spi.1",
455 .parent = &clk_pclk_psys.clk, 455 .parent = &clk_pclk_psys.clk,
456 .enable = s5pv210_clk_ip3_ctrl, 456 .enable = s5pv210_clk_ip3_ctrl,
457 .ctrlbit = (1<<13), 457 .ctrlbit = (1<<13),
458 }, { 458 }, {
459 .name = "spi", 459 .name = "spi",
460 .devname = "s3c64xx-spi.2", 460 .devname = "s5pv210-spi.2",
461 .parent = &clk_pclk_psys.clk, 461 .parent = &clk_pclk_psys.clk,
462 .enable = s5pv210_clk_ip3_ctrl, 462 .enable = s5pv210_clk_ip3_ctrl,
463 .ctrlbit = (1<<14), 463 .ctrlbit = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
1035static struct clksrc_clk clk_sclk_spi0 = { 1035static struct clksrc_clk clk_sclk_spi0 = {
1036 .clk = { 1036 .clk = {
1037 .name = "sclk_spi", 1037 .name = "sclk_spi",
1038 .devname = "s3c64xx-spi.0", 1038 .devname = "s5pv210-spi.0",
1039 .enable = s5pv210_clk_mask0_ctrl, 1039 .enable = s5pv210_clk_mask0_ctrl,
1040 .ctrlbit = (1 << 16), 1040 .ctrlbit = (1 << 16),
1041 }, 1041 },
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
1047static struct clksrc_clk clk_sclk_spi1 = { 1047static struct clksrc_clk clk_sclk_spi1 = {
1048 .clk = { 1048 .clk = {
1049 .name = "sclk_spi", 1049 .name = "sclk_spi",
1050 .devname = "s3c64xx-spi.1", 1050 .devname = "s5pv210-spi.1",
1051 .enable = s5pv210_clk_mask0_ctrl, 1051 .enable = s5pv210_clk_mask0_ctrl,
1052 .ctrlbit = (1 << 17), 1052 .ctrlbit = (1 << 17),
1053 }, 1053 },
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1331 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1331 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1332 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), 1332 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1333 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 1333 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1334 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 1334 CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1335 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 1335 CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1336}; 1336};
1337 1337
1338void __init s5pv210_register_clocks(void) 1338void __init s5pv210_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index f43c5048a37d..81aecc162f82 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -9,20 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 13
17#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata = { 15int s3c64xx_spi0_cfg_gpio(void)
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .tx_st_done = 25,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{ 16{
27 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); 17 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
28 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); 18 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
@@ -33,14 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
33#endif 23#endif
34 24
35#ifdef CONFIG_S3C64XX_DEV_SPI1 25#ifdef CONFIG_S3C64XX_DEV_SPI1
36struct s3c64xx_spi_info s3c64xx_spi1_pdata = { 26int s3c64xx_spi1_cfg_gpio(void)
37 .fifo_lvl_mask = 0x7f,
38 .rx_lvl_offset = 15,
39 .high_speed = 1,
40 .tx_st_done = 25,
41};
42
43int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
44{ 27{
45 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); 28 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 8040345bd971..435f00ca3c58 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -7,4 +7,5 @@ dtb-$(CONFIG_MACH_PAZ00) += tegra20-paz00.dtb
7dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb 7dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb
8dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb 8dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb
9dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb 9dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb
10dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
10dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb 11dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 53d3d46dec12..c013bbf79cac 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -41,6 +41,7 @@ config MACH_HREFV60
41config MACH_SNOWBALL 41config MACH_SNOWBALL
42 bool "U8500 Snowball platform" 42 bool "U8500 Snowball platform"
43 select MACH_MOP500 43 select MACH_MOP500
44 select LEDS_GPIO
44 help 45 help
45 Include support for the snowball development platform. 46 Include support for the snowball development platform.
46 47
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 920251cf834c..18ff781cfbe4 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -80,7 +80,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
80}; 80};
81#endif 81#endif
82 82
83static struct mmci_platform_data mop500_sdi0_data = { 83struct mmci_platform_data mop500_sdi0_data = {
84 .ios_handler = mop500_sdi0_ios_handler, 84 .ios_handler = mop500_sdi0_ios_handler,
85 .ocr_mask = MMC_VDD_29_30, 85 .ocr_mask = MMC_VDD_29_30,
86 .f_max = 50000000, 86 .f_max = 50000000,
@@ -227,7 +227,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
227}; 227};
228#endif 228#endif
229 229
230static struct mmci_platform_data mop500_sdi4_data = { 230struct mmci_platform_data mop500_sdi4_data = {
231 .ocr_mask = MMC_VDD_29_30, 231 .ocr_mask = MMC_VDD_29_30,
232 .f_max = 50000000, 232 .f_max = 50000000,
233 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | 233 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 4fd93f5c49ec..84461fa2a3ba 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -58,7 +58,7 @@
58static struct gpio_led snowball_led_array[] = { 58static struct gpio_led snowball_led_array[] = {
59 { 59 {
60 .name = "user_led", 60 .name = "user_led",
61 .default_trigger = "none", 61 .default_trigger = "heartbeat",
62 .gpio = 142, 62 .gpio = 142,
63 }, 63 },
64}; 64};
@@ -331,43 +331,12 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
331 }, 331 },
332}; 332};
333 333
334#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm) \
335static struct nmk_i2c_controller u8500_i2c##id##_data = { \
336 /* \
337 * slave data setup time, which is \
338 * 250 ns,100ns,10ns which is 14,6,2 \
339 * respectively for a 48 Mhz \
340 * i2c clock \
341 */ \
342 .slsu = _slsu, \
343 /* Tx FIFO threshold */ \
344 .tft = _tft, \
345 /* Rx FIFO threshold */ \
346 .rft = _rft, \
347 /* std. mode operation */ \
348 .clk_freq = clk, \
349 /* Slave response timeout(ms) */\
350 .timeout = t_out, \
351 .sm = _sm, \
352}
353
354/*
355 * The board uses 4 i2c controllers, initialize all of
356 * them with slave data setup time of 250 ns,
357 * Tx & Rx FIFO threshold values as 8 and standard
358 * mode of operation
359 */
360U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
361U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
362U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
363U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
364
365static void __init mop500_i2c_init(struct device *parent) 334static void __init mop500_i2c_init(struct device *parent)
366{ 335{
367 db8500_add_i2c0(parent, &u8500_i2c0_data); 336 db8500_add_i2c0(parent, NULL);
368 db8500_add_i2c1(parent, &u8500_i2c1_data); 337 db8500_add_i2c1(parent, NULL);
369 db8500_add_i2c2(parent, &u8500_i2c2_data); 338 db8500_add_i2c2(parent, NULL);
370 db8500_add_i2c3(parent, &u8500_i2c3_data); 339 db8500_add_i2c3(parent, NULL);
371} 340}
372 341
373static struct gpio_keys_button mop500_gpio_keys[] = { 342static struct gpio_keys_button mop500_gpio_keys[] = {
@@ -776,6 +745,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
776 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 745 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
777 /* Requires DMA bindings. */ 746 /* Requires DMA bindings. */
778 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 747 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
748 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
749 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
779 /* Requires clock name bindings. */ 750 /* Requires clock name bindings. */
780 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), 751 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
781 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), 752 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
@@ -786,6 +757,11 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
786 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), 757 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
787 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), 758 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
788 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), 759 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
760 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
761 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
762 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
763 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
764 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
789 /* Requires device name bindings. */ 765 /* Requires device name bindings. */
790 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), 766 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
791 {}, 767 {},
@@ -820,8 +796,6 @@ static void __init u8500_init_machine(void)
820 796
821 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) 797 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
822 mop500_platform_devs[i]->dev.parent = parent; 798 mop500_platform_devs[i]->dev.parent = parent;
823 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
824 snowball_platform_devs[i]->dev.parent = parent;
825 799
826 /* automatically probe child nodes of db8500 device */ 800 /* automatically probe child nodes of db8500 device */
827 of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); 801 of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
@@ -840,18 +814,6 @@ static void __init u8500_init_machine(void)
840 814
841 mop500_uib_init(); 815 mop500_uib_init();
842 816
843 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
844 /*
845 * Devices to be DT:ed:
846 * snowball_led_dev = todo
847 * snowball_key_dev = todo
848 * snowball_sbnet_dev = done
849 * ab8500_device = done
850 */
851 platform_add_devices(snowball_of_platform_devs,
852 ARRAY_SIZE(snowball_of_platform_devs));
853
854 snowball_sdi_init(parent);
855 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { 817 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
856 /* 818 /*
857 * The HREFv60 board removed a GPIO expander and routed 819 * The HREFv60 board removed a GPIO expander and routed
@@ -873,7 +835,6 @@ static void __init u8500_init_machine(void)
873 835
874 mop500_uib_init(); 836 mop500_uib_init();
875 } 837 }
876 mop500_i2c_init(parent);
877 838
878 /* This board has full regulator constraints */ 839 /* This board has full regulator constraints */
879 regulator_has_full_constraints(); 840 regulator_has_full_constraints();
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 2f87b25a908a..b5bfc1a78b1a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
9 9
10/* For NOMADIK_NR_GPIO */ 10/* For NOMADIK_NR_GPIO */
11#include <mach/irqs.h> 11#include <mach/irqs.h>
12#include <linux/amba/mmci.h>
12 13
13/* Snowball specific GPIO assignments, this board has no GPIO expander */ 14/* Snowball specific GPIO assignments, this board has no GPIO expander */
14#define SNOWBALL_ACCEL_INT1_GPIO 163 15#define SNOWBALL_ACCEL_INT1_GPIO 163
@@ -78,6 +79,8 @@
78 79
79struct device; 80struct device;
80struct i2c_board_info; 81struct i2c_board_info;
82extern struct mmci_platform_data mop500_sdi0_data;
83extern struct mmci_platform_data mop500_sdi4_data;
81 84
82extern void mop500_sdi_init(struct device *parent); 85extern void mop500_sdi_init(struct device *parent);
83extern void snowball_sdi_init(struct device *parent); 86extern void snowball_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 33275eb4c689..c8dd94f606dc 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -139,7 +139,6 @@ static struct platform_device *platform_devs[] __initdata = {
139 139
140static struct platform_device *of_platform_devs[] __initdata = { 140static struct platform_device *of_platform_devs[] __initdata = {
141 &u8500_dma40_device, 141 &u8500_dma40_device,
142 &db8500_pmu_device,
143}; 142};
144 143
145static resource_size_t __initdata db8500_gpio_base[] = { 144static resource_size_t __initdata db8500_gpio_base[] = {
@@ -237,7 +236,6 @@ struct device * __init u8500_of_init_devices(void)
237 236
238 parent = db8500_soc_device_init(); 237 parent = db8500_soc_device_init();
239 238
240 db8500_add_rtc(parent);
241 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 239 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
242 240
243 platform_device_register_data(parent, 241 platform_device_register_data(parent,
@@ -249,7 +247,7 @@ struct device * __init u8500_of_init_devices(void)
249 /* 247 /*
250 * Devices to be DT:ed: 248 * Devices to be DT:ed:
251 * u8500_dma40_device = todo 249 * u8500_dma40_device = todo
252 * db8500_pmu_device = todo 250 * db8500_pmu_device = done
253 * db8500_prcmu_device = done 251 * db8500_prcmu_device = done
254 */ 252 */
255 platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); 253 platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1b814a..7cfcc44537f0 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -67,6 +67,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
67extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 67extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
68 unsigned long ckih1, unsigned long ckih2); 68 unsigned long ckih1, unsigned long ckih2);
69extern int mx27_clocks_init_dt(void); 69extern int mx27_clocks_init_dt(void);
70extern int mx31_clocks_init_dt(void);
70extern int mx51_clocks_init_dt(void); 71extern int mx51_clocks_init_dt(void);
71extern int mx53_clocks_init_dt(void); 72extern int mx53_clocks_init_dt(void);
72extern int mx6q_clocks_init(void); 73extern int mx6q_clocks_init(void);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 6303974c2ee0..74e31ce35538 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1513,7 +1513,7 @@ static struct resource s3c64xx_spi0_resource[] = {
1513}; 1513};
1514 1514
1515struct platform_device s3c64xx_device_spi0 = { 1515struct platform_device s3c64xx_device_spi0 = {
1516 .name = "s3c64xx-spi", 1516 .name = "s3c6410-spi",
1517 .id = 0, 1517 .id = 0,
1518 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), 1518 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1519 .resource = s3c64xx_spi0_resource, 1519 .resource = s3c64xx_spi0_resource,
@@ -1523,13 +1523,10 @@ struct platform_device s3c64xx_device_spi0 = {
1523 }, 1523 },
1524}; 1524};
1525 1525
1526void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, 1526void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1527 int src_clk_nr, int num_cs) 1527 int num_cs)
1528{ 1528{
1529 if (!pd) { 1529 struct s3c64xx_spi_info pd;
1530 pr_err("%s:Need to pass platform data\n", __func__);
1531 return;
1532 }
1533 1530
1534 /* Reject invalid configuration */ 1531 /* Reject invalid configuration */
1535 if (!num_cs || src_clk_nr < 0) { 1532 if (!num_cs || src_clk_nr < 0) {
@@ -1537,12 +1534,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1537 return; 1534 return;
1538 } 1535 }
1539 1536
1540 pd->num_cs = num_cs; 1537 pd.num_cs = num_cs;
1541 pd->src_clk_nr = src_clk_nr; 1538 pd.src_clk_nr = src_clk_nr;
1542 if (!pd->cfg_gpio) 1539 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
1543 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1544 1540
1545 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0); 1541 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
1546} 1542}
1547#endif /* CONFIG_S3C64XX_DEV_SPI0 */ 1543#endif /* CONFIG_S3C64XX_DEV_SPI0 */
1548 1544
@@ -1555,7 +1551,7 @@ static struct resource s3c64xx_spi1_resource[] = {
1555}; 1551};
1556 1552
1557struct platform_device s3c64xx_device_spi1 = { 1553struct platform_device s3c64xx_device_spi1 = {
1558 .name = "s3c64xx-spi", 1554 .name = "s3c6410-spi",
1559 .id = 1, 1555 .id = 1,
1560 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), 1556 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1561 .resource = s3c64xx_spi1_resource, 1557 .resource = s3c64xx_spi1_resource,
@@ -1565,26 +1561,20 @@ struct platform_device s3c64xx_device_spi1 = {
1565 }, 1561 },
1566}; 1562};
1567 1563
1568void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, 1564void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1569 int src_clk_nr, int num_cs) 1565 int num_cs)
1570{ 1566{
1571 if (!pd) {
1572 pr_err("%s:Need to pass platform data\n", __func__);
1573 return;
1574 }
1575
1576 /* Reject invalid configuration */ 1567 /* Reject invalid configuration */
1577 if (!num_cs || src_clk_nr < 0) { 1568 if (!num_cs || src_clk_nr < 0) {
1578 pr_err("%s: Invalid SPI configuration\n", __func__); 1569 pr_err("%s: Invalid SPI configuration\n", __func__);
1579 return; 1570 return;
1580 } 1571 }
1581 1572
1582 pd->num_cs = num_cs; 1573 pd.num_cs = num_cs;
1583 pd->src_clk_nr = src_clk_nr; 1574 pd.src_clk_nr = src_clk_nr;
1584 if (!pd->cfg_gpio) 1575 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
1585 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1586 1576
1587 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1); 1577 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
1588} 1578}
1589#endif /* CONFIG_S3C64XX_DEV_SPI1 */ 1579#endif /* CONFIG_S3C64XX_DEV_SPI1 */
1590 1580
@@ -1597,7 +1587,7 @@ static struct resource s3c64xx_spi2_resource[] = {
1597}; 1587};
1598 1588
1599struct platform_device s3c64xx_device_spi2 = { 1589struct platform_device s3c64xx_device_spi2 = {
1600 .name = "s3c64xx-spi", 1590 .name = "s3c6410-spi",
1601 .id = 2, 1591 .id = 2,
1602 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), 1592 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1603 .resource = s3c64xx_spi2_resource, 1593 .resource = s3c64xx_spi2_resource,
@@ -1607,13 +1597,10 @@ struct platform_device s3c64xx_device_spi2 = {
1607 }, 1597 },
1608}; 1598};
1609 1599
1610void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, 1600void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
1611 int src_clk_nr, int num_cs) 1601 int num_cs)
1612{ 1602{
1613 if (!pd) { 1603 struct s3c64xx_spi_info pd;
1614 pr_err("%s:Need to pass platform data\n", __func__);
1615 return;
1616 }
1617 1604
1618 /* Reject invalid configuration */ 1605 /* Reject invalid configuration */
1619 if (!num_cs || src_clk_nr < 0) { 1606 if (!num_cs || src_clk_nr < 0) {
@@ -1621,11 +1608,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1621 return; 1608 return;
1622 } 1609 }
1623 1610
1624 pd->num_cs = num_cs; 1611 pd.num_cs = num_cs;
1625 pd->src_clk_nr = src_clk_nr; 1612 pd.src_clk_nr = src_clk_nr;
1626 if (!pd->cfg_gpio) 1613 pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
1627 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1628 1614
1629 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2); 1615 s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
1630} 1616}
1631#endif /* CONFIG_S3C64XX_DEV_SPI2 */ 1617#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index fa95e9a00972..ceba18d23a5a 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -18,7 +18,6 @@ struct platform_device;
18 * @fb_delay: Slave specific feedback delay. 18 * @fb_delay: Slave specific feedback delay.
19 * Refer to FB_CLK_SEL register definition in SPI chapter. 19 * Refer to FB_CLK_SEL register definition in SPI chapter.
20 * @line: Custom 'identity' of the CS line. 20 * @line: Custom 'identity' of the CS line.
21 * @set_level: CS line control.
22 * 21 *
23 * This is per SPI-Slave Chipselect information. 22 * This is per SPI-Slave Chipselect information.
24 * Allocate and initialize one in machine init code and make the 23 * Allocate and initialize one in machine init code and make the
@@ -27,57 +26,41 @@ struct platform_device;
27struct s3c64xx_spi_csinfo { 26struct s3c64xx_spi_csinfo {
28 u8 fb_delay; 27 u8 fb_delay;
29 unsigned line; 28 unsigned line;
30 void (*set_level)(unsigned line_id, int lvl);
31}; 29};
32 30
33/** 31/**
34 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
35 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
36 * @clk_from_cmu: If the SPI clock/prescalar control block is present
37 * by the platform's clock-management-unit and not in SPI controller.
38 * @num_cs: Number of CS this controller emulates. 34 * @num_cs: Number of CS this controller emulates.
39 * @cfg_gpio: Configure pins for this SPI controller. 35 * @cfg_gpio: Configure pins for this SPI controller.
40 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
41 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
42 * @high_speed: If the controller supports HIGH_SPEED_EN bit
43 * @tx_st_done: Depends on tx fifo_lvl field
44 */ 36 */
45struct s3c64xx_spi_info { 37struct s3c64xx_spi_info {
46 int src_clk_nr; 38 int src_clk_nr;
47 bool clk_from_cmu;
48
49 int num_cs; 39 int num_cs;
50 40 int (*cfg_gpio)(void);
51 int (*cfg_gpio)(struct platform_device *pdev);
52
53 /* Following two fields are for future compatibility */
54 int fifo_lvl_mask;
55 int rx_lvl_offset;
56 int high_speed;
57 int tx_st_done;
58}; 41};
59 42
60/** 43/**
61 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board 44 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
62 * initialization code. 45 * initialization code.
63 * @pd: SPI platform data to set. 46 * @cfg_gpio: Pointer to gpio setup function.
64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 47 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array. 48 * @num_cs: Number of elements in the 'cs' array.
66 * 49 *
67 * Call this from machine init code for each SPI Controller that 50 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it. 51 * has some chips attached to it.
69 */ 52 */
70extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, 53extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
71 int src_clk_nr, int num_cs); 54 int num_cs);
72extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, 55extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
73 int src_clk_nr, int num_cs); 56 int num_cs);
74extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, 57extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
75 int src_clk_nr, int num_cs); 58 int num_cs);
76 59
77/* defined by architecture to configure gpio */ 60/* defined by architecture to configure gpio */
78extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); 61extern int s3c64xx_spi0_cfg_gpio(void);
79extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); 62extern int s3c64xx_spi1_cfg_gpio(void);
80extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); 63extern int s3c64xx_spi2_cfg_gpio(void);
81 64
82extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; 65extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
83extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; 66extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 17:56:56 -0500