Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into sh/for-2.6.33

5 files changed, 358 insertions, 116 deletions

diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index c74fc93d7d15..2c4cbe8ee6b7 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -18,40 +18,45 @@
 #define gpio_to_irq     __gpio_to_irq
 
 /* GPIO bank sizes */
-#define S5PC1XX_GPIO_A0_NR      (8)
-#define S5PC1XX_GPIO_A1_NR      (5)
-#define S5PC1XX_GPIO_B_NR       (8)
-#define S5PC1XX_GPIO_C_NR       (5)
-#define S5PC1XX_GPIO_D_NR       (7)
-#define S5PC1XX_GPIO_E0_NR      (8)
-#define S5PC1XX_GPIO_E1_NR      (6)
-#define S5PC1XX_GPIO_F0_NR      (8)
-#define S5PC1XX_GPIO_F1_NR      (8)
-#define S5PC1XX_GPIO_F2_NR      (8)
-#define S5PC1XX_GPIO_F3_NR      (4)
-#define S5PC1XX_GPIO_G0_NR      (8)
-#define S5PC1XX_GPIO_G1_NR      (3)
-#define S5PC1XX_GPIO_G2_NR      (7)
-#define S5PC1XX_GPIO_G3_NR      (7)
-#define S5PC1XX_GPIO_H0_NR      (8)
-#define S5PC1XX_GPIO_H1_NR      (8)
-#define S5PC1XX_GPIO_H2_NR      (8)
-#define S5PC1XX_GPIO_H3_NR      (8)
-#define S5PC1XX_GPIO_I_NR       (8)
-#define S5PC1XX_GPIO_J0_NR      (8)
-#define S5PC1XX_GPIO_J1_NR      (5)
-#define S5PC1XX_GPIO_J2_NR      (8)
-#define S5PC1XX_GPIO_J3_NR      (8)
-#define S5PC1XX_GPIO_J4_NR      (4)
-#define S5PC1XX_GPIO_K0_NR      (8)
-#define S5PC1XX_GPIO_K1_NR      (6)
-#define S5PC1XX_GPIO_K2_NR      (8)
-#define S5PC1XX_GPIO_K3_NR      (8)
-#define S5PC1XX_GPIO_MP00_NR    (8)
-#define S5PC1XX_GPIO_MP01_NR    (8)
-#define S5PC1XX_GPIO_MP02_NR    (8)
-#define S5PC1XX_GPIO_MP03_NR    (8)
-#define S5PC1XX_GPIO_MP04_NR    (5)
+#define S5PC100_GPIO_A0_NR      (8)
+#define S5PC100_GPIO_A1_NR      (5)
+#define S5PC100_GPIO_B_NR       (8)
+#define S5PC100_GPIO_C_NR       (5)
+#define S5PC100_GPIO_D_NR       (7)
+#define S5PC100_GPIO_E0_NR      (8)
+#define S5PC100_GPIO_E1_NR      (6)
+#define S5PC100_GPIO_F0_NR      (8)
+#define S5PC100_GPIO_F1_NR      (8)
+#define S5PC100_GPIO_F2_NR      (8)
+#define S5PC100_GPIO_F3_NR      (4)
+#define S5PC100_GPIO_G0_NR      (8)
+#define S5PC100_GPIO_G1_NR      (3)
+#define S5PC100_GPIO_G2_NR      (7)
+#define S5PC100_GPIO_G3_NR      (7)
+#define S5PC100_GPIO_H0_NR      (8)
+#define S5PC100_GPIO_H1_NR      (8)
+#define S5PC100_GPIO_H2_NR      (8)
+#define S5PC100_GPIO_H3_NR      (8)
+#define S5PC100_GPIO_I_NR       (8)
+#define S5PC100_GPIO_J0_NR      (8)
+#define S5PC100_GPIO_J1_NR      (5)
+#define S5PC100_GPIO_J2_NR      (8)
+#define S5PC100_GPIO_J3_NR      (8)
+#define S5PC100_GPIO_J4_NR      (4)
+#define S5PC100_GPIO_K0_NR      (8)
+#define S5PC100_GPIO_K1_NR      (6)
+#define S5PC100_GPIO_K2_NR      (8)
+#define S5PC100_GPIO_K3_NR      (8)
+#define S5PC100_GPIO_L0_NR      (8)
+#define S5PC100_GPIO_L1_NR      (8)
+#define S5PC100_GPIO_L2_NR      (8)
+#define S5PC100_GPIO_L3_NR      (8)
+#define S5PC100_GPIO_L4_NR      (8)
+#define S5PC100_GPIO_MP00_NR    (8)
+#define S5PC100_GPIO_MP01_NR    (8)
+#define S5PC100_GPIO_MP02_NR    (8)
+#define S5PC100_GPIO_MP03_NR    (8)
+#define S5PC100_GPIO_MP04_NR    (5)
 
 /* GPIO bank numbes */
 
@@ -64,83 +69,94 @@
         ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
 
 enum s3c_gpio_number {
-        S5PC1XX_GPIO_A0_START   = 0,
-        S5PC1XX_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
-        S5PC1XX_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
-        S5PC1XX_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
-        S5PC1XX_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
-        S5PC1XX_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
-        S5PC1XX_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
-        S5PC1XX_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
-        S5PC1XX_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
-        S5PC1XX_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
-        S5PC1XX_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
-        S5PC1XX_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
-        S5PC1XX_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
-        S5PC1XX_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
-        S5PC1XX_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
-        S5PC1XX_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
-        S5PC1XX_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
-        S5PC1XX_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
-        S5PC1XX_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
-        S5PC1XX_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
-        S5PC1XX_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
-        S5PC1XX_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
-        S5PC1XX_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
-        S5PC1XX_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
-        S5PC1XX_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
-        S5PC1XX_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
-        S5PC1XX_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
-        S5PC1XX_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
-        S5PC1XX_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
-        S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
-        S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
-        S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
-        S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
-        S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
+        S5PC100_GPIO_A0_START   = 0,
+        S5PC100_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
+        S5PC100_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
+        S5PC100_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
+        S5PC100_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
+        S5PC100_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
+        S5PC100_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
+        S5PC100_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
+        S5PC100_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
+        S5PC100_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
+        S5PC100_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
+        S5PC100_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
+        S5PC100_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
+        S5PC100_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
+        S5PC100_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
+        S5PC100_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
+        S5PC100_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
+        S5PC100_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
+        S5PC100_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
+        S5PC100_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
+        S5PC100_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
+        S5PC100_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
+        S5PC100_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
+        S5PC100_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
+        S5PC100_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
+        S5PC100_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
+        S5PC100_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
+        S5PC100_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
+        S5PC100_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
+        S5PC100_GPIO_L0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
+        S5PC100_GPIO_L1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
+        S5PC100_GPIO_L2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
+        S5PC100_GPIO_L3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
+        S5PC100_GPIO_L4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
+        S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
+        S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
+        S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
+        S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
+        S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
+        S5PC100_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
 };
 
-/* S5PC1XX GPIO number definitions. */
-#define S5PC1XX_GPA0(_nr)       (S5PC1XX_GPIO_A0_START + (_nr))
-#define S5PC1XX_GPA1(_nr)       (S5PC1XX_GPIO_A1_START + (_nr))
-#define S5PC1XX_GPB(_nr)        (S5PC1XX_GPIO_B_START + (_nr))
-#define S5PC1XX_GPC(_nr)        (S5PC1XX_GPIO_C_START + (_nr))
-#define S5PC1XX_GPD(_nr)        (S5PC1XX_GPIO_D_START + (_nr))
-#define S5PC1XX_GPE0(_nr)       (S5PC1XX_GPIO_E0_START + (_nr))
-#define S5PC1XX_GPE1(_nr)       (S5PC1XX_GPIO_E1_START + (_nr))
-#define S5PC1XX_GPF0(_nr)       (S5PC1XX_GPIO_F0_START + (_nr))
-#define S5PC1XX_GPF1(_nr)       (S5PC1XX_GPIO_F1_START + (_nr))
-#define S5PC1XX_GPF2(_nr)       (S5PC1XX_GPIO_F2_START + (_nr))
-#define S5PC1XX_GPF3(_nr)       (S5PC1XX_GPIO_F3_START + (_nr))
-#define S5PC1XX_GPG0(_nr)       (S5PC1XX_GPIO_G0_START + (_nr))
-#define S5PC1XX_GPG1(_nr)       (S5PC1XX_GPIO_G1_START + (_nr))
-#define S5PC1XX_GPG2(_nr)       (S5PC1XX_GPIO_G2_START + (_nr))
-#define S5PC1XX_GPG3(_nr)       (S5PC1XX_GPIO_G3_START + (_nr))
-#define S5PC1XX_GPH0(_nr)       (S5PC1XX_GPIO_H0_START + (_nr))
-#define S5PC1XX_GPH1(_nr)       (S5PC1XX_GPIO_H1_START + (_nr))
-#define S5PC1XX_GPH2(_nr)       (S5PC1XX_GPIO_H2_START + (_nr))
-#define S5PC1XX_GPH3(_nr)       (S5PC1XX_GPIO_H3_START + (_nr))
-#define S5PC1XX_GPI(_nr)        (S5PC1XX_GPIO_I_START + (_nr))
-#define S5PC1XX_GPJ0(_nr)       (S5PC1XX_GPIO_J0_START + (_nr))
-#define S5PC1XX_GPJ1(_nr)       (S5PC1XX_GPIO_J1_START + (_nr))
-#define S5PC1XX_GPJ2(_nr)       (S5PC1XX_GPIO_J2_START + (_nr))
-#define S5PC1XX_GPJ3(_nr)       (S5PC1XX_GPIO_J3_START + (_nr))
-#define S5PC1XX_GPJ4(_nr)       (S5PC1XX_GPIO_J4_START + (_nr))
-#define S5PC1XX_GPK0(_nr)       (S5PC1XX_GPIO_K0_START + (_nr))
-#define S5PC1XX_GPK1(_nr)       (S5PC1XX_GPIO_K1_START + (_nr))
-#define S5PC1XX_GPK2(_nr)       (S5PC1XX_GPIO_K2_START + (_nr))
-#define S5PC1XX_GPK3(_nr)       (S5PC1XX_GPIO_K3_START + (_nr))
-#define S5PC1XX_MP00(_nr)       (S5PC1XX_GPIO_MP00_START + (_nr))
-#define S5PC1XX_MP01(_nr)       (S5PC1XX_GPIO_MP01_START + (_nr))
-#define S5PC1XX_MP02(_nr)       (S5PC1XX_GPIO_MP02_START + (_nr))
-#define S5PC1XX_MP03(_nr)       (S5PC1XX_GPIO_MP03_START + (_nr))
-#define S5PC1XX_MP04(_nr)       (S5PC1XX_GPIO_MP04_START + (_nr))
+/* S5PC100 GPIO number definitions. */
+#define S5PC100_GPA0(_nr)       (S5PC100_GPIO_A0_START + (_nr))
+#define S5PC100_GPA1(_nr)       (S5PC100_GPIO_A1_START + (_nr))
+#define S5PC100_GPB(_nr)        (S5PC100_GPIO_B_START + (_nr))
+#define S5PC100_GPC(_nr)        (S5PC100_GPIO_C_START + (_nr))
+#define S5PC100_GPD(_nr)        (S5PC100_GPIO_D_START + (_nr))
+#define S5PC100_GPE0(_nr)       (S5PC100_GPIO_E0_START + (_nr))
+#define S5PC100_GPE1(_nr)       (S5PC100_GPIO_E1_START + (_nr))
+#define S5PC100_GPF0(_nr)       (S5PC100_GPIO_F0_START + (_nr))
+#define S5PC100_GPF1(_nr)       (S5PC100_GPIO_F1_START + (_nr))
+#define S5PC100_GPF2(_nr)       (S5PC100_GPIO_F2_START + (_nr))
+#define S5PC100_GPF3(_nr)       (S5PC100_GPIO_F3_START + (_nr))
+#define S5PC100_GPG0(_nr)       (S5PC100_GPIO_G0_START + (_nr))
+#define S5PC100_GPG1(_nr)       (S5PC100_GPIO_G1_START + (_nr))
+#define S5PC100_GPG2(_nr)       (S5PC100_GPIO_G2_START + (_nr))
+#define S5PC100_GPG3(_nr)       (S5PC100_GPIO_G3_START + (_nr))
+#define S5PC100_GPH0(_nr)       (S5PC100_GPIO_H0_START + (_nr))
+#define S5PC100_GPH1(_nr)       (S5PC100_GPIO_H1_START + (_nr))
+#define S5PC100_GPH2(_nr)       (S5PC100_GPIO_H2_START + (_nr))
+#define S5PC100_GPH3(_nr)       (S5PC100_GPIO_H3_START + (_nr))
+#define S5PC100_GPI(_nr)        (S5PC100_GPIO_I_START + (_nr))
+#define S5PC100_GPJ0(_nr)       (S5PC100_GPIO_J0_START + (_nr))
+#define S5PC100_GPJ1(_nr)       (S5PC100_GPIO_J1_START + (_nr))
+#define S5PC100_GPJ2(_nr)       (S5PC100_GPIO_J2_START + (_nr))
+#define S5PC100_GPJ3(_nr)       (S5PC100_GPIO_J3_START + (_nr))
+#define S5PC100_GPJ4(_nr)       (S5PC100_GPIO_J4_START + (_nr))
+#define S5PC100_GPK0(_nr)       (S5PC100_GPIO_K0_START + (_nr))
+#define S5PC100_GPK1(_nr)       (S5PC100_GPIO_K1_START + (_nr))
+#define S5PC100_GPK2(_nr)       (S5PC100_GPIO_K2_START + (_nr))
+#define S5PC100_GPK3(_nr)       (S5PC100_GPIO_K3_START + (_nr))
+#define S5PC100_GPL0(_nr)       (S5PC100_GPIO_L0_START + (_nr))
+#define S5PC100_GPL1(_nr)       (S5PC100_GPIO_L1_START + (_nr))
+#define S5PC100_GPL2(_nr)       (S5PC100_GPIO_L2_START + (_nr))
+#define S5PC100_GPL3(_nr)       (S5PC100_GPIO_L3_START + (_nr))
+#define S5PC100_GPL4(_nr)       (S5PC100_GPIO_L4_START + (_nr))
+#define S5PC100_MP00(_nr)       (S5PC100_GPIO_MP00_START + (_nr))
+#define S5PC100_MP01(_nr)       (S5PC100_GPIO_MP01_START + (_nr))
+#define S5PC100_MP02(_nr)       (S5PC100_GPIO_MP02_START + (_nr))
+#define S5PC100_MP03(_nr)       (S5PC100_GPIO_MP03_START + (_nr))
+#define S5PC100_MP04(_nr)       (S5PC100_GPIO_MP04_START + (_nr))
+#define S5PC100_MP05(_nr)       (S5PC100_GPIO_MP05_START + (_nr))
 
-/* the end of the S5PC1XX specific gpios */
-#define S5PC1XX_GPIO_END        (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
-#define S3C_GPIO_END            S5PC1XX_GPIO_END
+/* It used the end of the S5PC1XX gpios */
+#define S3C_GPIO_END            S5PC100_GPIO_END
 
 /* define the number of gpios we need to the one after the MP04() range */
-#define ARCH_NR_GPIOS   (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
 
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 622720dba289..b53fa48a52c6 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,4 +11,9 @@
 
 #include <plat/irqs.h>
 
+/* LCD */
+#define IRQ_LCD_FIFO            IRQ_LCD0
+#define IRQ_LCD_VSYNC           IRQ_LCD1
+#define IRQ_LCD_SYSTEM          IRQ_LCD2
+
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 9e9f39130b2c..4681ebe8bef6 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -17,6 +17,19 @@
 
 #include <plat/map-base.h>
 
+/*
+ * map-base.h has already defined virtual memory address
+ * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
+ * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
+ * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
+ * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
+ * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
+ * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
+ *
+ * S5PC100 specific virtual memory address can be defined here
+ * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
+ *
+ */
 
 /* Chip ID */
 #define S5PC100_PA_CHIPID       (0xE0000000)
@@ -24,13 +37,20 @@
 #define S5PC1XX_VA_CHIPID       S3C_VA_SYS
 
 /* System */
-#define S5PC100_PA_SYS          (0xE0100000)
-#define S5PC100_PA_CLK          (S5PC100_PA_SYS + 0x0)
-#define S5PC100_PA_PWR          (S5PC100_PA_SYS + 0x8000)
+#define S5PC100_PA_CLK          (0xE0100000)
+#define S5PC100_PA_CLK_OTHER    (0xE0200000)
+#define S5PC100_PA_PWR          (0xE0108000)
 #define S5PC1XX_PA_CLK          S5PC100_PA_CLK
 #define S5PC1XX_PA_PWR          S5PC100_PA_PWR
+#define S5PC1XX_PA_CLK_OTHER    S5PC100_PA_CLK_OTHER
 #define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
 #define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
+#define S5PC1XX_VA_CLK_OTHER    (S3C_VA_SYS + 0x30000)
+
+/* GPIO */
+#define S5PC100_PA_GPIO         (0xE0300000)
+#define S5PC1XX_PA_GPIO         S5PC100_PA_GPIO
+#define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 
 /* Interrupt */
 #define S5PC100_PA_VIC          (0xE4000000)
@@ -40,23 +60,64 @@
 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
 
+/* DMA */
+#define S5PC100_PA_MDMA         (0xE8100000)
+#define S5PC100_PA_PDMA0        (0xE9000000)
+#define S5PC100_PA_PDMA1        (0xE9200000)
+
 /* Timer */
 #define S5PC100_PA_TIMER        (0xEA000000)
 #define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
 #define S5PC1XX_VA_TIMER        S3C_VA_TIMER
 
+/* RTC */
+#define S5PC100_PA_RTC          (0xEA300000)
+
 /* UART */
 #define S5PC100_PA_UART         (0xEC000000)
 #define S5PC1XX_PA_UART         S5PC100_PA_UART
 #define S5PC1XX_VA_UART         S3C_VA_UART
 
-/* IIC */
-#define S5PC100_PA_IIC          (0xEC100000)
+/* I2C */
+#define S5PC100_PA_I2C          (0xEC100000)
+#define S5PC100_PA_I2C1         (0xEC200000)
+
+/* USB HS OTG */
+#define S5PC100_PA_USB_HSOTG    (0xED200000)
+#define S5PC100_PA_USB_HSPHY    (0xED300000)
+
+/* SD/MMC */
+#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+#define S5PC100_PA_HSMMC0       S5PC100_PA_HSMMC(0)
+#define S5PC100_PA_HSMMC1       S5PC100_PA_HSMMC(1)
+#define S5PC100_PA_HSMMC2       S5PC100_PA_HSMMC(2)
+
+/* LCD */
+#define S5PC100_PA_FB           (0xEE000000)
+
+/* Multimedia */
+#define S5PC100_PA_G2D          (0xEE800000)
+#define S5PC100_PA_JPEG         (0xEE500000)
+#define S5PC100_PA_ROTATOR      (0xEE100000)
+#define S5PC100_PA_G3D          (0xEF000000)
+
+/* I2S */
+#define S5PC100_PA_I2S0         (0xF2000000)
+#define S5PC100_PA_I2S1         (0xF2100000)
+#define S5PC100_PA_I2S2         (0xF2200000)
+
+/* KEYPAD */
+#define S5PC100_PA_KEYPAD       (0xF3100000)
+
+/* ADC & TouchScreen */
+#define S5PC100_PA_TSADC        (0xF3000000)
 
 /* ETC */
 #define S5PC100_PA_SDRAM        (0x20000000)
+#define S5PC1XX_PA_SDRAM        S5PC100_PA_SDRAM
 
 /* compatibility defines. */
+#define S3C_PA_RTC              S5PC100_PA_RTC
 #define S3C_PA_UART             S5PC100_PA_UART
 #define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
 #define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
@@ -67,9 +128,23 @@
 #define S3C_VA_UART2            (S3C_VA_UART + 0x800)
 #define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
 #define S3C_UART_OFFSET         0x400
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S3C_PA_FB               S5PC100_PA_FB
+#define S3C_PA_G2D              S5PC100_PA_G2D
+#define S3C_PA_G3D              S5PC100_PA_G3D
+#define S3C_PA_JPEG             S5PC100_PA_JPEG
+#define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
 #define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
-#define S3C_PA_IIC              S5PC100_PA_IIC
+#define S3C_PA_IIC              S5PC100_PA_I2C
+#define S3C_PA_IIC1             S5PC100_PA_I2C1
+#define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
+#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC0
+#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC1
+#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC2
+#define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
+#define S3C_PA_TSADC            S5PC100_PA_TSADC
 
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
new file mode 100644
index 000000000000..1732cd28c765
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -0,0 +1,139 @@
+/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *   Pawel Osciak <p.osciak@samsung.com>
+ *
+ * Framebuffer register definitions for Samsung S5PC100.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_FB_H
+#define __ASM_ARCH_REGS_FB_H __FILE__
+
+#include <plat/regs-fb-v4.h>
+
+/* VP1 interface timing control */
+#define VP1CON0                                         (0x118)
+#define VP1_RATECON_EN                                  (1 << 31)
+#define VP1_CLKRATE_MASK                                (0xff)
+
+#define VP1CON1                                         (0x11c)
+#define VP1_VTREGCON_EN                                 (1 << 31)
+#define VP1_VBPD_MASK                                   (0xfff)
+#define VP1_VBPD_SHIFT                                  (16)
+
+
+#define WPALCON_H                                       (0x19c)
+#define WPALCON_L                                       (0x1a0)
+
+/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
+ * different for WPAL2-4
+ */
+/* In WPALCON_L (aka WPALCON) */
+#define WPALCON_W1PAL_32BPP_A888                        (0x7 << 3)
+#define WPALCON_W0PAL_32BPP_A888                        (0x7 << 0)
+
+/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
+ * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
+ */
+#define WPALCON_L_WxPAL_L_MASK                          (0x1)
+#define WPALCON_L_W2PAL_L_SHIFT                         (6)
+#define WPALCON_L_W3PAL_L_SHIFT                         (7)
+#define WPALCON_L_W4PAL_L_SHIFT                         (8)
+
+#define WPALCON_L_WxPAL_H_MASK                          (0x3)
+#define WPALCON_H_W2PAL_H_SHIFT                         (9)
+#define WPALCON_H_W3PAL_H_SHIFT                         (13)
+#define WPALCON_H_W4PAL_H_SHIFT                         (17)
+
+/* Per-window alpha value registers */
+/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
+ * for windows 1-4 alpha values consist of two parts, the 4 low bits are
+ * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
+ * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
+ */
+#define VIDWxALPHA0(_win)                               (0x200 + (_win * 8))
+#define VIDWxALPHA1(_win)                               (0x204 + (_win * 8))
+
+/* Only for window 0 in VIDW0ALPHAx. */
+#define VIDW0ALPHAx_R(_x)                               ((_x) << 16)
+#define VIDW0ALPHAx_R_MASK                              (0xff << 16)
+#define VIDW0ALPHAx_R_SHIFT                             (16)
+#define VIDW0ALPHAx_G(_x)                               ((_x) << 8)
+#define VIDW0ALPHAx_G_MASK                              (0xff << 8)
+#define VIDW0ALPHAx_G_SHIFT                             (8)
+#define VIDW0ALPHAx_B(_x)                               ((_x) << 0)
+#define VIDW0ALPHAx_B_MASK                              (0xff << 0)
+#define VIDW0ALPHAx_B_SHIFT                             (0)
+
+/* Low 4 bits of alpha0-1 for windows 1-4 */
+#define VIDW14ALPHAx_R_L(_x)                            ((_x) << 16)
+#define VIDW14ALPHAx_R_L_MASK                           (0xf << 16)
+#define VIDW14ALPHAx_R_L_SHIFT                          (16)
+#define VIDW14ALPHAx_G_L(_x)                            ((_x) << 8)
+#define VIDW14ALPHAx_G_L_MASK                           (0xf << 8)
+#define VIDW14ALPHAx_G_L_SHIFT                          (8)
+#define VIDW14ALPHAx_B_L(_x)                            ((_x) << 0)
+#define VIDW14ALPHAx_B_L_MASK                           (0xf << 0)
+#define VIDW14ALPHAx_B_L_SHIFT                          (0)
+
+
+/* Per-window blending equation control registers */
+#define BLENDEQx(_win)                                  (0x244 + ((_win) * 4))
+#define BLENDEQ1                                        (0x244)
+#define BLENDEQ2                                        (0x248)
+#define BLENDEQ3                                        (0x24c)
+#define BLENDEQ4                                        (0x250)
+
+#define BLENDEQx_Q_FUNC(_x)                             ((_x) << 18)
+#define BLENDEQx_Q_FUNC_MASK                            (0xf << 18)
+#define BLENDEQx_P_FUNC(_x)                             ((_x) << 12)
+#define BLENDEQx_P_FUNC_MASK                            (0xf << 12)
+#define BLENDEQx_B_FUNC(_x)                             ((_x) << 6)
+#define BLENDEQx_B_FUNC_MASK                            (0xf << 6)
+#define BLENDEQx_A_FUNC(_x)                             ((_x) << 0)
+#define BLENDEQx_A_FUNC_MASK                            (0xf << 0)
+
+#define BLENDCON                                        (0x260)
+#define BLENDCON_8BIT_ALPHA                             (1 << 0)
+
+/* Per-window palette base addresses (start of palette memory).
+ * Each window palette area consists of 256 32-bit entries.
+ * START is the first address (entry 0th), END is the address of 255th entry.
+ */
+#define WIN0_PAL_BASE                                   (0x2400)
+#define WIN0_PAL_END                                    (0x27fc)
+#define WIN1_PAL_BASE                                   (0x2800)
+#define WIN1_PAL_END                                    (0x2bfc)
+#define WIN2_PAL_BASE                                   (0x2c00)
+#define WIN2_PAL_END                                    (0x2ffc)
+#define WIN3_PAL_BASE                                   (0x3000)
+#define WIN3_PAL_END                                    (0x33fc)
+#define WIN4_PAL_BASE                                   (0x3400)
+#define WIN4_PAL_END                                    (0x37fc)
+
+#define WIN0_PAL(_entry)                        (WIN0_PAL_BASE + ((_entry) * 4))
+#define WIN1_PAL(_entry)                        (WIN1_PAL_BASE + ((_entry) * 4))
+#define WIN2_PAL(_entry)                        (WIN2_PAL_BASE + ((_entry) * 4))
+#define WIN3_PAL(_entry)                        (WIN3_PAL_BASE + ((_entry) * 4))
+#define WIN4_PAL(_entry)                        (WIN4_PAL_BASE + ((_entry) * 4))
+
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+        switch (window) {
+        case 0: return WIN0_PAL(reg);
+        case 1: return WIN1_PAL(reg);
+        case 2: return WIN2_PAL(reg);
+        case 3: return WIN3_PAL(reg);
+        case 4: return WIN4_PAL(reg);
+        }
+
+        BUG();
+}
+
+
+#endif /* __ASM_ARCH_REGS_FB_H */
+
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index e39014375470..f0d31a2a598c 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,14 +11,21 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
 
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+
+void (*s5pc1xx_idle)(void);
+
 static void arch_idle(void)
 {
-        /* nothing here yet */
+        if (s5pc1xx_idle)
+                s5pc1xx_idle();
 }
 
 static void arch_reset(char mode, const char *cmd)
 {
-        /* nothing here yet */
+        __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
+        return;
 }
-
 #endif /* __ASM_ARCH_IRQ_H */