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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 17:58:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 17:58:40 -0500
commitb274776c54c320763bc12eb035c0e244f76ccb43 (patch)
treec75b70d0824a7ae029229b19d61884039abf2127 /arch/arm/mach-s5p64x0
parentb24174b0cbbe383c5bb6097aeb24480b8fd2d338 (diff)
parent3b1209e7994c4d31ff9932a7f566ae1c96b3c443 (diff)
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann: "A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code." * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits) ARM: mvebu: correct gated clock documentation ARM: kirkwood: add missing include for nsa310 ARM: exynos: move exynos4210-combiner to drivers/irqchip mfd: db8500-prcmu: update resource passing drivers/db8500-cpufreq: delete dangling include ARM: at91: remove NEOCORE 926 board sunxi: Cleanup the reset code and add meaningful registers defines ARM: S3C24XX: header mach/regs-mem.h local ARM: S3C24XX: header mach/regs-power.h local ARM: S3C24XX: header mach/regs-s3c2412-mem.h local ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/ ARM: S3C24XX: transform s3c2443 subirqs into new structure ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs ARM: S3C24XX: move s3c2443 irq code to irq.c ARM: S3C24XX: transform s3c2416 irqs into new structure ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs ARM: S3C24XX: move s3c2416 irq init to common irq code ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property ARM: S3C24XX: Move irq syscore-ops to irq-pm clocksource: always define CLOCKSOURCE_OF_DECLARE ...
Diffstat (limited to 'arch/arm/mach-s5p64x0')
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c2
-rw-r--r--arch/arm/mach-s5p64x0/clock.h (renamed from arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h)9
-rw-r--r--arch/arm/mach-s5p64x0/gpiolib.c508
-rw-r--r--arch/arm/mach-s5p64x0/i2c.h (renamed from arch/arm/mach-s5p64x0/include/mach/i2c.h)3
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-irq.h1
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/tick.h29
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/uncompress.h28
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c6
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c6
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c0.c2
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c1.c2
12 files changed, 13 insertions, 585 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 5112371079d0..3537815247f1 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -23,7 +23,6 @@
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/map.h> 24#include <mach/map.h>
25#include <mach/regs-clock.h> 25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27 26
28#include <plat/cpu-freq.h> 27#include <plat/cpu-freq.h>
29#include <plat/clock.h> 28#include <plat/clock.h>
@@ -32,6 +31,7 @@
32#include <plat/s5p-clock.h> 31#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h> 32#include <plat/clock-clksrc.h>
34 33
34#include "clock.h"
35#include "common.h" 35#include "common.h"
36 36
37static u32 epll_div[][5] = { 37static u32 epll_div[][5] = {
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 154dea702d70..af384ddd2dcf 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -23,7 +23,6 @@
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/map.h> 24#include <mach/map.h>
25#include <mach/regs-clock.h> 25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27 26
28#include <plat/cpu-freq.h> 27#include <plat/cpu-freq.h>
29#include <plat/clock.h> 28#include <plat/clock.h>
@@ -32,6 +31,7 @@
32#include <plat/s5p-clock.h> 31#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h> 32#include <plat/clock-clksrc.h>
34 33
34#include "clock.h"
35#include "common.h" 35#include "common.h"
36 36
37static struct clksrc_clk clk_mout_dpll = { 37static struct clksrc_clk clk_mout_dpll = {
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/clock.h
index 0ef47d1b7670..28b8e3c6bd24 100644
--- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+++ b/arch/arm/mach-s5p64x0/clock.h
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
@@ -10,8 +9,8 @@
10 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
11*/ 10*/
12 11
13#ifndef __ASM_ARCH_CLOCK_H 12#ifndef __MACH_S5P64X0_CLOCK_H
14#define __ASM_ARCH_CLOCK_H __FILE__ 13#define __MACH_S5P64X0_CLOCK_H __FILE__
15 14
16#include <linux/clk.h> 15#include <linux/clk.h>
17 16
@@ -36,4 +35,4 @@ extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
36 35
37extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable); 36extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
38 37
39#endif /* __ASM_ARCH_CLOCK_H */ 38#endif /* __MACH_S5P64X0_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
deleted file mode 100644
index 700dac6c43f3..000000000000
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ /dev/null
@@ -1,508 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/gpiolib.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <mach/regs-gpio.h>
20#include <mach/regs-clock.h>
21
22#include <plat/cpu.h>
23#include <plat/gpio-core.h>
24#include <plat/gpio-cfg.h>
25#include <plat/gpio-cfg-helpers.h>
26
27/*
28 * S5P6440 GPIO bank summary:
29 *
30 * Bank GPIOs Style SlpCon ExtInt Group
31 * A 6 4Bit Yes 1
32 * B 7 4Bit Yes 1
33 * C 8 4Bit Yes 2
34 * F 2 2Bit Yes 4 [1]
35 * G 7 4Bit Yes 5
36 * H 10 4Bit[2] Yes 6
37 * I 16 2Bit Yes None
38 * J 12 2Bit Yes None
39 * N 16 2Bit No IRQ_EINT
40 * P 8 2Bit Yes 8
41 * R 15 4Bit[2] Yes 8
42 *
43 * S5P6450 GPIO bank summary:
44 *
45 * Bank GPIOs Style SlpCon ExtInt Group
46 * A 6 4Bit Yes 1
47 * B 7 4Bit Yes 1
48 * C 8 4Bit Yes 2
49 * D 8 4Bit Yes None
50 * F 2 2Bit Yes None
51 * G 14 4Bit[2] Yes 5
52 * H 10 4Bit[2] Yes 6
53 * I 16 2Bit Yes None
54 * J 12 2Bit Yes None
55 * K 5 4Bit Yes None
56 * N 16 2Bit No IRQ_EINT
57 * P 11 2Bit Yes 8
58 * Q 14 2Bit Yes None
59 * R 15 4Bit[2] Yes None
60 * S 8 2Bit Yes None
61 *
62 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
63 * [2] BANK has two control registers, GPxCON0 and GPxCON1
64 */
65
66static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
67 unsigned int offset)
68{
69 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
70 void __iomem *base = ourchip->base;
71 void __iomem *regcon = base;
72 unsigned long con;
73 unsigned long flags;
74
75 switch (offset) {
76 case 6:
77 offset += 1;
78 case 0:
79 case 1:
80 case 2:
81 case 3:
82 case 4:
83 case 5:
84 regcon -= 4;
85 break;
86 default:
87 offset -= 7;
88 break;
89 }
90
91 s3c_gpio_lock(ourchip, flags);
92
93 con = __raw_readl(regcon);
94 con &= ~(0xf << con_4bit_shift(offset));
95 __raw_writel(con, regcon);
96
97 s3c_gpio_unlock(ourchip, flags);
98
99 return 0;
100}
101
102static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
103 unsigned int offset, int value)
104{
105 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
106 void __iomem *base = ourchip->base;
107 void __iomem *regcon = base;
108 unsigned long con;
109 unsigned long dat;
110 unsigned long flags;
111 unsigned con_offset = offset;
112
113 switch (con_offset) {
114 case 6:
115 con_offset += 1;
116 case 0:
117 case 1:
118 case 2:
119 case 3:
120 case 4:
121 case 5:
122 regcon -= 4;
123 break;
124 default:
125 con_offset -= 7;
126 break;
127 }
128
129 s3c_gpio_lock(ourchip, flags);
130
131 con = __raw_readl(regcon);
132 con &= ~(0xf << con_4bit_shift(con_offset));
133 con |= 0x1 << con_4bit_shift(con_offset);
134
135 dat = __raw_readl(base + GPIODAT_OFF);
136 if (value)
137 dat |= 1 << offset;
138 else
139 dat &= ~(1 << offset);
140
141 __raw_writel(con, regcon);
142 __raw_writel(dat, base + GPIODAT_OFF);
143
144 s3c_gpio_unlock(ourchip, flags);
145
146 return 0;
147}
148
149int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
150 unsigned int off, unsigned int cfg)
151{
152 void __iomem *reg = chip->base;
153 unsigned int shift;
154 u32 con;
155
156 switch (off) {
157 case 0:
158 case 1:
159 case 2:
160 case 3:
161 case 4:
162 case 5:
163 shift = (off & 7) * 4;
164 reg -= 4;
165 break;
166 case 6:
167 shift = ((off + 1) & 7) * 4;
168 reg -= 4;
169 default:
170 shift = ((off + 1) & 7) * 4;
171 break;
172 }
173
174 if (s3c_gpio_is_cfg_special(cfg)) {
175 cfg &= 0xf;
176 cfg <<= shift;
177 }
178
179 con = __raw_readl(reg);
180 con &= ~(0xf << shift);
181 con |= cfg;
182 __raw_writel(con, reg);
183
184 return 0;
185}
186
187static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
188 {
189 .cfg_eint = 0,
190 }, {
191 .cfg_eint = 7,
192 }, {
193 .cfg_eint = 3,
194 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
195 }, {
196 .cfg_eint = 0,
197 .set_config = s3c_gpio_setcfg_s3c24xx,
198 .get_config = s3c_gpio_getcfg_s3c24xx,
199 }, {
200 .cfg_eint = 2,
201 .set_config = s3c_gpio_setcfg_s3c24xx,
202 .get_config = s3c_gpio_getcfg_s3c24xx,
203 }, {
204 .cfg_eint = 3,
205 .set_config = s3c_gpio_setcfg_s3c24xx,
206 .get_config = s3c_gpio_getcfg_s3c24xx,
207 },
208};
209
210static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
211 {
212 .base = S5P64X0_GPA_BASE,
213 .config = &s5p64x0_gpio_cfgs[1],
214 .chip = {
215 .base = S5P6440_GPA(0),
216 .ngpio = S5P6440_GPIO_A_NR,
217 .label = "GPA",
218 },
219 }, {
220 .base = S5P64X0_GPB_BASE,
221 .config = &s5p64x0_gpio_cfgs[1],
222 .chip = {
223 .base = S5P6440_GPB(0),
224 .ngpio = S5P6440_GPIO_B_NR,
225 .label = "GPB",
226 },
227 }, {
228 .base = S5P64X0_GPC_BASE,
229 .config = &s5p64x0_gpio_cfgs[1],
230 .chip = {
231 .base = S5P6440_GPC(0),
232 .ngpio = S5P6440_GPIO_C_NR,
233 .label = "GPC",
234 },
235 }, {
236 .base = S5P64X0_GPG_BASE,
237 .config = &s5p64x0_gpio_cfgs[1],
238 .chip = {
239 .base = S5P6440_GPG(0),
240 .ngpio = S5P6440_GPIO_G_NR,
241 .label = "GPG",
242 },
243 },
244};
245
246static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
247 {
248 .base = S5P64X0_GPH_BASE + 0x4,
249 .config = &s5p64x0_gpio_cfgs[1],
250 .chip = {
251 .base = S5P6440_GPH(0),
252 .ngpio = S5P6440_GPIO_H_NR,
253 .label = "GPH",
254 },
255 },
256};
257
258static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
259 {
260 .base = S5P64X0_GPR_BASE + 0x4,
261 .config = &s5p64x0_gpio_cfgs[2],
262 .chip = {
263 .base = S5P6440_GPR(0),
264 .ngpio = S5P6440_GPIO_R_NR,
265 .label = "GPR",
266 },
267 },
268};
269
270static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
271 {
272 .base = S5P64X0_GPF_BASE,
273 .config = &s5p64x0_gpio_cfgs[5],
274 .chip = {
275 .base = S5P6440_GPF(0),
276 .ngpio = S5P6440_GPIO_F_NR,
277 .label = "GPF",
278 },
279 }, {
280 .base = S5P64X0_GPI_BASE,
281 .config = &s5p64x0_gpio_cfgs[3],
282 .chip = {
283 .base = S5P6440_GPI(0),
284 .ngpio = S5P6440_GPIO_I_NR,
285 .label = "GPI",
286 },
287 }, {
288 .base = S5P64X0_GPJ_BASE,
289 .config = &s5p64x0_gpio_cfgs[3],
290 .chip = {
291 .base = S5P6440_GPJ(0),
292 .ngpio = S5P6440_GPIO_J_NR,
293 .label = "GPJ",
294 },
295 }, {
296 .base = S5P64X0_GPN_BASE,
297 .config = &s5p64x0_gpio_cfgs[4],
298 .chip = {
299 .base = S5P6440_GPN(0),
300 .ngpio = S5P6440_GPIO_N_NR,
301 .label = "GPN",
302 },
303 }, {
304 .base = S5P64X0_GPP_BASE,
305 .config = &s5p64x0_gpio_cfgs[5],
306 .chip = {
307 .base = S5P6440_GPP(0),
308 .ngpio = S5P6440_GPIO_P_NR,
309 .label = "GPP",
310 },
311 },
312};
313
314static struct s3c_gpio_chip s5p6450_gpio_4bit[] = {
315 {
316 .base = S5P64X0_GPA_BASE,
317 .config = &s5p64x0_gpio_cfgs[1],
318 .chip = {
319 .base = S5P6450_GPA(0),
320 .ngpio = S5P6450_GPIO_A_NR,
321 .label = "GPA",
322 },
323 }, {
324 .base = S5P64X0_GPB_BASE,
325 .config = &s5p64x0_gpio_cfgs[1],
326 .chip = {
327 .base = S5P6450_GPB(0),
328 .ngpio = S5P6450_GPIO_B_NR,
329 .label = "GPB",
330 },
331 }, {
332 .base = S5P64X0_GPC_BASE,
333 .config = &s5p64x0_gpio_cfgs[1],
334 .chip = {
335 .base = S5P6450_GPC(0),
336 .ngpio = S5P6450_GPIO_C_NR,
337 .label = "GPC",
338 },
339 }, {
340 .base = S5P6450_GPD_BASE,
341 .config = &s5p64x0_gpio_cfgs[1],
342 .chip = {
343 .base = S5P6450_GPD(0),
344 .ngpio = S5P6450_GPIO_D_NR,
345 .label = "GPD",
346 },
347 }, {
348 .base = S5P6450_GPK_BASE,
349 .config = &s5p64x0_gpio_cfgs[1],
350 .chip = {
351 .base = S5P6450_GPK(0),
352 .ngpio = S5P6450_GPIO_K_NR,
353 .label = "GPK",
354 },
355 },
356};
357
358static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = {
359 {
360 .base = S5P64X0_GPG_BASE + 0x4,
361 .config = &s5p64x0_gpio_cfgs[1],
362 .chip = {
363 .base = S5P6450_GPG(0),
364 .ngpio = S5P6450_GPIO_G_NR,
365 .label = "GPG",
366 },
367 }, {
368 .base = S5P64X0_GPH_BASE + 0x4,
369 .config = &s5p64x0_gpio_cfgs[1],
370 .chip = {
371 .base = S5P6450_GPH(0),
372 .ngpio = S5P6450_GPIO_H_NR,
373 .label = "GPH",
374 },
375 },
376};
377
378static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = {
379 {
380 .base = S5P64X0_GPR_BASE + 0x4,
381 .config = &s5p64x0_gpio_cfgs[2],
382 .chip = {
383 .base = S5P6450_GPR(0),
384 .ngpio = S5P6450_GPIO_R_NR,
385 .label = "GPR",
386 },
387 },
388};
389
390static struct s3c_gpio_chip s5p6450_gpio_2bit[] = {
391 {
392 .base = S5P64X0_GPF_BASE,
393 .config = &s5p64x0_gpio_cfgs[5],
394 .chip = {
395 .base = S5P6450_GPF(0),
396 .ngpio = S5P6450_GPIO_F_NR,
397 .label = "GPF",
398 },
399 }, {
400 .base = S5P64X0_GPI_BASE,
401 .config = &s5p64x0_gpio_cfgs[3],
402 .chip = {
403 .base = S5P6450_GPI(0),
404 .ngpio = S5P6450_GPIO_I_NR,
405 .label = "GPI",
406 },
407 }, {
408 .base = S5P64X0_GPJ_BASE,
409 .config = &s5p64x0_gpio_cfgs[3],
410 .chip = {
411 .base = S5P6450_GPJ(0),
412 .ngpio = S5P6450_GPIO_J_NR,
413 .label = "GPJ",
414 },
415 }, {
416 .base = S5P64X0_GPN_BASE,
417 .config = &s5p64x0_gpio_cfgs[4],
418 .chip = {
419 .base = S5P6450_GPN(0),
420 .ngpio = S5P6450_GPIO_N_NR,
421 .label = "GPN",
422 },
423 }, {
424 .base = S5P64X0_GPP_BASE,
425 .config = &s5p64x0_gpio_cfgs[5],
426 .chip = {
427 .base = S5P6450_GPP(0),
428 .ngpio = S5P6450_GPIO_P_NR,
429 .label = "GPP",
430 },
431 }, {
432 .base = S5P6450_GPQ_BASE,
433 .config = &s5p64x0_gpio_cfgs[4],
434 .chip = {
435 .base = S5P6450_GPQ(0),
436 .ngpio = S5P6450_GPIO_Q_NR,
437 .label = "GPQ",
438 },
439 }, {
440 .base = S5P6450_GPS_BASE,
441 .config = &s5p64x0_gpio_cfgs[5],
442 .chip = {
443 .base = S5P6450_GPS(0),
444 .ngpio = S5P6450_GPIO_S_NR,
445 .label = "GPS",
446 },
447 },
448};
449
450void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
451{
452 for (; nr_chips > 0; nr_chips--, chipcfg++) {
453 if (!chipcfg->set_config)
454 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
455 if (!chipcfg->get_config)
456 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
457 if (!chipcfg->set_pull)
458 chipcfg->set_pull = s3c_gpio_setpull_updown;
459 if (!chipcfg->get_pull)
460 chipcfg->get_pull = s3c_gpio_getpull_updown;
461 }
462}
463
464static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
465 int nr_chips)
466{
467 for (; nr_chips > 0; nr_chips--, chip++) {
468 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
469 chip->chip.direction_output =
470 s5p64x0_gpiolib_rbank_4bit2_output;
471 s3c_gpiolib_add(chip);
472 }
473}
474
475static int __init s5p64x0_gpiolib_init(void)
476{
477 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
478 ARRAY_SIZE(s5p64x0_gpio_cfgs));
479
480 if (soc_is_s5p6450()) {
481 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
482 ARRAY_SIZE(s5p6450_gpio_2bit));
483
484 samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
485 ARRAY_SIZE(s5p6450_gpio_4bit));
486
487 samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
488 ARRAY_SIZE(s5p6450_gpio_4bit2));
489
490 s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
491 ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
492 } else {
493 samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
494 ARRAY_SIZE(s5p6440_gpio_2bit));
495
496 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
497 ARRAY_SIZE(s5p6440_gpio_4bit));
498
499 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
500 ARRAY_SIZE(s5p6440_gpio_4bit2));
501
502 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
503 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
504 }
505
506 return 0;
507}
508core_initcall(s5p64x0_gpiolib_init);
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/i2c.h
index 887d25209e8e..1e5bb4ea200d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/i2c.h
+++ b/arch/arm/mach-s5p64x0/i2c.h
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
index 4aaebdace55f..d60397d1ff40 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -13,7 +13,6 @@
13#ifndef __ASM_ARCH_REGS_IRQ_H 13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__ 14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15 15
16#include <asm/hardware/vic.h>
17#include <mach/map.h> 16#include <mach/map.h>
18 17
19#endif /* __ASM_ARCH_REGS_IRQ_H */ 18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
deleted file mode 100644
index 00aa7f1d8e51..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/tick.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * S5P64X0 - Timer tick support definitions
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_ARCH_TICK_H
19#define __ASM_ARCH_TICK_H __FILE__
20
21static inline u32 s3c24xx_ostimer_pending(void)
22{
23 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
24 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
25}
26
27#define TICK_MAX (0xffffffff)
28
29#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 1608faf870ff..19e0d64d78c5 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -116,33 +116,6 @@ static inline void flush(void)
116 *((volatile unsigned int __force *)(ad)) = (d); \ 116 *((volatile unsigned int __force *)(ad)) = (d); \
117 } while (0) 117 } while (0)
118 118
119/*
120 * CONFIG_S3C_BOOT_WATCHDOG
121 *
122 * Simple boot-time watchdog setup, to reboot the system if there is
123 * any problem with the boot process
124 */
125
126#ifdef CONFIG_S3C_BOOT_WATCHDOG
127
128#define WDOG_COUNT (0xff00)
129
130static inline void arch_decomp_wdog(void)
131{
132 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
133}
134
135static void arch_decomp_wdog_start(void)
136{
137 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
138 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
139 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
140}
141
142#else
143#define arch_decomp_wdog_start()
144#define arch_decomp_wdog()
145#endif
146 119
147#ifdef CONFIG_S3C_BOOT_ERROR_RESET 120#ifdef CONFIG_S3C_BOOT_ERROR_RESET
148 121
@@ -192,7 +165,6 @@ static void arch_decomp_setup(void)
192 */ 165 */
193 166
194 arch_detect_cpu(); 167 arch_detect_cpu();
195 arch_decomp_wdog_start();
196 168
197 /* 169 /*
198 * Enable the UART FIFOs if they where not enabled and our 170 * Enable the UART FIFOs if they where not enabled and our
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 1af823558c60..e23723a5a214 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -29,7 +29,6 @@
29#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
30#include <video/samsung_fimd.h> 30#include <video/samsung_fimd.h>
31 31
32#include <asm/hardware/vic.h>
33#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 33#include <asm/mach/map.h>
35#include <asm/irq.h> 34#include <asm/irq.h>
@@ -38,7 +37,6 @@
38#include <mach/hardware.h> 37#include <mach/hardware.h>
39#include <mach/map.h> 38#include <mach/map.h>
40#include <mach/regs-clock.h> 39#include <mach/regs-clock.h>
41#include <mach/i2c.h>
42#include <mach/regs-gpio.h> 40#include <mach/regs-gpio.h>
43 41
44#include <plat/regs-serial.h> 42#include <plat/regs-serial.h>
@@ -56,6 +54,7 @@
56#include <plat/sdhci.h> 54#include <plat/sdhci.h>
57 55
58#include "common.h" 56#include "common.h"
57#include "i2c.h"
59 58
60#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 59#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
61 S3C2410_UCON_RXILEVEL | \ 60 S3C2410_UCON_RXILEVEL | \
@@ -272,9 +271,8 @@ MACHINE_START(SMDK6440, "SMDK6440")
272 .atag_offset = 0x100, 271 .atag_offset = 0x100,
273 272
274 .init_irq = s5p6440_init_irq, 273 .init_irq = s5p6440_init_irq,
275 .handle_irq = vic_handle_irq,
276 .map_io = smdk6440_map_io, 274 .map_io = smdk6440_map_io,
277 .init_machine = smdk6440_machine_init, 275 .init_machine = smdk6440_machine_init,
278 .timer = &s5p_timer, 276 .init_time = s5p_timer_init,
279 .restart = s5p64x0_restart, 277 .restart = s5p64x0_restart,
280MACHINE_END 278MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 62526ccf6b70..ca10963a959e 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -29,7 +29,6 @@
29#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
30#include <video/samsung_fimd.h> 30#include <video/samsung_fimd.h>
31 31
32#include <asm/hardware/vic.h>
33#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 33#include <asm/mach/map.h>
35#include <asm/irq.h> 34#include <asm/irq.h>
@@ -38,7 +37,6 @@
38#include <mach/hardware.h> 37#include <mach/hardware.h>
39#include <mach/map.h> 38#include <mach/map.h>
40#include <mach/regs-clock.h> 39#include <mach/regs-clock.h>
41#include <mach/i2c.h>
42#include <mach/regs-gpio.h> 40#include <mach/regs-gpio.h>
43 41
44#include <plat/regs-serial.h> 42#include <plat/regs-serial.h>
@@ -56,6 +54,7 @@
56#include <plat/sdhci.h> 54#include <plat/sdhci.h>
57 55
58#include "common.h" 56#include "common.h"
57#include "i2c.h"
59 58
60#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 59#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
61 S3C2410_UCON_RXILEVEL | \ 60 S3C2410_UCON_RXILEVEL | \
@@ -291,9 +290,8 @@ MACHINE_START(SMDK6450, "SMDK6450")
291 .atag_offset = 0x100, 290 .atag_offset = 0x100,
292 291
293 .init_irq = s5p6450_init_irq, 292 .init_irq = s5p6450_init_irq,
294 .handle_irq = vic_handle_irq,
295 .map_io = smdk6450_map_io, 293 .map_io = smdk6450_map_io,
296 .init_machine = smdk6450_machine_init, 294 .init_machine = smdk6450_machine_init,
297 .timer = &s5p_timer, 295 .init_time = s5p_timer_init,
298 .restart = s5p64x0_restart, 296 .restart = s5p64x0_restart,
299MACHINE_END 297MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index a32edc545e6c..569b76ac98cb 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <linux/platform_data/i2c-s3c2410.h> 22#include <linux/platform_data/i2c-s3c2410.h>
23 23
24#include <mach/i2c.h> 24#include "i2c.h"
25 25
26void s5p6440_i2c0_cfg_gpio(struct platform_device *dev) 26void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
27{ 27{
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index ca2c5c7f8aa6..867374e6d0bc 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -21,7 +21,7 @@ struct platform_device; /* don't need the contents */
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <linux/platform_data/i2c-s3c2410.h> 22#include <linux/platform_data/i2c-s3c2410.h>
23 23
24#include <mach/i2c.h> 24#include "i2c.h"
25 25
26void s5p6440_i2c1_cfg_gpio(struct platform_device *dev) 26void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
27{ 27{
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 07:29:10 -0400