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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 19:17:43 -0400
commit4f2d658b2f09c41677871a4285a09cf35f954dad (patch)
treeec0a626a598530203871bbc37a340224e5ac87ad /arch/arm/mach-s3c64xx
parente66d637134b7045ea6f14bdd416cd3695f73ed42 (diff)
parent1fc5f7d5c680ac36bd41e13a3d77cbe2eaa312e0 (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree description updates from Arnd Bergmann: "This branch contains two kinds of updates: Some platforms in the process of getting converted to device tree based booting, and the platform specific patches necessary for that are included here. Other platforms are already converted, so we just need to update the actual device tree source files and the binding documents to add support for new board and new drivers. In the future we will probably separate those into two branches, and in the long run, the plan is to move the device tree source files out of the kernel repository, but that has to wait until we have completed a much larger portion of the binding documents." Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly added clkdev registers next to a few removed unnecessary ones. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: LPC32xx: Add PWM to base dts file ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 ARM: EXYNOS: Add spi clock support for EXYNOS5 ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock ARM: ux500: Remove PMU platform registration when booting with DT ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure ARM: ux500: Ensure vendor specific properties have the vendor's identifier pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree ARM: ux500: Apply ab8500-debug node do the db8500 DT structure ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT ...
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/clock.c20
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/dma.h1
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c19
4 files changed, 14 insertions, 28 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a691cb..28041e83dc82 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
179 }, { 179 }, {
180 .name = "spi", 180 .name = "spi",
181 .devname = "s3c64xx-spi.0", 181 .devname = "s3c6410-spi.0",
182 .parent = &clk_p, 182 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 183 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 184 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
185 }, { 185 }, {
186 .name = "spi", 186 .name = "spi",
187 .devname = "s3c64xx-spi.1", 187 .devname = "s3c6410-spi.1",
188 .parent = &clk_p, 188 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 189 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 190 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
331 331
332static struct clk clk_48m_spi0 = { 332static struct clk clk_48m_spi0 = {
333 .name = "spi_48m", 333 .name = "spi_48m",
334 .devname = "s3c64xx-spi.0", 334 .devname = "s3c6410-spi.0",
335 .parent = &clk_48m, 335 .parent = &clk_48m,
336 .enable = s3c64xx_sclk_ctrl, 336 .enable = s3c64xx_sclk_ctrl,
337 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 337 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
339 339
340static struct clk clk_48m_spi1 = { 340static struct clk clk_48m_spi1 = {
341 .name = "spi_48m", 341 .name = "spi_48m",
342 .devname = "s3c64xx-spi.1", 342 .devname = "s3c6410-spi.1",
343 .parent = &clk_48m, 343 .parent = &clk_48m,
344 .enable = s3c64xx_sclk_ctrl, 344 .enable = s3c64xx_sclk_ctrl,
345 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 345 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
802static struct clksrc_clk clk_sclk_spi0 = { 802static struct clksrc_clk clk_sclk_spi0 = {
803 .clk = { 803 .clk = {
804 .name = "spi-bus", 804 .name = "spi-bus",
805 .devname = "s3c64xx-spi.0", 805 .devname = "s3c6410-spi.0",
806 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 806 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
807 .enable = s3c64xx_sclk_ctrl, 807 .enable = s3c64xx_sclk_ctrl,
808 }, 808 },
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
814static struct clksrc_clk clk_sclk_spi1 = { 814static struct clksrc_clk clk_sclk_spi1 = {
815 .clk = { 815 .clk = {
816 .name = "spi-bus", 816 .name = "spi-bus",
817 .devname = "s3c64xx-spi.1", 817 .devname = "s3c6410-spi.1",
818 .ctrlbit = S3C_CLKCON_SCLK_SPI1, 818 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
819 .enable = s3c64xx_sclk_ctrl, 819 .enable = s3c64xx_sclk_ctrl,
820 }, 820 },
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 858 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 859 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
860 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 860 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
861 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 861 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
862 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), 862 CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
863 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 863 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
864 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), 864 CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
865}; 865};
866 866
867#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 867#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98cf0e4c..57b1ff4b2d7c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,6 +21,7 @@
21 */ 21 */
22enum dma_ch { 22enum dma_ch {
23 /* DMA0/SDMA0 */ 23 /* DMA0/SDMA0 */
24 DMACH_DT_PROP = -1, /* not yet supported, do not use */
24 DMACH_UART0 = 0, 25 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2, 26 DMACH_UART0_SRC2,
26 DMACH_UART1, 27 DMACH_UART1,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d0c352d861f8..6dd4fae33a82 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -799,7 +799,7 @@ static void __init crag6410_machine_init(void)
799 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); 799 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
800 800
801 samsung_keypad_set_platdata(&crag6410_keypad_data); 801 samsung_keypad_set_platdata(&crag6410_keypad_data);
802 s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1); 802 s3c64xx_spi0_set_platdata(NULL, 0, 1);
803 803
804 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); 804 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
805 805
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad7a825..4dc53450d715 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -9,19 +9,10 @@
9 */ 9 */
10 10
11#include <linux/gpio.h> 11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h> 12#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16 13
17#ifdef CONFIG_S3C64XX_DEV_SPI0 14#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { 15int s3c64xx_spi0_cfg_gpio(void)
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{ 16{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, 17 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 18 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -30,13 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
30#endif 21#endif
31 22
32#ifdef CONFIG_S3C64XX_DEV_SPI1 23#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { 24int s3c64xx_spi1_cfg_gpio(void)
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{ 25{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, 26 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);