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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
commit6fa52ed33bea997374a88dbacbba5bf8c7ac4fef (patch)
treea0904b78d66c9b99d6acf944cf58bcaa0cffc511 /arch/arm/mach-s3c24xx/include
parent1db772216f48978d5146b858586f6178433aad38 (diff)
parentbc8fd900c4d460b4e4bf785bb48bfced0ac9941b (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson: "This is a rather large set of patches for device drivers that for one reason or another the subsystem maintainer preferred to get merged through the arm-soc tree. There are both new drivers as well as existing drivers that are getting converted from platform-specific code into standalone drivers using the appropriate subsystem specific interfaces. In particular, we can now have pinctrl, clk, clksource and irqchip drivers in one file per driver, without the need to call into platform specific interface, or to get called from platform specific code, as long as all information about the hardware is provided through a device tree. Most of the drivers we touch this time are for clocksource. Since now most of them are part of drivers/clocksource, I expect that we won't have to touch these again from arm-soc and can let the clocksource maintainers take care of these in the future. Another larger part of this series is specific to the exynos platform, which is seeing some significant effort in upstreaming and modernization of its device drivers this time around, which unfortunately is also the cause for the churn and a lot of the merge conflicts. There is one new subsystem that gets merged as part of this series: the reset controller interface, which is a very simple interface for taking devices on the SoC out of reset or back into reset. Patches to use this interface on i.MX follow later in this merge window, and we are going to have other platforms (at least tegra and sirf) get converted in 3.11. This will let us get rid of platform specific callbacks in a number of platform independent device drivers." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits) irqchip: s3c24xx: add missing __init annotations ARM: dts: Disable the RTC by default on exynos5 clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ARM: exynos: restore mach/regs-clock.h for exynos5 clocksource: exynos_mct: fix build error on non-DT pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register() irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: tegra: fix enum tegra114_clk to match binding ...
Diffstat (limited to 'arch/arm/mach-s3c24xx/include')
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/entry-macro.S70
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/irqs.h58
2 files changed, 31 insertions, 97 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for S3C2410-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9*/
10
11/* We have a problem that the INTOFFSET register does not always
12 * show one interrupt. Occasionally we get two interrupts through
13 * the prioritiser, and this causes the INTOFFSET register to show
14 * what looks like the logical-or of the two interrupt numbers.
15 *
16 * Thanks to Klaus, Shannon, et al for helping to debug this problem
17*/
18
19#define INTPND (0x10)
20#define INTOFFSET (0x14)
21
22#include <mach/hardware.h>
23#include <asm/irq.h>
24
25 .macro get_irqnr_preamble, base, tmp
26 .endm
27
28 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
29
30 mov \base, #S3C24XX_VA_IRQ
31
32 @@ try the interrupt offset register, since it is there
33
34 ldr \irqstat, [\base, #INTPND ]
35 teq \irqstat, #0
36 beq 1002f
37 ldr \irqnr, [\base, #INTOFFSET ]
38 mov \tmp, #1
39 tst \irqstat, \tmp, lsl \irqnr
40 bne 1001f
41
42 @@ the number specified is not a valid irq, so try
43 @@ and work it out for ourselves
44
45 mov \irqnr, #0 @@ start here
46
47 @@ work out which irq (if any) we got
48
49 movs \tmp, \irqstat, lsl#16
50 addeq \irqnr, \irqnr, #16
51 moveq \irqstat, \irqstat, lsr#16
52 tst \irqstat, #0xff
53 addeq \irqnr, \irqnr, #8
54 moveq \irqstat, \irqstat, lsr#8
55 tst \irqstat, #0xf
56 addeq \irqnr, \irqnr, #4
57 moveq \irqstat, \irqstat, lsr#4
58 tst \irqstat, #0x3
59 addeq \irqnr, \irqnr, #2
60 moveq \irqstat, \irqstat, lsr#2
61 tst \irqstat, #0x1
62 addeq \irqnr, \irqnr, #1
63
64 @@ we have the value
651001:
66 adds \irqnr, \irqnr, #IRQ_EINT0
671002:
68 @@ exit here, Z flag unset if IRQ
69
70 .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index 1e73f5fa8659..b6dd4cb5a2ec 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,53 @@
59#define IRQ_ADCPARENT S3C2410_IRQ(31) 59#define IRQ_ADCPARENT S3C2410_IRQ(31)
60 60
61/* interrupts generated from the external interrupts sources */ 61/* interrupts generated from the external interrupts sources */
62#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ 62#define IRQ_EINT0_2412 S3C2410_IRQ(32)
63#define IRQ_EINT5 S3C2410_IRQ(33) 63#define IRQ_EINT1_2412 S3C2410_IRQ(33)
64#define IRQ_EINT6 S3C2410_IRQ(34) 64#define IRQ_EINT2_2412 S3C2410_IRQ(34)
65#define IRQ_EINT7 S3C2410_IRQ(35) 65#define IRQ_EINT3_2412 S3C2410_IRQ(35)
66#define IRQ_EINT8 S3C2410_IRQ(36) 66#define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */
67#define IRQ_EINT9 S3C2410_IRQ(37) 67#define IRQ_EINT5 S3C2410_IRQ(37)
68#define IRQ_EINT10 S3C2410_IRQ(38) 68#define IRQ_EINT6 S3C2410_IRQ(38)
69#define IRQ_EINT11 S3C2410_IRQ(39) 69#define IRQ_EINT7 S3C2410_IRQ(39)
70#define IRQ_EINT12 S3C2410_IRQ(40) 70#define IRQ_EINT8 S3C2410_IRQ(40)
71#define IRQ_EINT13 S3C2410_IRQ(41) 71#define IRQ_EINT9 S3C2410_IRQ(41)
72#define IRQ_EINT14 S3C2410_IRQ(42) 72#define IRQ_EINT10 S3C2410_IRQ(42)
73#define IRQ_EINT15 S3C2410_IRQ(43) 73#define IRQ_EINT11 S3C2410_IRQ(43)
74#define IRQ_EINT16 S3C2410_IRQ(44) 74#define IRQ_EINT12 S3C2410_IRQ(44)
75#define IRQ_EINT17 S3C2410_IRQ(45) 75#define IRQ_EINT13 S3C2410_IRQ(45)
76#define IRQ_EINT18 S3C2410_IRQ(46) 76#define IRQ_EINT14 S3C2410_IRQ(46)
77#define IRQ_EINT19 S3C2410_IRQ(47) 77#define IRQ_EINT15 S3C2410_IRQ(47)
78#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ 78#define IRQ_EINT16 S3C2410_IRQ(48)
79#define IRQ_EINT21 S3C2410_IRQ(49) 79#define IRQ_EINT17 S3C2410_IRQ(49)
80#define IRQ_EINT22 S3C2410_IRQ(50) 80#define IRQ_EINT18 S3C2410_IRQ(50)
81#define IRQ_EINT23 S3C2410_IRQ(51) 81#define IRQ_EINT19 S3C2410_IRQ(51)
82#define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */
83#define IRQ_EINT21 S3C2410_IRQ(53)
84#define IRQ_EINT22 S3C2410_IRQ(54)
85#define IRQ_EINT23 S3C2410_IRQ(55)
82 86
83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) 87#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) 88#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
85 89
86#define IRQ_LCD_FIFO S3C2410_IRQ(52) 90#define IRQ_LCD_FIFO S3C2410_IRQ(56)
87#define IRQ_LCD_FRAME S3C2410_IRQ(53) 91#define IRQ_LCD_FRAME S3C2410_IRQ(57)
88 92
89/* IRQs for the interal UARTs, and ADC 93/* IRQs for the interal UARTs, and ADC
90 * these need to be ordered in number of appearance in the 94 * these need to be ordered in number of appearance in the
91 * SUBSRC mask register 95 * SUBSRC mask register
92*/ 96*/
93 97
94#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) 98#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58)
95 99
96#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ 100#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */
97#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) 101#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
98#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) 102#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
99 103
100#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ 104#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */
101#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) 105#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
102#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) 106#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
103 107
104#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ 108#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */
105#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) 109#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
106#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) 110#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
107 111
@@ -136,7 +140,7 @@
136 140
137/* second interrupt-register of s3c2416/s3c2450 */ 141/* second interrupt-register of s3c2416/s3c2450 */
138 142
139#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29) 143#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29)
140#define IRQ_S3C2416_2D S3C2416_IRQ(0) 144#define IRQ_S3C2416_2D S3C2416_IRQ(0)
141#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) 145#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
142#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) 146#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)