diff options
author | Ben Dooks <ben-linux@fluff.org> | 2009-11-30 20:24:37 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-01-15 03:10:10 -0500 |
commit | b3bf41be06634d69959a68a2b53e1ffc92f0d103 (patch) | |
tree | 7575fc3d60e9a2f99e74b2862e1b3a43b7df1f92 /arch/arm/mach-s3c2443 | |
parent | 13bbd88504bfa0d205fa4121322869d8d7e083d0 (diff) |
ARM: SAMSUNG: Reduce size of struct clk.
Reduce the size of struct clk by 12 bytes and make defining clocks with
common implementation functions easier by moving the set_rate, get_rate,
round_rate and set_parent calls into a new structure called 'struct clk_ops'
and using that instead.
This change does make a few clocks larger as they need their own clk_ops,
but this is outweighed by the number of clocks with either no ops or having
a common set of ops.
Update all the users of this.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2443')
-rw-r--r-- | arch/arm/mach-s3c2443/clock.c | 88 |
1 files changed, 59 insertions, 29 deletions
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 2785d69c95b0..91db4f54bb33 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c | |||
@@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) | |||
187 | static struct clk clk_epllref = { | 187 | static struct clk clk_epllref = { |
188 | .name = "epllref", | 188 | .name = "epllref", |
189 | .id = -1, | 189 | .id = -1, |
190 | .set_parent = s3c2443_setparent_epllref, | 190 | .ops = &(struct clk_ops) { |
191 | .set_parent = s3c2443_setparent_epllref, | ||
192 | }, | ||
191 | }; | 193 | }; |
192 | 194 | ||
193 | static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) | 195 | static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) |
@@ -205,7 +207,9 @@ static struct clk clk_mdivclk = { | |||
205 | .name = "mdivclk", | 207 | .name = "mdivclk", |
206 | .parent = &clk_mpllref, | 208 | .parent = &clk_mpllref, |
207 | .id = -1, | 209 | .id = -1, |
208 | .get_rate = s3c2443_getrate_mdivclk, | 210 | .ops = &(struct clk_ops) { |
211 | .get_rate = s3c2443_getrate_mdivclk, | ||
212 | }, | ||
209 | }; | 213 | }; |
210 | 214 | ||
211 | static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) | 215 | static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) |
@@ -232,7 +236,9 @@ static struct clk clk_msysclk = { | |||
232 | .name = "msysclk", | 236 | .name = "msysclk", |
233 | .parent = &clk_xtal, | 237 | .parent = &clk_xtal, |
234 | .id = -1, | 238 | .id = -1, |
235 | .set_parent = s3c2443_setparent_msysclk, | 239 | .ops = &(struct clk_ops) { |
240 | .set_parent = s3c2443_setparent_msysclk, | ||
241 | }, | ||
236 | }; | 242 | }; |
237 | 243 | ||
238 | /* armdiv | 244 | /* armdiv |
@@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent) | |||
273 | static struct clk clk_arm = { | 279 | static struct clk clk_arm = { |
274 | .name = "armclk", | 280 | .name = "armclk", |
275 | .id = -1, | 281 | .id = -1, |
276 | .set_parent = s3c2443_setparent_armclk, | 282 | .ops = &(struct clk_ops) { |
283 | .set_parent = s3c2443_setparent_armclk, | ||
284 | }, | ||
277 | }; | 285 | }; |
278 | 286 | ||
279 | /* esysclk | 287 | /* esysclk |
@@ -302,7 +310,9 @@ static struct clk clk_esysclk = { | |||
302 | .name = "esysclk", | 310 | .name = "esysclk", |
303 | .parent = &clk_epll, | 311 | .parent = &clk_epll, |
304 | .id = -1, | 312 | .id = -1, |
305 | .set_parent = s3c2443_setparent_esysclk, | 313 | .ops = &(struct clk_ops) { |
314 | .set_parent = s3c2443_setparent_esysclk, | ||
315 | }, | ||
306 | }; | 316 | }; |
307 | 317 | ||
308 | /* uartclk | 318 | /* uartclk |
@@ -341,9 +351,11 @@ static struct clk clk_uart = { | |||
341 | .name = "uartclk", | 351 | .name = "uartclk", |
342 | .id = -1, | 352 | .id = -1, |
343 | .parent = &clk_esysclk, | 353 | .parent = &clk_esysclk, |
344 | .get_rate = s3c2443_getrate_uart, | 354 | .ops = &(struct clk_ops) { |
345 | .set_rate = s3c2443_setrate_uart, | 355 | .get_rate = s3c2443_getrate_uart, |
346 | .round_rate = s3c2443_roundrate_clksrc16, | 356 | .set_rate = s3c2443_setrate_uart, |
357 | .round_rate = s3c2443_roundrate_clksrc16, | ||
358 | }, | ||
347 | }; | 359 | }; |
348 | 360 | ||
349 | /* hsspi | 361 | /* hsspi |
@@ -384,9 +396,11 @@ static struct clk clk_hsspi = { | |||
384 | .parent = &clk_esysclk, | 396 | .parent = &clk_esysclk, |
385 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, | 397 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, |
386 | .enable = s3c2443_clkcon_enable_s, | 398 | .enable = s3c2443_clkcon_enable_s, |
387 | .get_rate = s3c2443_getrate_hsspi, | 399 | .ops = &(struct clk_ops) { |
388 | .set_rate = s3c2443_setrate_hsspi, | 400 | .get_rate = s3c2443_getrate_hsspi, |
389 | .round_rate = s3c2443_roundrate_clksrc4, | 401 | .set_rate = s3c2443_setrate_hsspi, |
402 | .round_rate = s3c2443_roundrate_clksrc4, | ||
403 | }, | ||
390 | }; | 404 | }; |
391 | 405 | ||
392 | /* usbhost | 406 | /* usbhost |
@@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = { | |||
426 | .parent = &clk_esysclk, | 440 | .parent = &clk_esysclk, |
427 | .ctrlbit = S3C2443_SCLKCON_USBHOST, | 441 | .ctrlbit = S3C2443_SCLKCON_USBHOST, |
428 | .enable = s3c2443_clkcon_enable_s, | 442 | .enable = s3c2443_clkcon_enable_s, |
429 | .get_rate = s3c2443_getrate_usbhost, | 443 | .ops = &(struct clk_ops) { |
430 | .set_rate = s3c2443_setrate_usbhost, | 444 | .get_rate = s3c2443_getrate_usbhost, |
431 | .round_rate = s3c2443_roundrate_clksrc4, | 445 | .set_rate = s3c2443_setrate_usbhost, |
446 | .round_rate = s3c2443_roundrate_clksrc4, | ||
447 | }, | ||
432 | }; | 448 | }; |
433 | 449 | ||
434 | /* clk_hsmcc_div | 450 | /* clk_hsmcc_div |
@@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = { | |||
468 | .name = "hsmmc-div", | 484 | .name = "hsmmc-div", |
469 | .id = -1, | 485 | .id = -1, |
470 | .parent = &clk_esysclk, | 486 | .parent = &clk_esysclk, |
471 | .get_rate = s3c2443_getrate_hsmmc_div, | 487 | .ops = &(struct clk_ops) { |
472 | .set_rate = s3c2443_setrate_hsmmc_div, | 488 | .get_rate = s3c2443_getrate_hsmmc_div, |
473 | .round_rate = s3c2443_roundrate_clksrc4, | 489 | .set_rate = s3c2443_setrate_hsmmc_div, |
490 | .round_rate = s3c2443_roundrate_clksrc4, | ||
491 | }, | ||
474 | }; | 492 | }; |
475 | 493 | ||
476 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) | 494 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) |
@@ -505,7 +523,9 @@ static struct clk clk_hsmmc = { | |||
505 | .id = -1, | 523 | .id = -1, |
506 | .parent = &clk_hsmmc_div, | 524 | .parent = &clk_hsmmc_div, |
507 | .enable = s3c2443_enable_hsmmc, | 525 | .enable = s3c2443_enable_hsmmc, |
508 | .set_parent = s3c2443_setparent_hsmmc, | 526 | .ops = &(struct clk_ops) { |
527 | .set_parent = s3c2443_setparent_hsmmc, | ||
528 | }, | ||
509 | }; | 529 | }; |
510 | 530 | ||
511 | /* i2s_eplldiv | 531 | /* i2s_eplldiv |
@@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = { | |||
543 | .name = "i2s-eplldiv", | 563 | .name = "i2s-eplldiv", |
544 | .id = -1, | 564 | .id = -1, |
545 | .parent = &clk_esysclk, | 565 | .parent = &clk_esysclk, |
546 | .get_rate = s3c2443_getrate_i2s_eplldiv, | 566 | .ops = &(struct clk_ops) { |
547 | .set_rate = s3c2443_setrate_i2s_eplldiv, | 567 | .get_rate = s3c2443_getrate_i2s_eplldiv, |
548 | .round_rate = s3c2443_roundrate_clksrc16, | 568 | .set_rate = s3c2443_setrate_i2s_eplldiv, |
569 | .round_rate = s3c2443_roundrate_clksrc16, | ||
570 | }, | ||
549 | }; | 571 | }; |
550 | 572 | ||
551 | /* i2s-ref | 573 | /* i2s-ref |
@@ -578,7 +600,9 @@ static struct clk clk_i2s = { | |||
578 | .parent = &clk_i2s_eplldiv, | 600 | .parent = &clk_i2s_eplldiv, |
579 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, | 601 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, |
580 | .enable = s3c2443_clkcon_enable_s, | 602 | .enable = s3c2443_clkcon_enable_s, |
581 | .set_parent = s3c2443_setparent_i2s, | 603 | .ops = &(struct clk_ops) { |
604 | .set_parent = s3c2443_setparent_i2s, | ||
605 | }, | ||
582 | }; | 606 | }; |
583 | 607 | ||
584 | /* cam-if | 608 | /* cam-if |
@@ -618,9 +642,11 @@ static struct clk clk_cam = { | |||
618 | .parent = &clk_esysclk, | 642 | .parent = &clk_esysclk, |
619 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, | 643 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, |
620 | .enable = s3c2443_clkcon_enable_s, | 644 | .enable = s3c2443_clkcon_enable_s, |
621 | .get_rate = s3c2443_getrate_cam, | 645 | .ops = &(struct clk_ops) { |
622 | .set_rate = s3c2443_setrate_cam, | 646 | .get_rate = s3c2443_getrate_cam, |
623 | .round_rate = s3c2443_roundrate_clksrc16, | 647 | .set_rate = s3c2443_setrate_cam, |
648 | .round_rate = s3c2443_roundrate_clksrc16, | ||
649 | }, | ||
624 | }; | 650 | }; |
625 | 651 | ||
626 | /* display-if | 652 | /* display-if |
@@ -660,9 +686,11 @@ static struct clk clk_display = { | |||
660 | .parent = &clk_esysclk, | 686 | .parent = &clk_esysclk, |
661 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, | 687 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, |
662 | .enable = s3c2443_clkcon_enable_s, | 688 | .enable = s3c2443_clkcon_enable_s, |
663 | .get_rate = s3c2443_getrate_display, | 689 | .ops = &(struct clk_ops) { |
664 | .set_rate = s3c2443_setrate_display, | 690 | .get_rate = s3c2443_getrate_display, |
665 | .round_rate = s3c2443_roundrate_clksrc256, | 691 | .set_rate = s3c2443_setrate_display, |
692 | .round_rate = s3c2443_roundrate_clksrc256, | ||
693 | }, | ||
666 | }; | 694 | }; |
667 | 695 | ||
668 | /* prediv | 696 | /* prediv |
@@ -685,7 +713,9 @@ static struct clk clk_prediv = { | |||
685 | .name = "prediv", | 713 | .name = "prediv", |
686 | .id = -1, | 714 | .id = -1, |
687 | .parent = &clk_msysclk, | 715 | .parent = &clk_msysclk, |
688 | .get_rate = s3c2443_prediv_getrate, | 716 | .ops = &(struct clk_ops) { |
717 | .get_rate = s3c2443_prediv_getrate, | ||
718 | }, | ||
689 | }; | 719 | }; |
690 | 720 | ||
691 | /* standard clock definitions */ | 721 | /* standard clock definitions */ |