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-rw-r--r--arch/arm/mach-s3c2412/clock.c52
-rw-r--r--arch/arm/mach-s3c2440/clock.c6
-rw-r--r--arch/arm/mach-s3c2442/clock.c6
-rw-r--r--arch/arm/mach-s3c2443/clock.c88
-rw-r--r--arch/arm/plat-s3c/clock.c31
-rw-r--r--arch/arm/plat-s3c/pwm-clock.c94
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c22
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-clock.c4
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c14
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c8
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c126
-rw-r--r--arch/arm/plat-samsung/clock-clksrc.c17
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h29
13 files changed, 286 insertions, 211 deletions
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index a037df5e1c2d..0c0505b025cb 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -124,7 +124,9 @@ static struct clk clk_usysclk = {
124 .name = "usysclk", 124 .name = "usysclk",
125 .id = -1, 125 .id = -1,
126 .parent = &clk_xtal, 126 .parent = &clk_xtal,
127 .set_parent = s3c2412_setparent_usysclk, 127 .ops = &(struct clk_ops) {
128 .set_parent = s3c2412_setparent_usysclk,
129 },
128}; 130};
129 131
130static struct clk clk_mrefclk = { 132static struct clk clk_mrefclk = {
@@ -199,10 +201,12 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
199static struct clk clk_usbsrc = { 201static struct clk clk_usbsrc = {
200 .name = "usbsrc", 202 .name = "usbsrc",
201 .id = -1, 203 .id = -1,
202 .get_rate = s3c2412_getrate_usbsrc, 204 .ops = &(struct clk_ops) {
203 .set_rate = s3c2412_setrate_usbsrc, 205 .get_rate = s3c2412_getrate_usbsrc,
204 .round_rate = s3c2412_roundrate_usbsrc, 206 .set_rate = s3c2412_setrate_usbsrc,
205 .set_parent = s3c2412_setparent_usbsrc, 207 .round_rate = s3c2412_roundrate_usbsrc,
208 .set_parent = s3c2412_setparent_usbsrc,
209 },
206}; 210};
207 211
208static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) 212static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
@@ -225,7 +229,9 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
225static struct clk clk_msysclk = { 229static struct clk clk_msysclk = {
226 .name = "msysclk", 230 .name = "msysclk",
227 .id = -1, 231 .id = -1,
228 .set_parent = s3c2412_setparent_msysclk, 232 .ops = &(struct clk_ops) {
233 .set_parent = s3c2412_setparent_msysclk,
234 },
229}; 235};
230 236
231static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) 237static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
@@ -264,7 +270,9 @@ static struct clk clk_armclk = {
264 .name = "armclk", 270 .name = "armclk",
265 .id = -1, 271 .id = -1,
266 .parent = &clk_msysclk, 272 .parent = &clk_msysclk,
267 .set_parent = s3c2412_setparent_armclk, 273 .ops = &(struct clk_ops) {
274 .set_parent = s3c2412_setparent_armclk,
275 },
268}; 276};
269 277
270/* these next clocks have an divider immediately after them, 278/* these next clocks have an divider immediately after them,
@@ -337,10 +345,12 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
337static struct clk clk_uart = { 345static struct clk clk_uart = {
338 .name = "uartclk", 346 .name = "uartclk",
339 .id = -1, 347 .id = -1,
340 .get_rate = s3c2412_getrate_uart, 348 .ops = &(struct clk_ops) {
341 .set_rate = s3c2412_setrate_uart, 349 .get_rate = s3c2412_getrate_uart,
342 .set_parent = s3c2412_setparent_uart, 350 .set_rate = s3c2412_setrate_uart,
343 .round_rate = s3c2412_roundrate_clksrc, 351 .set_parent = s3c2412_setparent_uart,
352 .round_rate = s3c2412_roundrate_clksrc,
353 },
344}; 354};
345 355
346static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) 356static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
@@ -388,10 +398,12 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
388static struct clk clk_i2s = { 398static struct clk clk_i2s = {
389 .name = "i2sclk", 399 .name = "i2sclk",
390 .id = -1, 400 .id = -1,
391 .get_rate = s3c2412_getrate_i2s, 401 .ops = &(struct clk_ops) {
392 .set_rate = s3c2412_setrate_i2s, 402 .get_rate = s3c2412_getrate_i2s,
393 .set_parent = s3c2412_setparent_i2s, 403 .set_rate = s3c2412_setrate_i2s,
394 .round_rate = s3c2412_roundrate_clksrc, 404 .set_parent = s3c2412_setparent_i2s,
405 .round_rate = s3c2412_roundrate_clksrc,
406 },
395}; 407};
396 408
397static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) 409static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
@@ -438,10 +450,12 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
438static struct clk clk_cam = { 450static struct clk clk_cam = {
439 .name = "camif-upll", /* same as 2440 name */ 451 .name = "camif-upll", /* same as 2440 name */
440 .id = -1, 452 .id = -1,
441 .get_rate = s3c2412_getrate_cam, 453 .ops = &(struct clk_ops) {
442 .set_rate = s3c2412_setrate_cam, 454 .get_rate = s3c2412_getrate_cam,
443 .set_parent = s3c2412_setparent_cam, 455 .set_rate = s3c2412_setrate_cam,
444 .round_rate = s3c2412_roundrate_clksrc, 456 .set_parent = s3c2412_setparent_cam,
457 .round_rate = s3c2412_roundrate_clksrc,
458 },
445}; 459};
446 460
447/* standard clock definitions */ 461/* standard clock definitions */
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index d1c29b2537cd..3dc2426e2345 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -98,8 +98,10 @@ static struct clk s3c2440_clk_cam = {
98static struct clk s3c2440_clk_cam_upll = { 98static struct clk s3c2440_clk_cam_upll = {
99 .name = "camif-upll", 99 .name = "camif-upll",
100 .id = -1, 100 .id = -1,
101 .set_rate = s3c2440_camif_upll_setrate, 101 .ops = &(struct clk_ops) {
102 .round_rate = s3c2440_camif_upll_round, 102 .set_rate = s3c2440_camif_upll_setrate,
103 .round_rate = s3c2440_camif_upll_round,
104 },
103}; 105};
104 106
105static struct clk s3c2440_clk_ac97 = { 107static struct clk s3c2440_clk_ac97 = {
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
index ea1aa1f5157a..d9b692a12480 100644
--- a/arch/arm/mach-s3c2442/clock.c
+++ b/arch/arm/mach-s3c2442/clock.c
@@ -109,8 +109,10 @@ static struct clk s3c2442_clk_cam = {
109static struct clk s3c2442_clk_cam_upll = { 109static struct clk s3c2442_clk_cam_upll = {
110 .name = "camif-upll", 110 .name = "camif-upll",
111 .id = -1, 111 .id = -1,
112 .set_rate = s3c2442_camif_upll_setrate, 112 .ops = &(struct clk_ops) {
113 .round_rate = s3c2442_camif_upll_round, 113 .set_rate = s3c2442_camif_upll_setrate,
114 .round_rate = s3c2442_camif_upll_round,
115 },
114}; 116};
115 117
116static int s3c2442_clk_add(struct sys_device *sysdev) 118static int s3c2442_clk_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 2785d69c95b0..91db4f54bb33 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent)
187static struct clk clk_epllref = { 187static struct clk clk_epllref = {
188 .name = "epllref", 188 .name = "epllref",
189 .id = -1, 189 .id = -1,
190 .set_parent = s3c2443_setparent_epllref, 190 .ops = &(struct clk_ops) {
191 .set_parent = s3c2443_setparent_epllref,
192 },
191}; 193};
192 194
193static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) 195static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
@@ -205,7 +207,9 @@ static struct clk clk_mdivclk = {
205 .name = "mdivclk", 207 .name = "mdivclk",
206 .parent = &clk_mpllref, 208 .parent = &clk_mpllref,
207 .id = -1, 209 .id = -1,
208 .get_rate = s3c2443_getrate_mdivclk, 210 .ops = &(struct clk_ops) {
211 .get_rate = s3c2443_getrate_mdivclk,
212 },
209}; 213};
210 214
211static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) 215static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
@@ -232,7 +236,9 @@ static struct clk clk_msysclk = {
232 .name = "msysclk", 236 .name = "msysclk",
233 .parent = &clk_xtal, 237 .parent = &clk_xtal,
234 .id = -1, 238 .id = -1,
235 .set_parent = s3c2443_setparent_msysclk, 239 .ops = &(struct clk_ops) {
240 .set_parent = s3c2443_setparent_msysclk,
241 },
236}; 242};
237 243
238/* armdiv 244/* armdiv
@@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
273static struct clk clk_arm = { 279static struct clk clk_arm = {
274 .name = "armclk", 280 .name = "armclk",
275 .id = -1, 281 .id = -1,
276 .set_parent = s3c2443_setparent_armclk, 282 .ops = &(struct clk_ops) {
283 .set_parent = s3c2443_setparent_armclk,
284 },
277}; 285};
278 286
279/* esysclk 287/* esysclk
@@ -302,7 +310,9 @@ static struct clk clk_esysclk = {
302 .name = "esysclk", 310 .name = "esysclk",
303 .parent = &clk_epll, 311 .parent = &clk_epll,
304 .id = -1, 312 .id = -1,
305 .set_parent = s3c2443_setparent_esysclk, 313 .ops = &(struct clk_ops) {
314 .set_parent = s3c2443_setparent_esysclk,
315 },
306}; 316};
307 317
308/* uartclk 318/* uartclk
@@ -341,9 +351,11 @@ static struct clk clk_uart = {
341 .name = "uartclk", 351 .name = "uartclk",
342 .id = -1, 352 .id = -1,
343 .parent = &clk_esysclk, 353 .parent = &clk_esysclk,
344 .get_rate = s3c2443_getrate_uart, 354 .ops = &(struct clk_ops) {
345 .set_rate = s3c2443_setrate_uart, 355 .get_rate = s3c2443_getrate_uart,
346 .round_rate = s3c2443_roundrate_clksrc16, 356 .set_rate = s3c2443_setrate_uart,
357 .round_rate = s3c2443_roundrate_clksrc16,
358 },
347}; 359};
348 360
349/* hsspi 361/* hsspi
@@ -384,9 +396,11 @@ static struct clk clk_hsspi = {
384 .parent = &clk_esysclk, 396 .parent = &clk_esysclk,
385 .ctrlbit = S3C2443_SCLKCON_HSSPICLK, 397 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
386 .enable = s3c2443_clkcon_enable_s, 398 .enable = s3c2443_clkcon_enable_s,
387 .get_rate = s3c2443_getrate_hsspi, 399 .ops = &(struct clk_ops) {
388 .set_rate = s3c2443_setrate_hsspi, 400 .get_rate = s3c2443_getrate_hsspi,
389 .round_rate = s3c2443_roundrate_clksrc4, 401 .set_rate = s3c2443_setrate_hsspi,
402 .round_rate = s3c2443_roundrate_clksrc4,
403 },
390}; 404};
391 405
392/* usbhost 406/* usbhost
@@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = {
426 .parent = &clk_esysclk, 440 .parent = &clk_esysclk,
427 .ctrlbit = S3C2443_SCLKCON_USBHOST, 441 .ctrlbit = S3C2443_SCLKCON_USBHOST,
428 .enable = s3c2443_clkcon_enable_s, 442 .enable = s3c2443_clkcon_enable_s,
429 .get_rate = s3c2443_getrate_usbhost, 443 .ops = &(struct clk_ops) {
430 .set_rate = s3c2443_setrate_usbhost, 444 .get_rate = s3c2443_getrate_usbhost,
431 .round_rate = s3c2443_roundrate_clksrc4, 445 .set_rate = s3c2443_setrate_usbhost,
446 .round_rate = s3c2443_roundrate_clksrc4,
447 },
432}; 448};
433 449
434/* clk_hsmcc_div 450/* clk_hsmcc_div
@@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = {
468 .name = "hsmmc-div", 484 .name = "hsmmc-div",
469 .id = -1, 485 .id = -1,
470 .parent = &clk_esysclk, 486 .parent = &clk_esysclk,
471 .get_rate = s3c2443_getrate_hsmmc_div, 487 .ops = &(struct clk_ops) {
472 .set_rate = s3c2443_setrate_hsmmc_div, 488 .get_rate = s3c2443_getrate_hsmmc_div,
473 .round_rate = s3c2443_roundrate_clksrc4, 489 .set_rate = s3c2443_setrate_hsmmc_div,
490 .round_rate = s3c2443_roundrate_clksrc4,
491 },
474}; 492};
475 493
476static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) 494static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
@@ -505,7 +523,9 @@ static struct clk clk_hsmmc = {
505 .id = -1, 523 .id = -1,
506 .parent = &clk_hsmmc_div, 524 .parent = &clk_hsmmc_div,
507 .enable = s3c2443_enable_hsmmc, 525 .enable = s3c2443_enable_hsmmc,
508 .set_parent = s3c2443_setparent_hsmmc, 526 .ops = &(struct clk_ops) {
527 .set_parent = s3c2443_setparent_hsmmc,
528 },
509}; 529};
510 530
511/* i2s_eplldiv 531/* i2s_eplldiv
@@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = {
543 .name = "i2s-eplldiv", 563 .name = "i2s-eplldiv",
544 .id = -1, 564 .id = -1,
545 .parent = &clk_esysclk, 565 .parent = &clk_esysclk,
546 .get_rate = s3c2443_getrate_i2s_eplldiv, 566 .ops = &(struct clk_ops) {
547 .set_rate = s3c2443_setrate_i2s_eplldiv, 567 .get_rate = s3c2443_getrate_i2s_eplldiv,
548 .round_rate = s3c2443_roundrate_clksrc16, 568 .set_rate = s3c2443_setrate_i2s_eplldiv,
569 .round_rate = s3c2443_roundrate_clksrc16,
570 },
549}; 571};
550 572
551/* i2s-ref 573/* i2s-ref
@@ -578,7 +600,9 @@ static struct clk clk_i2s = {
578 .parent = &clk_i2s_eplldiv, 600 .parent = &clk_i2s_eplldiv,
579 .ctrlbit = S3C2443_SCLKCON_I2SCLK, 601 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
580 .enable = s3c2443_clkcon_enable_s, 602 .enable = s3c2443_clkcon_enable_s,
581 .set_parent = s3c2443_setparent_i2s, 603 .ops = &(struct clk_ops) {
604 .set_parent = s3c2443_setparent_i2s,
605 },
582}; 606};
583 607
584/* cam-if 608/* cam-if
@@ -618,9 +642,11 @@ static struct clk clk_cam = {
618 .parent = &clk_esysclk, 642 .parent = &clk_esysclk,
619 .ctrlbit = S3C2443_SCLKCON_CAMCLK, 643 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
620 .enable = s3c2443_clkcon_enable_s, 644 .enable = s3c2443_clkcon_enable_s,
621 .get_rate = s3c2443_getrate_cam, 645 .ops = &(struct clk_ops) {
622 .set_rate = s3c2443_setrate_cam, 646 .get_rate = s3c2443_getrate_cam,
623 .round_rate = s3c2443_roundrate_clksrc16, 647 .set_rate = s3c2443_setrate_cam,
648 .round_rate = s3c2443_roundrate_clksrc16,
649 },
624}; 650};
625 651
626/* display-if 652/* display-if
@@ -660,9 +686,11 @@ static struct clk clk_display = {
660 .parent = &clk_esysclk, 686 .parent = &clk_esysclk,
661 .ctrlbit = S3C2443_SCLKCON_DISPCLK, 687 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
662 .enable = s3c2443_clkcon_enable_s, 688 .enable = s3c2443_clkcon_enable_s,
663 .get_rate = s3c2443_getrate_display, 689 .ops = &(struct clk_ops) {
664 .set_rate = s3c2443_setrate_display, 690 .get_rate = s3c2443_getrate_display,
665 .round_rate = s3c2443_roundrate_clksrc256, 691 .set_rate = s3c2443_setrate_display,
692 .round_rate = s3c2443_roundrate_clksrc256,
693 },
666}; 694};
667 695
668/* prediv 696/* prediv
@@ -685,7 +713,9 @@ static struct clk clk_prediv = {
685 .name = "prediv", 713 .name = "prediv",
686 .id = -1, 714 .id = -1,
687 .parent = &clk_msysclk, 715 .parent = &clk_msysclk,
688 .get_rate = s3c2443_prediv_getrate, 716 .ops = &(struct clk_ops) {
717 .get_rate = s3c2443_prediv_getrate,
718 },
689}; 719};
690 720
691/* standard clock definitions */ 721/* standard clock definitions */
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
index 619cfa82dcab..fa91125c7e0e 100644
--- a/arch/arm/plat-s3c/clock.c
+++ b/arch/arm/plat-s3c/clock.c
@@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk)
150 if (clk->rate != 0) 150 if (clk->rate != 0)
151 return clk->rate; 151 return clk->rate;
152 152
153 if (clk->get_rate != NULL) 153 if (clk->ops != NULL && clk->ops->get_rate != NULL)
154 return (clk->get_rate)(clk); 154 return (clk->ops->get_rate)(clk);
155 155
156 if (clk->parent != NULL) 156 if (clk->parent != NULL)
157 return clk_get_rate(clk->parent); 157 return clk_get_rate(clk->parent);
@@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk)
161 161
162long clk_round_rate(struct clk *clk, unsigned long rate) 162long clk_round_rate(struct clk *clk, unsigned long rate)
163{ 163{
164 if (!IS_ERR(clk) && clk->round_rate) 164 if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
165 return (clk->round_rate)(clk, rate); 165 return (clk->ops->round_rate)(clk, rate);
166 166
167 return rate; 167 return rate;
168} 168}
@@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
178 * the clock may have been made this way by choice. 178 * the clock may have been made this way by choice.
179 */ 179 */
180 180
181 WARN_ON(clk->set_rate == NULL); 181 WARN_ON(clk->ops == NULL);
182 WARN_ON(clk->ops && clk->ops->set_rate == NULL);
182 183
183 if (clk->set_rate == NULL) 184 if (clk->ops == NULL || clk->ops->set_rate == NULL)
184 return -EINVAL; 185 return -EINVAL;
185 186
186 spin_lock(&clocks_lock); 187 spin_lock(&clocks_lock);
187 ret = (clk->set_rate)(clk, rate); 188 ret = (clk->ops->set_rate)(clk, rate);
188 spin_unlock(&clocks_lock); 189 spin_unlock(&clocks_lock);
189 190
190 return ret; 191 return ret;
@@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
204 205
205 spin_lock(&clocks_lock); 206 spin_lock(&clocks_lock);
206 207
207 if (clk->set_parent) 208 if (clk->ops && clk->ops->set_parent)
208 ret = (clk->set_parent)(clk, parent); 209 ret = (clk->ops->set_parent)(clk, parent);
209 210
210 spin_unlock(&clocks_lock); 211 spin_unlock(&clocks_lock);
211 212
@@ -230,6 +231,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate)
230 return 0; 231 return 0;
231} 232}
232 233
234static struct clk_ops clk_ops_def_setrate = {
235 .set_rate = clk_default_setrate,
236};
237
233struct clk clk_xtal = { 238struct clk clk_xtal = {
234 .name = "xtal", 239 .name = "xtal",
235 .id = -1, 240 .id = -1,
@@ -251,7 +256,7 @@ struct clk clk_epll = {
251struct clk clk_mpll = { 256struct clk clk_mpll = {
252 .name = "mpll", 257 .name = "mpll",
253 .id = -1, 258 .id = -1,
254 .set_rate = clk_default_setrate, 259 .ops = &clk_ops_def_setrate,
255}; 260};
256 261
257struct clk clk_upll = { 262struct clk clk_upll = {
@@ -267,7 +272,6 @@ struct clk clk_f = {
267 .rate = 0, 272 .rate = 0,
268 .parent = &clk_mpll, 273 .parent = &clk_mpll,
269 .ctrlbit = 0, 274 .ctrlbit = 0,
270 .set_rate = clk_default_setrate,
271}; 275};
272 276
273struct clk clk_h = { 277struct clk clk_h = {
@@ -276,7 +280,7 @@ struct clk clk_h = {
276 .rate = 0, 280 .rate = 0,
277 .parent = NULL, 281 .parent = NULL,
278 .ctrlbit = 0, 282 .ctrlbit = 0,
279 .set_rate = clk_default_setrate, 283 .ops = &clk_ops_def_setrate,
280}; 284};
281 285
282struct clk clk_p = { 286struct clk clk_p = {
@@ -285,7 +289,7 @@ struct clk clk_p = {
285 .rate = 0, 289 .rate = 0,
286 .parent = NULL, 290 .parent = NULL,
287 .ctrlbit = 0, 291 .ctrlbit = 0,
288 .set_rate = clk_default_setrate, 292 .ops = &clk_ops_def_setrate,
289}; 293};
290 294
291struct clk clk_usb_bus = { 295struct clk clk_usb_bus = {
@@ -296,7 +300,6 @@ struct clk clk_usb_bus = {
296}; 300};
297 301
298 302
299
300struct clk s3c24xx_uclk = { 303struct clk s3c24xx_uclk = {
301 .name = "uclk", 304 .name = "uclk",
302 .id = -1, 305 .id = -1,
diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c
index a318215ab535..1808fa88609a 100644
--- a/arch/arm/plat-s3c/pwm-clock.c
+++ b/arch/arm/plat-s3c/pwm-clock.c
@@ -130,20 +130,22 @@ static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
130 return 0; 130 return 0;
131} 131}
132 132
133static struct clk_ops clk_pwm_scaler_ops = {
134 .get_rate = clk_pwm_scaler_get_rate,
135 .set_rate = clk_pwm_scaler_set_rate,
136 .round_rate = clk_pwm_scaler_round_rate,
137};
138
133static struct clk clk_timer_scaler[] = { 139static struct clk clk_timer_scaler[] = {
134 [0] = { 140 [0] = {
135 .name = "pwm-scaler0", 141 .name = "pwm-scaler0",
136 .id = -1, 142 .id = -1,
137 .get_rate = clk_pwm_scaler_get_rate, 143 .ops = &clk_pwm_scaler_ops,
138 .set_rate = clk_pwm_scaler_set_rate,
139 .round_rate = clk_pwm_scaler_round_rate,
140 }, 144 },
141 [1] = { 145 [1] = {
142 .name = "pwm-scaler1", 146 .name = "pwm-scaler1",
143 .id = -1, 147 .id = -1,
144 .get_rate = clk_pwm_scaler_get_rate, 148 .ops = &clk_pwm_scaler_ops,
145 .set_rate = clk_pwm_scaler_set_rate,
146 .round_rate = clk_pwm_scaler_round_rate,
147 }, 149 },
148}; 150};
149 151
@@ -256,50 +258,46 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
256 return 0; 258 return 0;
257} 259}
258 260
261static struct clk_ops clk_tdiv_ops = {
262 .get_rate = clk_pwm_tdiv_get_rate,
263 .set_rate = clk_pwm_tdiv_set_rate,
264 .round_rate = clk_pwm_tdiv_round_rate,
265};
266
259static struct pwm_tdiv_clk clk_timer_tdiv[] = { 267static struct pwm_tdiv_clk clk_timer_tdiv[] = {
260 [0] = { 268 [0] = {
261 .clk = { 269 .clk = {
262 .name = "pwm-tdiv", 270 .name = "pwm-tdiv",
263 .parent = &clk_timer_scaler[0], 271 .ops = &clk_tdiv_ops,
264 .get_rate = clk_pwm_tdiv_get_rate, 272 .parent = &clk_timer_scaler[0],
265 .set_rate = clk_pwm_tdiv_set_rate,
266 .round_rate = clk_pwm_tdiv_round_rate,
267 }, 273 },
268 }, 274 },
269 [1] = { 275 [1] = {
270 .clk = { 276 .clk = {
271 .name = "pwm-tdiv", 277 .name = "pwm-tdiv",
272 .parent = &clk_timer_scaler[0], 278 .ops = &clk_tdiv_ops,
273 .get_rate = clk_pwm_tdiv_get_rate, 279 .parent = &clk_timer_scaler[0],
274 .set_rate = clk_pwm_tdiv_set_rate,
275 .round_rate = clk_pwm_tdiv_round_rate,
276 } 280 }
277 }, 281 },
278 [2] = { 282 [2] = {
279 .clk = { 283 .clk = {
280 .name = "pwm-tdiv", 284 .name = "pwm-tdiv",
281 .parent = &clk_timer_scaler[1], 285 .ops = &clk_tdiv_ops,
282 .get_rate = clk_pwm_tdiv_get_rate, 286 .parent = &clk_timer_scaler[1],
283 .set_rate = clk_pwm_tdiv_set_rate,
284 .round_rate = clk_pwm_tdiv_round_rate,
285 }, 287 },
286 }, 288 },
287 [3] = { 289 [3] = {
288 .clk = { 290 .clk = {
289 .name = "pwm-tdiv", 291 .name = "pwm-tdiv",
290 .parent = &clk_timer_scaler[1], 292 .ops = &clk_tdiv_ops,
291 .get_rate = clk_pwm_tdiv_get_rate, 293 .parent = &clk_timer_scaler[1],
292 .set_rate = clk_pwm_tdiv_set_rate,
293 .round_rate = clk_pwm_tdiv_round_rate,
294 }, 294 },
295 }, 295 },
296 [4] = { 296 [4] = {
297 .clk = { 297 .clk = {
298 .name = "pwm-tdiv", 298 .name = "pwm-tdiv",
299 .parent = &clk_timer_scaler[1], 299 .ops = &clk_tdiv_ops,
300 .get_rate = clk_pwm_tdiv_get_rate, 300 .parent = &clk_timer_scaler[1],
301 .set_rate = clk_pwm_tdiv_set_rate,
302 .round_rate = clk_pwm_tdiv_round_rate,
303 }, 301 },
304 }, 302 },
305}; 303};
@@ -356,31 +354,35 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
356 return 0; 354 return 0;
357} 355}
358 356
357static struct clk_ops clk_tin_ops = {
358 .set_parent = clk_pwm_tin_set_parent,
359};
360
359static struct clk clk_tin[] = { 361static struct clk clk_tin[] = {
360 [0] = { 362 [0] = {
361 .name = "pwm-tin", 363 .name = "pwm-tin",
362 .id = 0, 364 .id = 0,
363 .set_parent = clk_pwm_tin_set_parent, 365 .ops = &clk_tin_ops,
364 }, 366 },
365 [1] = { 367 [1] = {
366 .name = "pwm-tin", 368 .name = "pwm-tin",
367 .id = 1, 369 .id = 1,
368 .set_parent = clk_pwm_tin_set_parent, 370 .ops = &clk_tin_ops,
369 }, 371 },
370 [2] = { 372 [2] = {
371 .name = "pwm-tin", 373 .name = "pwm-tin",
372 .id = 2, 374 .id = 2,
373 .set_parent = clk_pwm_tin_set_parent, 375 .ops = &clk_tin_ops,
374 }, 376 },
375 [3] = { 377 [3] = {
376 .name = "pwm-tin", 378 .name = "pwm-tin",
377 .id = 3, 379 .id = 3,
378 .set_parent = clk_pwm_tin_set_parent, 380 .ops = &clk_tin_ops,
379 }, 381 },
380 [4] = { 382 [4] = {
381 .name = "pwm-tin", 383 .name = "pwm-tin",
382 .id = 4, 384 .id = 4,
383 .set_parent = clk_pwm_tin_set_parent, 385 .ops = &clk_tin_ops,
384 }, 386 },
385}; 387};
386 388
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index ac061a1bcb37..cf97caafe56b 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -161,14 +161,18 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
161 161
162/* external clock definitions */ 162/* external clock definitions */
163 163
164static struct clk_ops dclk_ops = {
165 .set_parent = s3c24xx_dclk_setparent,
166 .set_rate = s3c24xx_set_dclk_rate,
167 .round_rate = s3c24xx_round_dclk_rate,
168};
169
164struct clk s3c24xx_dclk0 = { 170struct clk s3c24xx_dclk0 = {
165 .name = "dclk0", 171 .name = "dclk0",
166 .id = -1, 172 .id = -1,
167 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 173 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
168 .enable = s3c24xx_dclk_enable, 174 .enable = s3c24xx_dclk_enable,
169 .set_parent = s3c24xx_dclk_setparent, 175 .ops = &dclk_ops,
170 .set_rate = s3c24xx_set_dclk_rate,
171 .round_rate = s3c24xx_round_dclk_rate,
172}; 176};
173 177
174struct clk s3c24xx_dclk1 = { 178struct clk s3c24xx_dclk1 = {
@@ -176,19 +180,21 @@ struct clk s3c24xx_dclk1 = {
176 .id = -1, 180 .id = -1,
177 .ctrlbit = S3C2410_DCLKCON_DCLK1EN, 181 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
178 .enable = s3c24xx_dclk_enable, 182 .enable = s3c24xx_dclk_enable,
179 .set_parent = s3c24xx_dclk_setparent, 183 .ops = &dclk_ops,
180 .set_rate = s3c24xx_set_dclk_rate, 184};
181 .round_rate = s3c24xx_round_dclk_rate, 185
186static struct clk_ops clkout_ops = {
187 .set_parent = s3c24xx_clkout_setparent,
182}; 188};
183 189
184struct clk s3c24xx_clkout0 = { 190struct clk s3c24xx_clkout0 = {
185 .name = "clkout0", 191 .name = "clkout0",
186 .id = -1, 192 .id = -1,
187 .set_parent = s3c24xx_clkout_setparent, 193 .ops = &clkout_ops,
188}; 194};
189 195
190struct clk s3c24xx_clkout1 = { 196struct clk s3c24xx_clkout1 = {
191 .name = "clkout1", 197 .name = "clkout1",
192 .id = -1, 198 .id = -1,
193 .set_parent = s3c24xx_clkout_setparent, 199 .ops = &clkout_ops,
194}; 200};
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index 79371091aa38..f8d96130d1d1 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -68,7 +68,9 @@ static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
68static struct clk clk_arm = { 68static struct clk clk_arm = {
69 .name = "armclk", 69 .name = "armclk",
70 .id = -1, 70 .id = -1,
71 .set_parent = s3c2440_setparent_armclk, 71 .ops = &(struct clk_ops) {
72 .set_parent = s3c2440_setparent_armclk,
73 },
72}; 74};
73 75
74static int s3c244x_clk_add(struct sys_device *sysdev) 76static int s3c244x_clk_add(struct sys_device *sysdev)
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 20af0c29979a..f85406a11385 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -165,9 +165,11 @@ static struct clk clk_arm = {
165 .name = "armclk", 165 .name = "armclk",
166 .id = -1, 166 .id = -1,
167 .parent = &clk_mout_apll.clk, 167 .parent = &clk_mout_apll.clk,
168 .get_rate = s3c64xx_clk_arm_get_rate, 168 .ops = &(struct clk_ops) {
169 .set_rate = s3c64xx_clk_arm_set_rate, 169 .get_rate = s3c64xx_clk_arm_get_rate,
170 .round_rate = s3c64xx_clk_arm_round_rate, 170 .set_rate = s3c64xx_clk_arm_set_rate,
171 .round_rate = s3c64xx_clk_arm_round_rate,
172 },
171}; 173};
172 174
173static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) 175static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
@@ -182,11 +184,15 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
182 return rate; 184 return rate;
183} 185}
184 186
187static struct clk_ops clk_dout_ops = {
188 .get_rate = s3c64xx_clk_doutmpll_get_rate,
189};
190
185static struct clk clk_dout_mpll = { 191static struct clk clk_dout_mpll = {
186 .name = "dout_mpll", 192 .name = "dout_mpll",
187 .id = -1, 193 .id = -1,
188 .parent = &clk_mout_mpll.clk, 194 .parent = &clk_mout_mpll.clk,
189 .get_rate = s3c64xx_clk_doutmpll_get_rate, 195 .ops = &clk_dout_ops,
190}; 196};
191 197
192static struct clk *clkset_spi_mmc_list[] = { 198static struct clk *clkset_spi_mmc_list[] = {
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
index 26c21d849790..2f4d8d4c4e1c 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -70,6 +70,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate)
70 return 0; 70 return 0;
71} 71}
72 72
73static struct clk_ops clk_ops_default_setrate = {
74 .set_rate = clk_default_setrate,
75};
76
73static int clk_dummy_enable(struct clk *clk, int enable) 77static int clk_dummy_enable(struct clk *clk, int enable)
74{ 78{
75 return 0; 79 return 0;
@@ -81,8 +85,8 @@ struct clk clk_hd0 = {
81 .rate = 0, 85 .rate = 0,
82 .parent = NULL, 86 .parent = NULL,
83 .ctrlbit = 0, 87 .ctrlbit = 0,
84 .set_rate = clk_default_setrate,
85 .enable = clk_dummy_enable, 88 .enable = clk_dummy_enable,
89 .ops = &clk_ops_default_setrate,
86}; 90};
87 91
88struct clk clk_pd0 = { 92struct clk clk_pd0 = {
@@ -91,7 +95,7 @@ struct clk clk_pd0 = {
91 .rate = 0, 95 .rate = 0,
92 .parent = NULL, 96 .parent = NULL,
93 .ctrlbit = 0, 97 .ctrlbit = 0,
94 .set_rate = clk_default_setrate, 98 .ops = &clk_ops_default_setrate,
95 .enable = clk_dummy_enable, 99 .enable = clk_dummy_enable,
96}; 100};
97 101
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index b436d44510c8..16f0b9077390 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -111,7 +111,9 @@ static struct clk clk_dout_apll = {
111 .name = "dout_apll", 111 .name = "dout_apll",
112 .id = -1, 112 .id = -1,
113 .parent = &clk_mout_apll.clk, 113 .parent = &clk_mout_apll.clk,
114 .get_rate = s5pc100_clk_dout_apll_get_rate, 114 .ops = &(struct clk_ops) {
115 .get_rate = s5pc100_clk_dout_apll_get_rate,
116 },
115}; 117};
116 118
117static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) 119static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
@@ -165,9 +167,11 @@ static struct clk clk_arm = {
165 .name = "armclk", 167 .name = "armclk",
166 .id = -1, 168 .id = -1,
167 .parent = &clk_dout_apll, 169 .parent = &clk_dout_apll,
168 .get_rate = s5pc100_clk_arm_get_rate, 170 .ops = &(struct clk_ops) {
169 .set_rate = s5pc100_clk_arm_set_rate, 171 .get_rate = s5pc100_clk_arm_get_rate,
170 .round_rate = s5pc100_clk_arm_round_rate, 172 .set_rate = s5pc100_clk_arm_set_rate,
173 .round_rate = s5pc100_clk_arm_round_rate,
174 },
171}; 175};
172 176
173static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) 177static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
@@ -185,7 +189,9 @@ static struct clk clk_dout_d0_bus = {
185 .name = "dout_d0_bus", 189 .name = "dout_d0_bus",
186 .id = -1, 190 .id = -1,
187 .parent = &clk_arm, 191 .parent = &clk_arm,
188 .get_rate = s5pc100_clk_dout_d0_bus_get_rate, 192 .ops = &(struct clk_ops) {
193 .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
194 },
189}; 195};
190 196
191static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) 197static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
@@ -203,7 +209,9 @@ static struct clk clk_dout_pclkd0 = {
203 .name = "dout_pclkd0", 209 .name = "dout_pclkd0",
204 .id = -1, 210 .id = -1,
205 .parent = &clk_dout_d0_bus, 211 .parent = &clk_dout_d0_bus,
206 .get_rate = s5pc100_clk_dout_pclkd0_get_rate, 212 .ops = &(struct clk_ops) {
213 .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
214 },
207}; 215};
208 216
209static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) 217static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
@@ -221,7 +229,9 @@ static struct clk clk_dout_apll2 = {
221 .name = "dout_apll2", 229 .name = "dout_apll2",
222 .id = -1, 230 .id = -1,
223 .parent = &clk_mout_apll.clk, 231 .parent = &clk_mout_apll.clk,
224 .get_rate = s5pc100_clk_dout_apll2_get_rate, 232 .ops = &(struct clk_ops) {
233 .get_rate = s5pc100_clk_dout_apll2_get_rate,
234 },
225}; 235};
226 236
227/* MPLL */ 237/* MPLL */
@@ -284,7 +294,9 @@ static struct clk clk_dout_d1_bus = {
284 .name = "dout_d1_bus", 294 .name = "dout_d1_bus",
285 .id = -1, 295 .id = -1,
286 .parent = &clk_mout_am.clk, 296 .parent = &clk_mout_am.clk,
287 .get_rate = s5pc100_clk_dout_d1_bus_get_rate, 297 .ops = &(struct clk_ops) {
298 .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
299 },
288}; 300};
289 301
290static struct clk *clkset_onenand_list[] = { 302static struct clk *clkset_onenand_list[] = {
@@ -325,7 +337,9 @@ static struct clk clk_dout_pclkd1 = {
325 .name = "dout_pclkd1", 337 .name = "dout_pclkd1",
326 .id = -1, 338 .id = -1,
327 .parent = &clk_dout_d1_bus, 339 .parent = &clk_dout_d1_bus,
328 .get_rate = s5pc100_clk_dout_pclkd1_get_rate, 340 .ops = &(struct clk_ops) {
341 .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
342 },
329}; 343};
330 344
331static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) 345static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
@@ -345,7 +359,9 @@ static struct clk clk_dout_mpll2 = {
345 .name = "dout_mpll2", 359 .name = "dout_mpll2",
346 .id = -1, 360 .id = -1,
347 .parent = &clk_mout_am.clk, 361 .parent = &clk_mout_am.clk,
348 .get_rate = s5pc100_clk_dout_mpll2_get_rate, 362 .ops = &(struct clk_ops) {
363 .get_rate = s5pc100_clk_dout_mpll2_get_rate,
364 },
349}; 365};
350 366
351static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) 367static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
@@ -365,7 +381,9 @@ static struct clk clk_dout_cam = {
365 .name = "dout_cam", 381 .name = "dout_cam",
366 .id = -1, 382 .id = -1,
367 .parent = &clk_dout_mpll2, 383 .parent = &clk_dout_mpll2,
368 .get_rate = s5pc100_clk_dout_cam_get_rate, 384 .ops = &(struct clk_ops) {
385 .get_rate = s5pc100_clk_dout_cam_get_rate,
386 },
369}; 387};
370 388
371static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) 389static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
@@ -385,7 +403,9 @@ static struct clk clk_dout_mpll = {
385 .name = "dout_mpll", 403 .name = "dout_mpll",
386 .id = -1, 404 .id = -1,
387 .parent = &clk_mout_am.clk, 405 .parent = &clk_mout_am.clk,
388 .get_rate = s5pc100_clk_dout_mpll_get_rate, 406 .ops = &(struct clk_ops) {
407 .get_rate = s5pc100_clk_dout_mpll_get_rate,
408 },
389}; 409};
390 410
391/* EPLL */ 411/* EPLL */
@@ -540,6 +560,13 @@ static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
540 return rate; 560 return rate;
541} 561}
542 562
563static struct clk_ops s5pc100_clksrc_ops = {
564 .set_parent = s5pc100_setparent_clksrc,
565 .get_rate = s5pc100_getrate_clksrc,
566 .set_rate = s5pc100_setrate_clksrc,
567 .round_rate = s5pc100_roundrate_clksrc,
568};
569
543static struct clk *clkset_spi_list[] = { 570static struct clk *clkset_spi_list[] = {
544 &clk_mout_epll.clk, 571 &clk_mout_epll.clk,
545 &clk_dout_mpll2, 572 &clk_dout_mpll2,
@@ -558,10 +585,7 @@ static struct clksrc_clk clk_spi0 = {
558 .id = 0, 585 .id = 0,
559 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, 586 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
560 .enable = s5pc100_sclk0_ctrl, 587 .enable = s5pc100_sclk0_ctrl,
561 .set_parent = s5pc100_setparent_clksrc, 588
562 .get_rate = s5pc100_getrate_clksrc,
563 .set_rate = s5pc100_setrate_clksrc,
564 .round_rate = s5pc100_roundrate_clksrc,
565 }, 589 },
566 .shift = S5PC100_CLKSRC1_SPI0_SHIFT, 590 .shift = S5PC100_CLKSRC1_SPI0_SHIFT,
567 .mask = S5PC100_CLKSRC1_SPI0_MASK, 591 .mask = S5PC100_CLKSRC1_SPI0_MASK,
@@ -577,10 +601,7 @@ static struct clksrc_clk clk_spi1 = {
577 .id = 1, 601 .id = 1,
578 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, 602 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
579 .enable = s5pc100_sclk0_ctrl, 603 .enable = s5pc100_sclk0_ctrl,
580 .set_parent = s5pc100_setparent_clksrc, 604 .ops = &s5pc100_clksrc_ops,
581 .get_rate = s5pc100_getrate_clksrc,
582 .set_rate = s5pc100_setrate_clksrc,
583 .round_rate = s5pc100_roundrate_clksrc,
584 }, 605 },
585 .shift = S5PC100_CLKSRC1_SPI1_SHIFT, 606 .shift = S5PC100_CLKSRC1_SPI1_SHIFT,
586 .mask = S5PC100_CLKSRC1_SPI1_MASK, 607 .mask = S5PC100_CLKSRC1_SPI1_MASK,
@@ -596,10 +617,7 @@ static struct clksrc_clk clk_spi2 = {
596 .id = 2, 617 .id = 2,
597 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, 618 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
598 .enable = s5pc100_sclk0_ctrl, 619 .enable = s5pc100_sclk0_ctrl,
599 .set_parent = s5pc100_setparent_clksrc, 620 .ops = &s5pc100_clksrc_ops,
600 .get_rate = s5pc100_getrate_clksrc,
601 .set_rate = s5pc100_setrate_clksrc,
602 .round_rate = s5pc100_roundrate_clksrc,
603 }, 621 },
604 .shift = S5PC100_CLKSRC1_SPI2_SHIFT, 622 .shift = S5PC100_CLKSRC1_SPI2_SHIFT,
605 .mask = S5PC100_CLKSRC1_SPI2_MASK, 623 .mask = S5PC100_CLKSRC1_SPI2_MASK,
@@ -625,10 +643,7 @@ static struct clksrc_clk clk_uart_uclk1 = {
625 .id = -1, 643 .id = -1,
626 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, 644 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
627 .enable = s5pc100_sclk0_ctrl, 645 .enable = s5pc100_sclk0_ctrl,
628 .set_parent = s5pc100_setparent_clksrc, 646 .ops = &s5pc100_clksrc_ops,
629 .get_rate = s5pc100_getrate_clksrc,
630 .set_rate = s5pc100_setrate_clksrc,
631 .round_rate = s5pc100_roundrate_clksrc,
632 }, 647 },
633 .shift = S5PC100_CLKSRC1_UART_SHIFT, 648 .shift = S5PC100_CLKSRC1_UART_SHIFT,
634 .mask = S5PC100_CLKSRC1_UART_MASK, 649 .mask = S5PC100_CLKSRC1_UART_MASK,
@@ -683,10 +698,7 @@ static struct clksrc_clk clk_audio0 = {
683 .id = 0, 698 .id = 0,
684 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, 699 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
685 .enable = s5pc100_sclk1_ctrl, 700 .enable = s5pc100_sclk1_ctrl,
686 .set_parent = s5pc100_setparent_clksrc, 701 .ops = &s5pc100_clksrc_ops,
687 .get_rate = s5pc100_getrate_clksrc,
688 .set_rate = s5pc100_setrate_clksrc,
689 .round_rate = s5pc100_roundrate_clksrc,
690 }, 702 },
691 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, 703 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT,
692 .mask = S5PC100_CLKSRC3_AUDIO0_MASK, 704 .mask = S5PC100_CLKSRC3_AUDIO0_MASK,
@@ -716,10 +728,7 @@ static struct clksrc_clk clk_audio1 = {
716 .id = 1, 728 .id = 1,
717 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, 729 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
718 .enable = s5pc100_sclk1_ctrl, 730 .enable = s5pc100_sclk1_ctrl,
719 .set_parent = s5pc100_setparent_clksrc, 731 .ops = &s5pc100_clksrc_ops,
720 .get_rate = s5pc100_getrate_clksrc,
721 .set_rate = s5pc100_setrate_clksrc,
722 .round_rate = s5pc100_roundrate_clksrc,
723 }, 732 },
724 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, 733 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
725 .mask = S5PC100_CLKSRC3_AUDIO1_MASK, 734 .mask = S5PC100_CLKSRC3_AUDIO1_MASK,
@@ -748,10 +757,7 @@ static struct clksrc_clk clk_audio2 = {
748 .id = 2, 757 .id = 2,
749 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, 758 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
750 .enable = s5pc100_sclk1_ctrl, 759 .enable = s5pc100_sclk1_ctrl,
751 .set_parent = s5pc100_setparent_clksrc, 760 .ops = &s5pc100_clksrc_ops,
752 .get_rate = s5pc100_getrate_clksrc,
753 .set_rate = s5pc100_setrate_clksrc,
754 .round_rate = s5pc100_roundrate_clksrc,
755 }, 761 },
756 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, 762 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
757 .mask = S5PC100_CLKSRC3_AUDIO2_MASK, 763 .mask = S5PC100_CLKSRC3_AUDIO2_MASK,
@@ -801,10 +807,7 @@ static struct clksrc_clk clk_lcd = {
801 .id = -1, 807 .id = -1,
802 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, 808 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
803 .enable = s5pc100_sclk1_ctrl, 809 .enable = s5pc100_sclk1_ctrl,
804 .set_parent = s5pc100_setparent_clksrc, 810 .ops = &s5pc100_clksrc_ops,
805 .get_rate = s5pc100_getrate_clksrc,
806 .set_rate = s5pc100_setrate_clksrc,
807 .round_rate = s5pc100_roundrate_clksrc,
808 }, 811 },
809 .shift = S5PC100_CLKSRC2_LCD_SHIFT, 812 .shift = S5PC100_CLKSRC2_LCD_SHIFT,
810 .mask = S5PC100_CLKSRC2_LCD_MASK, 813 .mask = S5PC100_CLKSRC2_LCD_MASK,
@@ -820,10 +823,7 @@ static struct clksrc_clk clk_fimc0 = {
820 .id = 0, 823 .id = 0,
821 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, 824 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
822 .enable = s5pc100_sclk1_ctrl, 825 .enable = s5pc100_sclk1_ctrl,
823 .set_parent = s5pc100_setparent_clksrc, 826 .ops = &s5pc100_clksrc_ops,
824 .get_rate = s5pc100_getrate_clksrc,
825 .set_rate = s5pc100_setrate_clksrc,
826 .round_rate = s5pc100_roundrate_clksrc,
827 }, 827 },
828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, 828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
829 .mask = S5PC100_CLKSRC2_FIMC0_MASK, 829 .mask = S5PC100_CLKSRC2_FIMC0_MASK,
@@ -839,10 +839,7 @@ static struct clksrc_clk clk_fimc1 = {
839 .id = 1, 839 .id = 1,
840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, 840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
841 .enable = s5pc100_sclk1_ctrl, 841 .enable = s5pc100_sclk1_ctrl,
842 .set_parent = s5pc100_setparent_clksrc, 842 .ops = &s5pc100_clksrc_ops,
843 .get_rate = s5pc100_getrate_clksrc,
844 .set_rate = s5pc100_setrate_clksrc,
845 .round_rate = s5pc100_roundrate_clksrc,
846 }, 843 },
847 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, 844 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
848 .mask = S5PC100_CLKSRC2_FIMC1_MASK, 845 .mask = S5PC100_CLKSRC2_FIMC1_MASK,
@@ -858,10 +855,7 @@ static struct clksrc_clk clk_fimc2 = {
858 .id = 2, 855 .id = 2,
859 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, 856 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
860 .enable = s5pc100_sclk1_ctrl, 857 .enable = s5pc100_sclk1_ctrl,
861 .set_parent = s5pc100_setparent_clksrc, 858 .ops = &s5pc100_clksrc_ops,
862 .get_rate = s5pc100_getrate_clksrc,
863 .set_rate = s5pc100_setrate_clksrc,
864 .round_rate = s5pc100_roundrate_clksrc,
865 }, 859 },
866 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, 860 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
867 .mask = S5PC100_CLKSRC2_FIMC2_MASK, 861 .mask = S5PC100_CLKSRC2_FIMC2_MASK,
@@ -889,10 +883,7 @@ static struct clksrc_clk clk_mmc0 = {
889 .id = 0, 883 .id = 0,
890 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, 884 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
891 .enable = s5pc100_sclk0_ctrl, 885 .enable = s5pc100_sclk0_ctrl,
892 .set_parent = s5pc100_setparent_clksrc, 886 .ops = &s5pc100_clksrc_ops,
893 .get_rate = s5pc100_getrate_clksrc,
894 .set_rate = s5pc100_setrate_clksrc,
895 .round_rate = s5pc100_roundrate_clksrc,
896 }, 887 },
897 .shift = S5PC100_CLKSRC2_MMC0_SHIFT, 888 .shift = S5PC100_CLKSRC2_MMC0_SHIFT,
898 .mask = S5PC100_CLKSRC2_MMC0_MASK, 889 .mask = S5PC100_CLKSRC2_MMC0_MASK,
@@ -908,10 +899,7 @@ static struct clksrc_clk clk_mmc1 = {
908 .id = 1, 899 .id = 1,
909 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, 900 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
910 .enable = s5pc100_sclk0_ctrl, 901 .enable = s5pc100_sclk0_ctrl,
911 .set_parent = s5pc100_setparent_clksrc, 902 .ops = &s5pc100_clksrc_ops,
912 .get_rate = s5pc100_getrate_clksrc,
913 .set_rate = s5pc100_setrate_clksrc,
914 .round_rate = s5pc100_roundrate_clksrc,
915 }, 903 },
916 .shift = S5PC100_CLKSRC2_MMC1_SHIFT, 904 .shift = S5PC100_CLKSRC2_MMC1_SHIFT,
917 .mask = S5PC100_CLKSRC2_MMC1_MASK, 905 .mask = S5PC100_CLKSRC2_MMC1_MASK,
@@ -927,10 +915,7 @@ static struct clksrc_clk clk_mmc2 = {
927 .id = 2, 915 .id = 2,
928 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, 916 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
929 .enable = s5pc100_sclk0_ctrl, 917 .enable = s5pc100_sclk0_ctrl,
930 .set_parent = s5pc100_setparent_clksrc, 918 .ops = &s5pc100_clksrc_ops,
931 .get_rate = s5pc100_getrate_clksrc,
932 .set_rate = s5pc100_setrate_clksrc,
933 .round_rate = s5pc100_roundrate_clksrc,
934 }, 919 },
935 .shift = S5PC100_CLKSRC2_MMC2_SHIFT, 920 .shift = S5PC100_CLKSRC2_MMC2_SHIFT,
936 .mask = S5PC100_CLKSRC2_MMC2_MASK, 921 .mask = S5PC100_CLKSRC2_MMC2_MASK,
@@ -959,10 +944,7 @@ static struct clksrc_clk clk_usbhost = {
959 .id = -1, 944 .id = -1,
960 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, 945 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
961 .enable = s5pc100_sclk0_ctrl, 946 .enable = s5pc100_sclk0_ctrl,
962 .set_parent = s5pc100_setparent_clksrc, 947 .ops = &s5pc100_clksrc_ops,
963 .get_rate = s5pc100_getrate_clksrc,
964 .set_rate = s5pc100_setrate_clksrc,
965 .round_rate = s5pc100_roundrate_clksrc,
966 }, 948 },
967 .shift = S5PC100_CLKSRC1_UHOST_SHIFT, 949 .shift = S5PC100_CLKSRC1_UHOST_SHIFT,
968 .mask = S5PC100_CLKSRC1_UHOST_MASK, 950 .mask = S5PC100_CLKSRC1_UHOST_MASK,
diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c
index 5872f0b62b7c..ad4e8723a811 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -150,20 +150,21 @@ void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk)
150 clk_get_rate(&clk->clk)); 150 clk_get_rate(&clk->clk));
151} 151}
152 152
153static struct clk_ops clksrc_ops = {
154 .set_parent = s3c_setparent_clksrc,
155 .get_rate = s3c_getrate_clksrc,
156 .set_rate = s3c_setrate_clksrc,
157 .round_rate = s3c_roundrate_clksrc,
158};
159
153void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) 160void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
154{ 161{
155 int ret; 162 int ret;
156 163
157 for (; size > 0; size--, clksrc++) { 164 for (; size > 0; size--, clksrc++) {
158 /* fill in the default functions */ 165 /* fill in the default functions */
159 if (!clksrc->clk.set_parent) 166 if (!clksrc->clk.ops)
160 clksrc->clk.set_parent = s3c_setparent_clksrc; 167 clksrc->clk.ops = &clksrc_ops;
161 if (!clksrc->clk.get_rate)
162 clksrc->clk.get_rate = s3c_getrate_clksrc;
163 if (!clksrc->clk.set_rate)
164 clksrc->clk.set_rate = s3c_setrate_clksrc;
165 if (!clksrc->clk.round_rate)
166 clksrc->clk.round_rate = s3c_roundrate_clksrc;
167 168
168 s3c_set_clksrc(clksrc); 169 s3c_set_clksrc(clksrc);
169 170
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index d86af84b5b8c..43324af24c6e 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -11,6 +11,30 @@
11 11
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13 13
14struct clk;
15
16/**
17 * struct clk_ops - standard clock operations
18 * @set_rate: set the clock rate, see clk_set_rate().
19 * @get_rate: get the clock rate, see clk_get_rate().
20 * @round_rate: round a given clock rate, see clk_round_rate().
21 * @set_parent: set the clock's parent, see clk_set_parent().
22 *
23 * Group the common clock implementations together so that we
24 * don't have to keep setting the same fiels again. We leave
25 * enable in struct clk.
26 *
27 * Adding an extra layer of indirection into the process should
28 * not be a problem as it is unlikely these operations are going
29 * to need to be called quickly.
30 */
31struct clk_ops {
32 int (*set_rate)(struct clk *c, unsigned long rate);
33 unsigned long (*get_rate)(struct clk *c);
34 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
35 int (*set_parent)(struct clk *c, struct clk *parent);
36};
37
14struct clk { 38struct clk {
15 struct list_head list; 39 struct list_head list;
16 struct module *owner; 40 struct module *owner;
@@ -21,11 +45,8 @@ struct clk {
21 unsigned long rate; 45 unsigned long rate;
22 unsigned long ctrlbit; 46 unsigned long ctrlbit;
23 47
48 struct clk_ops *ops;
24 int (*enable)(struct clk *, int enable); 49 int (*enable)(struct clk *, int enable);
25 int (*set_rate)(struct clk *c, unsigned long rate);
26 unsigned long (*get_rate)(struct clk *c);
27 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
28 int (*set_parent)(struct clk *c, struct clk *parent);
29}; 50};
30 51
31/* other clocks which may be registered by board support */ 52/* other clocks which may be registered by board support */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 16:02:35 -0500