diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-25 15:43:28 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-25 15:43:28 -0400 |
commit | 4b478cedcdc1b2d131170f22bd3f916e53472f52 (patch) | |
tree | 4a458a850d99fe3e2768fc62b2e3761c85ea05c2 /arch/arm/mach-s3c2410 | |
parent | ae4c42e4e4d76d003f8ca551fe1aef93ff9a4b21 (diff) | |
parent | c8b7d43b6d539218c36f0ac8a6ad434b93195703 (diff) |
Merge branch 'next/deletion' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/deletion' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
ARM: mach-loki: delete
ARM: mach-s3c2400: delete
ARM: mach-s3c24a0: delete
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/gpio-fns.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 241 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-mem.h | 28 |
3 files changed, 0 insertions, 275 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h index f453c4f2cb8e..bab139201761 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h | |||
@@ -52,12 +52,6 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); | |||
52 | 52 | ||
53 | extern int s3c2410_gpio_getirq(unsigned int pin); | 53 | extern int s3c2410_gpio_getirq(unsigned int pin); |
54 | 54 | ||
55 | #ifdef CONFIG_CPU_S3C2400 | ||
56 | |||
57 | extern int s3c2400_gpio_getirq(unsigned int pin); | ||
58 | |||
59 | #endif /* CONFIG_CPU_S3C2400 */ | ||
60 | |||
61 | /* s3c2410_gpio_irqfilter | 55 | /* s3c2410_gpio_irqfilter |
62 | * | 56 | * |
63 | * set the irq filtering on the given pin | 57 | * set the irq filtering on the given pin |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index a0a89d429296..cac1ad6b582c 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -16,11 +16,7 @@ | |||
16 | 16 | ||
17 | #include <mach/gpio-nrs.h> | 17 | #include <mach/gpio-nrs.h> |
18 | 18 | ||
19 | #ifdef CONFIG_CPU_S3C2400 | ||
20 | #define S3C24XX_MISCCR S3C2400_MISCCR | ||
21 | #else | ||
22 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) | 19 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) |
23 | #endif /* CONFIG_CPU_S3C2400 */ | ||
24 | 20 | ||
25 | /* general configuration options */ | 21 | /* general configuration options */ |
26 | 22 | ||
@@ -42,67 +38,33 @@ | |||
42 | /* configure GPIO ports A..G */ | 38 | /* configure GPIO ports A..G */ |
43 | 39 | ||
44 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output | 40 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output |
45 | * S3C2400: 18bits, zero in bit X makes pin X output | ||
46 | * 1 makes port special function, this is default | 41 | * 1 makes port special function, this is default |
47 | */ | 42 | */ |
48 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) | 43 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) |
49 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) | 44 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) |
50 | 45 | ||
51 | #define S3C2400_GPACON S3C2410_GPIOREG(0x00) | ||
52 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) | ||
53 | |||
54 | #define S3C2410_GPA0_ADDR0 (1<<0) | 46 | #define S3C2410_GPA0_ADDR0 (1<<0) |
55 | |||
56 | #define S3C2410_GPA1_ADDR16 (1<<1) | 47 | #define S3C2410_GPA1_ADDR16 (1<<1) |
57 | |||
58 | #define S3C2410_GPA2_ADDR17 (1<<2) | 48 | #define S3C2410_GPA2_ADDR17 (1<<2) |
59 | |||
60 | #define S3C2410_GPA3_ADDR18 (1<<3) | 49 | #define S3C2410_GPA3_ADDR18 (1<<3) |
61 | |||
62 | #define S3C2410_GPA4_ADDR19 (1<<4) | 50 | #define S3C2410_GPA4_ADDR19 (1<<4) |
63 | |||
64 | #define S3C2410_GPA5_ADDR20 (1<<5) | 51 | #define S3C2410_GPA5_ADDR20 (1<<5) |
65 | |||
66 | #define S3C2410_GPA6_ADDR21 (1<<6) | 52 | #define S3C2410_GPA6_ADDR21 (1<<6) |
67 | |||
68 | #define S3C2410_GPA7_ADDR22 (1<<7) | 53 | #define S3C2410_GPA7_ADDR22 (1<<7) |
69 | |||
70 | #define S3C2410_GPA8_ADDR23 (1<<8) | 54 | #define S3C2410_GPA8_ADDR23 (1<<8) |
71 | |||
72 | #define S3C2410_GPA9_ADDR24 (1<<9) | 55 | #define S3C2410_GPA9_ADDR24 (1<<9) |
73 | |||
74 | #define S3C2410_GPA10_ADDR25 (1<<10) | 56 | #define S3C2410_GPA10_ADDR25 (1<<10) |
75 | #define S3C2400_GPA10_SCKE (1<<10) | ||
76 | |||
77 | #define S3C2410_GPA11_ADDR26 (1<<11) | 57 | #define S3C2410_GPA11_ADDR26 (1<<11) |
78 | #define S3C2400_GPA11_nCAS0 (1<<11) | ||
79 | |||
80 | #define S3C2410_GPA12_nGCS1 (1<<12) | 58 | #define S3C2410_GPA12_nGCS1 (1<<12) |
81 | #define S3C2400_GPA12_nCAS1 (1<<12) | ||
82 | |||
83 | #define S3C2410_GPA13_nGCS2 (1<<13) | 59 | #define S3C2410_GPA13_nGCS2 (1<<13) |
84 | #define S3C2400_GPA13_nGCS1 (1<<13) | ||
85 | |||
86 | #define S3C2410_GPA14_nGCS3 (1<<14) | 60 | #define S3C2410_GPA14_nGCS3 (1<<14) |
87 | #define S3C2400_GPA14_nGCS2 (1<<14) | ||
88 | |||
89 | #define S3C2410_GPA15_nGCS4 (1<<15) | 61 | #define S3C2410_GPA15_nGCS4 (1<<15) |
90 | #define S3C2400_GPA15_nGCS3 (1<<15) | ||
91 | |||
92 | #define S3C2410_GPA16_nGCS5 (1<<16) | 62 | #define S3C2410_GPA16_nGCS5 (1<<16) |
93 | #define S3C2400_GPA16_nGCS4 (1<<16) | ||
94 | |||
95 | #define S3C2410_GPA17_CLE (1<<17) | 63 | #define S3C2410_GPA17_CLE (1<<17) |
96 | #define S3C2400_GPA17_nGCS5 (1<<17) | ||
97 | |||
98 | #define S3C2410_GPA18_ALE (1<<18) | 64 | #define S3C2410_GPA18_ALE (1<<18) |
99 | |||
100 | #define S3C2410_GPA19_nFWE (1<<19) | 65 | #define S3C2410_GPA19_nFWE (1<<19) |
101 | |||
102 | #define S3C2410_GPA20_nFRE (1<<20) | 66 | #define S3C2410_GPA20_nFRE (1<<20) |
103 | |||
104 | #define S3C2410_GPA21_nRSTOUT (1<<21) | 67 | #define S3C2410_GPA21_nRSTOUT (1<<21) |
105 | |||
106 | #define S3C2410_GPA22_nFCE (1<<22) | 68 | #define S3C2410_GPA22_nFCE (1<<22) |
107 | 69 | ||
108 | /* 0x08 and 0x0c are reserved on S3C2410 */ | 70 | /* 0x08 and 0x0c are reserved on S3C2410 */ |
@@ -111,10 +73,6 @@ | |||
111 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. | 73 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. |
112 | * 00 = input, 01 = output, 10=special function, 11=reserved | 74 | * 00 = input, 01 = output, 10=special function, 11=reserved |
113 | 75 | ||
114 | * S3C2400: | ||
115 | * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. | ||
116 | * 00 = input, 01 = output, 10=data, 11=special function | ||
117 | |||
118 | * bit 0,1 = pin 0, 2,3= pin 1... | 76 | * bit 0,1 = pin 0, 2,3= pin 1... |
119 | * | 77 | * |
120 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled | 78 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled |
@@ -124,78 +82,35 @@ | |||
124 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) | 82 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) |
125 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) | 83 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) |
126 | 84 | ||
127 | #define S3C2400_GPBCON S3C2410_GPIOREG(0x08) | ||
128 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) | ||
129 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) | ||
130 | |||
131 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ | 85 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ |
132 | 86 | ||
133 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) | 87 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) |
134 | #define S3C2400_GPB0_DATA16 (0x02 << 0) | ||
135 | 88 | ||
136 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) | 89 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) |
137 | #define S3C2400_GPB1_DATA17 (0x02 << 2) | ||
138 | 90 | ||
139 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) | 91 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) |
140 | #define S3C2400_GPB2_DATA18 (0x02 << 4) | ||
141 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) | ||
142 | 92 | ||
143 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) | 93 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) |
144 | #define S3C2400_GPB3_DATA19 (0x02 << 6) | ||
145 | #define S3C2400_GPB3_TXD1 (0x03 << 6) | ||
146 | 94 | ||
147 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) | 95 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) |
148 | #define S3C2400_GPB4_DATA20 (0x02 << 8) | ||
149 | #define S3C2410_GPB4_MASK (0x03 << 8) | 96 | #define S3C2410_GPB4_MASK (0x03 << 8) |
150 | #define S3C2400_GPB4_RXD1 (0x03 << 8) | ||
151 | #define S3C2400_GPB4_MASK (0x03 << 8) | ||
152 | 97 | ||
153 | #define S3C2410_GPB5_nXBACK (0x02 << 10) | 98 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
154 | #define S3C2443_GPB5_XBACK (0x03 << 10) | 99 | #define S3C2443_GPB5_XBACK (0x03 << 10) |
155 | #define S3C2400_GPB5_DATA21 (0x02 << 10) | ||
156 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | ||
157 | 100 | ||
158 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) | 101 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
159 | #define S3C2443_GPB6_XBREQ (0x03 << 12) | 102 | #define S3C2443_GPB6_XBREQ (0x03 << 12) |
160 | #define S3C2400_GPB6_DATA22 (0x02 << 12) | ||
161 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | ||
162 | 103 | ||
163 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) | 104 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
164 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) | 105 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) |
165 | #define S3C2400_GPB7_DATA23 (0x02 << 14) | ||
166 | 106 | ||
167 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) | 107 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) |
168 | #define S3C2400_GPB8_DATA24 (0x02 << 16) | ||
169 | 108 | ||
170 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) | 109 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
171 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) | 110 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) |
172 | #define S3C2400_GPB9_DATA25 (0x02 << 18) | ||
173 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | ||
174 | 111 | ||
175 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) | 112 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
176 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) | 113 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) |
177 | #define S3C2400_GPB10_DATA26 (0x02 << 20) | ||
178 | #define S3C2400_GPB10_nSS (0x03 << 20) | ||
179 | |||
180 | #define S3C2400_GPB11_INP (0x00 << 22) | ||
181 | #define S3C2400_GPB11_OUTP (0x01 << 22) | ||
182 | #define S3C2400_GPB11_DATA27 (0x02 << 22) | ||
183 | |||
184 | #define S3C2400_GPB12_INP (0x00 << 24) | ||
185 | #define S3C2400_GPB12_OUTP (0x01 << 24) | ||
186 | #define S3C2400_GPB12_DATA28 (0x02 << 24) | ||
187 | |||
188 | #define S3C2400_GPB13_INP (0x00 << 26) | ||
189 | #define S3C2400_GPB13_OUTP (0x01 << 26) | ||
190 | #define S3C2400_GPB13_DATA29 (0x02 << 26) | ||
191 | |||
192 | #define S3C2400_GPB14_INP (0x00 << 28) | ||
193 | #define S3C2400_GPB14_OUTP (0x01 << 28) | ||
194 | #define S3C2400_GPB14_DATA30 (0x02 << 28) | ||
195 | |||
196 | #define S3C2400_GPB15_INP (0x00 << 30) | ||
197 | #define S3C2400_GPB15_OUTP (0x01 << 30) | ||
198 | #define S3C2400_GPB15_DATA31 (0x02 << 30) | ||
199 | 114 | ||
200 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) | 115 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) |
201 | 116 | ||
@@ -208,59 +123,22 @@ | |||
208 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) | 123 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) |
209 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) | 124 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) |
210 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) | 125 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) |
211 | |||
212 | #define S3C2400_GPCCON S3C2410_GPIOREG(0x14) | ||
213 | #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) | ||
214 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) | ||
215 | |||
216 | #define S3C2410_GPC0_LEND (0x02 << 0) | 126 | #define S3C2410_GPC0_LEND (0x02 << 0) |
217 | #define S3C2400_GPC0_VD0 (0x02 << 0) | ||
218 | |||
219 | #define S3C2410_GPC1_VCLK (0x02 << 2) | 127 | #define S3C2410_GPC1_VCLK (0x02 << 2) |
220 | #define S3C2400_GPC1_VD1 (0x02 << 2) | ||
221 | |||
222 | #define S3C2410_GPC2_VLINE (0x02 << 4) | 128 | #define S3C2410_GPC2_VLINE (0x02 << 4) |
223 | #define S3C2400_GPC2_VD2 (0x02 << 4) | ||
224 | |||
225 | #define S3C2410_GPC3_VFRAME (0x02 << 6) | 129 | #define S3C2410_GPC3_VFRAME (0x02 << 6) |
226 | #define S3C2400_GPC3_VD3 (0x02 << 6) | ||
227 | |||
228 | #define S3C2410_GPC4_VM (0x02 << 8) | 130 | #define S3C2410_GPC4_VM (0x02 << 8) |
229 | #define S3C2400_GPC4_VD4 (0x02 << 8) | ||
230 | |||
231 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) | 131 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) |
232 | #define S3C2400_GPC5_VD5 (0x02 << 10) | ||
233 | |||
234 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) | 132 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) |
235 | #define S3C2400_GPC6_VD6 (0x02 << 12) | ||
236 | |||
237 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) | 133 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) |
238 | #define S3C2400_GPC7_VD7 (0x02 << 14) | ||
239 | |||
240 | #define S3C2410_GPC8_VD0 (0x02 << 16) | 134 | #define S3C2410_GPC8_VD0 (0x02 << 16) |
241 | #define S3C2400_GPC8_VD8 (0x02 << 16) | ||
242 | |||
243 | #define S3C2410_GPC9_VD1 (0x02 << 18) | 135 | #define S3C2410_GPC9_VD1 (0x02 << 18) |
244 | #define S3C2400_GPC9_VD9 (0x02 << 18) | ||
245 | |||
246 | #define S3C2410_GPC10_VD2 (0x02 << 20) | 136 | #define S3C2410_GPC10_VD2 (0x02 << 20) |
247 | #define S3C2400_GPC10_VD10 (0x02 << 20) | ||
248 | |||
249 | #define S3C2410_GPC11_VD3 (0x02 << 22) | 137 | #define S3C2410_GPC11_VD3 (0x02 << 22) |
250 | #define S3C2400_GPC11_VD11 (0x02 << 22) | ||
251 | |||
252 | #define S3C2410_GPC12_VD4 (0x02 << 24) | 138 | #define S3C2410_GPC12_VD4 (0x02 << 24) |
253 | #define S3C2400_GPC12_VD12 (0x02 << 24) | ||
254 | |||
255 | #define S3C2410_GPC13_VD5 (0x02 << 26) | 139 | #define S3C2410_GPC13_VD5 (0x02 << 26) |
256 | #define S3C2400_GPC13_VD13 (0x02 << 26) | ||
257 | |||
258 | #define S3C2410_GPC14_VD6 (0x02 << 28) | 140 | #define S3C2410_GPC14_VD6 (0x02 << 28) |
259 | #define S3C2400_GPC14_VD14 (0x02 << 28) | ||
260 | |||
261 | #define S3C2410_GPC15_VD7 (0x02 << 30) | 141 | #define S3C2410_GPC15_VD7 (0x02 << 30) |
262 | #define S3C2400_GPC15_VD15 (0x02 << 30) | ||
263 | |||
264 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) | 142 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) |
265 | 143 | ||
266 | /* | 144 | /* |
@@ -269,8 +147,6 @@ | |||
269 | * almost identical setup to port b, but the special functions are mostly | 147 | * almost identical setup to port b, but the special functions are mostly |
270 | * to do with the video system's data. | 148 | * to do with the video system's data. |
271 | * | 149 | * |
272 | * S3C2400: Port D consists of 11 GPIO/Special function | ||
273 | * | ||
274 | * almost identical setup to port c | 150 | * almost identical setup to port c |
275 | */ | 151 | */ |
276 | 152 | ||
@@ -278,46 +154,31 @@ | |||
278 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) | 154 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) |
279 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) | 155 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) |
280 | 156 | ||
281 | #define S3C2400_GPDCON S3C2410_GPIOREG(0x20) | ||
282 | #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) | ||
283 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) | ||
284 | |||
285 | #define S3C2410_GPD0_VD8 (0x02 << 0) | 157 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
286 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | ||
287 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) | 158 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) |
288 | 159 | ||
289 | #define S3C2410_GPD1_VD9 (0x02 << 2) | 160 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
290 | #define S3C2400_GPD1_VM (0x02 << 2) | ||
291 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) | 161 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) |
292 | 162 | ||
293 | #define S3C2410_GPD2_VD10 (0x02 << 4) | 163 | #define S3C2410_GPD2_VD10 (0x02 << 4) |
294 | #define S3C2400_GPD2_VLINE (0x02 << 4) | ||
295 | 164 | ||
296 | #define S3C2410_GPD3_VD11 (0x02 << 6) | 165 | #define S3C2410_GPD3_VD11 (0x02 << 6) |
297 | #define S3C2400_GPD3_VCLK (0x02 << 6) | ||
298 | 166 | ||
299 | #define S3C2410_GPD4_VD12 (0x02 << 8) | 167 | #define S3C2410_GPD4_VD12 (0x02 << 8) |
300 | #define S3C2400_GPD4_LEND (0x02 << 8) | ||
301 | 168 | ||
302 | #define S3C2410_GPD5_VD13 (0x02 << 10) | 169 | #define S3C2410_GPD5_VD13 (0x02 << 10) |
303 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) | ||
304 | 170 | ||
305 | #define S3C2410_GPD6_VD14 (0x02 << 12) | 171 | #define S3C2410_GPD6_VD14 (0x02 << 12) |
306 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) | ||
307 | 172 | ||
308 | #define S3C2410_GPD7_VD15 (0x02 << 14) | 173 | #define S3C2410_GPD7_VD15 (0x02 << 14) |
309 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) | ||
310 | 174 | ||
311 | #define S3C2410_GPD8_VD16 (0x02 << 16) | 175 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
312 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) | ||
313 | #define S3C2440_GPD8_SPIMISO1 (0x03 << 16) | 176 | #define S3C2440_GPD8_SPIMISO1 (0x03 << 16) |
314 | 177 | ||
315 | #define S3C2410_GPD9_VD17 (0x02 << 18) | 178 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
316 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) | ||
317 | #define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) | 179 | #define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) |
318 | 180 | ||
319 | #define S3C2410_GPD10_VD18 (0x02 << 20) | 181 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
320 | #define S3C2400_GPD10_nWAIT (0x02 << 20) | ||
321 | #define S3C2440_GPD10_SPICLK1 (0x03 << 20) | 182 | #define S3C2440_GPD10_SPICLK1 (0x03 << 20) |
322 | 183 | ||
323 | #define S3C2410_GPD11_VD19 (0x02 << 22) | 184 | #define S3C2410_GPD11_VD19 (0x02 << 22) |
@@ -340,9 +201,6 @@ | |||
340 | * again, the same as port B, but dealing with I2S, SDI, and | 201 | * again, the same as port B, but dealing with I2S, SDI, and |
341 | * more miscellaneous functions | 202 | * more miscellaneous functions |
342 | * | 203 | * |
343 | * S3C2400: | ||
344 | * Port E consists of 12 GPIO/Special function | ||
345 | * | ||
346 | * GPIO / interrupt inputs | 204 | * GPIO / interrupt inputs |
347 | */ | 205 | */ |
348 | 206 | ||
@@ -350,74 +208,51 @@ | |||
350 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) | 208 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) |
351 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) | 209 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) |
352 | 210 | ||
353 | #define S3C2400_GPECON S3C2410_GPIOREG(0x2C) | ||
354 | #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) | ||
355 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) | ||
356 | |||
357 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) | 211 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
358 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) | 212 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) |
359 | #define S3C2400_GPE0_EINT0 (0x02 << 0) | ||
360 | #define S3C2410_GPE0_MASK (0x03 << 0) | 213 | #define S3C2410_GPE0_MASK (0x03 << 0) |
361 | 214 | ||
362 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) | 215 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
363 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) | 216 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) |
364 | #define S3C2400_GPE1_EINT1 (0x02 << 2) | ||
365 | #define S3C2400_GPE1_nSS (0x03 << 2) | ||
366 | #define S3C2410_GPE1_MASK (0x03 << 2) | 217 | #define S3C2410_GPE1_MASK (0x03 << 2) |
367 | 218 | ||
368 | #define S3C2410_GPE2_CDCLK (0x02 << 4) | 219 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
369 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) | 220 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) |
370 | #define S3C2400_GPE2_EINT2 (0x02 << 4) | ||
371 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | ||
372 | 221 | ||
373 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) | 222 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
374 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) | 223 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) |
375 | #define S3C2400_GPE3_EINT3 (0x02 << 6) | ||
376 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) | ||
377 | #define S3C2410_GPE3_nSS0 (0x03 << 6) | 224 | #define S3C2410_GPE3_nSS0 (0x03 << 6) |
378 | #define S3C2410_GPE3_MASK (0x03 << 6) | 225 | #define S3C2410_GPE3_MASK (0x03 << 6) |
379 | 226 | ||
380 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) | 227 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
381 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) | 228 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) |
382 | #define S3C2400_GPE4_EINT4 (0x02 << 8) | ||
383 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) | ||
384 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) | 229 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) |
385 | #define S3C2410_GPE4_MASK (0x03 << 8) | 230 | #define S3C2410_GPE4_MASK (0x03 << 8) |
386 | 231 | ||
387 | #define S3C2410_GPE5_SDCLK (0x02 << 10) | 232 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
388 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) | 233 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) |
389 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | ||
390 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | ||
391 | #define S3C2443_GPE5_AC_BITCLK (0x03 << 10) | 234 | #define S3C2443_GPE5_AC_BITCLK (0x03 << 10) |
392 | 235 | ||
393 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | 236 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
394 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) | 237 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) |
395 | #define S3C2443_GPE6_AC_SDI (0x03 << 12) | 238 | #define S3C2443_GPE6_AC_SDI (0x03 << 12) |
396 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | ||
397 | 239 | ||
398 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | 240 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
399 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) | 241 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) |
400 | #define S3C2443_GPE7_AC_SDO (0x03 << 14) | 242 | #define S3C2443_GPE7_AC_SDO (0x03 << 14) |
401 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | ||
402 | 243 | ||
403 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | 244 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
404 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) | 245 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) |
405 | #define S3C2443_GPE8_AC_SYNC (0x03 << 16) | 246 | #define S3C2443_GPE8_AC_SYNC (0x03 << 16) |
406 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | ||
407 | 247 | ||
408 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | 248 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
409 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) | 249 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) |
410 | #define S3C2443_GPE9_AC_nRESET (0x03 << 18) | 250 | #define S3C2443_GPE9_AC_nRESET (0x03 << 18) |
411 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) | ||
412 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | ||
413 | 251 | ||
414 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | 252 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
415 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) | 253 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) |
416 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | ||
417 | 254 | ||
418 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) | 255 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |
419 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) | ||
420 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) | ||
421 | 256 | ||
422 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) | 257 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) |
423 | 258 | ||
@@ -447,9 +282,6 @@ | |||
447 | * | 282 | * |
448 | * pull up works like all other ports. | 283 | * pull up works like all other ports. |
449 | * | 284 | * |
450 | * S3C2400: | ||
451 | * Port F consists of 7 GPIO/Special function | ||
452 | * | ||
453 | * GPIO/serial/misc pins | 285 | * GPIO/serial/misc pins |
454 | */ | 286 | */ |
455 | 287 | ||
@@ -457,37 +289,14 @@ | |||
457 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) | 289 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) |
458 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) | 290 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) |
459 | 291 | ||
460 | #define S3C2400_GPFCON S3C2410_GPIOREG(0x38) | ||
461 | #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) | ||
462 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) | ||
463 | |||
464 | #define S3C2410_GPF0_EINT0 (0x02 << 0) | 292 | #define S3C2410_GPF0_EINT0 (0x02 << 0) |
465 | #define S3C2400_GPF0_RXD0 (0x02 << 0) | ||
466 | |||
467 | #define S3C2410_GPF1_EINT1 (0x02 << 2) | 293 | #define S3C2410_GPF1_EINT1 (0x02 << 2) |
468 | #define S3C2400_GPF1_RXD1 (0x02 << 2) | ||
469 | #define S3C2400_GPF1_IICSDA (0x03 << 2) | ||
470 | |||
471 | #define S3C2410_GPF2_EINT2 (0x02 << 4) | 294 | #define S3C2410_GPF2_EINT2 (0x02 << 4) |
472 | #define S3C2400_GPF2_TXD0 (0x02 << 4) | ||
473 | |||
474 | #define S3C2410_GPF3_EINT3 (0x02 << 6) | 295 | #define S3C2410_GPF3_EINT3 (0x02 << 6) |
475 | #define S3C2400_GPF3_TXD1 (0x02 << 6) | ||
476 | #define S3C2400_GPF3_IICSCL (0x03 << 6) | ||
477 | |||
478 | #define S3C2410_GPF4_EINT4 (0x02 << 8) | 296 | #define S3C2410_GPF4_EINT4 (0x02 << 8) |
479 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) | ||
480 | #define S3C2400_GPF4_nXBACK (0x03 << 8) | ||
481 | |||
482 | #define S3C2410_GPF5_EINT5 (0x02 << 10) | 297 | #define S3C2410_GPF5_EINT5 (0x02 << 10) |
483 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) | ||
484 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) | ||
485 | |||
486 | #define S3C2410_GPF6_EINT6 (0x02 << 12) | 298 | #define S3C2410_GPF6_EINT6 (0x02 << 12) |
487 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) | ||
488 | |||
489 | #define S3C2410_GPF7_EINT7 (0x02 << 14) | 299 | #define S3C2410_GPF7_EINT7 (0x02 << 14) |
490 | |||
491 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) | 300 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) |
492 | 301 | ||
493 | /* S3C2410: | 302 | /* S3C2410: |
@@ -497,62 +306,38 @@ | |||
497 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | 306 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
498 | * | 307 | * |
499 | * pull up works like all other ports. | 308 | * pull up works like all other ports. |
500 | * | ||
501 | * S3C2400: | ||
502 | * Port G consists of 10 GPIO/Special function | ||
503 | */ | 309 | */ |
504 | 310 | ||
505 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) | 311 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) |
506 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) | 312 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) |
507 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) | 313 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) |
508 | 314 | ||
509 | #define S3C2400_GPGCON S3C2410_GPIOREG(0x44) | ||
510 | #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) | ||
511 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) | ||
512 | |||
513 | #define S3C2410_GPG0_EINT8 (0x02 << 0) | 315 | #define S3C2410_GPG0_EINT8 (0x02 << 0) |
514 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) | ||
515 | 316 | ||
516 | #define S3C2410_GPG1_EINT9 (0x02 << 2) | 317 | #define S3C2410_GPG1_EINT9 (0x02 << 2) |
517 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) | ||
518 | 318 | ||
519 | #define S3C2410_GPG2_EINT10 (0x02 << 4) | 319 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
520 | #define S3C2410_GPG2_nSS0 (0x03 << 4) | 320 | #define S3C2410_GPG2_nSS0 (0x03 << 4) |
521 | #define S3C2400_GPG2_CDCLK (0x02 << 4) | ||
522 | 321 | ||
523 | #define S3C2410_GPG3_EINT11 (0x02 << 6) | 322 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
524 | #define S3C2410_GPG3_nSS1 (0x03 << 6) | 323 | #define S3C2410_GPG3_nSS1 (0x03 << 6) |
525 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) | ||
526 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | ||
527 | 324 | ||
528 | #define S3C2410_GPG4_EINT12 (0x02 << 8) | 325 | #define S3C2410_GPG4_EINT12 (0x02 << 8) |
529 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) | ||
530 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | ||
531 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) | 326 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) |
532 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) | 327 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) |
533 | 328 | ||
534 | #define S3C2410_GPG5_EINT13 (0x02 << 10) | 329 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
535 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) | ||
536 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | ||
537 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ | 330 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ |
538 | 331 | ||
539 | #define S3C2410_GPG6_EINT14 (0x02 << 12) | 332 | #define S3C2410_GPG6_EINT14 (0x02 << 12) |
540 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) | ||
541 | #define S3C2400_GPG6_IICSCL (0x03 << 12) | ||
542 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) | 333 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) |
543 | 334 | ||
544 | #define S3C2410_GPG7_EINT15 (0x02 << 14) | 335 | #define S3C2410_GPG7_EINT15 (0x02 << 14) |
545 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) | 336 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) |
546 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) | ||
547 | #define S3C2400_GPG7_IICSDA (0x03 << 14) | ||
548 | 337 | ||
549 | #define S3C2410_GPG8_EINT16 (0x02 << 16) | 338 | #define S3C2410_GPG8_EINT16 (0x02 << 16) |
550 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) | ||
551 | #define S3C2400_GPG8_IICSCL (0x03 << 16) | ||
552 | 339 | ||
553 | #define S3C2410_GPG9_EINT17 (0x02 << 18) | 340 | #define S3C2410_GPG9_EINT17 (0x02 << 18) |
554 | #define S3C2400_GPG9_SPICLK (0x02 << 18) | ||
555 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) | ||
556 | 341 | ||
557 | #define S3C2410_GPG10_EINT18 (0x02 << 20) | 342 | #define S3C2410_GPG10_EINT18 (0x02 << 20) |
558 | 343 | ||
@@ -660,7 +445,6 @@ | |||
660 | #define S3C2443_GPMUP S3C2410_GPIOREG(0x108) | 445 | #define S3C2443_GPMUP S3C2410_GPIOREG(0x108) |
661 | 446 | ||
662 | /* miscellaneous control */ | 447 | /* miscellaneous control */ |
663 | #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) | ||
664 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) | 448 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) |
665 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) | 449 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) |
666 | 450 | ||
@@ -674,14 +458,6 @@ | |||
674 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) | 458 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) |
675 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) | 459 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) |
676 | 460 | ||
677 | #define S3C2400_MISCCR_SPUCR_LEN (0<<0) | ||
678 | #define S3C2400_MISCCR_SPUCR_LDIS (1<<0) | ||
679 | #define S3C2400_MISCCR_SPUCR_HEN (0<<1) | ||
680 | #define S3C2400_MISCCR_SPUCR_HDIS (1<<1) | ||
681 | |||
682 | #define S3C2400_MISCCR_HZ_STOPEN (0<<2) | ||
683 | #define S3C2400_MISCCR_HZ_STOPPREV (1<<2) | ||
684 | |||
685 | #define S3C2410_MISCCR_USBDEV (0<<3) | 461 | #define S3C2410_MISCCR_USBDEV (0<<3) |
686 | #define S3C2410_MISCCR_USBHOST (1<<3) | 462 | #define S3C2410_MISCCR_USBHOST (1<<3) |
687 | 463 | ||
@@ -728,7 +504,6 @@ | |||
728 | * | 504 | * |
729 | * Samsung datasheet p9-25 | 505 | * Samsung datasheet p9-25 |
730 | */ | 506 | */ |
731 | #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) | ||
732 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) | 507 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) |
733 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) | 508 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) |
734 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) | 509 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) |
@@ -796,22 +571,6 @@ | |||
796 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | 571 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) |
797 | #define S3C2410_GSTATUS2_PONRESET (1<<0) | 572 | #define S3C2410_GSTATUS2_PONRESET (1<<0) |
798 | 573 | ||
799 | /* open drain control register */ | ||
800 | #define S3C2400_OPENCR S3C2410_GPIOREG(0x50) | ||
801 | |||
802 | #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) | ||
803 | #define S3C2400_OPENCR_OPC_RXD1EN (1<<0) | ||
804 | #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) | ||
805 | #define S3C2400_OPENCR_OPC_TXD1EN (1<<1) | ||
806 | #define S3C2400_OPENCR_OPC_CMDDIS (0<<2) | ||
807 | #define S3C2400_OPENCR_OPC_CMDEN (1<<2) | ||
808 | #define S3C2400_OPENCR_OPC_DATDIS (0<<3) | ||
809 | #define S3C2400_OPENCR_OPC_DATEN (1<<3) | ||
810 | #define S3C2400_OPENCR_OPC_MISODIS (0<<4) | ||
811 | #define S3C2400_OPENCR_OPC_MISOEN (1<<4) | ||
812 | #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) | ||
813 | #define S3C2400_OPENCR_OPC_MOSIEN (1<<5) | ||
814 | |||
815 | /* 2412/2413 sleep configuration registers */ | 574 | /* 2412/2413 sleep configuration registers */ |
816 | 575 | ||
817 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) | 576 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h index 988a6863e54b..e0c67b0163d8 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h | |||
@@ -145,29 +145,8 @@ | |||
145 | #define S3C2410_BANKCON_Tacs_SHIFT (13) | 145 | #define S3C2410_BANKCON_Tacs_SHIFT (13) |
146 | 146 | ||
147 | #define S3C2410_BANKCON_SRAM (0x0 << 15) | 147 | #define S3C2410_BANKCON_SRAM (0x0 << 15) |
148 | #define S3C2400_BANKCON_EDODRAM (0x2 << 15) | ||
149 | #define S3C2410_BANKCON_SDRAM (0x3 << 15) | 148 | #define S3C2410_BANKCON_SDRAM (0x3 << 15) |
150 | 149 | ||
151 | /* next bits only for EDO DRAM in 6,7 */ | ||
152 | #define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4) | ||
153 | #define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4) | ||
154 | #define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4) | ||
155 | #define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4) | ||
156 | |||
157 | /* CAS pulse width */ | ||
158 | #define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3) | ||
159 | #define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3) | ||
160 | |||
161 | /* CAS pre-charge */ | ||
162 | #define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2) | ||
163 | #define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2) | ||
164 | |||
165 | /* control column address select */ | ||
166 | #define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0) | ||
167 | #define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0) | ||
168 | #define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0) | ||
169 | #define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0) | ||
170 | |||
171 | /* next bits only for SDRAM in 6,7 */ | 150 | /* next bits only for SDRAM in 6,7 */ |
172 | #define S3C2410_BANKCON_Trcd2 (0x00 << 2) | 151 | #define S3C2410_BANKCON_Trcd2 (0x00 << 2) |
173 | #define S3C2410_BANKCON_Trcd3 (0x01 << 2) | 152 | #define S3C2410_BANKCON_Trcd3 (0x01 << 2) |
@@ -194,12 +173,6 @@ | |||
194 | #define S3C2410_REFRESH_TRP_3clk (1<<20) | 173 | #define S3C2410_REFRESH_TRP_3clk (1<<20) |
195 | #define S3C2410_REFRESH_TRP_4clk (2<<20) | 174 | #define S3C2410_REFRESH_TRP_4clk (2<<20) |
196 | 175 | ||
197 | #define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20) | ||
198 | #define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20) | ||
199 | #define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20) | ||
200 | #define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20) | ||
201 | #define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20) | ||
202 | |||
203 | #define S3C2410_REFRESH_TSRC_MASK (3<<18) | 176 | #define S3C2410_REFRESH_TSRC_MASK (3<<18) |
204 | #define S3C2410_REFRESH_TSRC_4clk (0<<18) | 177 | #define S3C2410_REFRESH_TSRC_4clk (0<<18) |
205 | #define S3C2410_REFRESH_TSRC_5clk (1<<18) | 178 | #define S3C2410_REFRESH_TSRC_5clk (1<<18) |
@@ -222,7 +195,6 @@ | |||
222 | #define S3C2410_BANKSIZE_4M (0x5 << 0) | 195 | #define S3C2410_BANKSIZE_4M (0x5 << 0) |
223 | #define S3C2410_BANKSIZE_2M (0x4 << 0) | 196 | #define S3C2410_BANKSIZE_2M (0x4 << 0) |
224 | #define S3C2410_BANKSIZE_MASK (0x7 << 0) | 197 | #define S3C2410_BANKSIZE_MASK (0x7 << 0) |
225 | #define S3C2400_BANKSIZE_MASK (0x4 << 0) | ||
226 | #define S3C2410_BANKSIZE_SCLK_EN (1<<4) | 198 | #define S3C2410_BANKSIZE_SCLK_EN (1<<4) |
227 | #define S3C2410_BANKSIZE_SCKE_EN (1<<5) | 199 | #define S3C2410_BANKSIZE_SCKE_EN (1<<5) |
228 | #define S3C2410_BANKSIZE_BURST (1<<7) | 200 | #define S3C2410_BANKSIZE_BURST (1<<7) |