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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-25 15:43:28 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-25 15:43:28 -0400
commit4b478cedcdc1b2d131170f22bd3f916e53472f52 (patch)
tree4a458a850d99fe3e2768fc62b2e3761c85ea05c2 /arch
parentae4c42e4e4d76d003f8ca551fe1aef93ff9a4b21 (diff)
parentc8b7d43b6d539218c36f0ac8a6ad434b93195703 (diff)
Merge branch 'next/deletion' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/deletion' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: ARM: mach-loki: delete ARM: mach-s3c2400: delete ARM: mach-s3c24a0: delete
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/Makefile4
-rw-r--r--arch/arm/configs/loki_defconfig120
-rw-r--r--arch/arm/mach-loki/Kconfig13
-rw-r--r--arch/arm/mach-loki/Makefile3
-rw-r--r--arch/arm/mach-loki/Makefile.boot3
-rw-r--r--arch/arm/mach-loki/addr-map.c122
-rw-r--r--arch/arm/mach-loki/common.c162
-rw-r--r--arch/arm/mach-loki/common.h37
-rw-r--r--arch/arm/mach-loki/include/mach/bridge-regs.h28
-rw-r--r--arch/arm/mach-loki/include/mach/debug-macro.S19
-rw-r--r--arch/arm/mach-loki/include/mach/entry-macro.S30
-rw-r--r--arch/arm/mach-loki/include/mach/hardware.h15
-rw-r--r--arch/arm/mach-loki/include/mach/io.h26
-rw-r--r--arch/arm/mach-loki/include/mach/irqs.h58
-rw-r--r--arch/arm/mach-loki/include/mach/loki.h83
-rw-r--r--arch/arm/mach-loki/include/mach/memory.h10
-rw-r--r--arch/arm/mach-loki/include/mach/system.h36
-rw-r--r--arch/arm/mach-loki/include/mach/timex.h11
-rw-r--r--arch/arm/mach-loki/include/mach/uncompress.h47
-rw-r--r--arch/arm/mach-loki/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-loki/irq.c22
-rw-r--r--arch/arm/mach-loki/lb88rc8480-setup.c99
-rw-r--r--arch/arm/mach-s3c2400/Kconfig7
-rw-r--r--arch/arm/mach-s3c2400/Makefile15
-rw-r--r--arch/arm/mach-s3c2400/gpio.c42
-rw-r--r--arch/arm/mach-s3c2400/include/mach/map.h66
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-fns.h6
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h241
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-mem.h28
-rw-r--r--arch/arm/mach-s3c2412/Kconfig2
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/debug-macro.S27
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/io.h18
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/irqs.h117
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/map.h86
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/memory.h21
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/regs-clock.h88
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/regs-irq.h25
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/system.h25
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/tick.h15
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/timex.h18
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/vmalloc.h17
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig2
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c15
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-iis.h9
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-spi.h1
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2400.h31
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h8
49 files changed, 4 insertions, 1892 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ebaa380fde29..9cb1f4bd7618 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -493,14 +493,6 @@ config ARCH_KIRKWOOD
493 Support for the following Marvell Kirkwood series SoCs: 493 Support for the following Marvell Kirkwood series SoCs:
494 88F6180, 88F6192 and 88F6281. 494 88F6180, 88F6192 and 88F6281.
495 495
496config ARCH_LOKI
497 bool "Marvell Loki (88RC8480)"
498 select CPU_FEROCEON
499 select GENERIC_CLOCKEVENTS
500 select PLAT_ORION
501 help
502 Support for the Marvell Loki (88RC8480) SoC.
503
504config ARCH_LPC32XX 496config ARCH_LPC32XX
505 bool "NXP LPC32XX" 497 bool "NXP LPC32XX"
506 select CLKSRC_MMIO 498 select CLKSRC_MMIO
@@ -937,8 +929,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
937 929
938source "arch/arm/mach-ks8695/Kconfig" 930source "arch/arm/mach-ks8695/Kconfig"
939 931
940source "arch/arm/mach-loki/Kconfig"
941
942source "arch/arm/mach-lpc32xx/Kconfig" 932source "arch/arm/mach-lpc32xx/Kconfig"
943 933
944source "arch/arm/mach-msm/Kconfig" 934source "arch/arm/mach-msm/Kconfig"
@@ -982,7 +972,6 @@ source "arch/arm/plat-spear/Kconfig"
982source "arch/arm/plat-tcc/Kconfig" 972source "arch/arm/plat-tcc/Kconfig"
983 973
984if ARCH_S3C2410 974if ARCH_S3C2410
985source "arch/arm/mach-s3c2400/Kconfig"
986source "arch/arm/mach-s3c2410/Kconfig" 975source "arch/arm/mach-s3c2410/Kconfig"
987source "arch/arm/mach-s3c2412/Kconfig" 976source "arch/arm/mach-s3c2412/Kconfig"
988source "arch/arm/mach-s3c2416/Kconfig" 977source "arch/arm/mach-s3c2416/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f5b2b390c8f2..206c34ecb9e3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -150,7 +150,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
150machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 150machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
151machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood 151machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
152machine-$(CONFIG_ARCH_KS8695) := ks8695 152machine-$(CONFIG_ARCH_KS8695) := ks8695
153machine-$(CONFIG_ARCH_LOKI) := loki
154machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx 153machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
155machine-$(CONFIG_ARCH_MMP) := mmp 154machine-$(CONFIG_ARCH_MMP) := mmp
156machine-$(CONFIG_ARCH_MSM) := msm 155machine-$(CONFIG_ARCH_MSM) := msm
@@ -172,8 +171,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008
172machine-$(CONFIG_ARCH_PXA) := pxa 171machine-$(CONFIG_ARCH_PXA) := pxa
173machine-$(CONFIG_ARCH_REALVIEW) := realview 172machine-$(CONFIG_ARCH_REALVIEW) := realview
174machine-$(CONFIG_ARCH_RPC) := rpc 173machine-$(CONFIG_ARCH_RPC) := rpc
175machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 174machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2412 s3c2416 s3c2440 s3c2443
176machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
177machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx 175machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
178machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 176machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
179machine-$(CONFIG_ARCH_S5PC100) := s5pc100 177machine-$(CONFIG_ARCH_S5PC100) := s5pc100
diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig
deleted file mode 100644
index 1ba752b2dc6d..000000000000
--- a/arch/arm/configs/loki_defconfig
+++ /dev/null
@@ -1,120 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_LOG_BUF_SHIFT=14
4CONFIG_EXPERT=y
5CONFIG_SLAB=y
6CONFIG_MODULES=y
7CONFIG_MODULE_UNLOAD=y
8# CONFIG_BLK_DEV_BSG is not set
9CONFIG_ARCH_LOKI=y
10CONFIG_MACH_LB88RC8480=y
11# CONFIG_CPU_FEROCEON_OLD_ID is not set
12CONFIG_NO_HZ=y
13CONFIG_HIGH_RES_TIMERS=y
14CONFIG_PREEMPT=y
15CONFIG_AEABI=y
16CONFIG_ZBOOT_ROM_TEXT=0x0
17CONFIG_ZBOOT_ROM_BSS=0x0
18CONFIG_NET=y
19CONFIG_PACKET=y
20CONFIG_UNIX=y
21CONFIG_INET=y
22CONFIG_IP_MULTICAST=y
23CONFIG_IP_PNP=y
24CONFIG_IP_PNP_DHCP=y
25CONFIG_IP_PNP_BOOTP=y
26# CONFIG_IPV6 is not set
27CONFIG_NET_PKTGEN=m
28CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
29CONFIG_MTD=y
30CONFIG_MTD_PARTITIONS=y
31CONFIG_MTD_CMDLINE_PARTS=y
32CONFIG_MTD_CHAR=y
33CONFIG_MTD_BLOCK=y
34CONFIG_FTL=y
35CONFIG_NFTL=y
36CONFIG_MTD_CFI=y
37CONFIG_MTD_JEDECPROBE=y
38CONFIG_MTD_CFI_ADV_OPTIONS=y
39CONFIG_MTD_CFI_GEOMETRY=y
40CONFIG_MTD_CFI_I4=y
41CONFIG_MTD_CFI_INTELEXT=y
42CONFIG_MTD_CFI_AMDSTD=y
43CONFIG_MTD_CFI_STAA=y
44CONFIG_MTD_PHYSMAP=y
45CONFIG_MTD_M25P80=y
46CONFIG_MTD_NAND=y
47CONFIG_MTD_NAND_VERIFY_WRITE=y
48CONFIG_MTD_NAND_ORION=y
49CONFIG_BLK_DEV_LOOP=y
50# CONFIG_MISC_DEVICES is not set
51# CONFIG_SCSI_PROC_FS is not set
52CONFIG_BLK_DEV_SD=y
53CONFIG_BLK_DEV_SR=m
54CONFIG_CHR_DEV_SG=m
55CONFIG_ATA=y
56CONFIG_SATA_MV=y
57CONFIG_NETDEVICES=y
58CONFIG_NET_ETHERNET=y
59CONFIG_MII=y
60CONFIG_MV643XX_ETH=y
61# CONFIG_NETDEV_10000 is not set
62# CONFIG_INPUT_KEYBOARD is not set
63# CONFIG_INPUT_MOUSE is not set
64# CONFIG_SERIO is not set
65CONFIG_SERIAL_8250=y
66CONFIG_SERIAL_8250_CONSOLE=y
67CONFIG_SERIAL_8250_RUNTIME_UARTS=2
68CONFIG_LEGACY_PTY_COUNT=16
69CONFIG_I2C=y
70CONFIG_I2C_CHARDEV=y
71CONFIG_I2C_MV64XXX=y
72CONFIG_SPI=y
73# CONFIG_HWMON is not set
74# CONFIG_VGA_CONSOLE is not set
75CONFIG_USB=y
76CONFIG_USB_DEVICEFS=y
77CONFIG_USB_PRINTER=y
78CONFIG_USB_STORAGE=y
79CONFIG_USB_STORAGE_DATAFAB=y
80CONFIG_USB_STORAGE_FREECOM=y
81CONFIG_USB_STORAGE_SDDR09=y
82CONFIG_USB_STORAGE_SDDR55=y
83CONFIG_USB_STORAGE_JUMPSHOT=y
84CONFIG_NEW_LEDS=y
85CONFIG_EXT2_FS=y
86CONFIG_EXT3_FS=y
87# CONFIG_EXT3_FS_XATTR is not set
88CONFIG_XFS_FS=y
89CONFIG_INOTIFY=y
90CONFIG_ISO9660_FS=y
91CONFIG_UDF_FS=m
92CONFIG_MSDOS_FS=y
93CONFIG_VFAT_FS=y
94CONFIG_TMPFS=y
95CONFIG_JFFS2_FS=y
96CONFIG_CRAMFS=y
97CONFIG_NFS_FS=y
98CONFIG_NFS_V3=y
99CONFIG_ROOT_NFS=y
100CONFIG_PARTITION_ADVANCED=y
101CONFIG_BSD_DISKLABEL=y
102CONFIG_MINIX_SUBPARTITION=y
103CONFIG_SOLARIS_X86_PARTITION=y
104CONFIG_UNIXWARE_DISKLABEL=y
105CONFIG_LDM_PARTITION=y
106CONFIG_LDM_DEBUG=y
107CONFIG_SUN_PARTITION=y
108CONFIG_NLS_CODEPAGE_437=y
109CONFIG_NLS_CODEPAGE_850=y
110CONFIG_NLS_ISO8859_1=y
111CONFIG_NLS_ISO8859_2=y
112CONFIG_MAGIC_SYSRQ=y
113CONFIG_SYSCTL_SYSCALL_CHECK=y
114CONFIG_DEBUG_USER=y
115CONFIG_CRYPTO_CBC=m
116CONFIG_CRYPTO_ECB=m
117CONFIG_CRYPTO_PCBC=m
118CONFIG_CRC_CCITT=y
119CONFIG_CRC16=y
120CONFIG_LIBCRC32C=y
diff --git a/arch/arm/mach-loki/Kconfig b/arch/arm/mach-loki/Kconfig
deleted file mode 100644
index 0045bdd761ca..000000000000
--- a/arch/arm/mach-loki/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
1if ARCH_LOKI
2
3menu "Marvell Loki (88RC8480) Implementations"
4
5config MACH_LB88RC8480
6 bool "Marvell LB88RC8480 Development Board"
7 help
8 Say 'Y' here if you want your kernel to support the
9 Marvell LB88RC8480 Development Board.
10
11endmenu
12
13endif
diff --git a/arch/arm/mach-loki/Makefile b/arch/arm/mach-loki/Makefile
deleted file mode 100644
index d43233ee590f..000000000000
--- a/arch/arm/mach-loki/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1obj-y += common.o addr-map.o irq.o
2
3obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o
diff --git a/arch/arm/mach-loki/Makefile.boot b/arch/arm/mach-loki/Makefile.boot
deleted file mode 100644
index 67039c3e0c48..000000000000
--- a/arch/arm/mach-loki/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
deleted file mode 100644
index b9537c97beba..000000000000
--- a/arch/arm/mach-loki/addr-map.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * arch/arm/mach-loki/addr-map.c
3 *
4 * Address map functions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <mach/hardware.h>
16#include "common.h"
17
18/*
19 * Generic Address Decode Windows bit settings
20 */
21#define TARGET_DDR 0
22#define TARGET_DEV_BUS 1
23#define TARGET_PCIE0 3
24#define TARGET_PCIE1 4
25#define ATTR_DEV_BOOT 0x0f
26#define ATTR_DEV_CS2 0x1b
27#define ATTR_DEV_CS1 0x1d
28#define ATTR_DEV_CS0 0x1e
29#define ATTR_PCIE_IO 0x51
30#define ATTR_PCIE_MEM 0x59
31
32/*
33 * Helpers to get DDR bank info
34 */
35#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
36#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
37
38/*
39 * CPU Address Decode Windows registers
40 */
41#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
42#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
43#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
44#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
45#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4))
46
47
48struct mbus_dram_target_info loki_mbus_dram_info;
49
50static void __init setup_cpu_win(int win, u32 base, u32 size,
51 u8 target, u8 attr, int remap)
52{
53 u32 ctrl;
54
55 base &= 0xffff0000;
56 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
57
58 writel(base, CPU_WIN_BASE(win));
59 writel(ctrl, CPU_WIN_CTRL(win));
60 if (win < 2) {
61 if (remap < 0)
62 remap = base;
63
64 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
65 writel(0, CPU_WIN_REMAP_HI(win));
66 }
67}
68
69void __init loki_setup_cpu_mbus(void)
70{
71 int i;
72 int cs;
73
74 /*
75 * First, disable and clear windows.
76 */
77 for (i = 0; i < 8; i++) {
78 writel(0, CPU_WIN_BASE(i));
79 writel(0, CPU_WIN_CTRL(i));
80 if (i < 2) {
81 writel(0, CPU_WIN_REMAP_LO(i));
82 writel(0, CPU_WIN_REMAP_HI(i));
83 }
84 }
85
86 /*
87 * Setup windows for PCIe IO+MEM space.
88 */
89 setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
90 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
91 setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
92 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
93
94 /*
95 * Setup MBUS dram target info.
96 */
97 loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
98
99 for (i = 0, cs = 0; i < 4; i++) {
100 u32 base = readl(DDR_BASE_CS(i));
101 u32 size = readl(DDR_SIZE_CS(i));
102
103 /*
104 * Chip select enabled?
105 */
106 if (size & 1) {
107 struct mbus_dram_window *w;
108
109 w = &loki_mbus_dram_info.cs[cs++];
110 w->cs_index = i;
111 w->mbus_attr = 0xf & ~(1 << i);
112 w->base = base & 0xffff0000;
113 w->size = (size | 0x0000ffff) + 1;
114 }
115 }
116 loki_mbus_dram_info.num_cs = cs;
117}
118
119void __init loki_setup_dev_boot_win(u32 base, u32 size)
120{
121 setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
122}
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
deleted file mode 100644
index 5f02664db812..000000000000
--- a/arch/arm/mach-loki/common.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * arch/arm/mach-loki/common.c
3 *
4 * Core functions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/dma-mapping.h>
17#include <asm/page.h>
18#include <asm/timex.h>
19#include <asm/mach/map.h>
20#include <asm/mach/time.h>
21#include <mach/bridge-regs.h>
22#include <mach/loki.h>
23#include <plat/orion_nand.h>
24#include <plat/time.h>
25#include <plat/common.h>
26#include "common.h"
27
28/*****************************************************************************
29 * I/O Address Mapping
30 ****************************************************************************/
31static struct map_desc loki_io_desc[] __initdata = {
32 {
33 .virtual = LOKI_REGS_VIRT_BASE,
34 .pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
35 .length = LOKI_REGS_SIZE,
36 .type = MT_DEVICE,
37 },
38};
39
40void __init loki_map_io(void)
41{
42 iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
43}
44
45
46/*****************************************************************************
47 * GE00
48 ****************************************************************************/
49void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
50{
51 writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
52
53 orion_ge00_init(eth_data, &loki_mbus_dram_info,
54 GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
55 0, LOKI_TCLK);
56}
57
58
59/*****************************************************************************
60 * GE01
61 ****************************************************************************/
62void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
63{
64 writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
65
66 orion_ge01_init(eth_data, &loki_mbus_dram_info,
67 GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
68 0, LOKI_TCLK);
69}
70
71
72/*****************************************************************************
73 * SAS/SATA
74 ****************************************************************************/
75static struct resource loki_sas_resources[] = {
76 {
77 .name = "mvsas0 mem",
78 .start = SAS0_PHYS_BASE,
79 .end = SAS0_PHYS_BASE + 0x01ff,
80 .flags = IORESOURCE_MEM,
81 }, {
82 .name = "mvsas0 irq",
83 .start = IRQ_LOKI_SAS_A,
84 .end = IRQ_LOKI_SAS_A,
85 .flags = IORESOURCE_IRQ,
86 }, {
87 .name = "mvsas1 mem",
88 .start = SAS1_PHYS_BASE,
89 .end = SAS1_PHYS_BASE + 0x01ff,
90 .flags = IORESOURCE_MEM,
91 }, {
92 .name = "mvsas1 irq",
93 .start = IRQ_LOKI_SAS_B,
94 .end = IRQ_LOKI_SAS_B,
95 .flags = IORESOURCE_IRQ,
96 },
97};
98
99static struct platform_device loki_sas = {
100 .name = "mvsas",
101 .id = 0,
102 .dev = {
103 .coherent_dma_mask = DMA_BIT_MASK(32),
104 },
105 .num_resources = ARRAY_SIZE(loki_sas_resources),
106 .resource = loki_sas_resources,
107};
108
109void __init loki_sas_init(void)
110{
111 writel(0x8300f707, DDR_REG(0x1424));
112 platform_device_register(&loki_sas);
113}
114
115
116/*****************************************************************************
117 * UART0
118 ****************************************************************************/
119void __init loki_uart0_init(void)
120{
121 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
122 IRQ_LOKI_UART0, LOKI_TCLK);
123}
124
125/*****************************************************************************
126 * UART1
127 ****************************************************************************/
128void __init loki_uart1_init(void)
129{
130 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
131 IRQ_LOKI_UART1, LOKI_TCLK);
132}
133
134
135/*****************************************************************************
136 * Time handling
137 ****************************************************************************/
138void __init loki_init_early(void)
139{
140 orion_time_set_base(TIMER_VIRT_BASE);
141}
142
143static void loki_timer_init(void)
144{
145 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
146 IRQ_LOKI_BRIDGE, LOKI_TCLK);
147}
148
149struct sys_timer loki_timer = {
150 .init = loki_timer_init,
151};
152
153
154/*****************************************************************************
155 * General
156 ****************************************************************************/
157void __init loki_init(void)
158{
159 printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
160
161 loki_setup_cpu_mbus();
162}
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
deleted file mode 100644
index a315dcf8887c..000000000000
--- a/arch/arm/mach-loki/common.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * arch/arm/mach-loki/common.h
3 *
4 * Core functions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_LOKI_COMMON_H
12#define __ARCH_LOKI_COMMON_H
13
14struct mv643xx_eth_platform_data;
15
16/*
17 * Basic Loki init functions used early by machine-setup.
18 */
19void loki_map_io(void);
20void loki_init(void);
21void loki_init_early(void);
22void loki_init_irq(void);
23
24extern struct mbus_dram_target_info loki_mbus_dram_info;
25void loki_setup_cpu_mbus(void);
26void loki_setup_dev_boot_win(u32 base, u32 size);
27
28void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
29void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
30void loki_sas_init(void);
31void loki_uart0_init(void);
32void loki_uart1_init(void);
33
34extern struct sys_timer loki_timer;
35
36
37#endif
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
deleted file mode 100644
index fd87732097cd..000000000000
--- a/arch/arm/mach-loki/include/mach/bridge-regs.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/bridge-regs.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_BRIDGE_REGS_H
10#define __ASM_ARCH_BRIDGE_REGS_H
11
12#include <mach/loki.h>
13
14#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
15#define SOFT_RESET_OUT_EN 0x00000004
16
17#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
18#define SOFT_RESET 0x00000001
19
20#define BRIDGE_INT_TIMER1_CLR 0x0004
21
22#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
23#define IRQ_CAUSE_OFF 0x0000
24#define IRQ_MASK_OFF 0x0004
25
26#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
27
28#endif
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S
deleted file mode 100644
index cc90d99ac76c..000000000000
--- a/arch/arm/mach-loki/include/mach/debug-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <mach/loki.h>
10
11 .macro addruart, rp, rv
12 ldr \rp, =LOKI_REGS_PHYS_BASE
13 ldr \rv, =LOKI_REGS_VIRT_BASE
14 orr \rp, \rp, #0x00012000
15 orr \rv, \rv, #0x00012000
16 .endm
17
18#define UART_SHIFT 2
19#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-loki/include/mach/entry-macro.S b/arch/arm/mach-loki/include/mach/entry-macro.S
deleted file mode 100644
index bc917ed3a62d..000000000000
--- a/arch/arm/mach-loki/include/mach/entry-macro.S
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <mach/bridge-regs.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
25 ldr \tmp, [\base, #IRQ_MASK_OFF]
26 mov \irqnr, #0
27 ands \irqstat, \irqstat, \tmp
28 clzne \irqnr, \irqstat
29 rsbne \irqnr, \irqnr, #31
30 .endm
diff --git a/arch/arm/mach-loki/include/mach/hardware.h b/arch/arm/mach-loki/include/mach/hardware.h
deleted file mode 100644
index d7bfc8f17729..000000000000
--- a/arch/arm/mach-loki/include/mach/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "loki.h"
13
14
15#endif
diff --git a/arch/arm/mach-loki/include/mach/io.h b/arch/arm/mach-loki/include/mach/io.h
deleted file mode 100644
index a373cd582c84..000000000000
--- a/arch/arm/mach-loki/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "loki.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
19 + LOKI_PCIE0_IO_VIRT_BASE);
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/arch/arm/mach-loki/include/mach/irqs.h b/arch/arm/mach-loki/include/mach/irqs.h
deleted file mode 100644
index 9fbd3326867b..000000000000
--- a/arch/arm/mach-loki/include/mach/irqs.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/irqs.h
3 *
4 * IRQ definitions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "loki.h" /* need GPIO_MAX */
15
16/*
17 * Interrupt Controller
18 */
19#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
20#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
21#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
22#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
23#define IRQ_LOKI_COM_A_ERR 6
24#define IRQ_LOKI_COM_A_IN 7
25#define IRQ_LOKI_COM_A_OUT 8
26#define IRQ_LOKI_COM_B_ERR 9
27#define IRQ_LOKI_COM_B_IN 10
28#define IRQ_LOKI_COM_B_OUT 11
29#define IRQ_LOKI_DMA_A 12
30#define IRQ_LOKI_DMA_B 13
31#define IRQ_LOKI_SAS_A 14
32#define IRQ_LOKI_SAS_B 15
33#define IRQ_LOKI_DDR 16
34#define IRQ_LOKI_XOR 17
35#define IRQ_LOKI_BRIDGE 18
36#define IRQ_LOKI_PCIE_A_ERR 20
37#define IRQ_LOKI_PCIE_A_INT 21
38#define IRQ_LOKI_PCIE_B_ERR 22
39#define IRQ_LOKI_PCIE_B_INT 23
40#define IRQ_LOKI_GBE_A_INT 24
41#define IRQ_LOKI_GBE_B_INT 25
42#define IRQ_LOKI_DEV_ERR 26
43#define IRQ_LOKI_UART0 27
44#define IRQ_LOKI_UART1 28
45#define IRQ_LOKI_TWSI 29
46#define IRQ_LOKI_GPIO_23_0 30
47#define IRQ_LOKI_GPIO_25_24 31
48
49/*
50 * Loki General Purpose Pins
51 */
52#define IRQ_LOKI_GPIO_START 32
53#define NR_GPIO_IRQS GPIO_MAX
54
55#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
56
57
58#endif
diff --git a/arch/arm/mach-loki/include/mach/loki.h b/arch/arm/mach-loki/include/mach/loki.h
deleted file mode 100644
index bfca7c265f43..000000000000
--- a/arch/arm/mach-loki/include/mach/loki.h
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/loki.h
3 *
4 * Generic definitions for Marvell Loki (88RC8480) SoC flavors
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_LOKI_H
12#define __ASM_ARCH_LOKI_H
13
14/*
15 * Marvell Loki (88RC8480) address maps.
16 *
17 * phys
18 * d0000000 on-chip peripheral registers
19 * e0000000 PCIe 0 Memory space
20 * e8000000 PCIe 1 Memory space
21 * f0000000 PCIe 0 I/O space
22 * f0100000 PCIe 1 I/O space
23 *
24 * virt phys size
25 * fed00000 d0000000 1M on-chip peripheral registers
26 * fee00000 f0000000 64K PCIe 0 I/O space
27 * fef00000 f0100000 64K PCIe 1 I/O space
28 */
29
30#define LOKI_REGS_PHYS_BASE 0xd0000000
31#define LOKI_REGS_VIRT_BASE 0xfed00000
32#define LOKI_REGS_SIZE SZ_1M
33
34#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
35#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
36#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
37#define LOKI_PCIE0_IO_SIZE SZ_64K
38
39#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
40#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
41#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
42#define LOKI_PCIE1_IO_SIZE SZ_64K
43
44#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
45#define LOKI_PCIE0_MEM_SIZE SZ_128M
46
47#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
48#define LOKI_PCIE1_MEM_SIZE SZ_128M
49
50/*
51 * Register Map
52 */
53#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
54#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
55#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
56#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
57#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
58#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
59
60#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
61
62#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
63
64#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
65
66#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
67
68#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
69
70#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
71#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
72
73#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
74#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
75
76#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
77#define DDR_REG(x) (DDR_VIRT_BASE | (x))
78
79
80#define GPIO_MAX 8
81
82
83#endif
diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h
deleted file mode 100644
index 66366657a875..000000000000
--- a/arch/arm/mach-loki/include/mach/memory.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PLAT_PHYS_OFFSET UL(0x00000000)
9
10#endif
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h
deleted file mode 100644
index 71895199a534..000000000000
--- a/arch/arm/mach-loki/include/mach/system.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <mach/bridge-regs.h>
13
14static inline void arch_idle(void)
15{
16 cpu_do_idle();
17}
18
19static inline void arch_reset(char mode, const char *cmd)
20{
21 /*
22 * Enable soft reset to assert RSTOUTn.
23 */
24 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
25
26 /*
27 * Assert soft reset.
28 */
29 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
30
31 while (1)
32 ;
33}
34
35
36#endif
diff --git a/arch/arm/mach-loki/include/mach/timex.h b/arch/arm/mach-loki/include/mach/timex.h
deleted file mode 100644
index 9df210915297..000000000000
--- a/arch/arm/mach-loki/include/mach/timex.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
10
11#define LOKI_TCLK 180000000
diff --git a/arch/arm/mach-loki/include/mach/uncompress.h b/arch/arm/mach-loki/include/mach/uncompress.h
deleted file mode 100644
index 90b2a7e65da3..000000000000
--- a/arch/arm/mach-loki/include/mach/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <mach/loki.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/arch/arm/mach-loki/include/mach/vmalloc.h b/arch/arm/mach-loki/include/mach/vmalloc.h
deleted file mode 100644
index 5dcbd865443f..000000000000
--- a/arch/arm/mach-loki/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * arch/arm/mach-loki/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe800000UL
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c
deleted file mode 100644
index 76b211bfcca2..000000000000
--- a/arch/arm/mach-loki/irq.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * arch/arm/mach-loki/irq.c
3 *
4 * Marvell Loki (88RC8480) IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/io.h>
15#include <mach/bridge-regs.h>
16#include <plat/irq.h>
17#include "common.h"
18
19void __init loki_init_irq(void)
20{
21 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
22}
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
deleted file mode 100644
index 35eae4e6abb2..000000000000
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * arch/arm/mach-loki/lb88rc8480-setup.c
3 *
4 * Marvell LB88RC8480 Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/irq.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mtd/nand.h>
17#include <linux/timer.h>
18#include <linux/ata_platform.h>
19#include <linux/mv643xx_eth.h>
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <mach/loki.h>
23#include "common.h"
24
25#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000
26#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M
27
28#define LB88RC8480_NOR_BOOT_BASE 0xff000000
29#define LB88RC8480_NOR_BOOT_SIZE SZ_16M
30
31static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
32 {
33 .name = "kernel",
34 .offset = 0,
35 .size = SZ_2M,
36 }, {
37 .name = "root-fs",
38 .offset = SZ_2M,
39 .size = (SZ_8M + SZ_4M + SZ_1M),
40 }, {
41 .name = "u-boot",
42 .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
43 .size = SZ_1M,
44 },
45};
46
47static struct physmap_flash_data lb88rc8480_boot_flash_data = {
48 .parts = lb88rc8480_boot_flash_parts,
49 .nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
50 .width = 1, /* 8 bit bus width */
51};
52
53static struct resource lb88rc8480_boot_flash_resource = {
54 .flags = IORESOURCE_MEM,
55 .start = LB88RC8480_NOR_BOOT_BASE,
56 .end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
57};
58
59static struct platform_device lb88rc8480_boot_flash = {
60 .name = "physmap-flash",
61 .id = 0,
62 .dev = {
63 .platform_data = &lb88rc8480_boot_flash_data,
64 },
65 .num_resources = 1,
66 .resource = &lb88rc8480_boot_flash_resource,
67};
68
69static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
70 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
71 .mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
72};
73
74static void __init lb88rc8480_init(void)
75{
76 /*
77 * Basic setup. Needs to be called early.
78 */
79 loki_init();
80
81 loki_ge0_init(&lb88rc8480_ge0_data);
82 loki_sas_init();
83 loki_uart0_init();
84 loki_uart1_init();
85
86 loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
87 LB88RC8480_FLASH_BOOT_CS_SIZE);
88 platform_device_register(&lb88rc8480_boot_flash);
89}
90
91MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
92 /* Maintainer: Ke Wei <kewei@marvell.com> */
93 .boot_params = 0x00000100,
94 .init_machine = lb88rc8480_init,
95 .map_io = loki_map_io,
96 .init_early = loki_init_early,
97 .init_irq = loki_init_irq,
98 .timer = &loki_timer,
99MACHINE_END
diff --git a/arch/arm/mach-s3c2400/Kconfig b/arch/arm/mach-s3c2400/Kconfig
deleted file mode 100644
index fdd8f5e96faf..000000000000
--- a/arch/arm/mach-s3c2400/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
1# Copyright 2007 Simtec Electronics
2#
3# Licensed under GPLv2
4
5menu "S3C2400 Machines"
6
7endmenu
diff --git a/arch/arm/mach-s3c2400/Makefile b/arch/arm/mach-s3c2400/Makefile
deleted file mode 100644
index 7e23f4e13766..000000000000
--- a/arch/arm/mach-s3c2400/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
1# arch/arm/mach-s3c2400/Makefile
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12obj-$(CONFIG_CPU_S3C2400) += gpio.o
13
14# Machine support
15
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
deleted file mode 100644
index 6c68e78f3595..000000000000
--- a/arch/arm/mach-s3c2400/gpio.c
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s3c2400/gpio.c
2 *
3 * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
4 *
5 * S3C2400 GPIO support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20*/
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/interrupt.h>
26#include <linux/ioport.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <mach/regs-gpio.h>
33
34int s3c2400_gpio_getirq(unsigned int pin)
35{
36 if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
37 return -EINVAL; /* not valid interrupts */
38
39 return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
40}
41
42EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2400/include/mach/map.h b/arch/arm/mach-s3c2400/include/mach/map.h
deleted file mode 100644
index 3fd889200e99..000000000000
--- a/arch/arm/mach-s3c2400/include/mach/map.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/* arch/arm/mach-s3c2400/include/mach/map.h
2 *
3 * Copyright 2003-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Copyright 2003, Lucas Correia Villa Real
8 *
9 * S3C2400 - Memory map definitions
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#define S3C2400_PA_MEMCTRL (0x14000000)
17#define S3C2400_PA_USBHOST (0x14200000)
18#define S3C2400_PA_IRQ (0x14400000)
19#define S3C2400_PA_DMA (0x14600000)
20#define S3C2400_PA_CLKPWR (0x14800000)
21#define S3C2400_PA_LCD (0x14A00000)
22#define S3C2400_PA_UART (0x15000000)
23#define S3C2400_PA_TIMER (0x15100000)
24#define S3C2400_PA_USBDEV (0x15200140)
25#define S3C2400_PA_WATCHDOG (0x15300000)
26#define S3C2400_PA_IIC (0x15400000)
27#define S3C2400_PA_IIS (0x15508000)
28#define S3C2400_PA_GPIO (0x15600000)
29#define S3C2400_PA_RTC (0x15700040)
30#define S3C2400_PA_ADC (0x15800000)
31#define S3C2400_PA_SPI (0x15900000)
32
33#define S3C2400_PA_MMC (0x15A00000)
34#define S3C2400_SZ_MMC SZ_1M
35
36/* physical addresses of all the chip-select areas */
37
38#define S3C2400_CS0 (0x00000000)
39#define S3C2400_CS1 (0x02000000)
40#define S3C2400_CS2 (0x04000000)
41#define S3C2400_CS3 (0x06000000)
42#define S3C2400_CS4 (0x08000000)
43#define S3C2400_CS5 (0x0A000000)
44#define S3C2400_CS6 (0x0C000000)
45#define S3C2400_CS7 (0x0E000000)
46
47#define S3C2400_SDRAM_PA (S3C2400_CS6)
48
49/* Use a single interface for common resources between S3C24XX cpus */
50
51#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
52#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
53#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
54#define S3C24XX_PA_DMA S3C2400_PA_DMA
55#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
56#define S3C24XX_PA_LCD S3C2400_PA_LCD
57#define S3C24XX_PA_UART S3C2400_PA_UART
58#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
59#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
60#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
61#define S3C24XX_PA_IIC S3C2400_PA_IIC
62#define S3C24XX_PA_IIS S3C2400_PA_IIS
63#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
64#define S3C24XX_PA_RTC S3C2400_PA_RTC
65#define S3C24XX_PA_ADC S3C2400_PA_ADC
66#define S3C24XX_PA_SPI S3C2400_PA_SPI
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index f453c4f2cb8e..bab139201761 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -52,12 +52,6 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
52 52
53extern int s3c2410_gpio_getirq(unsigned int pin); 53extern int s3c2410_gpio_getirq(unsigned int pin);
54 54
55#ifdef CONFIG_CPU_S3C2400
56
57extern int s3c2400_gpio_getirq(unsigned int pin);
58
59#endif /* CONFIG_CPU_S3C2400 */
60
61/* s3c2410_gpio_irqfilter 55/* s3c2410_gpio_irqfilter
62 * 56 *
63 * set the irq filtering on the given pin 57 * set the irq filtering on the given pin
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index a0a89d429296..cac1ad6b582c 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -16,11 +16,7 @@
16 16
17#include <mach/gpio-nrs.h> 17#include <mach/gpio-nrs.h>
18 18
19#ifdef CONFIG_CPU_S3C2400
20#define S3C24XX_MISCCR S3C2400_MISCCR
21#else
22#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) 19#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
23#endif /* CONFIG_CPU_S3C2400 */
24 20
25/* general configuration options */ 21/* general configuration options */
26 22
@@ -42,67 +38,33 @@
42/* configure GPIO ports A..G */ 38/* configure GPIO ports A..G */
43 39
44/* port A - S3C2410: 22bits, zero in bit X makes pin X output 40/* port A - S3C2410: 22bits, zero in bit X makes pin X output
45 * S3C2400: 18bits, zero in bit X makes pin X output
46 * 1 makes port special function, this is default 41 * 1 makes port special function, this is default
47*/ 42*/
48#define S3C2410_GPACON S3C2410_GPIOREG(0x00) 43#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
49#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) 44#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
50 45
51#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
52#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
53
54#define S3C2410_GPA0_ADDR0 (1<<0) 46#define S3C2410_GPA0_ADDR0 (1<<0)
55
56#define S3C2410_GPA1_ADDR16 (1<<1) 47#define S3C2410_GPA1_ADDR16 (1<<1)
57
58#define S3C2410_GPA2_ADDR17 (1<<2) 48#define S3C2410_GPA2_ADDR17 (1<<2)
59
60#define S3C2410_GPA3_ADDR18 (1<<3) 49#define S3C2410_GPA3_ADDR18 (1<<3)
61
62#define S3C2410_GPA4_ADDR19 (1<<4) 50#define S3C2410_GPA4_ADDR19 (1<<4)
63
64#define S3C2410_GPA5_ADDR20 (1<<5) 51#define S3C2410_GPA5_ADDR20 (1<<5)
65
66#define S3C2410_GPA6_ADDR21 (1<<6) 52#define S3C2410_GPA6_ADDR21 (1<<6)
67
68#define S3C2410_GPA7_ADDR22 (1<<7) 53#define S3C2410_GPA7_ADDR22 (1<<7)
69
70#define S3C2410_GPA8_ADDR23 (1<<8) 54#define S3C2410_GPA8_ADDR23 (1<<8)
71
72#define S3C2410_GPA9_ADDR24 (1<<9) 55#define S3C2410_GPA9_ADDR24 (1<<9)
73
74#define S3C2410_GPA10_ADDR25 (1<<10) 56#define S3C2410_GPA10_ADDR25 (1<<10)
75#define S3C2400_GPA10_SCKE (1<<10)
76
77#define S3C2410_GPA11_ADDR26 (1<<11) 57#define S3C2410_GPA11_ADDR26 (1<<11)
78#define S3C2400_GPA11_nCAS0 (1<<11)
79
80#define S3C2410_GPA12_nGCS1 (1<<12) 58#define S3C2410_GPA12_nGCS1 (1<<12)
81#define S3C2400_GPA12_nCAS1 (1<<12)
82
83#define S3C2410_GPA13_nGCS2 (1<<13) 59#define S3C2410_GPA13_nGCS2 (1<<13)
84#define S3C2400_GPA13_nGCS1 (1<<13)
85
86#define S3C2410_GPA14_nGCS3 (1<<14) 60#define S3C2410_GPA14_nGCS3 (1<<14)
87#define S3C2400_GPA14_nGCS2 (1<<14)
88
89#define S3C2410_GPA15_nGCS4 (1<<15) 61#define S3C2410_GPA15_nGCS4 (1<<15)
90#define S3C2400_GPA15_nGCS3 (1<<15)
91
92#define S3C2410_GPA16_nGCS5 (1<<16) 62#define S3C2410_GPA16_nGCS5 (1<<16)
93#define S3C2400_GPA16_nGCS4 (1<<16)
94
95#define S3C2410_GPA17_CLE (1<<17) 63#define S3C2410_GPA17_CLE (1<<17)
96#define S3C2400_GPA17_nGCS5 (1<<17)
97
98#define S3C2410_GPA18_ALE (1<<18) 64#define S3C2410_GPA18_ALE (1<<18)
99
100#define S3C2410_GPA19_nFWE (1<<19) 65#define S3C2410_GPA19_nFWE (1<<19)
101
102#define S3C2410_GPA20_nFRE (1<<20) 66#define S3C2410_GPA20_nFRE (1<<20)
103
104#define S3C2410_GPA21_nRSTOUT (1<<21) 67#define S3C2410_GPA21_nRSTOUT (1<<21)
105
106#define S3C2410_GPA22_nFCE (1<<22) 68#define S3C2410_GPA22_nFCE (1<<22)
107 69
108/* 0x08 and 0x0c are reserved on S3C2410 */ 70/* 0x08 and 0x0c are reserved on S3C2410 */
@@ -111,10 +73,6 @@
111 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. 73 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
112 * 00 = input, 01 = output, 10=special function, 11=reserved 74 * 00 = input, 01 = output, 10=special function, 11=reserved
113 75
114 * S3C2400:
115 * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
116 * 00 = input, 01 = output, 10=data, 11=special function
117
118 * bit 0,1 = pin 0, 2,3= pin 1... 76 * bit 0,1 = pin 0, 2,3= pin 1...
119 * 77 *
120 * CPBUP = pull up resistor control, 1=disabled, 0=enabled 78 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
@@ -124,78 +82,35 @@
124#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) 82#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
125#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) 83#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
126 84
127#define S3C2400_GPBCON S3C2410_GPIOREG(0x08)
128#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
129#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
130
131/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 85/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
132 86
133#define S3C2410_GPB0_TOUT0 (0x02 << 0) 87#define S3C2410_GPB0_TOUT0 (0x02 << 0)
134#define S3C2400_GPB0_DATA16 (0x02 << 0)
135 88
136#define S3C2410_GPB1_TOUT1 (0x02 << 2) 89#define S3C2410_GPB1_TOUT1 (0x02 << 2)
137#define S3C2400_GPB1_DATA17 (0x02 << 2)
138 90
139#define S3C2410_GPB2_TOUT2 (0x02 << 4) 91#define S3C2410_GPB2_TOUT2 (0x02 << 4)
140#define S3C2400_GPB2_DATA18 (0x02 << 4)
141#define S3C2400_GPB2_TCLK1 (0x03 << 4)
142 92
143#define S3C2410_GPB3_TOUT3 (0x02 << 6) 93#define S3C2410_GPB3_TOUT3 (0x02 << 6)
144#define S3C2400_GPB3_DATA19 (0x02 << 6)
145#define S3C2400_GPB3_TXD1 (0x03 << 6)
146 94
147#define S3C2410_GPB4_TCLK0 (0x02 << 8) 95#define S3C2410_GPB4_TCLK0 (0x02 << 8)
148#define S3C2400_GPB4_DATA20 (0x02 << 8)
149#define S3C2410_GPB4_MASK (0x03 << 8) 96#define S3C2410_GPB4_MASK (0x03 << 8)
150#define S3C2400_GPB4_RXD1 (0x03 << 8)
151#define S3C2400_GPB4_MASK (0x03 << 8)
152 97
153#define S3C2410_GPB5_nXBACK (0x02 << 10) 98#define S3C2410_GPB5_nXBACK (0x02 << 10)
154#define S3C2443_GPB5_XBACK (0x03 << 10) 99#define S3C2443_GPB5_XBACK (0x03 << 10)
155#define S3C2400_GPB5_DATA21 (0x02 << 10)
156#define S3C2400_GPB5_nCTS1 (0x03 << 10)
157 100
158#define S3C2410_GPB6_nXBREQ (0x02 << 12) 101#define S3C2410_GPB6_nXBREQ (0x02 << 12)
159#define S3C2443_GPB6_XBREQ (0x03 << 12) 102#define S3C2443_GPB6_XBREQ (0x03 << 12)
160#define S3C2400_GPB6_DATA22 (0x02 << 12)
161#define S3C2400_GPB6_nRTS1 (0x03 << 12)
162 103
163#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 104#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
164#define S3C2443_GPB7_XDACK1 (0x03 << 14) 105#define S3C2443_GPB7_XDACK1 (0x03 << 14)
165#define S3C2400_GPB7_DATA23 (0x02 << 14)
166 106
167#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 107#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
168#define S3C2400_GPB8_DATA24 (0x02 << 16)
169 108
170#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 109#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
171#define S3C2443_GPB9_XDACK0 (0x03 << 18) 110#define S3C2443_GPB9_XDACK0 (0x03 << 18)
172#define S3C2400_GPB9_DATA25 (0x02 << 18)
173#define S3C2400_GPB9_I2SSDI (0x03 << 18)
174 111
175#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 112#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
176#define S3C2443_GPB10_XDREQ0 (0x03 << 20) 113#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
177#define S3C2400_GPB10_DATA26 (0x02 << 20)
178#define S3C2400_GPB10_nSS (0x03 << 20)
179
180#define S3C2400_GPB11_INP (0x00 << 22)
181#define S3C2400_GPB11_OUTP (0x01 << 22)
182#define S3C2400_GPB11_DATA27 (0x02 << 22)
183
184#define S3C2400_GPB12_INP (0x00 << 24)
185#define S3C2400_GPB12_OUTP (0x01 << 24)
186#define S3C2400_GPB12_DATA28 (0x02 << 24)
187
188#define S3C2400_GPB13_INP (0x00 << 26)
189#define S3C2400_GPB13_OUTP (0x01 << 26)
190#define S3C2400_GPB13_DATA29 (0x02 << 26)
191
192#define S3C2400_GPB14_INP (0x00 << 28)
193#define S3C2400_GPB14_OUTP (0x01 << 28)
194#define S3C2400_GPB14_DATA30 (0x02 << 28)
195
196#define S3C2400_GPB15_INP (0x00 << 30)
197#define S3C2400_GPB15_OUTP (0x01 << 30)
198#define S3C2400_GPB15_DATA31 (0x02 << 30)
199 114
200#define S3C2410_GPB_PUPDIS(x) (1<<(x)) 115#define S3C2410_GPB_PUPDIS(x) (1<<(x))
201 116
@@ -208,59 +123,22 @@
208#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) 123#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
209#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) 124#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
210#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) 125#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
211
212#define S3C2400_GPCCON S3C2410_GPIOREG(0x14)
213#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
214#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
215
216#define S3C2410_GPC0_LEND (0x02 << 0) 126#define S3C2410_GPC0_LEND (0x02 << 0)
217#define S3C2400_GPC0_VD0 (0x02 << 0)
218
219#define S3C2410_GPC1_VCLK (0x02 << 2) 127#define S3C2410_GPC1_VCLK (0x02 << 2)
220#define S3C2400_GPC1_VD1 (0x02 << 2)
221
222#define S3C2410_GPC2_VLINE (0x02 << 4) 128#define S3C2410_GPC2_VLINE (0x02 << 4)
223#define S3C2400_GPC2_VD2 (0x02 << 4)
224
225#define S3C2410_GPC3_VFRAME (0x02 << 6) 129#define S3C2410_GPC3_VFRAME (0x02 << 6)
226#define S3C2400_GPC3_VD3 (0x02 << 6)
227
228#define S3C2410_GPC4_VM (0x02 << 8) 130#define S3C2410_GPC4_VM (0x02 << 8)
229#define S3C2400_GPC4_VD4 (0x02 << 8)
230
231#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 131#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
232#define S3C2400_GPC5_VD5 (0x02 << 10)
233
234#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 132#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
235#define S3C2400_GPC6_VD6 (0x02 << 12)
236
237#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 133#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
238#define S3C2400_GPC7_VD7 (0x02 << 14)
239
240#define S3C2410_GPC8_VD0 (0x02 << 16) 134#define S3C2410_GPC8_VD0 (0x02 << 16)
241#define S3C2400_GPC8_VD8 (0x02 << 16)
242
243#define S3C2410_GPC9_VD1 (0x02 << 18) 135#define S3C2410_GPC9_VD1 (0x02 << 18)
244#define S3C2400_GPC9_VD9 (0x02 << 18)
245
246#define S3C2410_GPC10_VD2 (0x02 << 20) 136#define S3C2410_GPC10_VD2 (0x02 << 20)
247#define S3C2400_GPC10_VD10 (0x02 << 20)
248
249#define S3C2410_GPC11_VD3 (0x02 << 22) 137#define S3C2410_GPC11_VD3 (0x02 << 22)
250#define S3C2400_GPC11_VD11 (0x02 << 22)
251
252#define S3C2410_GPC12_VD4 (0x02 << 24) 138#define S3C2410_GPC12_VD4 (0x02 << 24)
253#define S3C2400_GPC12_VD12 (0x02 << 24)
254
255#define S3C2410_GPC13_VD5 (0x02 << 26) 139#define S3C2410_GPC13_VD5 (0x02 << 26)
256#define S3C2400_GPC13_VD13 (0x02 << 26)
257
258#define S3C2410_GPC14_VD6 (0x02 << 28) 140#define S3C2410_GPC14_VD6 (0x02 << 28)
259#define S3C2400_GPC14_VD14 (0x02 << 28)
260
261#define S3C2410_GPC15_VD7 (0x02 << 30) 141#define S3C2410_GPC15_VD7 (0x02 << 30)
262#define S3C2400_GPC15_VD15 (0x02 << 30)
263
264#define S3C2410_GPC_PUPDIS(x) (1<<(x)) 142#define S3C2410_GPC_PUPDIS(x) (1<<(x))
265 143
266/* 144/*
@@ -269,8 +147,6 @@
269 * almost identical setup to port b, but the special functions are mostly 147 * almost identical setup to port b, but the special functions are mostly
270 * to do with the video system's data. 148 * to do with the video system's data.
271 * 149 *
272 * S3C2400: Port D consists of 11 GPIO/Special function
273 *
274 * almost identical setup to port c 150 * almost identical setup to port c
275*/ 151*/
276 152
@@ -278,46 +154,31 @@
278#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) 154#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
279#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) 155#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
280 156
281#define S3C2400_GPDCON S3C2410_GPIOREG(0x20)
282#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
283#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
284
285#define S3C2410_GPD0_VD8 (0x02 << 0) 157#define S3C2410_GPD0_VD8 (0x02 << 0)
286#define S3C2400_GPD0_VFRAME (0x02 << 0)
287#define S3C2442_GPD0_nSPICS1 (0x03 << 0) 158#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
288 159
289#define S3C2410_GPD1_VD9 (0x02 << 2) 160#define S3C2410_GPD1_VD9 (0x02 << 2)
290#define S3C2400_GPD1_VM (0x02 << 2)
291#define S3C2442_GPD1_SPICLK1 (0x03 << 2) 161#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
292 162
293#define S3C2410_GPD2_VD10 (0x02 << 4) 163#define S3C2410_GPD2_VD10 (0x02 << 4)
294#define S3C2400_GPD2_VLINE (0x02 << 4)
295 164
296#define S3C2410_GPD3_VD11 (0x02 << 6) 165#define S3C2410_GPD3_VD11 (0x02 << 6)
297#define S3C2400_GPD3_VCLK (0x02 << 6)
298 166
299#define S3C2410_GPD4_VD12 (0x02 << 8) 167#define S3C2410_GPD4_VD12 (0x02 << 8)
300#define S3C2400_GPD4_LEND (0x02 << 8)
301 168
302#define S3C2410_GPD5_VD13 (0x02 << 10) 169#define S3C2410_GPD5_VD13 (0x02 << 10)
303#define S3C2400_GPD5_TOUT0 (0x02 << 10)
304 170
305#define S3C2410_GPD6_VD14 (0x02 << 12) 171#define S3C2410_GPD6_VD14 (0x02 << 12)
306#define S3C2400_GPD6_TOUT1 (0x02 << 12)
307 172
308#define S3C2410_GPD7_VD15 (0x02 << 14) 173#define S3C2410_GPD7_VD15 (0x02 << 14)
309#define S3C2400_GPD7_TOUT2 (0x02 << 14)
310 174
311#define S3C2410_GPD8_VD16 (0x02 << 16) 175#define S3C2410_GPD8_VD16 (0x02 << 16)
312#define S3C2400_GPD8_TOUT3 (0x02 << 16)
313#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) 176#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
314 177
315#define S3C2410_GPD9_VD17 (0x02 << 18) 178#define S3C2410_GPD9_VD17 (0x02 << 18)
316#define S3C2400_GPD9_TCLK0 (0x02 << 18)
317#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) 179#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
318 180
319#define S3C2410_GPD10_VD18 (0x02 << 20) 181#define S3C2410_GPD10_VD18 (0x02 << 20)
320#define S3C2400_GPD10_nWAIT (0x02 << 20)
321#define S3C2440_GPD10_SPICLK1 (0x03 << 20) 182#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
322 183
323#define S3C2410_GPD11_VD19 (0x02 << 22) 184#define S3C2410_GPD11_VD19 (0x02 << 22)
@@ -340,9 +201,6 @@
340 * again, the same as port B, but dealing with I2S, SDI, and 201 * again, the same as port B, but dealing with I2S, SDI, and
341 * more miscellaneous functions 202 * more miscellaneous functions
342 * 203 *
343 * S3C2400:
344 * Port E consists of 12 GPIO/Special function
345 *
346 * GPIO / interrupt inputs 204 * GPIO / interrupt inputs
347*/ 205*/
348 206
@@ -350,74 +208,51 @@
350#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) 208#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
351#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) 209#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
352 210
353#define S3C2400_GPECON S3C2410_GPIOREG(0x2C)
354#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
355#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
356
357#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 211#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
358#define S3C2443_GPE0_AC_nRESET (0x03 << 0) 212#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
359#define S3C2400_GPE0_EINT0 (0x02 << 0)
360#define S3C2410_GPE0_MASK (0x03 << 0) 213#define S3C2410_GPE0_MASK (0x03 << 0)
361 214
362#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 215#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
363#define S3C2443_GPE1_AC_SYNC (0x03 << 2) 216#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
364#define S3C2400_GPE1_EINT1 (0x02 << 2)
365#define S3C2400_GPE1_nSS (0x03 << 2)
366#define S3C2410_GPE1_MASK (0x03 << 2) 217#define S3C2410_GPE1_MASK (0x03 << 2)
367 218
368#define S3C2410_GPE2_CDCLK (0x02 << 4) 219#define S3C2410_GPE2_CDCLK (0x02 << 4)
369#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 220#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
370#define S3C2400_GPE2_EINT2 (0x02 << 4)
371#define S3C2400_GPE2_I2SSDI (0x03 << 4)
372 221
373#define S3C2410_GPE3_I2SSDI (0x02 << 6) 222#define S3C2410_GPE3_I2SSDI (0x02 << 6)
374#define S3C2443_GPE3_AC_SDI (0x03 << 6) 223#define S3C2443_GPE3_AC_SDI (0x03 << 6)
375#define S3C2400_GPE3_EINT3 (0x02 << 6)
376#define S3C2400_GPE3_nCTS1 (0x03 << 6)
377#define S3C2410_GPE3_nSS0 (0x03 << 6) 224#define S3C2410_GPE3_nSS0 (0x03 << 6)
378#define S3C2410_GPE3_MASK (0x03 << 6) 225#define S3C2410_GPE3_MASK (0x03 << 6)
379 226
380#define S3C2410_GPE4_I2SSDO (0x02 << 8) 227#define S3C2410_GPE4_I2SSDO (0x02 << 8)
381#define S3C2443_GPE4_AC_SDO (0x03 << 8) 228#define S3C2443_GPE4_AC_SDO (0x03 << 8)
382#define S3C2400_GPE4_EINT4 (0x02 << 8)
383#define S3C2400_GPE4_nRTS1 (0x03 << 8)
384#define S3C2410_GPE4_I2SSDI (0x03 << 8) 229#define S3C2410_GPE4_I2SSDI (0x03 << 8)
385#define S3C2410_GPE4_MASK (0x03 << 8) 230#define S3C2410_GPE4_MASK (0x03 << 8)
386 231
387#define S3C2410_GPE5_SDCLK (0x02 << 10) 232#define S3C2410_GPE5_SDCLK (0x02 << 10)
388#define S3C2443_GPE5_SD1_CLK (0x02 << 10) 233#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
389#define S3C2400_GPE5_EINT5 (0x02 << 10)
390#define S3C2400_GPE5_TCLK1 (0x03 << 10)
391#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) 234#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
392 235
393#define S3C2410_GPE6_SDCMD (0x02 << 12) 236#define S3C2410_GPE6_SDCMD (0x02 << 12)
394#define S3C2443_GPE6_SD1_CMD (0x02 << 12) 237#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
395#define S3C2443_GPE6_AC_SDI (0x03 << 12) 238#define S3C2443_GPE6_AC_SDI (0x03 << 12)
396#define S3C2400_GPE6_EINT6 (0x02 << 12)
397 239
398#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 240#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
399#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 241#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
400#define S3C2443_GPE7_AC_SDO (0x03 << 14) 242#define S3C2443_GPE7_AC_SDO (0x03 << 14)
401#define S3C2400_GPE7_EINT7 (0x02 << 14)
402 243
403#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 244#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
404#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 245#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
405#define S3C2443_GPE8_AC_SYNC (0x03 << 16) 246#define S3C2443_GPE8_AC_SYNC (0x03 << 16)
406#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
407 247
408#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 248#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
409#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 249#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
410#define S3C2443_GPE9_AC_nRESET (0x03 << 18) 250#define S3C2443_GPE9_AC_nRESET (0x03 << 18)
411#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
412#define S3C2400_GPE9_nXBACK (0x03 << 18)
413 251
414#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 252#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
415#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 253#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
416#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
417 254
418#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 255#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
419#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
420#define S3C2400_GPE11_nXBREQ (0x03 << 22)
421 256
422#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 257#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
423 258
@@ -447,9 +282,6 @@
447 * 282 *
448 * pull up works like all other ports. 283 * pull up works like all other ports.
449 * 284 *
450 * S3C2400:
451 * Port F consists of 7 GPIO/Special function
452 *
453 * GPIO/serial/misc pins 285 * GPIO/serial/misc pins
454*/ 286*/
455 287
@@ -457,37 +289,14 @@
457#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) 289#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
458#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) 290#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
459 291
460#define S3C2400_GPFCON S3C2410_GPIOREG(0x38)
461#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
462#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
463
464#define S3C2410_GPF0_EINT0 (0x02 << 0) 292#define S3C2410_GPF0_EINT0 (0x02 << 0)
465#define S3C2400_GPF0_RXD0 (0x02 << 0)
466
467#define S3C2410_GPF1_EINT1 (0x02 << 2) 293#define S3C2410_GPF1_EINT1 (0x02 << 2)
468#define S3C2400_GPF1_RXD1 (0x02 << 2)
469#define S3C2400_GPF1_IICSDA (0x03 << 2)
470
471#define S3C2410_GPF2_EINT2 (0x02 << 4) 294#define S3C2410_GPF2_EINT2 (0x02 << 4)
472#define S3C2400_GPF2_TXD0 (0x02 << 4)
473
474#define S3C2410_GPF3_EINT3 (0x02 << 6) 295#define S3C2410_GPF3_EINT3 (0x02 << 6)
475#define S3C2400_GPF3_TXD1 (0x02 << 6)
476#define S3C2400_GPF3_IICSCL (0x03 << 6)
477
478#define S3C2410_GPF4_EINT4 (0x02 << 8) 296#define S3C2410_GPF4_EINT4 (0x02 << 8)
479#define S3C2400_GPF4_nRTS0 (0x02 << 8)
480#define S3C2400_GPF4_nXBACK (0x03 << 8)
481
482#define S3C2410_GPF5_EINT5 (0x02 << 10) 297#define S3C2410_GPF5_EINT5 (0x02 << 10)
483#define S3C2400_GPF5_nCTS0 (0x02 << 10)
484#define S3C2400_GPF5_nXBREQ (0x03 << 10)
485
486#define S3C2410_GPF6_EINT6 (0x02 << 12) 298#define S3C2410_GPF6_EINT6 (0x02 << 12)
487#define S3C2400_GPF6_CLKOUT (0x02 << 12)
488
489#define S3C2410_GPF7_EINT7 (0x02 << 14) 299#define S3C2410_GPF7_EINT7 (0x02 << 14)
490
491#define S3C2410_GPF_PUPDIS(x) (1<<(x)) 300#define S3C2410_GPF_PUPDIS(x) (1<<(x))
492 301
493/* S3C2410: 302/* S3C2410:
@@ -497,62 +306,38 @@
497 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 306 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
498 * 307 *
499 * pull up works like all other ports. 308 * pull up works like all other ports.
500 *
501 * S3C2400:
502 * Port G consists of 10 GPIO/Special function
503*/ 309*/
504 310
505#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) 311#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
506#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) 312#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
507#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) 313#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
508 314
509#define S3C2400_GPGCON S3C2410_GPIOREG(0x44)
510#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
511#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
512
513#define S3C2410_GPG0_EINT8 (0x02 << 0) 315#define S3C2410_GPG0_EINT8 (0x02 << 0)
514#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
515 316
516#define S3C2410_GPG1_EINT9 (0x02 << 2) 317#define S3C2410_GPG1_EINT9 (0x02 << 2)
517#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
518 318
519#define S3C2410_GPG2_EINT10 (0x02 << 4) 319#define S3C2410_GPG2_EINT10 (0x02 << 4)
520#define S3C2410_GPG2_nSS0 (0x03 << 4) 320#define S3C2410_GPG2_nSS0 (0x03 << 4)
521#define S3C2400_GPG2_CDCLK (0x02 << 4)
522 321
523#define S3C2410_GPG3_EINT11 (0x02 << 6) 322#define S3C2410_GPG3_EINT11 (0x02 << 6)
524#define S3C2410_GPG3_nSS1 (0x03 << 6) 323#define S3C2410_GPG3_nSS1 (0x03 << 6)
525#define S3C2400_GPG3_I2SSDO (0x02 << 6)
526#define S3C2400_GPG3_I2SSDI (0x03 << 6)
527 324
528#define S3C2410_GPG4_EINT12 (0x02 << 8) 325#define S3C2410_GPG4_EINT12 (0x02 << 8)
529#define S3C2400_GPG4_MMCCLK (0x02 << 8)
530#define S3C2400_GPG4_I2SSDI (0x03 << 8)
531#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 326#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
532#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 327#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
533 328
534#define S3C2410_GPG5_EINT13 (0x02 << 10) 329#define S3C2410_GPG5_EINT13 (0x02 << 10)
535#define S3C2400_GPG5_MMCCMD (0x02 << 10)
536#define S3C2400_GPG5_IICSDA (0x03 << 10)
537#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 330#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
538 331
539#define S3C2410_GPG6_EINT14 (0x02 << 12) 332#define S3C2410_GPG6_EINT14 (0x02 << 12)
540#define S3C2400_GPG6_MMCDAT (0x02 << 12)
541#define S3C2400_GPG6_IICSCL (0x03 << 12)
542#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 333#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
543 334
544#define S3C2410_GPG7_EINT15 (0x02 << 14) 335#define S3C2410_GPG7_EINT15 (0x02 << 14)
545#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 336#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
546#define S3C2400_GPG7_SPIMISO (0x02 << 14)
547#define S3C2400_GPG7_IICSDA (0x03 << 14)
548 337
549#define S3C2410_GPG8_EINT16 (0x02 << 16) 338#define S3C2410_GPG8_EINT16 (0x02 << 16)
550#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
551#define S3C2400_GPG8_IICSCL (0x03 << 16)
552 339
553#define S3C2410_GPG9_EINT17 (0x02 << 18) 340#define S3C2410_GPG9_EINT17 (0x02 << 18)
554#define S3C2400_GPG9_SPICLK (0x02 << 18)
555#define S3C2400_GPG9_MMCCLK (0x03 << 18)
556 341
557#define S3C2410_GPG10_EINT18 (0x02 << 20) 342#define S3C2410_GPG10_EINT18 (0x02 << 20)
558 343
@@ -660,7 +445,6 @@
660#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) 445#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
661 446
662/* miscellaneous control */ 447/* miscellaneous control */
663#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
664#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 448#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
665#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 449#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
666 450
@@ -674,14 +458,6 @@
674#define S3C2410_MISCCR_SPUCR_LEN (0<<1) 458#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
675#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) 459#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
676 460
677#define S3C2400_MISCCR_SPUCR_LEN (0<<0)
678#define S3C2400_MISCCR_SPUCR_LDIS (1<<0)
679#define S3C2400_MISCCR_SPUCR_HEN (0<<1)
680#define S3C2400_MISCCR_SPUCR_HDIS (1<<1)
681
682#define S3C2400_MISCCR_HZ_STOPEN (0<<2)
683#define S3C2400_MISCCR_HZ_STOPPREV (1<<2)
684
685#define S3C2410_MISCCR_USBDEV (0<<3) 461#define S3C2410_MISCCR_USBDEV (0<<3)
686#define S3C2410_MISCCR_USBHOST (1<<3) 462#define S3C2410_MISCCR_USBHOST (1<<3)
687 463
@@ -728,7 +504,6 @@
728 * 504 *
729 * Samsung datasheet p9-25 505 * Samsung datasheet p9-25
730*/ 506*/
731#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)
732#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) 507#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
733#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 508#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
734#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 509#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
@@ -796,22 +571,6 @@
796#define S3C2410_GSTATUS2_OFFRESET (1<<1) 571#define S3C2410_GSTATUS2_OFFRESET (1<<1)
797#define S3C2410_GSTATUS2_PONRESET (1<<0) 572#define S3C2410_GSTATUS2_PONRESET (1<<0)
798 573
799/* open drain control register */
800#define S3C2400_OPENCR S3C2410_GPIOREG(0x50)
801
802#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)
803#define S3C2400_OPENCR_OPC_RXD1EN (1<<0)
804#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)
805#define S3C2400_OPENCR_OPC_TXD1EN (1<<1)
806#define S3C2400_OPENCR_OPC_CMDDIS (0<<2)
807#define S3C2400_OPENCR_OPC_CMDEN (1<<2)
808#define S3C2400_OPENCR_OPC_DATDIS (0<<3)
809#define S3C2400_OPENCR_OPC_DATEN (1<<3)
810#define S3C2400_OPENCR_OPC_MISODIS (0<<4)
811#define S3C2400_OPENCR_OPC_MISOEN (1<<4)
812#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
813#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
814
815/* 2412/2413 sleep configuration registers */ 574/* 2412/2413 sleep configuration registers */
816 575
817#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) 576#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 988a6863e54b..e0c67b0163d8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -145,29 +145,8 @@
145#define S3C2410_BANKCON_Tacs_SHIFT (13) 145#define S3C2410_BANKCON_Tacs_SHIFT (13)
146 146
147#define S3C2410_BANKCON_SRAM (0x0 << 15) 147#define S3C2410_BANKCON_SRAM (0x0 << 15)
148#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
149#define S3C2410_BANKCON_SDRAM (0x3 << 15) 148#define S3C2410_BANKCON_SDRAM (0x3 << 15)
150 149
151/* next bits only for EDO DRAM in 6,7 */
152#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
153#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
154#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
155#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
156
157/* CAS pulse width */
158#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
159#define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3)
160
161/* CAS pre-charge */
162#define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2)
163#define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2)
164
165/* control column address select */
166#define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0)
167#define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0)
168#define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0)
169#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
170
171/* next bits only for SDRAM in 6,7 */ 150/* next bits only for SDRAM in 6,7 */
172#define S3C2410_BANKCON_Trcd2 (0x00 << 2) 151#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
173#define S3C2410_BANKCON_Trcd3 (0x01 << 2) 152#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
@@ -194,12 +173,6 @@
194#define S3C2410_REFRESH_TRP_3clk (1<<20) 173#define S3C2410_REFRESH_TRP_3clk (1<<20)
195#define S3C2410_REFRESH_TRP_4clk (2<<20) 174#define S3C2410_REFRESH_TRP_4clk (2<<20)
196 175
197#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20)
198#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
199#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
200#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
201#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
202
203#define S3C2410_REFRESH_TSRC_MASK (3<<18) 176#define S3C2410_REFRESH_TSRC_MASK (3<<18)
204#define S3C2410_REFRESH_TSRC_4clk (0<<18) 177#define S3C2410_REFRESH_TSRC_4clk (0<<18)
205#define S3C2410_REFRESH_TSRC_5clk (1<<18) 178#define S3C2410_REFRESH_TSRC_5clk (1<<18)
@@ -222,7 +195,6 @@
222#define S3C2410_BANKSIZE_4M (0x5 << 0) 195#define S3C2410_BANKSIZE_4M (0x5 << 0)
223#define S3C2410_BANKSIZE_2M (0x4 << 0) 196#define S3C2410_BANKSIZE_2M (0x4 << 0)
224#define S3C2410_BANKSIZE_MASK (0x7 << 0) 197#define S3C2410_BANKSIZE_MASK (0x7 << 0)
225#define S3C2400_BANKSIZE_MASK (0x4 << 0)
226#define S3C2410_BANKSIZE_SCLK_EN (1<<4) 198#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
227#define S3C2410_BANKSIZE_SCKE_EN (1<<5) 199#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
228#define S3C2410_BANKSIZE_BURST (1<<7) 200#define S3C2410_BANKSIZE_BURST (1<<7)
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index e82ab4aa7ab9..c2cf4e569989 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -15,7 +15,7 @@ config CPU_S3C2412
15 15
16config CPU_S3C2412_ONLY 16config CPU_S3C2412_ONLY
17 bool 17 bool
18 depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \ 18 depends on ARCH_S3C2410 && !CPU_S3C2410 && \
19 !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \ 19 !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
20 !CPU_S3C2443 && CPU_S3C2412 20 !CPU_S3C2443 && CPU_S3C2412
21 default y if CPU_S3C2412 21 default y if CPU_S3C2412
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
deleted file mode 100644
index 0c5a73805560..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 as
5 * published by the Free Software Foundation.
6*/
7
8/* pull in the relevant register and map files. */
9
10#include <mach/map.h>
11#include <plat/regs-serial.h>
12
13 .macro addruart, rp, rv
14 ldr \rp, = S3C24XX_PA_UART
15 ldr \rv, = S3C24XX_VA_UART
16#if CONFIG_DEBUG_S3C_UART != 0
17 add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
18 add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
19#endif
20 .endm
21
22/* include the reset of the code which will do the work, we're only
23 * compiling for a single cpu processor type so the default of s3c2440
24 * will be fine with us.
25 */
26
27#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c24a0/include/mach/io.h b/arch/arm/mach-s3c24a0/include/mach/io.h
deleted file mode 100644
index 4326c30fabcb..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s3c24a0/include/mach/io.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben-linux@fluff.org>
5 *
6 * Default IO routines for S3C24A0
7 */
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12/* No current ISA/PCI bus support. */
13#define __io(a) __typesafe_io(a)
14#define __mem_pci(a) (a)
15
16#define IO_SPACE_LIMIT (0xFFFFFFFF)
17
18#endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h
deleted file mode 100644
index 83ce2a7a9dae..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/irqs.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef __ASM_ARCH_24A0_IRQS_H
13#define __ASM_ARCH_24A0_IRQS_H __FILE__
14
15#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
16/* for generic entry-macro.S */
17#define IRQ_EINT0 IRQ_EINT0t2
18
19#define IRQ_EINT3t6 S3C2410_IRQ(1)
20#define IRQ_EINT7t10 S3C2410_IRQ(2)
21#define IRQ_EINT11t14 S3C2410_IRQ(3)
22#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
23#define IRQ_TICK S3C2410_IRQ(5)
24#define IRQ_DCTQ S3C2410_IRQ(6)
25#define IRQ_MC S3C2410_IRQ(7)
26#define IRQ_ME S3C2410_IRQ(8) /* 24 */
27#define IRQ_KEYPAD S3C2410_IRQ(9)
28#define IRQ_TIMER0 S3C2410_IRQ(10)
29#define IRQ_TIMER1 S3C2410_IRQ(11)
30#define IRQ_TIMER2 S3C2410_IRQ(12)
31#define IRQ_TIMER3_4 S3C2410_IRQ(13)
32#define IRQ_OS_TIMER IRQ_TIMER3_4
33#define IRQ_LCD S3C2410_IRQ(14)
34#define IRQ_CAM_C S3C2410_IRQ(15)
35#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
36#define IRQ_UART0 S3C2410_IRQ(17)
37#define IRQ_CAM_P S3C2410_IRQ(18)
38#define IRQ_MODEM S3C2410_IRQ(19)
39#define IRQ_DMA S3C2410_IRQ(20)
40#define IRQ_SDI S3C2410_IRQ(21)
41#define IRQ_SPI0 S3C2410_IRQ(22)
42#define IRQ_UART1 S3C2410_IRQ(23)
43#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
44#define IRQ_USBD S3C2410_IRQ(25)
45#define IRQ_USBH S3C2410_IRQ(26)
46#define IRQ_IIC S3C2410_IRQ(27)
47#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
48#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
49#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
50#define IRQ_ADC_PEN S3C2410_IRQ(31)
51
52/* interrupts generated from the external interrupts sources */
53#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
54#define IRQ_EINT1 S3C2410_IRQ(33)
55#define IRQ_EINT2 S3C2410_IRQ(34)
56#define IRQ_EINT3 S3C2410_IRQ(35)
57#define IRQ_EINT4 S3C2410_IRQ(36)
58#define IRQ_EINT5 S3C2410_IRQ(37)
59#define IRQ_EINT6 S3C2410_IRQ(38)
60#define IRQ_EINT7 S3C2410_IRQ(39)
61#define IRQ_EINT8 S3C2410_IRQ(40)
62#define IRQ_EINT9 S3C2410_IRQ(41)
63#define IRQ_EINT10 S3C2410_IRQ(42)
64#define IRQ_EINT11 S3C2410_IRQ(43)
65#define IRQ_EINT12 S3C2410_IRQ(44)
66#define IRQ_EINT13 S3C2410_IRQ(45)
67#define IRQ_EINT14 S3C2410_IRQ(46)
68#define IRQ_EINT15 S3C2410_IRQ(47)
69#define IRQ_EINT16 S3C2410_IRQ(48)
70#define IRQ_EINT17 S3C2410_IRQ(49)
71#define IRQ_EINT18 S3C2410_IRQ(50)
72
73#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
74
75/* SUB IRQS */
76#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
77#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
78#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
79
80#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
81#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
82#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
83
84#define IRQ_S3CUART_RX2 (0x0)
85#define IRQ_S3CUART_TX2 (0x0)
86#define IRQ_S3CUART_ERR2 (0x0)
87
88
89#define IRQ_IRDA S3C2410_IRQ(57)
90#define IRQ_MSTICK S3C2410_IRQ(58)
91#define IRQ_RESERVED0 S3C2410_IRQ(59)
92#define IRQ_RESERVED1 S3C2410_IRQ(60)
93#define IRQ_RESERVED2 S3C2410_IRQ(61)
94#define IRQ_TIMER3 S3C2410_IRQ(62)
95#define IRQ_TIMER4 S3C2410_IRQ(63)
96#define IRQ_WDT S3C2410_IRQ(64)
97#define IRQ_BATFLT S3C2410_IRQ(65)
98#define IRQ_POST S3C2410_IRQ(66)
99#define IRQ_DISP_FIFO S3C2410_IRQ(67)
100#define IRQ_PENUP S3C2410_IRQ(68)
101#define IRQ_PENDN S3C2410_IRQ(69)
102#define IRQ_ADC S3C2410_IRQ(70)
103#define IRQ_DISP_FRAME S3C2410_IRQ(71)
104#define IRQ_NFLASH S3C2410_IRQ(72)
105#define IRQ_AC97 S3C2410_IRQ(73)
106#define IRQ_SPI1 S3C2410_IRQ(74)
107#define IRQ_VLX S3C2410_IRQ(75)
108#define IRQ_DMA0 S3C2410_IRQ(76)
109#define IRQ_DMA1 S3C2410_IRQ(77)
110#define IRQ_DMA2 S3C2410_IRQ(78)
111#define IRQ_DMA3 S3C2410_IRQ(79)
112
113#define IRQ_TC (0x0)
114
115#define NR_IRQS (IRQ_DMA3+1)
116
117#endif /* __ASM_ARCH_24A0_IRQS_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
deleted file mode 100644
index d88c8b24fe34..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
2 *
3 * Copyright 2003-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24A0 - Memory map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_24A0_MAP_H
15#define __ASM_ARCH_24A0_MAP_H __FILE__
16
17#include <plat/map-base.h>
18#include <plat/map.h>
19
20#define S3C24A0_PA_IO_BASE (0x40000000)
21#define S3C24A0_PA_CLKPWR (0x40000000)
22#define S3C24A0_PA_IRQ (0x40200000)
23#define S3C24A0_PA_DMA (0x40400000)
24#define S3C24A0_PA_MEMCTRL (0x40C00000)
25#define S3C24A0_PA_NAND (0x40C00000)
26#define S3C24A0_PA_SROM (0x40C20000)
27#define S3C24A0_PA_SDRAM (0x40C40000)
28#define S3C24A0_PA_BUSM (0x40CE0000)
29#define S3C24A0_PA_USBHOST (0x41000000)
30#define S3C24A0_PA_MODEMIF (0x41180000)
31#define S3C24A0_PA_IRDA (0x41800000)
32#define S3C24A0_PA_TIMER (0x44000000)
33#define S3C24A0_PA_WATCHDOG (0x44100000)
34#define S3C24A0_PA_RTC (0x44200000)
35#define S3C24A0_PA_UART (0x44400000)
36#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
37#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
38#define S3C24A0_PA_SPI (0x44500000)
39#define S3C24A0_PA_IIC (0x44600000)
40#define S3C24A0_PA_IIS (0x44700000)
41#define S3C24A0_PA_GPIO (0x44800000)
42#define S3C24A0_PA_KEYIF (0x44900000)
43#define S3C24A0_PA_USBDEV (0x44A00000)
44#define S3C24A0_PA_AC97 (0x45000000)
45#define S3C24A0_PA_ADC (0x45800000)
46#define S3C24A0_PA_SDI (0x46000000)
47#define S3C24A0_PA_MS (0x46100000)
48#define S3C24A0_PA_LCD (0x4A000000)
49#define S3C24A0_PA_VPOST (0x4A100000)
50
51/* physical addresses of all the chip-select areas */
52
53#define S3C24A0_CS0 (0x00000000)
54#define S3C24A0_CS1 (0x04000000)
55#define S3C24A0_CS2 (0x08000000)
56#define S3C24A0_CS3 (0x0C000000)
57#define S3C24A0_CS4 (0x10000000)
58#define S3C24A0_CS5 (0x40000000)
59
60#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
61
62/* Use a single interface for common resources between S3C24XX cpus */
63
64#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
65#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
66#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
67#define S3C24XX_PA_DMA S3C24A0_PA_DMA
68#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
69#define S3C24XX_PA_LCD S3C24A0_PA_LCD
70#define S3C24XX_PA_UART S3C24A0_PA_UART
71#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
72#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
73#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
74#define S3C24XX_PA_IIS S3C24A0_PA_IIS
75#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
76#define S3C24XX_PA_RTC S3C24A0_PA_RTC
77#define S3C24XX_PA_ADC S3C24A0_PA_ADC
78#define S3C24XX_PA_SPI S3C24A0_PA_SPI
79#define S3C24XX_PA_SDI S3C24A0_PA_SDI
80#define S3C24XX_PA_NAND S3C24A0_PA_NAND
81
82#define S3C_PA_UART S3C24A0_PA_UART
83#define S3C_PA_IIC S3C24A0_PA_IIC
84#define S3C_PA_NAND S3C24XX_PA_NAND
85
86#endif /* __ASM_ARCH_24A0_MAP_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h
deleted file mode 100644
index 7d208a71b172..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/memory.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
2 * from linux/include/asm-arm/arch-rpc/memory.h
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_ARCH_24A0_MEMORY_H
12#define __ASM_ARCH_24A0_MEMORY_H __FILE__
13
14#define PLAT_PHYS_OFFSET UL(0x10000000)
15
16#define __virt_to_bus(x) __virt_to_phys(x)
17#define __bus_to_virt(x) __phys_to_virt(x)
18#define __pfn_to_bus(x) __pfn_to_phys(x)
19#define __bus_to_pfn(x) __phys_to_pfn(x)
20
21#endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
deleted file mode 100644
index be0af518b488..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24A0 clock register definitions
11*/
12
13#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
14#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
15
16#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
17#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
18#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
19#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
20#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
21
22/* CLKCON register bits */
23
24#define S3C24A0_CLKCON_VLX (1<<29)
25#define S3C24A0_CLKCON_VPOST (1<<28)
26#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
27#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
28#define S3C24A0_CLKCON_VPOSTIF (1<<25)
29#define S3C24A0_CLKCON_MPEG4IF (1<<24)
30#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
31#define S3C24A0_CLKCON_LCDC (1<<22)
32#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
33#define S3C24A0_CLKCON_MPEG4 (1<<20)
34#define S3C24A0_CLKCON_KEYPAD (1<<19)
35#define S3C24A0_CLKCON_ADC (1<<18)
36#define S3C24A0_CLKCON_SDI (1<<17)
37#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
38#define S3C24A0_CLKCON_USBD (1<<15)
39#define S3C24A0_CLKCON_GPIO (1<<14)
40#define S3C24A0_CLKCON_IIS (1<<13)
41#define S3C24A0_CLKCON_IIC (1<<12)
42#define S3C24A0_CLKCON_SPI (1<<11)
43#define S3C24A0_CLKCON_UART1 (1<<10)
44#define S3C24A0_CLKCON_UART0 (1<<9)
45#define S3C24A0_CLKCON_PWMT (1<<8)
46#define S3C24A0_CLKCON_USBH (1<<7)
47#define S3C24A0_CLKCON_AC97 (1<<6)
48#define S3C24A0_CLKCON_IrDA (1<<4)
49#define S3C24A0_CLKCON_IDLE (1<<2)
50#define S3C24A0_CLKCON_MON (1<<1)
51#define S3C24A0_CLKCON_STOP (1<<0)
52
53/* CLKSRC register bits */
54
55#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
56#define S3C24A0_CLKSRC_UPLL (1<<7)
57#define S3C24A0_CLKSRC_MPLL (1<<5)
58#define S3C24A0_CLKSRC_EXT (1<<4)
59
60/* Use a single interface with the common code, for s3c24xx */
61
62#define S3C2410_MPLLCON S3C24A0_MPLLCON
63#define S3C2410_UPLLCON S3C24A0_UPLLCON
64#define S3C2410_CLKCON S3C24A0_CLKCON
65#define S3C2410_CLKSLOW S3C24A0_CLKSRC
66#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
67
68#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
69#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
70#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
71#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
72#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
73#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
74#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
75#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
76#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
77#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
78#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
79#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
80#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
81#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
82
83#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
84#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
85#define S3C2410_CLKSLOW_SLOW (0xFF)
86#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
87
88#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
deleted file mode 100644
index 6086f6f189eb..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
13#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
14
15
16#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
17#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
18
19#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
20#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
21
22#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
23
24
25
diff --git a/arch/arm/mach-s3c24a0/include/mach/system.h b/arch/arm/mach-s3c24a0/include/mach/system.h
deleted file mode 100644
index bd1bd1957656..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24A0 - System function defines and includes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <mach/hardware.h>
14#include <asm/io.h>
15
16#include <mach/map.h>
17
18static void arch_idle(void)
19{
20 /* currently no specific idle support. */
21}
22
23void (*s3c24xx_reset_hook)(void);
24
25#include <asm/plat-s3c24xx/system-reset.h>
diff --git a/arch/arm/mach-s3c24a0/include/mach/tick.h b/arch/arm/mach-s3c24a0/include/mach/tick.h
deleted file mode 100644
index 9dea8ba6fb72..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/tick.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24A0 - timer tick support
8 */
9
10#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
11
12static inline int s3c24xx_ostimer_pending(void)
13{
14 return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
15}
diff --git a/arch/arm/mach-s3c24a0/include/mach/timex.h b/arch/arm/mach-s3c24a0/include/mach/timex.h
deleted file mode 100644
index 98573424a016..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16#define CLOCK_TICK_RATE 12000000
17
18#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
deleted file mode 100644
index 6480b15277f3..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
2 *
3 * Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
4
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C24A0 vmalloc definition
10*/
11
12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H
14
15#define VMALLOC_END 0xF6000000UL
16
17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index d9c4096ebf45..8c5b3029b39f 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -4,7 +4,7 @@
4 4
5config PLAT_S3C24XX 5config PLAT_S3C24XX
6 bool 6 bool
7 depends on ARCH_S3C2410 || ARCH_S3C24A0 7 depends on ARCH_S3C2410
8 default y 8 default y
9 select NO_IOPORT 9 select NO_IOPORT
10 select ARCH_REQUIRE_GPIOLIB 10 select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 4a10c0f684b2..c1fc6c6fac72 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -46,7 +46,6 @@
46#include <plat/cpu.h> 46#include <plat/cpu.h>
47#include <plat/devs.h> 47#include <plat/devs.h>
48#include <plat/clock.h> 48#include <plat/clock.h>
49#include <plat/s3c2400.h>
50#include <plat/s3c2410.h> 49#include <plat/s3c2410.h>
51#include <plat/s3c2412.h> 50#include <plat/s3c2412.h>
52#include <plat/s3c2416.h> 51#include <plat/s3c2416.h>
@@ -55,7 +54,6 @@
55 54
56/* table of supported CPUs */ 55/* table of supported CPUs */
57 56
58static const char name_s3c2400[] = "S3C2400";
59static const char name_s3c2410[] = "S3C2410"; 57static const char name_s3c2410[] = "S3C2410";
60static const char name_s3c2412[] = "S3C2412"; 58static const char name_s3c2412[] = "S3C2412";
61static const char name_s3c2416[] = "S3C2416/S3C2450"; 59static const char name_s3c2416[] = "S3C2416/S3C2450";
@@ -157,15 +155,6 @@ static struct cpu_table cpu_ids[] __initdata = {
157 .init = s3c2443_init, 155 .init = s3c2443_init,
158 .name = name_s3c2443, 156 .name = name_s3c2443,
159 }, 157 },
160 {
161 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
162 .idmask = 0xffffffff,
163 .map_io = s3c2400_map_io,
164 .init_clocks = s3c2400_init_clocks,
165 .init_uarts = s3c2400_init_uarts,
166 .init = s3c2400_init,
167 .name = name_s3c2400
168 },
169}; 158};
170 159
171/* minimal IO mapping */ 160/* minimal IO mapping */
@@ -200,11 +189,7 @@ static unsigned long s3c24xx_read_idcode_v5(void)
200 189
201static unsigned long s3c24xx_read_idcode_v4(void) 190static unsigned long s3c24xx_read_idcode_v4(void)
202{ 191{
203#ifndef CONFIG_CPU_S3C2400
204 return __raw_readl(S3C2410_GSTATUS1); 192 return __raw_readl(S3C2410_GSTATUS1);
205#else
206 return 0UL;
207#endif
208} 193}
209 194
210/* Hook for arm_pm_restart to ensure we execute the reset code 195/* Hook for arm_pm_restart to ensure we execute the reset code
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
index a6f1d5df13b4..cc44e0e931e9 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
@@ -64,14 +64,5 @@
64#define S3C2410_IISFCON_RXMASK (0x3f) 64#define S3C2410_IISFCON_RXMASK (0x3f)
65#define S3C2410_IISFCON_RXSHIFT (0) 65#define S3C2410_IISFCON_RXSHIFT (0)
66 66
67#define S3C2400_IISFCON_TXDMA (1<<11)
68#define S3C2400_IISFCON_RXDMA (1<<10)
69#define S3C2400_IISFCON_TXENABLE (1<<9)
70#define S3C2400_IISFCON_RXENABLE (1<<8)
71#define S3C2400_IISFCON_TXMASK (0x07 << 4)
72#define S3C2400_IISFCON_TXSHIFT (4)
73#define S3C2400_IISFCON_RXMASK (0x07)
74#define S3C2400_IISFCON_RXSHIFT (0)
75
76#define S3C2410_IISFIFO (0x10) 67#define S3C2410_IISFIFO (0x10)
77#endif /* __ASM_ARCH_REGS_IIS_H */ 68#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
index 2b35479ee35c..892e2f680fca 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -67,7 +67,6 @@
67 67
68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ 68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
69#define S3C2410_SPPIN_RESERVED (1<<1) 69#define S3C2410_SPPIN_RESERVED (1<<1)
70#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
71#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ 70#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
72 71
73#define S3C2410_SPPRE (0x0C) 72#define S3C2410_SPPRE (0x0C)
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
deleted file mode 100644
index b3feaea5c70b..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2400 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 09-Fev-2006 LCVR First version, based on s3c2410.h
14*/
15
16#ifdef CONFIG_CPU_S3C2400
17
18extern int s3c2400_init(void);
19
20extern void s3c2400_map_io(void);
21
22extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23
24extern void s3c2400_init_clocks(int xtal);
25
26#else
27#define s3c2400_init_clocks NULL
28#define s3c2400_init_uarts NULL
29#define s3c2400_map_io NULL
30#define s3c2400_init NULL
31#endif
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 3ad8386599c3..9a4e53d52967 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -140,7 +140,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
140 140
141/* Pull-{up,down} resistor controls. 141/* Pull-{up,down} resistor controls.
142 * 142 *
143 * S3C2410,S3C2440,S3C24A0 = Pull-UP, 143 * S3C2410,S3C2440 = Pull-UP,
144 * S3C2412,S3C2413 = Pull-Down 144 * S3C2412,S3C2413 = Pull-Down
145 * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] 145 * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
146 * S3C2443 = Pull-Both [not same as S3C6400] 146 * S3C2443 = Pull-Both [not same as S3C6400]
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 116edfe120b9..bac36fa3becb 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -155,14 +155,6 @@
155#define S3C2410_UFSTAT_RXMASK (15<<0) 155#define S3C2410_UFSTAT_RXMASK (15<<0)
156#define S3C2410_UFSTAT_RXSHIFT (0) 156#define S3C2410_UFSTAT_RXSHIFT (0)
157 157
158/* UFSTAT S3C24A0 */
159#define S3C24A0_UFSTAT_TXFULL (1 << 14)
160#define S3C24A0_UFSTAT_RXFULL (1 << 6)
161#define S3C24A0_UFSTAT_TXMASK (63 << 8)
162#define S3C24A0_UFSTAT_TXSHIFT (8)
163#define S3C24A0_UFSTAT_RXMASK (63)
164#define S3C24A0_UFSTAT_RXSHIFT (0)
165
166/* UFSTAT S3C2443 same as S3C2440 */ 158/* UFSTAT S3C2443 same as S3C2440 */
167#define S3C2440_UFSTAT_TXFULL (1<<14) 159#define S3C2440_UFSTAT_TXFULL (1<<14)
168#define S3C2440_UFSTAT_RXFULL (1<<6) 160#define S3C2440_UFSTAT_RXFULL (1<<6)
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 16:26:34 -0500